Skip to content

Commit 4ebb6f5

Browse files
josharianjosharian
committed
cmd/compile: automate resultInArg0 register checks
No functional changes; passes toolstash-check. No measureable performance changes. Change-Id: I2629f73d4a3cc56d80f512f33cf57cf41d8f15d3 Reviewed-on: https://go-review.googlesource.com/c/go/+/296010 Trust: Josh Bleecher Snyder <[email protected]> Run-TryBot: Josh Bleecher Snyder <[email protected]> TryBot-Result: Go Bot <[email protected]> Reviewed-by: Keith Randall <[email protected]>
1 parent 1a3e968 commit 4ebb6f5

File tree

12 files changed

+52
-166
lines changed

12 files changed

+52
-166
lines changed

‎src/cmd/compile/internal/amd64/ssa.go

Lines changed: 13 additions & 63 deletions
Original file line numberDiff line numberDiff line change
@@ -202,9 +202,6 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
202202
p.From = obj.Addr{Type: obj.TYPE_REG, Reg: v.Args[2].Reg()}
203203
p.To = obj.Addr{Type: obj.TYPE_REG, Reg: v.Reg()}
204204
p.SetFrom3(obj.Addr{Type: obj.TYPE_REG, Reg: v.Args[1].Reg()})
205-
if v.Reg() != v.Args[0].Reg() {
206-
v.Fatalf("input[0] and output not in same register %s", v.LongString())
207-
}
208205
case ssa.OpAMD64ADDQ, ssa.OpAMD64ADDL:
209206
r := v.Reg()
210207
r1 := v.Args[0].Reg()
@@ -254,11 +251,7 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
254251
ssa.OpAMD64BTSL, ssa.OpAMD64BTSQ,
255252
ssa.OpAMD64BTCL, ssa.OpAMD64BTCQ,
256253
ssa.OpAMD64BTRL, ssa.OpAMD64BTRQ:
257-
r := v.Reg()
258-
if r != v.Args[0].Reg() {
259-
v.Fatalf("input[0] and output not in same register %s", v.LongString())
260-
}
261-
opregreg(s, v.Op.Asm(), r, v.Args[1].Reg())
254+
opregreg(s, v.Op.Asm(), v.Reg(), v.Args[1].Reg())
262255

263256
case ssa.OpAMD64DIVQU, ssa.OpAMD64DIVLU, ssa.OpAMD64DIVWU:
264257
// Arg[0] (the dividend) is in AX.
@@ -401,20 +394,16 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
401394
// compute (x+y)/2 unsigned.
402395
// Do a 64-bit add, the overflow goes into the carry.
403396
// Shift right once and pull the carry back into the 63rd bit.
404-
r := v.Reg()
405-
if r != v.Args[0].Reg() {
406-
v.Fatalf("input[0] and output not in same register %s", v.LongString())
407-
}
408397
p := s.Prog(x86.AADDQ)
409398
p.From.Type = obj.TYPE_REG
410399
p.To.Type = obj.TYPE_REG
411-
p.To.Reg = r
400+
p.To.Reg = v.Reg()
412401
p.From.Reg = v.Args[1].Reg()
413402
p = s.Prog(x86.ARCRQ)
414403
p.From.Type = obj.TYPE_CONST
415404
p.From.Offset = 1
416405
p.To.Type = obj.TYPE_REG
417-
p.To.Reg = r
406+
p.To.Reg = v.Reg()
418407

419408
case ssa.OpAMD64ADDQcarry, ssa.OpAMD64ADCQ:
420409
r := v.Reg0()
@@ -530,21 +519,13 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
530519
ssa.OpAMD64CMOVQCS, ssa.OpAMD64CMOVLCS, ssa.OpAMD64CMOVWCS,
531520
ssa.OpAMD64CMOVQGTF, ssa.OpAMD64CMOVLGTF, ssa.OpAMD64CMOVWGTF,
532521
ssa.OpAMD64CMOVQGEF, ssa.OpAMD64CMOVLGEF, ssa.OpAMD64CMOVWGEF:
533-
r := v.Reg()
534-
if r != v.Args[0].Reg() {
535-
v.Fatalf("input[0] and output not in same register %s", v.LongString())
536-
}
537522
p := s.Prog(v.Op.Asm())
538523
p.From.Type = obj.TYPE_REG
539524
p.From.Reg = v.Args[1].Reg()
540525
p.To.Type = obj.TYPE_REG
541-
p.To.Reg = r
526+
p.To.Reg = v.Reg()
542527

543528
case ssa.OpAMD64CMOVQNEF, ssa.OpAMD64CMOVLNEF, ssa.OpAMD64CMOVWNEF:
544-
r := v.Reg()
545-
if r != v.Args[0].Reg() {
546-
v.Fatalf("input[0] and output not in same register %s", v.LongString())
547-
}
548529
// Flag condition: ^ZERO || PARITY
549530
// Generate:
550531
// CMOV*NE SRC,DST
@@ -553,7 +534,7 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
553534
p.From.Type = obj.TYPE_REG
554535
p.From.Reg = v.Args[1].Reg()
555536
p.To.Type = obj.TYPE_REG
556-
p.To.Reg = r
537+
p.To.Reg = v.Reg()
557538
var q *obj.Prog
558539
if v.Op == ssa.OpAMD64CMOVQNEF {
559540
q = s.Prog(x86.ACMOVQPS)
@@ -565,14 +546,9 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
565546
q.From.Type = obj.TYPE_REG
566547
q.From.Reg = v.Args[1].Reg()
567548
q.To.Type = obj.TYPE_REG
568-
q.To.Reg = r
549+
q.To.Reg = v.Reg()
569550

570551
case ssa.OpAMD64CMOVQEQF, ssa.OpAMD64CMOVLEQF, ssa.OpAMD64CMOVWEQF:
571-
r := v.Reg()
572-
if r != v.Args[0].Reg() {
573-
v.Fatalf("input[0] and output not in same register %s", v.LongString())
574-
}
575-
576552
// Flag condition: ZERO && !PARITY
577553
// Generate:
578554
// MOV SRC,AX
@@ -589,7 +565,7 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
589565
}
590566
p := s.Prog(v.Op.Asm())
591567
p.From.Type = obj.TYPE_REG
592-
p.From.Reg = r
568+
p.From.Reg = v.Reg()
593569
p.To.Type = obj.TYPE_REG
594570
p.To.Reg = x86.REG_AX
595571
var q *obj.Prog
@@ -603,7 +579,7 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
603579
q.From.Type = obj.TYPE_REG
604580
q.From.Reg = x86.REG_AX
605581
q.To.Type = obj.TYPE_REG
606-
q.To.Reg = r
582+
q.To.Reg = v.Reg()
607583

608584
case ssa.OpAMD64MULQconst, ssa.OpAMD64MULLconst:
609585
r := v.Reg()
@@ -622,15 +598,11 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
622598
ssa.OpAMD64SHRQconst, ssa.OpAMD64SHRLconst, ssa.OpAMD64SHRWconst, ssa.OpAMD64SHRBconst,
623599
ssa.OpAMD64SARQconst, ssa.OpAMD64SARLconst, ssa.OpAMD64SARWconst, ssa.OpAMD64SARBconst,
624600
ssa.OpAMD64ROLQconst, ssa.OpAMD64ROLLconst, ssa.OpAMD64ROLWconst, ssa.OpAMD64ROLBconst:
625-
r := v.Reg()
626-
if r != v.Args[0].Reg() {
627-
v.Fatalf("input[0] and output not in same register %s", v.LongString())
628-
}
629601
p := s.Prog(v.Op.Asm())
630602
p.From.Type = obj.TYPE_CONST
631603
p.From.Offset = v.AuxInt
632604
p.To.Type = obj.TYPE_REG
633-
p.To.Reg = r
605+
p.To.Reg = v.Reg()
634606
case ssa.OpAMD64SBBQcarrymask, ssa.OpAMD64SBBLcarrymask:
635607
r := v.Reg()
636608
p := s.Prog(v.Op.Asm())
@@ -913,9 +885,6 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
913885
ssagen.AddAux(&p.From, v)
914886
p.To.Type = obj.TYPE_REG
915887
p.To.Reg = v.Reg()
916-
if v.Reg() != v.Args[0].Reg() {
917-
v.Fatalf("input[0] and output not in same register %s", v.LongString())
918-
}
919888
case ssa.OpAMD64ADDLloadidx1, ssa.OpAMD64ADDLloadidx4, ssa.OpAMD64ADDLloadidx8, ssa.OpAMD64ADDQloadidx1, ssa.OpAMD64ADDQloadidx8,
920889
ssa.OpAMD64SUBLloadidx1, ssa.OpAMD64SUBLloadidx4, ssa.OpAMD64SUBLloadidx8, ssa.OpAMD64SUBQloadidx1, ssa.OpAMD64SUBQloadidx8,
921890
ssa.OpAMD64ANDLloadidx1, ssa.OpAMD64ANDLloadidx4, ssa.OpAMD64ANDLloadidx8, ssa.OpAMD64ANDQloadidx1, ssa.OpAMD64ANDQloadidx8,
@@ -939,9 +908,6 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
939908
ssagen.AddAux(&p.From, v)
940909
p.To.Type = obj.TYPE_REG
941910
p.To.Reg = v.Reg()
942-
if v.Reg() != v.Args[0].Reg() {
943-
v.Fatalf("input[0] and output not in same register %s", v.LongString())
944-
}
945911
case ssa.OpAMD64DUFFZERO:
946912
if s.ABI != obj.ABIInternal {
947913
v.Fatalf("MOVOconst can be only used in ABIInternal functions")
@@ -1078,22 +1044,14 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
10781044
case ssa.OpAMD64NEGQ, ssa.OpAMD64NEGL,
10791045
ssa.OpAMD64BSWAPQ, ssa.OpAMD64BSWAPL,
10801046
ssa.OpAMD64NOTQ, ssa.OpAMD64NOTL:
1081-
r := v.Reg()
1082-
if r != v.Args[0].Reg() {
1083-
v.Fatalf("input[0] and output not in same register %s", v.LongString())
1084-
}
10851047
p := s.Prog(v.Op.Asm())
10861048
p.To.Type = obj.TYPE_REG
1087-
p.To.Reg = r
1049+
p.To.Reg = v.Reg()
10881050

10891051
case ssa.OpAMD64NEGLflags:
1090-
r := v.Reg0()
1091-
if r != v.Args[0].Reg() {
1092-
v.Fatalf("input[0] and output not in same register %s", v.LongString())
1093-
}
10941052
p := s.Prog(v.Op.Asm())
10951053
p.To.Type = obj.TYPE_REG
1096-
p.To.Reg = r
1054+
p.To.Reg = v.Reg0()
10971055

10981056
case ssa.OpAMD64BSFQ, ssa.OpAMD64BSRQ, ssa.OpAMD64BSFL, ssa.OpAMD64BSRL, ssa.OpAMD64SQRTSD:
10991057
p := s.Prog(v.Op.Asm())
@@ -1214,25 +1172,17 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
12141172
p.To.Type = obj.TYPE_REG
12151173
p.To.Reg = v.Reg0()
12161174
case ssa.OpAMD64XCHGB, ssa.OpAMD64XCHGL, ssa.OpAMD64XCHGQ:
1217-
r := v.Reg0()
1218-
if r != v.Args[0].Reg() {
1219-
v.Fatalf("input[0] and output[0] not in same register %s", v.LongString())
1220-
}
12211175
p := s.Prog(v.Op.Asm())
12221176
p.From.Type = obj.TYPE_REG
1223-
p.From.Reg = r
1177+
p.From.Reg = v.Reg0()
12241178
p.To.Type = obj.TYPE_MEM
12251179
p.To.Reg = v.Args[1].Reg()
12261180
ssagen.AddAux(&p.To, v)
12271181
case ssa.OpAMD64XADDLlock, ssa.OpAMD64XADDQlock:
1228-
r := v.Reg0()
1229-
if r != v.Args[0].Reg() {
1230-
v.Fatalf("input[0] and output[0] not in same register %s", v.LongString())
1231-
}
12321182
s.Prog(x86.ALOCK)
12331183
p := s.Prog(v.Op.Asm())
12341184
p.From.Type = obj.TYPE_REG
1235-
p.From.Reg = r
1185+
p.From.Reg = v.Reg0()
12361186
p.To.Type = obj.TYPE_MEM
12371187
p.To.Reg = v.Args[1].Reg()
12381188
ssagen.AddAux(&p.To, v)

‎src/cmd/compile/internal/arm/ssa.go

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -173,9 +173,6 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
173173
p.To.Type = obj.TYPE_REG
174174
p.To.Reg = y
175175
case ssa.OpARMMOVWnop:
176-
if v.Reg() != v.Args[0].Reg() {
177-
v.Fatalf("input[0] and output not in same register %s", v.LongString())
178-
}
179176
// nothing to do
180177
case ssa.OpLoadReg:
181178
if v.Type.IsFlags() {

‎src/cmd/compile/internal/arm64/ssa.go

Lines changed: 1 addition & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -142,9 +142,6 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
142142
p.To.Type = obj.TYPE_REG
143143
p.To.Reg = y
144144
case ssa.OpARM64MOVDnop:
145-
if v.Reg() != v.Args[0].Reg() {
146-
v.Fatalf("input[0] and output not in same register %s", v.LongString())
147-
}
148145
// nothing to do
149146
case ssa.OpLoadReg:
150147
if v.Type.IsFlags() {
@@ -522,17 +519,13 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
522519
ssagen.AddAux(&p.To, v)
523520
case ssa.OpARM64BFI,
524521
ssa.OpARM64BFXIL:
525-
r := v.Reg()
526-
if r != v.Args[0].Reg() {
527-
v.Fatalf("input[0] and output not in same register %s", v.LongString())
528-
}
529522
p := s.Prog(v.Op.Asm())
530523
p.From.Type = obj.TYPE_CONST
531524
p.From.Offset = v.AuxInt >> 8
532525
p.SetFrom3(obj.Addr{Type: obj.TYPE_CONST, Offset: v.AuxInt & 0xff})
533526
p.Reg = v.Args[1].Reg()
534527
p.To.Type = obj.TYPE_REG
535-
p.To.Reg = r
528+
p.To.Reg = v.Reg()
536529
case ssa.OpARM64SBFIZ,
537530
ssa.OpARM64SBFX,
538531
ssa.OpARM64UBFIZ,

‎src/cmd/compile/internal/mips/ssa.go

Lines changed: 0 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -112,9 +112,6 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
112112
p.To.Reg = y
113113
}
114114
case ssa.OpMIPSMOVWnop:
115-
if v.Reg() != v.Args[0].Reg() {
116-
v.Fatalf("input[0] and output not in same register %s", v.LongString())
117-
}
118115
// nothing to do
119116
case ssa.OpLoadReg:
120117
if v.Type.IsFlags() {
@@ -244,19 +241,13 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
244241
p.To.Type = obj.TYPE_REG
245242
p.To.Reg = v.Reg()
246243
case ssa.OpMIPSCMOVZ:
247-
if v.Reg() != v.Args[0].Reg() {
248-
v.Fatalf("input[0] and output not in same register %s", v.LongString())
249-
}
250244
p := s.Prog(v.Op.Asm())
251245
p.From.Type = obj.TYPE_REG
252246
p.From.Reg = v.Args[2].Reg()
253247
p.Reg = v.Args[1].Reg()
254248
p.To.Type = obj.TYPE_REG
255249
p.To.Reg = v.Reg()
256250
case ssa.OpMIPSCMOVZzero:
257-
if v.Reg() != v.Args[0].Reg() {
258-
v.Fatalf("input[0] and output not in same register %s", v.LongString())
259-
}
260251
p := s.Prog(v.Op.Asm())
261252
p.From.Type = obj.TYPE_REG
262253
p.From.Reg = v.Args[1].Reg()

‎src/cmd/compile/internal/mips64/ssa.go

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -115,9 +115,6 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
115115
p.To.Reg = y
116116
}
117117
case ssa.OpMIPS64MOVVnop:
118-
if v.Reg() != v.Args[0].Reg() {
119-
v.Fatalf("input[0] and output not in same register %s", v.LongString())
120-
}
121118
// nothing to do
122119
case ssa.OpLoadReg:
123120
if v.Type.IsFlags() {

‎src/cmd/compile/internal/riscv64/ssa.go

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -211,9 +211,6 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
211211
p.To.Type = obj.TYPE_REG
212212
p.To.Reg = rd
213213
case ssa.OpRISCV64MOVDnop:
214-
if v.Reg() != v.Args[0].Reg() {
215-
v.Fatalf("input[0] and output not in same register %s", v.LongString())
216-
}
217214
// nothing to do
218215
case ssa.OpLoadReg:
219216
if v.Type.IsFlags() {

0 commit comments

Comments
 (0)