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cmd/compile, runtime: use R20, R21 in ARM64's Duff's devices
Currently we use R16 and R17 for ARM64's Duff's devices. According to ARM64 ABI, R16 and R17 can be used by the (external) linker as scratch registers in trampolines. So don't use these registers to pass information across functions. It seems unlikely that calling Duff's devices would need a trampoline in normal cases. But it could happen if the call target is out of the 128 MB direct jump limit. The choice of R20 and R21 is kind of arbitrary. The register allocator allocates from low-numbered registers. High numbered registers are chosen so it is unlikely to hold a live value and forces a spill. Fixes #32773. Change-Id: Id22d555b5afeadd4efcf62797d1580d641c39218 Reviewed-on: https://go-review.googlesource.com/c/go/+/183842 Run-TryBot: Cherry Zhang <[email protected]> Reviewed-by: Keith Randall <[email protected]>
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7 files changed

+220
-220
lines changed

7 files changed

+220
-220
lines changed

src/cmd/compile/internal/arm64/ggen.go

+3-3
Original file line numberDiff line numberDiff line change
@@ -36,9 +36,9 @@ func zerorange(pp *gc.Progs, p *obj.Prog, off, cnt int64, _ *uint32) *obj.Prog {
3636
off += int64(gc.Widthptr)
3737
cnt -= int64(gc.Widthptr)
3838
}
39-
p = pp.Appendpp(p, arm64.AMOVD, obj.TYPE_REG, arm64.REGSP, 0, obj.TYPE_REG, arm64.REGRT1, 0)
40-
p = pp.Appendpp(p, arm64.AADD, obj.TYPE_CONST, 0, 8+off, obj.TYPE_REG, arm64.REGRT1, 0)
41-
p.Reg = arm64.REGRT1
39+
p = pp.Appendpp(p, arm64.AMOVD, obj.TYPE_REG, arm64.REGSP, 0, obj.TYPE_REG, arm64.REG_R20, 0)
40+
p = pp.Appendpp(p, arm64.AADD, obj.TYPE_CONST, 0, 8+off, obj.TYPE_REG, arm64.REG_R20, 0)
41+
p.Reg = arm64.REG_R20
4242
p = pp.Appendpp(p, obj.ADUFFZERO, obj.TYPE_NONE, 0, 0, obj.TYPE_MEM, 0, 0)
4343
p.To.Name = obj.NAME_EXTERN
4444
p.To.Sym = gc.Duffzero

src/cmd/compile/internal/arm64/ssa.go

+1-1
Original file line numberDiff line numberDiff line change
@@ -820,7 +820,7 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
820820
p.To.Type = obj.TYPE_REG
821821
p.To.Reg = v.Reg()
822822
case ssa.OpARM64DUFFZERO:
823-
// runtime.duffzero expects start address in R16
823+
// runtime.duffzero expects start address in R20
824824
p := s.Prog(obj.ADUFFZERO)
825825
p.To.Type = obj.TYPE_MEM
826826
p.To.Name = obj.NAME_EXTERN

src/cmd/compile/internal/ssa/gen/ARM64Ops.go

+8-8
Original file line numberDiff line numberDiff line change
@@ -495,14 +495,14 @@ func init() {
495495
// arg1 = mem
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// auxint = offset into duffzero code to start executing
497497
// returns mem
498-
// R16 aka arm64.REGRT1 changed as side effect
498+
// R20 changed as side effect
499499
{
500500
name: "DUFFZERO",
501501
aux: "Int64",
502502
argLength: 2,
503503
reg: regInfo{
504-
inputs: []regMask{buildReg("R16")},
505-
clobbers: buildReg("R16 R30"),
504+
inputs: []regMask{buildReg("R20")},
505+
clobbers: buildReg("R20 R30"),
506506
},
507507
faultOnNilArg0: true,
508508
},
@@ -529,19 +529,19 @@ func init() {
529529
},
530530

531531
// duffcopy
532-
// arg0 = address of dst memory (in R17 aka arm64.REGRT2, changed as side effect)
533-
// arg1 = address of src memory (in R16 aka arm64.REGRT1, changed as side effect)
532+
// arg0 = address of dst memory (in R21, changed as side effect)
533+
// arg1 = address of src memory (in R20, changed as side effect)
534534
// arg2 = mem
535535
// auxint = offset into duffcopy code to start executing
536536
// returns mem
537-
// R16, R17 changed as side effect
537+
// R20, R21 changed as side effect
538538
{
539539
name: "DUFFCOPY",
540540
aux: "Int64",
541541
argLength: 3,
542542
reg: regInfo{
543-
inputs: []regMask{buildReg("R17"), buildReg("R16")},
544-
clobbers: buildReg("R16 R17 R26 R30"),
543+
inputs: []regMask{buildReg("R21"), buildReg("R20")},
544+
clobbers: buildReg("R20 R21 R26 R30"),
545545
},
546546
faultOnNilArg0: true,
547547
faultOnNilArg1: true,

src/cmd/compile/internal/ssa/opGen.go

+5-5
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src/cmd/internal/obj/arm64/a.out.go

+2-2
Original file line numberDiff line numberDiff line change
@@ -241,8 +241,8 @@ const (
241241
// compiler allocates external registers F26 down
242242
const (
243243
REGMIN = REG_R7 // register variables allocated from here to REGMAX
244-
REGRT1 = REG_R16 // ARM64 IP0, for external linker, runtime, duffzero and duffcopy
245-
REGRT2 = REG_R17 // ARM64 IP1, for external linker, runtime, duffcopy
244+
REGRT1 = REG_R16 // ARM64 IP0, external linker may use as a scrach register in trampoline
245+
REGRT2 = REG_R17 // ARM64 IP1, external linker may use as a scrach register in trampoline
246246
REGPR = REG_R18 // ARM64 platform register, unused in the Go toolchain
247247
REGMAX = REG_R25
248248

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