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mundaymmundaym
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cmd, runtime: remove s390x 3 operand immediate logical ops
These are emulated by the assembler and we don't need them. Change-Id: I2b07c5315a5b642fdb5e50b468453260ae121164 Reviewed-on: https://go-review.googlesource.com/31758 Reviewed-by: Brad Fitzpatrick <[email protected]>
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4 files changed

+43
-60
lines changed

4 files changed

+43
-60
lines changed

‎src/cmd/compile/internal/s390x/ssa.go

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -809,12 +809,11 @@ func ssaGenBlock(s *gc.SSAGenState, b, next *ssa.Block) {
809809
// defer returns in R3:
810810
// 0 if we should continue executing
811811
// 1 if we should jump to deferreturn call
812-
p := gc.Prog(s390x.AAND)
813-
p.From.Type = obj.TYPE_CONST
814-
p.From.Offset = 0xFFFFFFFF
815-
p.Reg = s390x.REG_R3
816-
p.To.Type = obj.TYPE_REG
817-
p.To.Reg = s390x.REG_R3
812+
p := gc.Prog(s390x.ACMPW)
813+
p.From.Type = obj.TYPE_REG
814+
p.From.Reg = s390x.REG_R3
815+
p.To.Type = obj.TYPE_CONST
816+
p.To.Offset = 0
818817
p = gc.Prog(s390x.ABNE)
819818
p.To.Type = obj.TYPE_BRANCH
820819
s.Branches = append(s.Branches, gc.Branch{P: p, B: b.Succs[1].Block()})

‎src/cmd/internal/obj/s390x/asmz.go

Lines changed: 28 additions & 49 deletions
Original file line numberDiff line numberDiff line change
@@ -161,7 +161,6 @@ var optab = []Optab{
161161
Optab{AAND, C_REG, C_REG, C_NONE, C_REG, 6, 0},
162162
Optab{AAND, C_REG, C_NONE, C_NONE, C_REG, 6, 0},
163163
Optab{AAND, C_LCON, C_NONE, C_NONE, C_REG, 23, 0},
164-
Optab{AAND, C_LCON, C_REG, C_NONE, C_REG, 23, 0},
165164
Optab{AAND, C_LOREG, C_NONE, C_NONE, C_REG, 12, 0},
166165
Optab{AAND, C_LAUTO, C_NONE, C_NONE, C_REG, 12, REGSP},
167166
Optab{AANDW, C_REG, C_REG, C_NONE, C_REG, 6, 0},
@@ -3063,57 +3062,37 @@ func asmout(ctxt *obj.Link, asm *[]byte) {
30633062
zRIE(_d, oprie, uint32(p.To.Reg), uint32(r), uint32(v), 0, 0, 0, 0, asm)
30643063
}
30653064

3066-
case 23: // 64-bit logical op $constant [reg] reg
3067-
// TODO(mundaym): remove the optional register and merge with case 24.
3065+
case 23: // 64-bit logical op $constant reg
3066+
// TODO(mundaym): merge with case 24.
30683067
v := vregoff(ctxt, &p.From)
3069-
var opcode uint32
3070-
r := p.Reg
3071-
if r == 0 {
3072-
r = p.To.Reg
3073-
}
3074-
if r == p.To.Reg {
3075-
switch p.As {
3076-
default:
3077-
ctxt.Diag("%v is not supported", p)
3078-
case AAND:
3079-
if v >= 0 { // needs zero extend
3080-
zRIL(_a, op_LGFI, REGTMP, uint32(v), asm)
3081-
zRRE(op_NGR, uint32(p.To.Reg), REGTMP, asm)
3082-
} else if int64(int16(v)) == v {
3083-
zRI(op_NILL, uint32(p.To.Reg), uint32(v), asm)
3084-
} else { // r.To.Reg & 0xffffffff00000000 & uint32(v)
3085-
zRIL(_a, op_NILF, uint32(p.To.Reg), uint32(v), asm)
3086-
}
3087-
case AOR:
3088-
if int64(uint32(v)) != v { // needs sign extend
3089-
zRIL(_a, op_LGFI, REGTMP, uint32(v), asm)
3090-
zRRE(op_OGR, uint32(p.To.Reg), REGTMP, asm)
3091-
} else if int64(uint16(v)) == v {
3092-
zRI(op_OILL, uint32(p.To.Reg), uint32(v), asm)
3093-
} else {
3094-
zRIL(_a, op_OILF, uint32(p.To.Reg), uint32(v), asm)
3095-
}
3096-
case AXOR:
3097-
if int64(uint32(v)) != v { // needs sign extend
3098-
zRIL(_a, op_LGFI, REGTMP, uint32(v), asm)
3099-
zRRE(op_XGR, uint32(p.To.Reg), REGTMP, asm)
3100-
} else {
3101-
zRIL(_a, op_XILF, uint32(p.To.Reg), uint32(v), asm)
3102-
}
3068+
switch p.As {
3069+
default:
3070+
ctxt.Diag("%v is not supported", p)
3071+
case AAND:
3072+
if v >= 0 { // needs zero extend
3073+
zRIL(_a, op_LGFI, REGTMP, uint32(v), asm)
3074+
zRRE(op_NGR, uint32(p.To.Reg), REGTMP, asm)
3075+
} else if int64(int16(v)) == v {
3076+
zRI(op_NILL, uint32(p.To.Reg), uint32(v), asm)
3077+
} else { // r.To.Reg & 0xffffffff00000000 & uint32(v)
3078+
zRIL(_a, op_NILF, uint32(p.To.Reg), uint32(v), asm)
31033079
}
3104-
} else {
3105-
switch p.As {
3106-
default:
3107-
ctxt.Diag("%v is not supported", p)
3108-
case AAND:
3109-
opcode = op_NGRK
3110-
case AOR:
3111-
opcode = op_OGRK
3112-
case AXOR:
3113-
opcode = op_XGRK
3080+
case AOR:
3081+
if int64(uint32(v)) != v { // needs sign extend
3082+
zRIL(_a, op_LGFI, REGTMP, uint32(v), asm)
3083+
zRRE(op_OGR, uint32(p.To.Reg), REGTMP, asm)
3084+
} else if int64(uint16(v)) == v {
3085+
zRI(op_OILL, uint32(p.To.Reg), uint32(v), asm)
3086+
} else {
3087+
zRIL(_a, op_OILF, uint32(p.To.Reg), uint32(v), asm)
3088+
}
3089+
case AXOR:
3090+
if int64(uint32(v)) != v { // needs sign extend
3091+
zRIL(_a, op_LGFI, REGTMP, uint32(v), asm)
3092+
zRRE(op_XGR, uint32(p.To.Reg), REGTMP, asm)
3093+
} else {
3094+
zRIL(_a, op_XILF, uint32(p.To.Reg), uint32(v), asm)
31143095
}
3115-
zRIL(_a, op_LGFI, REGTMP, uint32(v), asm)
3116-
zRRF(opcode, uint32(r), 0, uint32(p.To.Reg), REGTMP, asm)
31173096
}
31183097

31193098
case 24: // 32-bit logical op $constant reg

‎src/runtime/asm_s390x.s

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -918,12 +918,14 @@ notfoundr0:
918918

919919
vectorimpl:
920920
//if the address is not 16byte aligned, use loop for the header
921-
AND $15, R3, R8
921+
MOVD R3, R8
922+
AND $15, R8
922923
CMPBGT R8, $0, notaligned
923924

924925
aligned:
925926
ADD R6, R4, R8
926-
AND $-16, R8, R7
927+
MOVD R8, R7
928+
AND $-16, R7
927929
// replicate c across V17
928930
VLVGB $0, R5, V19
929931
VREPB $0, V19, V17
@@ -944,7 +946,8 @@ vectorloop:
944946
RET
945947

946948
notaligned:
947-
AND $-16, R3, R8
949+
MOVD R3, R8
950+
AND $-16, R8
948951
ADD $16, R8
949952
notalignedloop:
950953
CMPBEQ R3, R8, aligned

‎src/runtime/internal/atomic/asm_s390x.s

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -141,7 +141,8 @@ TEXT ·Or8(SB), NOSPLIT, $0-9
141141
MOVD ptr+0(FP), R3
142142
MOVBZ val+8(FP), R4
143143
// Calculate shift.
144-
AND $3, R3, R5
144+
MOVD R3, R5
145+
AND $3, R5
145146
XOR $3, R5 // big endian - flip direction
146147
SLD $3, R5 // MUL $8, R5
147148
SLD R5, R4
@@ -159,7 +160,8 @@ TEXT ·And8(SB), NOSPLIT, $0-9
159160
MOVD ptr+0(FP), R3
160161
MOVBZ val+8(FP), R4
161162
// Calculate shift.
162-
AND $3, R3, R5
163+
MOVD R3, R5
164+
AND $3, R5
163165
XOR $3, R5 // big endian - flip direction
164166
SLD $3, R5 // MUL $8, R5
165167
OR $-256, R4 // create 0xffffffffffffffxx

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