cmd/internal/obj/riscv: rework instruction generation

Rework instruction generation so that multiple instructions are generated
from a single obj.Prog, rather than the current approach where obj.Progs
are rewritten. This allows the original obj.Prog to remain intact, before
being converted into an architecture specific instruction form.

This simplifies the code and removes a level of indirection that results
from trying to manipulate obj.Prog.To/obj.Prog.From into forms that match
the instruction encoding. Furthermore, the errors reported make more sense
since it matches up with the actual assembly that was parsed.

Note that the CALL/JMP/JALR type sequences have not yet been migrated to
this framework and will likely be converted at a later time.

Updates #27532

Change-Id: I9fd12562ed1db0a08cfdc32793897d2a1920ebaa
Reviewed-on: https://go-review.googlesource.com/c/go/+/211917
Reviewed-by: Cherry Zhang <[email protected]>
Run-TryBot: Cherry Zhang <[email protected]>
TryBot-Result: Gobot Gobot <[email protected]>

Author: 4a6f656c

src/cmd/asm/internal/asm/testdata/riscvenc.s

@@ -290,19 +290,11 @@ start:
 
 	// F extension
 	FNEGS	F0, F1					// d3100020
-
-	// TODO(jsing): FNES gets encoded as FEQS+XORI - this should
-	// be handled as a single *obj.Prog so that the full two
-	// instruction encoding is tested here.
-	FNES	F0, F1, X7				// d3a300a0
+	FNES	F0, F1, X7				// d3a300a093c31300
 
 	// D extension
 	FNEGD	F0, F1					// d3100022
-	FEQD	F0, F1, X5				// d3a200a2
+	FNED	F0, F1, X5				// d3a200a293c21200
 	FLTD	F0, F1, X5				// d39200a2
 	FLED	F0, F1, X5				// d38200a2
-
-	// TODO(jsing): FNED gets encoded as FEQD+XORI - this should
-	// be handled as a single *obj.Prog so that the full two
-	// instruction encoding is tested here.
-	FNED	F0, F1, X5				// d3a200a2
+	FEQD	F0, F1, X5				// d3a200a2