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cmd/compile/internal/amd64: simplify code generation for signed division
The same switch statement handles code generation for signed division of words, double words and quad words. Rather than using multiple switch statements to select the appropriate instructions, determine all of the correctly sized operands up front, then use them as needed. Updates #59089 Change-Id: I2b7567c8e0ecb9904c37607332538c95b0521dca Reviewed-on: https://go-review.googlesource.com/c/go/+/482657 Run-TryBot: Joel Sing <[email protected]> Reviewed-by: Keith Randall <[email protected]> Reviewed-by: Michael Knyszek <[email protected]> Reviewed-by: Keith Randall <[email protected]> TryBot-Result: Gopher Robot <[email protected]>
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  • src/cmd/compile/internal/amd64

1 file changed

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src/cmd/compile/internal/amd64/ssa.go

Lines changed: 14 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -338,18 +338,20 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
338338
r := v.Args[1].Reg()
339339
var j1 *obj.Prog
340340

341+
var opCMP, opNEG, opSXD obj.As
342+
switch v.Op {
343+
case ssa.OpAMD64DIVQ:
344+
opCMP, opNEG, opSXD = x86.ACMPQ, x86.ANEGQ, x86.ACQO
345+
case ssa.OpAMD64DIVL:
346+
opCMP, opNEG, opSXD = x86.ACMPL, x86.ANEGL, x86.ACDQ
347+
case ssa.OpAMD64DIVW:
348+
opCMP, opNEG, opSXD = x86.ACMPW, x86.ANEGW, x86.ACWD
349+
}
350+
341351
// CPU faults upon signed overflow, which occurs when the most
342352
// negative int is divided by -1. Handle divide by -1 as a special case.
343353
if ssa.DivisionNeedsFixUp(v) {
344-
var c *obj.Prog
345-
switch v.Op {
346-
case ssa.OpAMD64DIVQ:
347-
c = s.Prog(x86.ACMPQ)
348-
case ssa.OpAMD64DIVL:
349-
c = s.Prog(x86.ACMPL)
350-
case ssa.OpAMD64DIVW:
351-
c = s.Prog(x86.ACMPW)
352-
}
354+
c := s.Prog(opCMP)
353355
c.From.Type = obj.TYPE_REG
354356
c.From.Reg = r
355357
c.To.Type = obj.TYPE_CONST
@@ -358,17 +360,8 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
358360
j1.To.Type = obj.TYPE_BRANCH
359361
}
360362

361-
// Sign extend dividend.
362-
switch v.Op {
363-
case ssa.OpAMD64DIVQ:
364-
s.Prog(x86.ACQO)
365-
case ssa.OpAMD64DIVL:
366-
s.Prog(x86.ACDQ)
367-
case ssa.OpAMD64DIVW:
368-
s.Prog(x86.ACWD)
369-
}
370-
371-
// Issue divide.
363+
// Sign extend dividend and perform division.
364+
s.Prog(opSXD)
372365
p := s.Prog(v.Op.Asm())
373366
p.From.Type = obj.TYPE_REG
374367
p.From.Reg = r
@@ -380,15 +373,7 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
380373

381374
// Issue -1 fixup code.
382375
// n / -1 = -n
383-
var n1 *obj.Prog
384-
switch v.Op {
385-
case ssa.OpAMD64DIVQ:
386-
n1 = s.Prog(x86.ANEGQ)
387-
case ssa.OpAMD64DIVL:
388-
n1 = s.Prog(x86.ANEGL)
389-
case ssa.OpAMD64DIVW:
390-
n1 = s.Prog(x86.ANEGW)
391-
}
376+
n1 := s.Prog(opNEG)
392377
n1.To.Type = obj.TYPE_REG
393378
n1.To.Reg = x86.REG_AX
394379

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