Skip to content

Commit 0f003f9

Browse files
xen0nabner-chenc
authored andcommitted
internal/cpu, runtime: make linux/loong64 HWCAP data available
This can be used to toggle runtime usages of ISA extensions as such usages appear. Only the CRC32 bit is exposed for now, as the others are not going to be utilized in the standard library for a while. Change-Id: I774032ca84dc8bcf1c9f17558917315af07c7314 Reviewed-on: https://go-review.googlesource.com/c/go/+/482416 Reviewed-by: Ian Lance Taylor <[email protected]> Reviewed-by: xiaodong liu <[email protected]> LUCI-TryBot-Result: Go LUCI <[email protected]> Reviewed-by: Dmitri Shuralyov <[email protected]> Reviewed-by: abner chenc <[email protected]>
1 parent 9e8ea56 commit 0f003f9

File tree

5 files changed

+64
-2
lines changed

5 files changed

+64
-2
lines changed

src/internal/cpu/cpu.go

+8
Original file line numberDiff line numberDiff line change
@@ -78,6 +78,14 @@ var ARM64 struct {
7878
_ CacheLinePad
7979
}
8080

81+
// The booleans in Loong64 contain the correspondingly named cpu feature bit.
82+
// The struct is padded to avoid false sharing.
83+
var Loong64 struct {
84+
_ CacheLinePad
85+
HasCRC32 bool
86+
_ CacheLinePad
87+
}
88+
8189
var MIPS64X struct {
8290
_ CacheLinePad
8391
HasMSA bool // MIPS SIMD architecture

src/internal/cpu/cpu_loong64.go

+7-1
Original file line numberDiff line numberDiff line change
@@ -10,4 +10,10 @@ package cpu
1010
// We choose 64 because Loongson 3A5000 the L1 Dcache is 4-way 256-line 64-byte-per-line.
1111
const CacheLinePadSize = 64
1212

13-
func doinit() {}
13+
func doinit() {
14+
options = []option{
15+
{Name: "crc32", Feature: &Loong64.HasCRC32},
16+
}
17+
18+
osInit()
19+
}

src/internal/cpu/cpu_loong64_hwcap.go

+30
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,30 @@
1+
// Copyright 2023 The Go Authors. All rights reserved.
2+
// Use of this source code is governed by a BSD-style
3+
// license that can be found in the LICENSE file.
4+
5+
//go:build loong64 && linux
6+
7+
package cpu
8+
9+
// This is initialized by archauxv and should not be changed after it is
10+
// initialized.
11+
var HWCap uint
12+
13+
// HWCAP bits. These are exposed by the Linux kernel.
14+
const (
15+
hwcap_LOONGARCH_CRC32 = 1 << 6
16+
)
17+
18+
func hwcapInit() {
19+
// It is not taken from CPUCFG data regardless of availability of
20+
// CPUCFG, because the CPUCFG data only reflects capabilities of the
21+
// hardware, but not kernel support.
22+
//
23+
// As of 2023, we do not know for sure if the CPUCFG data can be
24+
// patched in software, nor does any known LoongArch kernel do that.
25+
Loong64.HasCRC32 = isSet(HWCap, hwcap_LOONGARCH_CRC32)
26+
}
27+
28+
func isSet(hwc uint, value uint) bool {
29+
return hwc&value != 0
30+
}

src/internal/cpu/cpu_loong64_linux.go

+11
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,11 @@
1+
// Copyright 2023 The Go Authors. All rights reserved.
2+
// Use of this source code is governed by a BSD-style
3+
// license that can be found in the LICENSE file.
4+
5+
//go:build loong64 && linux
6+
7+
package cpu
8+
9+
func osInit() {
10+
hwcapInit()
11+
}

src/runtime/os_linux_loong64.go

+8-1
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,13 @@
66

77
package runtime
88

9-
func archauxv(tag, val uintptr) {}
9+
import "internal/cpu"
10+
11+
func archauxv(tag, val uintptr) {
12+
switch tag {
13+
case _AT_HWCAP:
14+
cpu.HWCap = uint(val)
15+
}
16+
}
1017

1118
func osArchInit() {}

0 commit comments

Comments
 (0)