add tft pins

Author: brentru

variants/pybadge_airlift_m4/variant.cpp

@@ -98,7 +98,7 @@ const PinDescription g_APinDescription[] =
 
         // 41..46 - TFT SPI port + control pins
         // --------------------
-        {PORTB, 15, PIO_DIGITAL, PIN_ATTR_PWM_F, No_ADC_Channel, TCC4_CH1, TC5_CH1, EXTERNAL_INT_15}, // MOSI
+        {PORTB, 15, PIO_SERCOM, PIN_ATTR_PWM_F, No_ADC_Channel, TCC4_CH1, TC5_CH1, EXTERNAL_INT_15},         // SERCOM 4.3 MOSI
         {PORTB, 13, PIO_SERCOM, PIN_ATTR_DIGITAL, No_ADC_Channel, NOT_ON_PWM, NOT_ON_TIMER, EXTERNAL_INT_13}, // SERCOM 4.1 SCK
         {PORTB, 12, PIO_SERCOM, PIN_ATTR_DIGITAL, No_ADC_Channel, NOT_ON_PWM, NOT_ON_TIMER, EXTERNAL_INT_12}, // SERCOM 4.0 'miso' (NC)
         {PORTB, 6, PIO_OUTPUT, PIN_ATTR_DIGITAL, No_ADC_Channel, NOT_ON_PWM, NOT_ON_TIMER, EXTERNAL_INT_6},   // D44 TFT CS
@@ -118,8 +118,8 @@ const PinDescription g_APinDescription[] =
 
         // ESP GPIO0, BUSY, RESET (52-54)
         {PORTA, 31, PIO_DIGITAL, PIN_ATTR_NONE, No_ADC_Channel, NOT_ON_PWM, NOT_ON_TIMER, EXTERNAL_INT_NONE}, // D52 ESP32_GPIO0
-        {PORTA, 0, PIO_DIGITAL, PIN_ATTR_PWM_E, No_ADC_Channel, TC2_CH0, TC2_CH0, EXTERNAL_INT_0}, // D53 ESP32_BUSY
-        {PORTB, 12, PIO_DIGITAL, PIN_ATTR_PWM_F, No_ADC_Channel, TCC3_CH0, TC4_CH0, EXTERNAL_INT_12}, // D54 ESP32_RESET
+        {PORTA, 0, PIO_DIGITAL, PIN_ATTR_PWM_E, No_ADC_Channel, TC2_CH0, TC2_CH0, EXTERNAL_INT_0},            // D53 ESP32_BUSY
+        {PORTB, 12, PIO_DIGITAL, PIN_ATTR_PWM_F, No_ADC_Channel, TCC3_CH0, TC4_CH0, EXTERNAL_INT_12},         // D54 ESP32_RESET 
 
 };
 

variants/pybadge_airlift_m4/variant.h

@@ -163,9 +163,9 @@ static const uint8_t MISO = PIN_SPI_MISO ;
 static const uint8_t SCK  = PIN_SPI_SCK ;
 
 // Internal SPI for TFT
-#define PIN_SPI1_MOSI         (23u)
-#define PIN_SPI1_SCK          (13u)
-#define PIN_SPI1_MISO         (12u)
+#define PIN_SPI1_MOSI         (41u)
+#define PIN_SPI1_SCK          (42u)
+#define PIN_SPI1_MISO         (43u)
 #define PERIPH_SPI1           sercom4
 #define PAD_SPI1_TX           SPI_PAD_3_SCK_1
 #define PAD_SPI1_RX           SERCOM_RX_PAD_0