@@ -7389,7 +7389,7 @@ inline void ggml_cuda_op_mul_mat_cublas(
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const int compute_capability = g_compute_capabilities[id];
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- if (compute_capability >= CC_VOLTA && (src0->type == GGML_TYPE_F16 || ggml_is_quantized(src0->type)) && ggml_is_contiguous(src0) && row_diff == src0->ne[1] && dst->op_params[0] == GGML_PREC_DEFAULT ) {
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+ if (compute_capability >= CC_VOLTA && (src0->type == GGML_TYPE_F16 || ggml_is_quantized(src0->type)) && ggml_is_contiguous(src0) && row_diff == src0->ne[1]) {
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// convert src0 and src1 to fp16, multiply as fp16, convert dst to fp32
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half * src0_as_f16 = nullptr;
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size_t src0_as = 0;
@@ -7412,26 +7412,47 @@ inline void ggml_cuda_op_mul_mat_cublas(
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to_fp16_cuda(src1_ddf_i, src1_as_f16, ne, stream);
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}
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const half * src1_ptr = src1->type == GGML_TYPE_F16 ? (const half *) src1_ddf_i : src1_as_f16;
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- size_t dst_as = 0;
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- half * dst_f16 = (half *) ggml_cuda_pool_malloc(row_diff*src1_ncols * sizeof(half), &dst_as);
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- const half alpha_f16 = 1.0f;
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- const half beta_f16 = 0.0f;
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-
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- CUBLAS_CHECK(cublasSetStream(g_cublas_handles[id], stream));
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- CUBLAS_CHECK(
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- cublasGemmEx(g_cublas_handles[id], CUBLAS_OP_T, CUBLAS_OP_N,
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- row_diff, src1_ncols, ne10,
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- &alpha_f16, src0_ptr, CUDA_R_16F, ne00,
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- src1_ptr, CUDA_R_16F, ne10,
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- &beta_f16, dst_f16, CUDA_R_16F, ldc,
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- CUBLAS_COMPUTE_16F,
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- CUBLAS_GEMM_DEFAULT_TENSOR_OP));
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-
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- const to_fp32_cuda_t to_fp32_cuda = ggml_get_to_fp32_cuda(GGML_TYPE_F16);
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- to_fp32_cuda(dst_f16, dst_dd_i, row_diff*src1_ncols, stream);
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-
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- ggml_cuda_pool_free(dst_f16, dst_as);
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+ switch (dst->op_params[0]) {
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+ case GGML_PREC_DEFAULT:
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+ {
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+ size_t dst_as = 0;
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+ half * dst_f16 = (half *) ggml_cuda_pool_malloc(row_diff*src1_ncols * sizeof(half), &dst_as);
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+
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+ const half alpha_f16 = 1.0f;
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+ const half beta_f16 = 0.0f;
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+
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+ CUBLAS_CHECK(cublasSetStream(g_cublas_handles[id], stream));
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+ CUBLAS_CHECK(
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+ cublasGemmEx(g_cublas_handles[id], CUBLAS_OP_T, CUBLAS_OP_N,
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+ row_diff, src1_ncols, ne10,
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+ &alpha_f16, src0_ptr, CUDA_R_16F, ne00,
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+ src1_ptr, CUDA_R_16F, ne10,
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+ &beta_f16, dst_f16, CUDA_R_16F, ldc,
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+ CUBLAS_COMPUTE_16F,
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+ CUBLAS_GEMM_DEFAULT_TENSOR_OP));
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+
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+ const to_fp32_cuda_t to_fp32_cuda = ggml_get_to_fp32_cuda(GGML_TYPE_F16);
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+ to_fp32_cuda(dst_f16, dst_dd_i, row_diff*src1_ncols, stream);
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+
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+ ggml_cuda_pool_free(dst_f16, dst_as);
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+ } break;
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+ case GGML_PREC_F32:
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+ {
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+ const float alpha_f32 = 1.0f;
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+ const float beta_f32 = 0.0f;
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+
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+ CUBLAS_CHECK(cublasSetStream(g_cublas_handles[id], stream));
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+ CUBLAS_CHECK(
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+ cublasGemmEx(g_cublas_handles[id], CUBLAS_OP_T, CUBLAS_OP_N,
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+ row_diff, src1_ncols, ne10,
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+ &alpha_f32, src0_ptr, CUDA_R_16F, ne00,
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+ src1_ptr, CUDA_R_16F, ne10,
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+ &beta_f32, dst_dd_i, CUDA_R_32F, ldc,
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+ CUBLAS_COMPUTE_32F,
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+ CUBLAS_GEMM_DEFAULT_TENSOR_OP));
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+ } break;
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+ }
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if (src0_as != 0) {
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ggml_cuda_pool_free(src0_as_f16, src0_as);
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