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[Xtensa] Added SR registers.
Closes #15
1 parent da01845 commit 654ba11

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2 files changed

+118
-43
lines changed

2 files changed

+118
-43
lines changed

‎llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp‎

Lines changed: 34 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -108,16 +108,40 @@ static DecodeStatus DecodeBRRegisterClass(MCInst &Inst, uint64_t RegNo,
108108
}
109109

110110
static const unsigned SRDecoderTable[] = {
111-
Xtensa::SAR, 3, Xtensa::SCOMPARE1, 12, Xtensa::IBREAKENABLE, 96,
112-
Xtensa::MEMCTL, 97, Xtensa::IBREAKA0, 128, Xtensa::IBREAKA1, 129,
113-
Xtensa::DBREAKA0, 144, Xtensa::DBREAKA1, 145, Xtensa::DBREAKC0, 160,
114-
Xtensa::DBREAKC1, 161, Xtensa::CONFIGID0, 176, Xtensa::CONFIGID1, 208,
115-
Xtensa::EPC1, 177, Xtensa::EPC2, 178, Xtensa::EPC3, 179,
116-
Xtensa::EPC4, 180, Xtensa::EPC5, 181, Xtensa::EPC6, 182,
117-
Xtensa::EPC7, 183, Xtensa::INTSET, 226, Xtensa::INTENABLE, 228,
118-
Xtensa::PS, 230, Xtensa::VECBASE, 231, Xtensa::DEBUGCAUSE, 233,
119-
Xtensa::CCOUNT, 234, Xtensa::PRID, 235, Xtensa::CCOMPARE0, 240,
120-
Xtensa::CCOMPARE1, 241, Xtensa::CCOMPARE2, 242};
111+
Xtensa::LBEG, 0, Xtensa::LEND, 1,
112+
Xtensa::LCOUNT, 2, Xtensa::SAR, 3,
113+
Xtensa::BREG, 4, Xtensa::LITBASE, 5,
114+
Xtensa::SCOMPARE1, 12, Xtensa::ACCLO, 16,
115+
Xtensa::ACCHI, 17, Xtensa::M0, 32,
116+
Xtensa::M1, 33, Xtensa::M2, 34,
117+
Xtensa::M2, 35, Xtensa::WINDOWBASE, 72,
118+
Xtensa::WINDOWSTART, 73, Xtensa::IBREAKENABLE, 96,
119+
Xtensa::MEMCTL, 97, Xtensa::ATOMCTL, 99,
120+
Xtensa::DDR, 104, Xtensa::IBREAKA0, 128,
121+
Xtensa::IBREAKA1, 129, Xtensa::DBREAKA0, 144,
122+
Xtensa::DBREAKA1, 145, Xtensa::DBREAKC0, 160,
123+
Xtensa::DBREAKC1, 161, Xtensa::CONFIGID0, 176,
124+
Xtensa::EPC1, 177, Xtensa::EPC2, 178,
125+
Xtensa::EPC3, 179, Xtensa::EPC4, 180,
126+
Xtensa::EPC5, 181, Xtensa::EPC6, 182,
127+
Xtensa::EPC7, 183, Xtensa::DEPC, 192,
128+
Xtensa::EPS2, 194, Xtensa::EPS3, 195,
129+
Xtensa::EPS4, 196, Xtensa::EPS5, 197,
130+
Xtensa::EPS6, 198, Xtensa::EPS7, 199,
131+
Xtensa::CONFIGID1, 208, Xtensa::EXCSAVE1, 209,
132+
Xtensa::EXCSAVE2, 210, Xtensa::EXCSAVE3, 211,
133+
Xtensa::EXCSAVE4, 212, Xtensa::EXCSAVE5, 213,
134+
Xtensa::EXCSAVE6, 214, Xtensa::EXCSAVE7, 215,
135+
Xtensa::CPENABLE, 224, Xtensa::INTSET, 226,
136+
Xtensa::INTENABLE, 228, Xtensa::PS, 230,
137+
Xtensa::VECBASE, 231, Xtensa::EXCCAUSE, 232,
138+
Xtensa::DEBUGCAUSE, 233, Xtensa::CCOUNT, 234,
139+
Xtensa::PRID, 235, Xtensa::ICOUNT, 236,
140+
Xtensa::ICOUNTLEVEL, 237, Xtensa::EXCVADDR, 238,
141+
Xtensa::CCOMPARE0, 240, Xtensa::CCOMPARE1, 241,
142+
Xtensa::CCOMPARE2, 242, Xtensa::MISC0, 244,
143+
Xtensa::MISC1, 245, Xtensa::MISC2, 246,
144+
Xtensa::MISC3, 247};
121145

122146
static DecodeStatus DecodeSRRegisterClass(MCInst &Inst, uint64_t RegNo,
123147
uint64_t Address,

‎llvm/lib/Target/Xtensa/XtensaRegisterInfo.td‎

Lines changed: 84 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -72,93 +72,144 @@ class SRReg<bits<8> num, string n, list<string> alt = []> : XtensaReg<n> {
7272
let AltNames = alt;
7373
}
7474

75+
76+
def LBEG : SRReg<0, "lbeg", ["LBEG", "0"]>;
77+
def LEND : SRReg<1, "lend", ["LEND", "1"]>;
78+
def LCOUNT : SRReg<2, "lcount", ["LCOUNT", "2"]>;
79+
7580
// Shift Amount Register
76-
def SAR : SRReg<3, "sar", ["SAR","3"]>;
81+
def SAR : SRReg<3, "sar", ["SAR", "3"]>;
82+
83+
def BREG : SRReg<4, "br", ["BR", "4"]>;
84+
def LITBASE : SRReg<5, "litbase", ["LITBASE", "5"]>;
7785

7886
// Expected data value for S32C1I operation
79-
def SCOMPARE1 : SRReg<12, "scompare1", ["SCOMPARE1"]>;
87+
def SCOMPARE1 : SRReg<12, "scompare1", ["SCOMPARE1", "12"]>;
88+
89+
def ACCLO : SRReg<16, "acclo", ["ACCLO", "16"]>;
90+
def ACCHI : SRReg<17, "acchi", ["ACCHI", "17"]>;
91+
def M0 : SRReg<32, "m0", ["M0", "32"]>;
92+
def M1 : SRReg<33, "m1", ["M1", "33"]>;
93+
def M2 : SRReg<34, "m2", ["M2", "34"]>;
94+
def M3 : SRReg<35, "m3", ["M3", "35"]>;
95+
def WINDOWBASE : SRReg<72, "windowbase", ["WINDOWBASE", "72"]>;
96+
def WINDOWSTART : SRReg<73, "windowstart", ["WINDOWSTART", "73"]>;
8097

8198
// Instuction breakpoint enable register
82-
def IBREAKENABLE : SRReg<96, "ibreakenable", ["IBREAKENABLE"]>;
99+
def IBREAKENABLE : SRReg<96, "ibreakenable", ["IBREAKENABLE", "96"]>;
83100

84101
// Memory Control Register
85-
def MEMCTL : SRReg<97, "memctl", ["MEMCTL"]>;
102+
def MEMCTL : SRReg<97, "memctl", ["MEMCTL", "97"]>;
103+
104+
def ATOMCTL : SRReg<99, "atomctl", ["ATOMCTL", "99"]>;
105+
def DDR : SRReg<104, "ddr", ["DDR", "104"]>;
86106

87107
// Instuction break address register 0
88-
def IBREAKA0 : SRReg<128, "ibreaka0", ["IBREAKA0"]>;
108+
def IBREAKA0 : SRReg<128, "ibreaka0", ["IBREAKA0", "128"]>;
89109

90110
// Instuction break address register 1
91-
def IBREAKA1 : SRReg<129, "ibreaka1", ["IBREAKA1"]>;
111+
def IBREAKA1 : SRReg<129, "ibreaka1", ["IBREAKA1", "129"]>;
92112

93113
// Data break address register 0
94-
def DBREAKA0 : SRReg<144, "dbreaka0", ["DBREAKA0"]>;
114+
def DBREAKA0 : SRReg<144, "dbreaka0", ["DBREAKA0", "144"]>;
95115

96116
// Data break address register 1
97-
def DBREAKA1 : SRReg<145, "dbreaka1", ["DBREAKA1"]>;
117+
def DBREAKA1 : SRReg<145, "dbreaka1", ["DBREAKA1", "145"]>;
98118

99119
// Data breakpoint control register 0
100-
def DBREAKC0 : SRReg<160, "dbreakc0", ["DBREAKC0"]>;
120+
def DBREAKC0 : SRReg<160, "dbreakc0", ["DBREAKC0", "160"]>;
101121

102122
// Data breakpoint control register 1
103-
def DBREAKC1 : SRReg<161, "dbreakc1", ["DBREAKC1"]>;
123+
def DBREAKC1 : SRReg<161, "dbreakc1", ["DBREAKC1", "161"]>;
104124

105-
def CONFIGID0 : SRReg<176, "configid0", ["CONFIGID0"]>;
125+
def CONFIGID0 : SRReg<176, "configid0", ["CONFIGID0", "176"]>;
106126

107127
// Exception PC1
108-
def EPC1 : SRReg<177, "epc1", ["EPC1"]>;
128+
def EPC1 : SRReg<177, "epc1", ["EPC1", "177"]>;
109129

110130
// Exception PC2
111-
def EPC2 : SRReg<178, "epc2", ["EPC2"]>;
131+
def EPC2 : SRReg<178, "epc2", ["EPC2", "178"]>;
112132

113133
// Exception PC3
114-
def EPC3 : SRReg<179, "epc3", ["EPC3"]>;
134+
def EPC3 : SRReg<179, "epc3", ["EPC3", "179"]>;
115135

116136
// Exception PC4
117-
def EPC4 : SRReg<180, "epc4", ["EPC4"]>;
137+
def EPC4 : SRReg<180, "epc4", ["EPC4", "180"]>;
118138

119139
// Exception PC5
120-
def EPC5 : SRReg<181, "epc5", ["EPC5"]>;
140+
def EPC5 : SRReg<181, "epc5", ["EPC5", "181"]>;
121141

122142
// Exception PC6
123-
def EPC6 : SRReg<182, "epc6", ["EPC6"]>;
143+
def EPC6 : SRReg<182, "epc6", ["EPC6", "182"]>;
124144

125145
// Exception PC7
126-
def EPC7 : SRReg<183, "epc7", ["EPC7"]>;
127-
128-
def CONFIGID1 : SRReg<208, "configid1", ["CONFIGID1"]>;
146+
def EPC7 : SRReg<183, "epc7", ["EPC7", "183"]>;
147+
148+
def DEPC : SRReg<192, "depc", ["DEPC", "192"]>;
149+
def EPS2 : SRReg<194, "eps2", ["EPS2", "194"]>;
150+
def EPS3 : SRReg<195, "eps3", ["EPS3", "195"]>;
151+
def EPS4 : SRReg<196, "eps4", ["EPS4", "196"]>;
152+
def EPS5 : SRReg<197, "eps5", ["EPS5", "197"]>;
153+
def EPS6 : SRReg<198, "eps6", ["EPS6", "198"]>;
154+
def EPS7 : SRReg<199, "eps7", ["EPS7", "199"]>;
155+
def CONFIGID1 : SRReg<208, "configid1", ["CONFIGID1", "208"]>;
156+
def EXCSAVE1 : SRReg<209, "excsave1", ["EXCSAVE1", "209"]>;
157+
def EXCSAVE2 : SRReg<210, "excsave2", ["EXCSAVE2", "210"]>;
158+
def EXCSAVE3 : SRReg<211, "excsave3", ["EXCSAVE3", "211"]>;
159+
def EXCSAVE4 : SRReg<212, "excsave4", ["EXCSAVE4", "212"]>;
160+
def EXCSAVE5 : SRReg<213, "excsave5", ["EXCSAVE5", "213"]>;
161+
def EXCSAVE6 : SRReg<214, "excsave6", ["EXCSAVE6", "214"]>;
162+
def EXCSAVE7 : SRReg<215, "excsave7", ["EXCSAVE7", "215"]>;
163+
def CPENABLE : SRReg<224, "cpenable", ["CPENABLE", "224"]>;
129164

130165
// Interrupt enable mask register
131-
def INTSET : SRReg<226, "intset", ["INTSET"]>;
166+
def INTSET : SRReg<226, "interrupt", ["INTERRUPT", "226"]>;
132167

133-
// Interrupt enable mask register
134-
def INTENABLE : SRReg<228, "intenable", ["INTENABLE"]>;
168+
def INTENABLE : SRReg<228, "intenable", ["INTENABLE", "228"]>;
135169

136170
// Processor State
137171
def PS : SRReg<230, "ps", ["PS", "230"]>;
138172

139173
// Vector base register
140-
def VECBASE : SRReg<231, "vecbase", ["VECBASE"]>;
174+
def VECBASE : SRReg<231, "vecbase", ["VECBASE", "231"]>;
175+
176+
def EXCCAUSE : SRReg<232, "exccause", ["EXCCAUSE", "232"]>;
141177

142178
// Cause of last debug exception register
143-
def DEBUGCAUSE : SRReg<233, "debugcause", ["DEBUGCAUSE"]>;
179+
def DEBUGCAUSE : SRReg<233, "debugcause", ["DEBUGCAUSE", "233"]>;
144180

145181
// Processor Clock Count Register
146-
def CCOUNT : SRReg<234, "ccount", ["CCOUNT"]>;
182+
def CCOUNT : SRReg<234, "ccount", ["CCOUNT", "234"]>;
147183

148184
// Processor ID Register
149-
def PRID : SRReg<235, "prid", ["PRID"]>;
185+
def PRID : SRReg<235, "prid", ["PRID", "235"]>;
186+
187+
def ICOUNT : SRReg<236, "icount", ["ICOUNT", "236"]>;
188+
def ICOUNTLEVEL : SRReg<237, "icountlevel", ["ICOUNTLEVEL", "237"]>;
189+
def EXCVADDR : SRReg<238, "excvaddr", ["EXCVADDR", "238"]>;
150190

151191
// Cycle number to interrupt register 0
152-
def CCOMPARE0 : SRReg<240, "ccompare0", ["CCOMPARE0"]>;
192+
def CCOMPARE0 : SRReg<240, "ccompare0", ["CCOMPARE0", "240"]>;
153193

154194
// Cycle number to interrupt register 1
155-
def CCOMPARE1 : SRReg<241, "ccompare1", ["CCOMPARE1"]>;
195+
def CCOMPARE1 : SRReg<241, "ccompare1", ["CCOMPARE1", "241"]>;
156196

157197
// Cycle number to interrupt register 2
158-
def CCOMPARE2 : SRReg<242, "ccompare2", ["CCOMPARE2"]>;
159-
160-
def SR : RegisterClass<"Xtensa", [i32], 32, (add SAR, SCOMPARE1, IBREAKENABLE, MEMCTL, IBREAKA0, IBREAKA1, DBREAKA0, DBREAKA1,
161-
DBREAKC0, DBREAKC1, CONFIGID0, CONFIGID1, EPC1, EPC2, EPC3, EPC4, EPC5, EPC6, EPC7, INTSET, INTENABLE, PS, VECBASE, DEBUGCAUSE, CCOUNT, PRID, CCOMPARE0, CCOMPARE1, CCOMPARE2)>;
198+
def CCOMPARE2 : SRReg<242, "ccompare2", ["CCOMPARE2", "242"]>;
199+
200+
def MISC0 : SRReg<244, "misc0", ["MISC0", "244"]>;
201+
def MISC1 : SRReg<245, "misc1", ["MISC1", "245"]>;
202+
def MISC2 : SRReg<246, "misc2", ["MISC2", "246"]>;
203+
def MISC3 : SRReg<247, "misc3", ["MISC3", "247"]>;
204+
205+
def SR : RegisterClass<"Xtensa", [i32], 32, (add
206+
LBEG, LEND, LCOUNT, SAR, BREG, LITBASE, SCOMPARE1, ACCLO, ACCHI, M0, M1, M2, M3,
207+
WINDOWBASE, WINDOWSTART, IBREAKENABLE, MEMCTL, ATOMCTL, DDR, IBREAKA0, IBREAKA1,
208+
DBREAKA0, DBREAKA1, DBREAKC0, DBREAKC1, CONFIGID0, EPC1, EPC2, EPC3, EPC4, EPC5,
209+
EPC6, EPC7, DEPC, EPS2, EPS3, EPS4, EPS5, EPS6, EPS7, CONFIGID1, EXCSAVE1, EXCSAVE2,
210+
EXCSAVE3, EXCSAVE4, EXCSAVE5, EXCSAVE6, EXCSAVE7, CPENABLE, INTSET, INTENABLE, PS,
211+
VECBASE, EXCCAUSE, DEBUGCAUSE, CCOUNT, PRID, ICOUNT, ICOUNTLEVEL, EXCVADDR, CCOMPARE0,
212+
CCOMPARE1, CCOMPARE2, MISC0, MISC1, MISC2, MISC3)>;
162213

163214
//===----------------------------------------------------------------------===//
164215
// USER registers

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