diff --git a/.gitignore b/.gitignore index 99966711..e18dc002 100644 --- a/.gitignore +++ b/.gitignore @@ -1,5 +1,5 @@ /target **/*.rs.bk Cargo.lock -svd/esp32.svd +#svd/esp32.svd src/ diff --git a/Cargo.toml b/Cargo.toml index c2048e99..4c0e9493 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -1,6 +1,6 @@ [package] name = "esp32" -version = "0.2.2" +version = "0.3.0" authors = ["Scott Mabin "] edition = "2018" readme = "README.md" @@ -21,4 +21,10 @@ license = "MIT OR Apache-2.0" [dependencies] bare-metal = "0.2" -vcell = "0.1" \ No newline at end of file +vcell = "0.1" +xtensa-lx6-rt = { git = "https://github.com/esp-rs/xtensa-lx6-rt.git" } + +[features] +default=["rt"] + +rt=[] diff --git a/Makefile b/Makefile index 2f225af8..f1218225 100644 --- a/Makefile +++ b/Makefile @@ -12,7 +12,7 @@ patch: mv svd/$(BASE).patched svd/$(OUTPUT) generate: - svd2rust --target none -i svd/$(OUTPUT) + svd2rust --target esp32 -i svd/$(OUTPUT) form: form -i lib.rs -o src/ @@ -23,4 +23,4 @@ fmt: build: cargo clean - cargo build + cargo xbuild --target xtensa-esp32-none-elf diff --git a/build.rs b/build.rs new file mode 100644 index 00000000..597923f5 --- /dev/null +++ b/build.rs @@ -0,0 +1,16 @@ +use std::env; +use std::fs::File; +use std::io::Write; +use std::path::PathBuf; +fn main() { + if env::var_os("CARGO_FEATURE_RT").is_some() { + let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); + File::create(out.join("device.x")) + .unwrap() + .write_all(include_bytes!("device.x")) + .unwrap(); + println!("cargo:rustc-link-search={}", out.display()); + println!("cargo:rerun-if-changed=device.x"); + } + println!("cargo:rerun-if-changed=build.rs"); +} diff --git a/device.x b/device.x new file mode 100644 index 00000000..c772ba7b --- /dev/null +++ b/device.x @@ -0,0 +1,76 @@ +PROVIDE(WIFI_MAC_INTR = DefaultHandler); +PROVIDE(WIFI_MAC_NMI = DefaultHandler); +PROVIDE(WIFI_BB_INTR = DefaultHandler); +PROVIDE(BT_MAC_INTR = DefaultHandler); +PROVIDE(BT_BB_INTR = DefaultHandler); +PROVIDE(BT_BB_NMI = DefaultHandler); +PROVIDE(RWBT_INTR = DefaultHandler); +PROVIDE(RWBLE_INTR = DefaultHandler); +PROVIDE(RWBT_NMI = DefaultHandler); +PROVIDE(RWBLE_NMI = DefaultHandler); +PROVIDE(SLC0_INTR = DefaultHandler); +PROVIDE(SLC1_INTR = DefaultHandler); +PROVIDE(UHCI0_INTR = DefaultHandler); +PROVIDE(UHCI1_INTR = DefaultHandler); +PROVIDE(TG0_T0_LEVEL_INTR = DefaultHandler); +PROVIDE(TG0_T1_LEVEL_INTR = DefaultHandler); +PROVIDE(TG0_WDT_LEVEL_INTR = DefaultHandler); +PROVIDE(TG0_LACT_LEVEL_INTR = DefaultHandler); +PROVIDE(TG1_T0_LEVEL_INTR = DefaultHandler); +PROVIDE(TG1_T1_LEVEL_INTR = DefaultHandler); +PROVIDE(TG1_WDT_LEVEL_INTR = DefaultHandler); +PROVIDE(TG1_LACT_LEVEL_INTR = DefaultHandler); +PROVIDE(GPIO_INTR = DefaultHandler); +PROVIDE(GPIO_NMI = DefaultHandler); +PROVIDE(FROM_CPU_INTR0 = DefaultHandler); +PROVIDE(FROM_CPU_INTR1 = DefaultHandler); +PROVIDE(FROM_CPU_INTR2 = DefaultHandler); +PROVIDE(FROM_CPU_INTR3 = DefaultHandler); +PROVIDE(SPI0_INTR = DefaultHandler); +PROVIDE(SPI1_INTR = DefaultHandler); +PROVIDE(SPI2_INTR = DefaultHandler); +PROVIDE(SPI3_INTR = DefaultHandler); +PROVIDE(I2S0_INTR = DefaultHandler); +PROVIDE(I2S1_INTR = DefaultHandler); +PROVIDE(UART0_INTR = DefaultHandler); +PROVIDE(UART1_INTR = DefaultHandler); +PROVIDE(UART2_INTR = DefaultHandler); +PROVIDE(SDIO_HOST_INTR = DefaultHandler); +PROVIDE(ETH_MAC_INTR = DefaultHandler); +PROVIDE(PWM0_INTR = DefaultHandler); +PROVIDE(PWM1_INTR = DefaultHandler); +PROVIDE(PWM2_INTR = DefaultHandler); +PROVIDE(PWM3_INTR = DefaultHandler); +PROVIDE(LEDC_INTR = DefaultHandler); +PROVIDE(EFUSE_INTR = DefaultHandler); +PROVIDE(CAN_INTR = DefaultHandler); +PROVIDE(RTC_CORE_INTR = DefaultHandler); +PROVIDE(RMT_INTR = DefaultHandler); +PROVIDE(PCNT_INTR = DefaultHandler); +PROVIDE(I2C_EXT0_INTR = DefaultHandler); +PROVIDE(I2C_EXT1_INTR = DefaultHandler); +PROVIDE(RSA_INTR = DefaultHandler); +PROVIDE(SPI1_DMA_INTR = DefaultHandler); +PROVIDE(SPI2_DMA_INTR = DefaultHandler); +PROVIDE(SPI3_DMA_INTR = DefaultHandler); +PROVIDE(WDT_INTR = DefaultHandler); +PROVIDE(TIMER1_INTR = DefaultHandler); +PROVIDE(TIMER2_INTR = DefaultHandler); +PROVIDE(TG0_T0_EDGE_INTR = DefaultHandler); +PROVIDE(TG0_T1_EDGE_INTR = DefaultHandler); +PROVIDE(TG0_WDT_EDGE_INTR = DefaultHandler); +PROVIDE(TG0_LACT_EDGE_INTR = DefaultHandler); +PROVIDE(TG1_T0_EDGE_INTR = DefaultHandler); +PROVIDE(TG1_T1_EDGE_INTR = DefaultHandler); +PROVIDE(TG1_WDT_EDGE_INTR = DefaultHandler); +PROVIDE(TG1_LACT_EDGE_INTR = DefaultHandler); +PROVIDE(MMU_IA_INTR = DefaultHandler); +PROVIDE(MPU_IA_INTR = DefaultHandler); +PROVIDE(CACHE_IA_INTR = DefaultHandler); +PROVIDE(INTERNAL_TIMER0_INTR = DefaultHandler); +PROVIDE(INTERNAL_SOFTWARE_LEVEL_1_INTR = DefaultHandler); +PROVIDE(INTERNAL_PROFILING_INTR = DefaultHandler); +PROVIDE(INTERNAL_TIMER1_INTR = DefaultHandler); +PROVIDE(INTERNAL_TIMER2_INTR = DefaultHandler); +PROVIDE(INTERNAL_SOFTWARE_LEVEL_3_INTR = DefaultHandler); + diff --git a/svd/esp32.svd b/svd/esp32.svd new file mode 100644 index 00000000..66863c18 --- /dev/null +++ b/svd/esp32.svd @@ -0,0 +1,47619 @@ + + Espressif + 1.0 + 32 + + Xtensa LX6 + 1 + little + false + true + 3 + false + + + + AES + 0x3ff01000 + + 0 + 0x00000000 + registers + + + + + HINF + 0x3ff4b000 + + 0 + 0x000001a0 + registers + + + + CFG_DATA0 + 0x0 + HINF_CFG_DATA0 + 32 + 0x00000000 + + + DEVICE_ID_FN1 + 16 + 16 + + + USER_ID_FN1 + 0 + 16 + + + + + CFG_DATA1 + 0x4 + HINF_CFG_DATA1 + 32 + 0x00000000 + + + SDIO20_CONF1 + 29 + 3 + + + FUNC2_EPS + 28 + 1 + + + SDIO_VER + 16 + 12 + + + SDIO20_CONF0 + 12 + 4 + + + IOENABLE1 + 11 + 1 + + + EMP + 10 + 1 + + + FUNC1_EPS + 9 + 1 + + + CD_DISABLE + 8 + 1 + + + IOENABLE2 + 7 + 1 + + + SDIO_INT_MASK + 6 + 1 + + + SDIO_IOREADY2 + 5 + 1 + + + SDIO_CD_ENABLE + 4 + 1 + + + HIGHSPEED_MODE + 3 + 1 + + + HIGHSPEED_ENABLE + 2 + 1 + + + SDIO_IOREADY1 + 1 + 1 + + + SDIO_ENABLE + 0 + 1 + + + + + CFG_DATA7 + 0x1c + HINF_CFG_DATA7 + 32 + 0x00000000 + + + SDIO_IOREADY0 + 17 + 1 + + + SDIO_RST + 16 + 1 + + + CHIP_STATE + 8 + 8 + + + PIN_STATE + 0 + 8 + + + + + CIS_CONF0 + 0x20 + HINF_CIS_CONF0 + 32 + 0x00000000 + + + CIS_CONF_W0 + 0 + 32 + + + + + CIS_CONF1 + 0x24 + HINF_CIS_CONF1 + 32 + 0x00000000 + + + CIS_CONF_W1 + 0 + 32 + + + + + CIS_CONF2 + 0x28 + HINF_CIS_CONF2 + 32 + 0x00000000 + + + CIS_CONF_W2 + 0 + 32 + + + + + CIS_CONF3 + 0x2c + HINF_CIS_CONF3 + 32 + 0x00000000 + + + CIS_CONF_W3 + 0 + 32 + + + + + CIS_CONF4 + 0x30 + HINF_CIS_CONF4 + 32 + 0x00000000 + + + CIS_CONF_W4 + 0 + 32 + + + + + CIS_CONF5 + 0x34 + HINF_CIS_CONF5 + 32 + 0x00000000 + + + CIS_CONF_W5 + 0 + 32 + + + + + CIS_CONF6 + 0x38 + HINF_CIS_CONF6 + 32 + 0x00000000 + + + CIS_CONF_W6 + 0 + 32 + + + + + CIS_CONF7 + 0x3c + HINF_CIS_CONF7 + 32 + 0x00000000 + + + CIS_CONF_W7 + 0 + 32 + + + + + CFG_DATA16 + 0x40 + HINF_CFG_DATA16 + 32 + 0x00000000 + + + DEVICE_ID_FN2 + 16 + 16 + + + USER_ID_FN2 + 0 + 16 + + + + + DATE + 0xfc + HINF_DATE + 32 + 0x00000000 + + + SDIO_DATE + 0 + 32 + + + + + + + SPI + 0x0 + + 0 + 0x00000860 + registers + + + + CMD + 0x0 + SPI_CMD + 32 + 0x00000000 + + + FLASH_READ + 31 + 1 + + + FLASH_WREN + 30 + 1 + + + FLASH_WRDI + 29 + 1 + + + FLASH_RDID + 28 + 1 + + + FLASH_RDSR + 27 + 1 + + + FLASH_WRSR + 26 + 1 + + + FLASH_PP + 25 + 1 + + + FLASH_SE + 24 + 1 + + + FLASH_BE + 23 + 1 + + + FLASH_CE + 22 + 1 + + + FLASH_DP + 21 + 1 + + + FLASH_RES + 20 + 1 + + + FLASH_HPM + 19 + 1 + + + USR + 18 + 1 + + + FLASH_PES + 17 + 1 + + + FLASH_PER + 16 + 1 + + + + + CTRL + 0x8 + SPI_CTRL + 32 + 0x00000000 + + + WR_BIT_ORDER + 26 + 1 + + + RD_BIT_ORDER + 25 + 1 + + + FREAD_QIO + 24 + 1 + + + FREAD_DIO + 23 + 1 + + + WRSR_2B + 22 + 1 + + + WP_REG + 21 + 1 + + + FREAD_QUAD + 20 + 1 + + + RESANDRES + 15 + 1 + + + FREAD_DUAL + 14 + 1 + + + FASTRD_MODE + 13 + 1 + + + WAIT_FLASH_IDLE_EN + 12 + 1 + + + TX_CRC_EN + 11 + 1 + + + FCS_CRC_EN + 10 + 1 + + + + + CTRL1 + 0xc + SPI_CTRL1 + 32 + 0x00000000 + + + CS_HOLD_DELAY + 28 + 4 + + + CS_HOLD_DELAY_RES + 16 + 12 + + + + + RD_STATUS + 0x10 + SPI_RD_STATUS + 32 + 0x00000000 + + + STATUS_EXT + 24 + 8 + + + WB_MODE + 16 + 8 + + + STATUS + 0 + 16 + + + + + CTRL2 + 0x14 + SPI_CTRL2 + 32 + 0x00000000 + + + CS_DELAY_NUM + 28 + 4 + + + CS_DELAY_MODE + 26 + 2 + + + MOSI_DELAY_NUM + 23 + 3 + + + MOSI_DELAY_MODE + 21 + 2 + + + MISO_DELAY_NUM + 18 + 3 + + + MISO_DELAY_MODE + 16 + 2 + + + CK_OUT_HIGH_MODE + 12 + 4 + + + CK_OUT_LOW_MODE + 8 + 4 + + + HOLD_TIME + 4 + 4 + + + SETUP_TIME + 0 + 4 + + + + + CLOCK + 0x18 + SPI_CLOCK + 32 + 0x00000000 + + + CLK_EQU_SYSCLK + 31 + 1 + + + CLKDIV_PRE + 18 + 13 + + + CLKCNT_N + 12 + 6 + + + CLKCNT_H + 6 + 6 + + + CLKCNT_L + 0 + 6 + + + + + USER + 0x1c + SPI_USER + 32 + 0x00000000 + + + USR_COMMAND + 31 + 1 + + + USR_ADDR + 30 + 1 + + + USR_DUMMY + 29 + 1 + + + USR_MISO + 28 + 1 + + + USR_MOSI + 27 + 1 + + + USR_DUMMY_IDLE + 26 + 1 + + + USR_MOSI_HIGHPART + 25 + 1 + + + USR_MISO_HIGHPART + 24 + 1 + + + USR_PREP_HOLD + 23 + 1 + + + USR_CMD_HOLD + 22 + 1 + + + USR_ADDR_HOLD + 21 + 1 + + + USR_DUMMY_HOLD + 20 + 1 + + + USR_DIN_HOLD + 19 + 1 + + + USR_DOUT_HOLD + 18 + 1 + + + USR_HOLD_POL + 17 + 1 + + + SIO + 16 + 1 + + + FWRITE_QIO + 15 + 1 + + + FWRITE_DIO + 14 + 1 + + + FWRITE_QUAD + 13 + 1 + + + FWRITE_DUAL + 12 + 1 + + + WR_BYTE_ORDER + 11 + 1 + + + RD_BYTE_ORDER + 10 + 1 + + + CK_OUT_EDGE + 7 + 1 + + + CK_I_EDGE + 6 + 1 + + + CS_SETUP + 5 + 1 + + + CS_HOLD + 4 + 1 + + + DOUTDIN + 0 + 1 + + + + + USER1 + 0x20 + SPI_USER1 + 32 + 0x00000000 + + + USR_ADDR_BITLEN + 26 + 6 + + + USR_DUMMY_CYCLELEN + 0 + 8 + + + + + USER2 + 0x24 + SPI_USER2 + 32 + 0x00000000 + + + USR_COMMAND_BITLEN + 28 + 4 + + + USR_COMMAND_VALUE + 0 + 16 + + + + + MOSI_DLEN + 0x28 + SPI_MOSI_DLEN + 32 + 0x00000000 + + + USR_MOSI_DBITLEN + 0 + 24 + + + + + MISO_DLEN + 0x2c + SPI_MISO_DLEN + 32 + 0x00000000 + + + USR_MISO_DBITLEN + 0 + 24 + + + + + SLV_WR_STATUS + 0x30 + SPI_SLV_WR_STATUS + 32 + 0x00000000 + + + SLV_WR_ST + 0 + 32 + + + + + PIN + 0x34 + SPI_PIN + 32 + 0x00000000 + + + CS_KEEP_ACTIVE + 30 + 1 + + + CK_IDLE_EDGE + 29 + 1 + + + MASTER_CK_SEL + 11 + 3 + + + MASTER_CS_POL + 6 + 3 + + + CK_DIS + 5 + 1 + + + CS2_DIS + 2 + 1 + + + CS1_DIS + 1 + 1 + + + CS0_DIS + 0 + 1 + + + + + SLAVE + 0x38 + SPI_SLAVE + 32 + 0x00000000 + + + SYNC_RESET + 31 + 1 + + + SLAVE_MODE + 30 + 1 + + + SLV_WR_RD_BUF_EN + 29 + 1 + + + SLV_WR_RD_STA_EN + 28 + 1 + + + SLV_CMD_DEFINE + 27 + 1 + + + TRANS_CNT + 23 + 4 + + + SLV_LAST_STATE + 20 + 3 + + + SLV_LAST_COMMAND + 17 + 3 + + + CS_I_MODE + 10 + 2 + + + INT_EN + 5 + 5 + + + TRANS_DONE + 4 + 1 + + + SLV_WR_STA_DONE + 3 + 1 + + + SLV_RD_STA_DONE + 2 + 1 + + + SLV_WR_BUF_DONE + 1 + 1 + + + SLV_RD_BUF_DONE + 0 + 1 + + + + + SLAVE1 + 0x3c + SPI_SLAVE1 + 32 + 0x00000000 + + + SLV_STATUS_BITLEN + 27 + 5 + + + SLV_STATUS_FAST_EN + 26 + 1 + + + SLV_STATUS_READBACK + 25 + 1 + + + SLV_RD_ADDR_BITLEN + 10 + 6 + + + SLV_WR_ADDR_BITLEN + 4 + 6 + + + SLV_WRSTA_DUMMY_EN + 3 + 1 + + + SLV_RDSTA_DUMMY_EN + 2 + 1 + + + SLV_WRBUF_DUMMY_EN + 1 + 1 + + + SLV_RDBUF_DUMMY_EN + 0 + 1 + + + + + SLAVE2 + 0x40 + SPI_SLAVE2 + 32 + 0x00000000 + + + SLV_WRBUF_DUMMY_CYCLELEN + 24 + 8 + + + SLV_RDBUF_DUMMY_CYCLELEN + 16 + 8 + + + SLV_WRSTA_DUMMY_CYCLELEN + 8 + 8 + + + SLV_RDSTA_DUMMY_CYCLELEN + 0 + 8 + + + + + SLAVE3 + 0x44 + SPI_SLAVE3 + 32 + 0x00000000 + + + SLV_WRSTA_CMD_VALUE + 24 + 8 + + + SLV_RDSTA_CMD_VALUE + 16 + 8 + + + SLV_WRBUF_CMD_VALUE + 8 + 8 + + + SLV_RDBUF_CMD_VALUE + 0 + 8 + + + + + SLV_WRBUF_DLEN + 0x48 + SPI_SLV_WRBUF_DLEN + 32 + 0x00000000 + + + SLV_WRBUF_DBITLEN + 0 + 24 + + + + + SLV_RDBUF_DLEN + 0x4c + SPI_SLV_RDBUF_DLEN + 32 + 0x00000000 + + + SLV_RDBUF_DBITLEN + 0 + 24 + + + + + CACHE_FCTRL + 0x50 + SPI_CACHE_FCTRL + 32 + 0x00000000 + + + CACHE_FLASH_PES_EN + 3 + 1 + + + CACHE_FLASH_USR_CMD + 2 + 1 + + + CACHE_USR_CMD_4BYTE + 1 + 1 + + + CACHE_REQ_EN + 0 + 1 + + + + + CACHE_SCTRL + 0x54 + SPI_CACHE_SCTRL + 32 + 0x00000000 + + + CACHE_SRAM_USR_WCMD + 28 + 1 + + + SRAM_ADDR_BITLEN + 22 + 6 + + + SRAM_DUMMY_CYCLELEN + 14 + 8 + + + SRAM_BYTES_LEN + 6 + 8 + + + CACHE_SRAM_USR_RCMD + 5 + 1 + + + USR_RD_SRAM_DUMMY + 4 + 1 + + + USR_WR_SRAM_DUMMY + 3 + 1 + + + USR_SRAM_QIO + 2 + 1 + + + USR_SRAM_DIO + 1 + 1 + + + + + SRAM_CMD + 0x58 + SPI_SRAM_CMD + 32 + 0x00000000 + + + SRAM_RSTIO + 4 + 1 + + + SRAM_QIO + 1 + 1 + + + SRAM_DIO + 0 + 1 + + + + + SRAM_DRD_CMD + 0x5c + SPI_SRAM_DRD_CMD + 32 + 0x00000000 + + + CACHE_SRAM_USR_RD_CMD_BITLEN + 28 + 4 + + + CACHE_SRAM_USR_RD_CMD_VALUE + 0 + 16 + + + + + SRAM_DWR_CMD + 0x60 + SPI_SRAM_DWR_CMD + 32 + 0x00000000 + + + CACHE_SRAM_USR_WR_CMD_BITLEN + 28 + 4 + + + CACHE_SRAM_USR_WR_CMD_VALUE + 0 + 16 + + + + + SLV_RD_BIT + 0x64 + SPI_SLV_RD_BIT + 32 + 0x00000000 + + + SLV_RDATA_BIT + 0 + 24 + + + + + W0 + 0x80 + SPI_W0 + 32 + 0x00000000 + + + BUF0 + 0 + 32 + + + + + W1 + 0x84 + SPI_W1 + 32 + 0x00000000 + + + BUF1 + 0 + 32 + + + + + W2 + 0x88 + SPI_W2 + 32 + 0x00000000 + + + BUF2 + 0 + 32 + + + + + W3 + 0x8c + SPI_W3 + 32 + 0x00000000 + + + BUF3 + 0 + 32 + + + + + W4 + 0x90 + SPI_W4 + 32 + 0x00000000 + + + BUF4 + 0 + 32 + + + + + W5 + 0x94 + SPI_W5 + 32 + 0x00000000 + + + BUF5 + 0 + 32 + + + + + W6 + 0x98 + SPI_W6 + 32 + 0x00000000 + + + BUF6 + 0 + 32 + + + + + W7 + 0x9c + SPI_W7 + 32 + 0x00000000 + + + BUF7 + 0 + 32 + + + + + W8 + 0xa0 + SPI_W8 + 32 + 0x00000000 + + + BUF8 + 0 + 32 + + + + + W9 + 0xa4 + SPI_W9 + 32 + 0x00000000 + + + BUF9 + 0 + 32 + + + + + W10 + 0xa8 + SPI_W10 + 32 + 0x00000000 + + + BUF10 + 0 + 32 + + + + + W11 + 0xac + SPI_W11 + 32 + 0x00000000 + + + BUF11 + 0 + 32 + + + + + W12 + 0xb0 + SPI_W12 + 32 + 0x00000000 + + + BUF12 + 0 + 32 + + + + + W13 + 0xb4 + SPI_W13 + 32 + 0x00000000 + + + BUF13 + 0 + 32 + + + + + W14 + 0xb8 + SPI_W14 + 32 + 0x00000000 + + + BUF14 + 0 + 32 + + + + + W15 + 0xbc + SPI_W15 + 32 + 0x00000000 + + + BUF15 + 0 + 32 + + + + + TX_CRC + 0xc0 + SPI_TX_CRC + 32 + 0x00000000 + + + TX_CRC_DATA + 0 + 32 + + + + + EXT0 + 0xf0 + SPI_EXT0 + 32 + 0x00000000 + + + T_PP_ENA + 31 + 1 + + + T_PP_SHIFT + 16 + 4 + + + T_PP_TIME + 0 + 12 + + + + + EXT1 + 0xf4 + SPI_EXT1 + 32 + 0x00000000 + + + T_ERASE_ENA + 31 + 1 + + + T_ERASE_SHIFT + 16 + 4 + + + T_ERASE_TIME + 0 + 12 + + + + + EXT2 + 0xf8 + SPI_EXT2 + 32 + 0x00000000 + + + ST + 0 + 3 + + + + + EXT3 + 0xfc + SPI_EXT3 + 32 + 0x00000000 + + + INT_HOLD_ENA + 0 + 2 + + + + + DMA_CONF + 0x100 + SPI_DMA_CONF + 32 + 0x00000000 + + + DMA_CONTINUE + 16 + 1 + + + DMA_TX_STOP + 15 + 1 + + + DMA_RX_STOP + 14 + 1 + + + OUT_DATA_BURST_EN + 12 + 1 + + + INDSCR_BURST_EN + 11 + 1 + + + OUTDSCR_BURST_EN + 10 + 1 + + + OUT_EOF_MODE + 9 + 1 + + + OUT_AUTO_WRBACK + 8 + 1 + + + OUT_LOOP_TEST + 7 + 1 + + + IN_LOOP_TEST + 6 + 1 + + + AHBM_RST + 5 + 1 + + + AHBM_FIFO_RST + 4 + 1 + + + OUT_RST + 3 + 1 + + + IN_RST + 2 + 1 + + + + + DMA_OUT_LINK + 0x104 + SPI_DMA_OUT_LINK + 32 + 0x00000000 + + + OUTLINK_RESTART + 30 + 1 + + + OUTLINK_START + 29 + 1 + + + OUTLINK_STOP + 28 + 1 + + + OUTLINK_ADDR + 0 + 20 + + + + + DMA_IN_LINK + 0x108 + SPI_DMA_IN_LINK + 32 + 0x00000000 + + + INLINK_RESTART + 30 + 1 + + + INLINK_START + 29 + 1 + + + INLINK_STOP + 28 + 1 + + + INLINK_AUTO_RET + 20 + 1 + + + INLINK_ADDR + 0 + 20 + + + + + DMA_STATUS + 0x10c + SPI_DMA_STATUS + 32 + 0x00000000 + + + DMA_TX_EN + 1 + 1 + + + DMA_RX_EN + 0 + 1 + + + + + DMA_INT_ENA + 0x110 + SPI_DMA_INT_ENA + 32 + 0x00000000 + + + OUT_TOTAL_EOF_INT_ENA + 8 + 1 + + + OUT_EOF_INT_ENA + 7 + 1 + + + OUT_DONE_INT_ENA + 6 + 1 + + + IN_SUC_EOF_INT_ENA + 5 + 1 + + + IN_ERR_EOF_INT_ENA + 4 + 1 + + + IN_DONE_INT_ENA + 3 + 1 + + + INLINK_DSCR_ERROR_INT_ENA + 2 + 1 + + + OUTLINK_DSCR_ERROR_INT_ENA + 1 + 1 + + + INLINK_DSCR_EMPTY_INT_ENA + 0 + 1 + + + + + DMA_INT_RAW + 0x114 + SPI_DMA_INT_RAW + 32 + 0x00000000 + + + OUT_TOTAL_EOF_INT_RAW + 8 + 1 + + + OUT_EOF_INT_RAW + 7 + 1 + + + OUT_DONE_INT_RAW + 6 + 1 + + + IN_SUC_EOF_INT_RAW + 5 + 1 + + + IN_ERR_EOF_INT_RAW + 4 + 1 + + + IN_DONE_INT_RAW + 3 + 1 + + + INLINK_DSCR_ERROR_INT_RAW + 2 + 1 + + + OUTLINK_DSCR_ERROR_INT_RAW + 1 + 1 + + + INLINK_DSCR_EMPTY_INT_RAW + 0 + 1 + + + + + DMA_INT_ST + 0x118 + SPI_DMA_INT_ST + 32 + 0x00000000 + + + OUT_TOTAL_EOF_INT_ST + 8 + 1 + + + OUT_EOF_INT_ST + 7 + 1 + + + OUT_DONE_INT_ST + 6 + 1 + + + IN_SUC_EOF_INT_ST + 5 + 1 + + + IN_ERR_EOF_INT_ST + 4 + 1 + + + IN_DONE_INT_ST + 3 + 1 + + + INLINK_DSCR_ERROR_INT_ST + 2 + 1 + + + OUTLINK_DSCR_ERROR_INT_ST + 1 + 1 + + + INLINK_DSCR_EMPTY_INT_ST + 0 + 1 + + + + + DMA_INT_CLR + 0x11c + SPI_DMA_INT_CLR + 32 + 0x00000000 + + + OUT_TOTAL_EOF_INT_CLR + 8 + 1 + + + OUT_EOF_INT_CLR + 7 + 1 + + + OUT_DONE_INT_CLR + 6 + 1 + + + IN_SUC_EOF_INT_CLR + 5 + 1 + + + IN_ERR_EOF_INT_CLR + 4 + 1 + + + IN_DONE_INT_CLR + 3 + 1 + + + INLINK_DSCR_ERROR_INT_CLR + 2 + 1 + + + OUTLINK_DSCR_ERROR_INT_CLR + 1 + 1 + + + INLINK_DSCR_EMPTY_INT_CLR + 0 + 1 + + + + + IN_ERR_EOF_DES_ADDR + 0x120 + SPI_IN_ERR_EOF_DES_ADDR + 32 + 0x00000000 + + + DMA_IN_ERR_EOF_DES_ADDR + 0 + 32 + + + + + IN_SUC_EOF_DES_ADDR + 0x124 + SPI_IN_SUC_EOF_DES_ADDR + 32 + 0x00000000 + + + DMA_IN_SUC_EOF_DES_ADDR + 0 + 32 + + + + + INLINK_DSCR + 0x128 + SPI_INLINK_DSCR + 32 + 0x00000000 + + + DMA_INLINK_DSCR + 0 + 32 + + + + + INLINK_DSCR_BF0 + 0x12c + SPI_INLINK_DSCR_BF0 + 32 + 0x00000000 + + + DMA_INLINK_DSCR_BF0 + 0 + 32 + + + + + INLINK_DSCR_BF1 + 0x130 + SPI_INLINK_DSCR_BF1 + 32 + 0x00000000 + + + DMA_INLINK_DSCR_BF1 + 0 + 32 + + + + + OUT_EOF_BFR_DES_ADDR + 0x134 + SPI_OUT_EOF_BFR_DES_ADDR + 32 + 0x00000000 + + + DMA_OUT_EOF_BFR_DES_ADDR + 0 + 32 + + + + + OUT_EOF_DES_ADDR + 0x138 + SPI_OUT_EOF_DES_ADDR + 32 + 0x00000000 + + + DMA_OUT_EOF_DES_ADDR + 0 + 32 + + + + + OUTLINK_DSCR + 0x13c + SPI_OUTLINK_DSCR + 32 + 0x00000000 + + + DMA_OUTLINK_DSCR + 0 + 32 + + + + + OUTLINK_DSCR_BF0 + 0x140 + SPI_OUTLINK_DSCR_BF0 + 32 + 0x00000000 + + + DMA_OUTLINK_DSCR_BF0 + 0 + 32 + + + + + OUTLINK_DSCR_BF1 + 0x144 + SPI_OUTLINK_DSCR_BF1 + 32 + 0x00000000 + + + DMA_OUTLINK_DSCR_BF1 + 0 + 32 + + + + + DMA_RSTATUS + 0x148 + SPI_DMA_RSTATUS + 32 + 0x00000000 + + + DMA_OUT_STATUS + 0 + 32 + + + + + DMA_TSTATUS + 0x14c + SPI_DMA_TSTATUS + 32 + 0x00000000 + + + DMA_IN_STATUS + 0 + 32 + + + + + DATE + 0x3fc + SPI_DATE + 32 + 0x00000000 + + + DATE + 0 + 28 + + + + + SPI1_DMA_INTRinterrupt of SPI1 DMA, SPI1 is for flash read/write, do not use this52 + SPI2_DMA_INTRinterrupt of SPI2 DMA, level53 + SPI3_DMA_INTRinterrupt of SPI3 DMA, level54 + + + I2C1 + 0x3ff67000 + + + I2C + 0x0 + + 0 + 0x000004c0 + registers + + + + SCL_LOW_PERIOD + 0x0 + I2C_SCL_LOW_PERIOD + 32 + 0x00000000 + + + PERIOD + 0 + 14 + + + + + CTR + 0x4 + I2C_CTR + 32 + 0x00000000 + + + CLK_EN + 8 + 1 + + + RX_LSB_FIRST + 7 + 1 + + + TX_LSB_FIRST + 6 + 1 + + + TRANS_START + 5 + 1 + + + MS_MODE + 4 + 1 + + + SAMPLE_SCL_LEVEL + 2 + 1 + + + SCL_FORCE_OUT + 1 + 1 + + + SDA_FORCE_OUT + 0 + 1 + + + + + SR + 0x8 + I2C_SR + 32 + 0x00000000 + + + SCL_STATE_LAST + 28 + 3 + + + SCL_MAIN_STATE_LAST + 24 + 3 + + + TXFIFO_CNT + 18 + 6 + + + RXFIFO_CNT + 8 + 6 + + + BYTE_TRANS + 6 + 1 + + + SLAVE_ADDRESSED + 5 + 1 + + + BUS_BUSY + 4 + 1 + + + ARB_LOST + 3 + 1 + + + TIME_OUT + 2 + 1 + + + SLAVE_RW + 1 + 1 + + + ACK_REC + 0 + 1 + + + + + TO + 0xc + I2C_TO + 32 + 0x00000000 + + + TIME_OUT_REG + 0 + 20 + + + + + SLAVE_ADDR + 0x10 + I2C_SLAVE_ADDR + 32 + 0x00000000 + + + ADDR_10BIT_EN + 31 + 1 + + + SLAVE_ADDR + 0 + 15 + + + + + RXFIFO_ST + 0x14 + I2C_RXFIFO_ST + 32 + 0x00000000 + + + TXFIFO_END_ADDR + 15 + 5 + + + TXFIFO_START_ADDR + 10 + 5 + + + RXFIFO_END_ADDR + 5 + 5 + + + RXFIFO_START_ADDR + 0 + 5 + + + + + FIFO_CONF + 0x18 + I2C_FIFO_CONF + 32 + 0x00000000 + + + NONFIFO_TX_THRES + 20 + 6 + + + NONFIFO_RX_THRES + 14 + 6 + + + TX_FIFO_RST + 13 + 1 + + + RX_FIFO_RST + 12 + 1 + + + FIFO_ADDR_CFG_EN + 11 + 1 + + + NONFIFO_EN + 10 + 1 + + + TXFIFO_EMPTY_THRHD + 5 + 5 + + + RXFIFO_FULL_THRHD + 0 + 5 + + + + + DATA + 0x1c + I2C_DATA + 32 + 0x00000000 + + + FIFO_RDATA + 0 + 8 + + + + + INT_RAW + 0x20 + I2C_INT_RAW + 32 + 0x00000000 + + + TX_SEND_EMPTY_INT_RAW + 12 + 1 + + + RX_REC_FULL_INT_RAW + 11 + 1 + + + ACK_ERR_INT_RAW + 10 + 1 + + + TRANS_START_INT_RAW + 9 + 1 + + + TIME_OUT_INT_RAW + 8 + 1 + + + TRANS_COMPLETE_INT_RAW + 7 + 1 + + + MASTER_TRAN_COMP_INT_RAW + 6 + 1 + + + ARBITRATION_LOST_INT_RAW + 5 + 1 + + + SLAVE_TRAN_COMP_INT_RAW + 4 + 1 + + + END_DETECT_INT_RAW + 3 + 1 + + + RXFIFO_OVF_INT_RAW + 2 + 1 + + + TXFIFO_EMPTY_INT_RAW + 1 + 1 + + + RXFIFO_FULL_INT_RAW + 0 + 1 + + + + + INT_CLR + 0x24 + I2C_INT_CLR + 32 + 0x00000000 + + + TX_SEND_EMPTY_INT_CLR + 12 + 1 + + + RX_REC_FULL_INT_CLR + 11 + 1 + + + ACK_ERR_INT_CLR + 10 + 1 + + + TRANS_START_INT_CLR + 9 + 1 + + + TIME_OUT_INT_CLR + 8 + 1 + + + TRANS_COMPLETE_INT_CLR + 7 + 1 + + + MASTER_TRAN_COMP_INT_CLR + 6 + 1 + + + ARBITRATION_LOST_INT_CLR + 5 + 1 + + + SLAVE_TRAN_COMP_INT_CLR + 4 + 1 + + + END_DETECT_INT_CLR + 3 + 1 + + + RXFIFO_OVF_INT_CLR + 2 + 1 + + + TXFIFO_EMPTY_INT_CLR + 1 + 1 + + + RXFIFO_FULL_INT_CLR + 0 + 1 + + + + + INT_ENA + 0x28 + I2C_INT_ENA + 32 + 0x00000000 + + + TX_SEND_EMPTY_INT_ENA + 12 + 1 + + + RX_REC_FULL_INT_ENA + 11 + 1 + + + ACK_ERR_INT_ENA + 10 + 1 + + + TRANS_START_INT_ENA + 9 + 1 + + + TIME_OUT_INT_ENA + 8 + 1 + + + TRANS_COMPLETE_INT_ENA + 7 + 1 + + + MASTER_TRAN_COMP_INT_ENA + 6 + 1 + + + ARBITRATION_LOST_INT_ENA + 5 + 1 + + + SLAVE_TRAN_COMP_INT_ENA + 4 + 1 + + + END_DETECT_INT_ENA + 3 + 1 + + + RXFIFO_OVF_INT_ENA + 2 + 1 + + + TXFIFO_EMPTY_INT_ENA + 1 + 1 + + + RXFIFO_FULL_INT_ENA + 0 + 1 + + + + + INT_STATUS + 0x2c + I2C_INT_STATUS + 32 + 0x00000000 + + + TX_SEND_EMPTY_INT_ST + 12 + 1 + + + RX_REC_FULL_INT_ST + 11 + 1 + + + ACK_ERR_INT_ST + 10 + 1 + + + TRANS_START_INT_ST + 9 + 1 + + + TIME_OUT_INT_ST + 8 + 1 + + + TRANS_COMPLETE_INT_ST + 7 + 1 + + + MASTER_TRAN_COMP_INT_ST + 6 + 1 + + + ARBITRATION_LOST_INT_ST + 5 + 1 + + + SLAVE_TRAN_COMP_INT_ST + 4 + 1 + + + END_DETECT_INT_ST + 3 + 1 + + + RXFIFO_OVF_INT_ST + 2 + 1 + + + TXFIFO_EMPTY_INT_ST + 1 + 1 + + + RXFIFO_FULL_INT_ST + 0 + 1 + + + + + SDA_HOLD + 0x30 + I2C_SDA_HOLD + 32 + 0x00000000 + + + TIME + 0 + 10 + + + + + SDA_SAMPLE + 0x34 + I2C_SDA_SAMPLE + 32 + 0x00000000 + + + TIME + 0 + 10 + + + + + SCL_HIGH_PERIOD + 0x38 + I2C_SCL_HIGH_PERIOD + 32 + 0x00000000 + + + PERIOD + 0 + 14 + + + + + SCL_START_HOLD + 0x40 + I2C_SCL_START_HOLD + 32 + 0x00000000 + + + TIME + 0 + 10 + + + + + SCL_RSTART_SETUP + 0x44 + I2C_SCL_RSTART_SETUP + 32 + 0x00000000 + + + TIME + 0 + 10 + + + + + SCL_STOP_HOLD + 0x48 + I2C_SCL_STOP_HOLD + 32 + 0x00000000 + + + TIME + 0 + 14 + + + + + SCL_STOP_SETUP + 0x4c + I2C_SCL_STOP_SETUP + 32 + 0x00000000 + + + TIME + 0 + 10 + + + + + SCL_FILTER_CFG + 0x50 + I2C_SCL_FILTER_CFG + 32 + 0x00000000 + + + SCL_FILTER_EN + 3 + 1 + + + SCL_FILTER_THRES + 0 + 3 + + + + + SDA_FILTER_CFG + 0x54 + I2C_SDA_FILTER_CFG + 32 + 0x00000000 + + + SDA_FILTER_EN + 3 + 1 + + + SDA_FILTER_THRES + 0 + 3 + + + + + COMD0 + 0x58 + I2C_COMD0 + 32 + 0x00000000 + + + COMMAND0_DONE + 31 + 1 + + + COMMAND0 + 0 + 14 + + + + + COMD1 + 0x5c + I2C_COMD1 + 32 + 0x00000000 + + + COMMAND1_DONE + 31 + 1 + + + COMMAND1 + 0 + 14 + + + + + COMD2 + 0x60 + I2C_COMD2 + 32 + 0x00000000 + + + COMMAND2_DONE + 31 + 1 + + + COMMAND2 + 0 + 14 + + + + + COMD3 + 0x64 + I2C_COMD3 + 32 + 0x00000000 + + + COMMAND3_DONE + 31 + 1 + + + COMMAND3 + 0 + 14 + + + + + COMD4 + 0x68 + I2C_COMD4 + 32 + 0x00000000 + + + COMMAND4_DONE + 31 + 1 + + + COMMAND4 + 0 + 14 + + + + + COMD5 + 0x6c + I2C_COMD5 + 32 + 0x00000000 + + + COMMAND5_DONE + 31 + 1 + + + COMMAND5 + 0 + 14 + + + + + COMD6 + 0x70 + I2C_COMD6 + 32 + 0x00000000 + + + COMMAND6_DONE + 31 + 1 + + + COMMAND6 + 0 + 14 + + + + + COMD7 + 0x74 + I2C_COMD7 + 32 + 0x00000000 + + + COMMAND7_DONE + 31 + 1 + + + COMMAND7 + 0 + 14 + + + + + COMD8 + 0x78 + I2C_COMD8 + 32 + 0x00000000 + + + COMMAND8_DONE + 31 + 1 + + + COMMAND8 + 0 + 14 + + + + + COMD9 + 0x7c + I2C_COMD9 + 32 + 0x00000000 + + + COMMAND9_DONE + 31 + 1 + + + COMMAND9 + 0 + 14 + + + + + COMD10 + 0x80 + I2C_COMD10 + 32 + 0x00000000 + + + COMMAND10_DONE + 31 + 1 + + + COMMAND10 + 0 + 14 + + + + + COMD11 + 0x84 + I2C_COMD11 + 32 + 0x00000000 + + + COMMAND11_DONE + 31 + 1 + + + COMMAND11 + 0 + 14 + + + + + COMD12 + 0x88 + I2C_COMD12 + 32 + 0x00000000 + + + COMMAND12_DONE + 31 + 1 + + + COMMAND12 + 0 + 14 + + + + + COMD13 + 0x8c + I2C_COMD13 + 32 + 0x00000000 + + + COMMAND13_DONE + 31 + 1 + + + COMMAND13 + 0 + 14 + + + + + COMD14 + 0x90 + I2C_COMD14 + 32 + 0x00000000 + + + COMMAND14_DONE + 31 + 1 + + + COMMAND14 + 0 + 14 + + + + + COMD15 + 0x94 + I2C_COMD15 + 32 + 0x00000000 + + + COMMAND15_DONE + 31 + 1 + + + COMMAND15 + 0 + 14 + + + + + DATE + 0xf8 + I2C_DATE + 32 + 0x00000000 + + + DATE + 0 + 32 + + + + + I2C_EXT0_INTRinterrupt of I2C controller0, level49 + I2C_EXT1_INTRinterrupt of I2C controller1, level50 + PWM0_INTRinterrupt of PWM0, level, Reserved39 + PWM1_INTRinterrupt of PWM1, level, Reserved40 + PWM2_INTRinterrupt of PWM2, level41 + PWM3_INTRinterrupt of PWM3, level42 + + + EFUSE + 0x3ff5a000 + + 0 + 0x00000920 + registers + + + + BLK0_RDATA0 + 0x0 + EFUSE_BLK0_RDATA0 + 32 + 0x00000000 + + + RD_FLASH_CRYPT_CNT + 20 + 7 + + + RD_EFUSE_RD_DIS + 16 + 4 + + + + + BLK0_RDATA1 + 0x4 + EFUSE_BLK0_RDATA1 + 32 + 0x00000000 + + + RD_WIFI_MAC_CRC_LOW + 0 + 32 + + + + + BLK0_RDATA2 + 0x8 + EFUSE_BLK0_RDATA2 + 32 + 0x00000000 + + + RD_WIFI_MAC_CRC_HIGH + 0 + 24 + + + + + BLK0_RDATA3 + 0xc + EFUSE_BLK0_RDATA3 + 32 + 0x00000000 + + + RD_CHIP_VER_REV1 + 15 + 1 + + + RD_CHIP_CPU_FREQ_RATED + 13 + 1 + + + RD_CHIP_CPU_FREQ_LOW + 12 + 1 + + + RD_CHIP_VER_PKG + 9 + 3 + + + RD_SPI_PAD_CONFIG_HD + 4 + 5 + + + RD_CHIP_VER_DIS_CACHE + 3 + 1 + + + RD_CHIP_VER_32PAD + 2 + 1 + + + RD_CHIP_VER_DIS_BT + 1 + 1 + + + RD_CHIP_VER_DIS_APP_CPU + 0 + 1 + + + + + BLK0_RDATA4 + 0x10 + EFUSE_BLK0_RDATA4 + 32 + 0x00000000 + + + RD_SDIO_FORCE + 16 + 1 + + + RD_SDIO_TIEH + 15 + 1 + + + RD_XPD_SDIO_REG + 14 + 1 + + + RD_ADC_VREF + 8 + 5 + + + RD_SDIO_DREFL + 12 + 2 + + + RD_SDIO_DREFM + 10 + 2 + + + RD_SDIO_DREFH + 8 + 2 + + + RD_CK8M_FREQ + 0 + 8 + + + + + BLK0_RDATA5 + 0x14 + EFUSE_BLK0_RDATA5 + 32 + 0x00000000 + + + RD_FLASH_CRYPT_CONFIG + 28 + 4 + + + RD_INST_CONFIG + 20 + 8 + + + RD_SPI_PAD_CONFIG_D + 10 + 5 + + + RD_SPI_PAD_CONFIG_Q + 5 + 5 + + + RD_SPI_PAD_CONFIG_CLK + 0 + 5 + + + + + BLK0_RDATA6 + 0x18 + EFUSE_BLK0_RDATA6 + 32 + 0x00000000 + + + RD_KEY_STATUS + 10 + 1 + + + RD_DISABLE_DL_CACHE + 9 + 1 + + + RD_DISABLE_DL_DECRYPT + 8 + 1 + + + RD_DISABLE_DL_ENCRYPT + 7 + 1 + + + RD_DISABLE_JTAG + 6 + 1 + + + RD_ABS_DONE_1 + 5 + 1 + + + RD_ABS_DONE_0 + 4 + 1 + + + RD_DISABLE_SDIO_HOST + 3 + 1 + + + RD_CONSOLE_DEBUG_DISABLE + 2 + 1 + + + RD_CODING_SCHEME + 0 + 2 + + + + + BLK0_WDATA0 + 0x1c + EFUSE_BLK0_WDATA0 + 32 + 0x00000000 + + + FLASH_CRYPT_CNT + 20 + 7 + + + RD_DIS + 16 + 4 + + + WR_DIS + 0 + 16 + + + + + BLK0_WDATA1 + 0x20 + EFUSE_BLK0_WDATA1 + 32 + 0x00000000 + + + WIFI_MAC_CRC_LOW + 0 + 32 + + + + + BLK0_WDATA2 + 0x24 + EFUSE_BLK0_WDATA2 + 32 + 0x00000000 + + + WIFI_MAC_CRC_HIGH + 0 + 24 + + + + + BLK0_WDATA3 + 0x28 + EFUSE_BLK0_WDATA3 + 32 + 0x00000000 + + + CHIP_VER_REV1 + 15 + 1 + + + CHIP_CPU_FREQ_RATED + 13 + 1 + + + CHIP_CPU_FREQ_LOW + 12 + 1 + + + CHIP_VER_PKG + 9 + 3 + + + SPI_PAD_CONFIG_HD + 4 + 5 + + + CHIP_VER_DIS_CACHE + 3 + 1 + + + CHIP_VER_32PAD + 2 + 1 + + + CHIP_VER_DIS_BT + 1 + 1 + + + CHIP_VER_DIS_APP_CPU + 0 + 1 + + + + + BLK0_WDATA4 + 0x2c + EFUSE_BLK0_WDATA4 + 32 + 0x00000000 + + + SDIO_FORCE + 16 + 1 + + + SDIO_TIEH + 15 + 1 + + + XPD_SDIO_REG + 14 + 1 + + + ADC_VREF + 8 + 5 + + + SDIO_DREFL + 12 + 2 + + + SDIO_DREFM + 10 + 2 + + + SDIO_DREFH + 8 + 2 + + + CK8M_FREQ + 0 + 8 + + + + + BLK0_WDATA5 + 0x30 + EFUSE_BLK0_WDATA5 + 32 + 0x00000000 + + + FLASH_CRYPT_CONFIG + 28 + 4 + + + INST_CONFIG + 20 + 8 + + + SPI_PAD_CONFIG_D + 10 + 5 + + + SPI_PAD_CONFIG_Q + 5 + 5 + + + SPI_PAD_CONFIG_CLK + 0 + 5 + + + + + BLK0_WDATA6 + 0x34 + EFUSE_BLK0_WDATA6 + 32 + 0x00000000 + + + KEY_STATUS + 10 + 1 + + + DISABLE_DL_CACHE + 9 + 1 + + + DISABLE_DL_DECRYPT + 8 + 1 + + + DISABLE_DL_ENCRYPT + 7 + 1 + + + DISABLE_JTAG + 6 + 1 + + + ABS_DONE_1 + 5 + 1 + + + ABS_DONE_0 + 4 + 1 + + + DISABLE_SDIO_HOST + 3 + 1 + + + CONSOLE_DEBUG_DISABLE + 2 + 1 + + + CODING_SCHEME + 0 + 2 + + + + + BLK1_RDATA0 + 0x38 + EFUSE_BLK1_RDATA0 + 32 + 0x00000000 + + + BLK1_DOUT0 + 0 + 32 + + + + + BLK1_RDATA1 + 0x3c + EFUSE_BLK1_RDATA1 + 32 + 0x00000000 + + + BLK1_DOUT1 + 0 + 32 + + + + + BLK1_RDATA2 + 0x40 + EFUSE_BLK1_RDATA2 + 32 + 0x00000000 + + + BLK1_DOUT2 + 0 + 32 + + + + + BLK1_RDATA3 + 0x44 + EFUSE_BLK1_RDATA3 + 32 + 0x00000000 + + + BLK1_DOUT3 + 0 + 32 + + + + + BLK1_RDATA4 + 0x48 + EFUSE_BLK1_RDATA4 + 32 + 0x00000000 + + + BLK1_DOUT4 + 0 + 32 + + + + + BLK1_RDATA5 + 0x4c + EFUSE_BLK1_RDATA5 + 32 + 0x00000000 + + + BLK1_DOUT5 + 0 + 32 + + + + + BLK1_RDATA6 + 0x50 + EFUSE_BLK1_RDATA6 + 32 + 0x00000000 + + + BLK1_DOUT6 + 0 + 32 + + + + + BLK1_RDATA7 + 0x54 + EFUSE_BLK1_RDATA7 + 32 + 0x00000000 + + + BLK1_DOUT7 + 0 + 32 + + + + + BLK2_RDATA0 + 0x58 + EFUSE_BLK2_RDATA0 + 32 + 0x00000000 + + + BLK2_DOUT0 + 0 + 32 + + + + + BLK2_RDATA1 + 0x5c + EFUSE_BLK2_RDATA1 + 32 + 0x00000000 + + + BLK2_DOUT1 + 0 + 32 + + + + + BLK2_RDATA2 + 0x60 + EFUSE_BLK2_RDATA2 + 32 + 0x00000000 + + + BLK2_DOUT2 + 0 + 32 + + + + + BLK2_RDATA3 + 0x64 + EFUSE_BLK2_RDATA3 + 32 + 0x00000000 + + + BLK2_DOUT3 + 0 + 32 + + + + + BLK2_RDATA4 + 0x68 + EFUSE_BLK2_RDATA4 + 32 + 0x00000000 + + + BLK2_DOUT4 + 0 + 32 + + + + + BLK2_RDATA5 + 0x6c + EFUSE_BLK2_RDATA5 + 32 + 0x00000000 + + + BLK2_DOUT5 + 0 + 32 + + + + + BLK2_RDATA6 + 0x70 + EFUSE_BLK2_RDATA6 + 32 + 0x00000000 + + + BLK2_DOUT6 + 0 + 32 + + + + + BLK2_RDATA7 + 0x74 + EFUSE_BLK2_RDATA7 + 32 + 0x00000000 + + + BLK2_DOUT7 + 0 + 32 + + + + + BLK3_RDATA0 + 0x78 + EFUSE_BLK3_RDATA0 + 32 + 0x00000000 + + + BLK3_DOUT0 + 0 + 32 + + + + + BLK3_RDATA1 + 0x7c + EFUSE_BLK3_RDATA1 + 32 + 0x00000000 + + + BLK3_DOUT1 + 0 + 32 + + + + + BLK3_RDATA2 + 0x80 + EFUSE_BLK3_RDATA2 + 32 + 0x00000000 + + + BLK3_DOUT2 + 0 + 32 + + + + + BLK3_RDATA3 + 0x84 + EFUSE_BLK3_RDATA3 + 32 + 0x00000000 + + + BLK3_DOUT3 + 0 + 32 + + + RD_ADC2_TP_HIGH + 23 + 9 + + + RD_ADC2_TP_LOW + 16 + 7 + + + RD_ADC1_TP_HIGH + 7 + 9 + + + RD_ADC1_TP_LOW + 0 + 7 + + + + + BLK3_RDATA4 + 0x88 + EFUSE_BLK3_RDATA4 + 32 + 0x00000000 + + + BLK3_DOUT4 + 0 + 32 + + + + + BLK3_RDATA5 + 0x8c + EFUSE_BLK3_RDATA5 + 32 + 0x00000000 + + + BLK3_DOUT5 + 0 + 32 + + + + + BLK3_RDATA6 + 0x90 + EFUSE_BLK3_RDATA6 + 32 + 0x00000000 + + + BLK3_DOUT6 + 0 + 32 + + + + + BLK3_RDATA7 + 0x94 + EFUSE_BLK3_RDATA7 + 32 + 0x00000000 + + + BLK3_DOUT7 + 0 + 32 + + + + + BLK1_WDATA0 + 0x98 + EFUSE_BLK1_WDATA0 + 32 + 0x00000000 + + + BLK1_DIN0 + 0 + 32 + + + + + BLK1_WDATA1 + 0x9c + EFUSE_BLK1_WDATA1 + 32 + 0x00000000 + + + BLK1_DIN1 + 0 + 32 + + + + + BLK1_WDATA2 + 0xa0 + EFUSE_BLK1_WDATA2 + 32 + 0x00000000 + + + BLK1_DIN2 + 0 + 32 + + + + + BLK1_WDATA3 + 0xa4 + EFUSE_BLK1_WDATA3 + 32 + 0x00000000 + + + BLK1_DIN3 + 0 + 32 + + + + + BLK1_WDATA4 + 0xa8 + EFUSE_BLK1_WDATA4 + 32 + 0x00000000 + + + BLK1_DIN4 + 0 + 32 + + + + + BLK1_WDATA5 + 0xac + EFUSE_BLK1_WDATA5 + 32 + 0x00000000 + + + BLK1_DIN5 + 0 + 32 + + + + + BLK1_WDATA6 + 0xb0 + EFUSE_BLK1_WDATA6 + 32 + 0x00000000 + + + BLK1_DIN6 + 0 + 32 + + + + + BLK1_WDATA7 + 0xb4 + EFUSE_BLK1_WDATA7 + 32 + 0x00000000 + + + BLK1_DIN7 + 0 + 32 + + + + + BLK2_WDATA0 + 0xb8 + EFUSE_BLK2_WDATA0 + 32 + 0x00000000 + + + BLK2_DIN0 + 0 + 32 + + + + + BLK2_WDATA1 + 0xbc + EFUSE_BLK2_WDATA1 + 32 + 0x00000000 + + + BLK2_DIN1 + 0 + 32 + + + + + BLK2_WDATA2 + 0xc0 + EFUSE_BLK2_WDATA2 + 32 + 0x00000000 + + + BLK2_DIN2 + 0 + 32 + + + + + BLK2_WDATA3 + 0xc4 + EFUSE_BLK2_WDATA3 + 32 + 0x00000000 + + + BLK2_DIN3 + 0 + 32 + + + + + BLK2_WDATA4 + 0xc8 + EFUSE_BLK2_WDATA4 + 32 + 0x00000000 + + + BLK2_DIN4 + 0 + 32 + + + + + BLK2_WDATA5 + 0xcc + EFUSE_BLK2_WDATA5 + 32 + 0x00000000 + + + BLK2_DIN5 + 0 + 32 + + + + + BLK2_WDATA6 + 0xd0 + EFUSE_BLK2_WDATA6 + 32 + 0x00000000 + + + BLK2_DIN6 + 0 + 32 + + + + + BLK2_WDATA7 + 0xd4 + EFUSE_BLK2_WDATA7 + 32 + 0x00000000 + + + BLK2_DIN7 + 0 + 32 + + + + + BLK3_WDATA0 + 0xd8 + EFUSE_BLK3_WDATA0 + 32 + 0x00000000 + + + BLK3_DIN0 + 0 + 32 + + + + + BLK3_WDATA1 + 0xdc + EFUSE_BLK3_WDATA1 + 32 + 0x00000000 + + + BLK3_DIN1 + 0 + 32 + + + + + BLK3_WDATA2 + 0xe0 + EFUSE_BLK3_WDATA2 + 32 + 0x00000000 + + + BLK3_DIN2 + 0 + 32 + + + + + BLK3_WDATA3 + 0xe4 + EFUSE_BLK3_WDATA3 + 32 + 0x00000000 + + + BLK3_DIN3 + 0 + 32 + + + ADC2_TP_HIGH + 23 + 9 + + + ADC2_TP_LOW + 16 + 7 + + + ADC1_TP_HIGH + 7 + 9 + + + ADC1_TP_LOW + 0 + 7 + + + + + BLK3_WDATA4 + 0xe8 + EFUSE_BLK3_WDATA4 + 32 + 0x00000000 + + + BLK3_DIN4 + 0 + 32 + + + + + BLK3_WDATA5 + 0xec + EFUSE_BLK3_WDATA5 + 32 + 0x00000000 + + + BLK3_DIN5 + 0 + 32 + + + + + BLK3_WDATA6 + 0xf0 + EFUSE_BLK3_WDATA6 + 32 + 0x00000000 + + + BLK3_DIN6 + 0 + 32 + + + + + BLK3_WDATA7 + 0xf4 + EFUSE_BLK3_WDATA7 + 32 + 0x00000000 + + + BLK3_DIN7 + 0 + 32 + + + + + CLK + 0xf8 + EFUSE_CLK + 32 + 0x00000000 + + + CLK_EN + 16 + 1 + + + CLK_SEL1 + 8 + 8 + + + CLK_SEL0 + 0 + 8 + + + + + CONF + 0xfc + EFUSE_CONF + 32 + 0x00000000 + + + FORCE_NO_WR_RD_DIS + 16 + 1 + + + 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CNT_THR_EVENT_U4_INT_ENA + 4 + 1 + + + CNT_THR_EVENT_U3_INT_ENA + 3 + 1 + + + CNT_THR_EVENT_U2_INT_ENA + 2 + 1 + + + CNT_THR_EVENT_U1_INT_ENA + 1 + 1 + + + CNT_THR_EVENT_U0_INT_ENA + 0 + 1 + + + + + INT_CLR + 0x8c + PCNT_INT_CLR + 32 + 0x00000000 + + + CNT_THR_EVENT_U7_INT_CLR + 7 + 1 + + + CNT_THR_EVENT_U6_INT_CLR + 6 + 1 + + + CNT_THR_EVENT_U5_INT_CLR + 5 + 1 + + + CNT_THR_EVENT_U4_INT_CLR + 4 + 1 + + + CNT_THR_EVENT_U3_INT_CLR + 3 + 1 + + + CNT_THR_EVENT_U2_INT_CLR + 2 + 1 + + + CNT_THR_EVENT_U1_INT_CLR + 1 + 1 + + + CNT_THR_EVENT_U0_INT_CLR + 0 + 1 + + + + + U0_STATUS + 0x90 + PCNT_U0_STATUS + 32 + 0x00000000 + + + CORE_STATUS_U0 + 0 + 32 + + + + + U1_STATUS + 0x94 + PCNT_U1_STATUS + 32 + 0x00000000 + + + CORE_STATUS_U1 + 0 + 32 + + + + + U2_STATUS + 0x98 + PCNT_U2_STATUS + 32 + 0x00000000 + + + CORE_STATUS_U2 + 0 + 32 + + + + + U3_STATUS + 0x9c + PCNT_U3_STATUS + 32 + 0x00000000 + + + CORE_STATUS_U3 + 0 + 32 + + + + + U4_STATUS + 0xa0 + PCNT_U4_STATUS + 32 + 0x00000000 + + + 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+ RMT_CH6_TX_LIM + 32 + 0x00000000 + + + TX_LIM_CH6 + 0 + 9 + + + + + CH7_TX_LIM + 0xec + RMT_CH7_TX_LIM + 32 + 0x00000000 + + + TX_LIM_CH7 + 0 + 9 + + + + + APB_CONF + 0xf0 + RMT_APB_CONF + 32 + 0x00000000 + + + MEM_TX_WRAP_EN + 1 + 1 + + + APB_FIFO_MASK + 0 + 1 + + + + + DATE + 0xfc + RMT_DATE + 32 + 0x00000000 + + + DATE + 0 + 32 + + + + + RMT_INTRinterrupt of remote controller, level47 + + + EMAC + 0x3ff69000 + + 0 + 0x00000000 + registers + + + + + RTCMEM2 + 0x3ff63000 + + 0 + 0x00000000 + registers + + + + + GPIO + 0x3ff44000 + + 0 + 0x00002e60 + registers + + + + BT_SELECT + 0x0 + GPIO_BT_SELECT + 32 + 0x00000000 + + + BT_SEL + 0 + 32 + + + + + OUT + 0x4 + GPIO_OUT + 32 + 0x00000000 + + + OUT_DATA + 0 + 32 + + + + + OUT_W1TS + 0x8 + GPIO_OUT_W1TS + 32 + 0x00000000 + + + OUT_DATA_W1TS + 0 + 32 + + + + + OUT_W1TC + 0xc + GPIO_OUT_W1TC + 32 + 0x00000000 + + + OUT_DATA_W1TC + 0 + 32 + + + + + OUT1 + 0x10 + GPIO_OUT1 + 32 + 0x00000000 + + + OUT1_DATA + 0 + 8 + + + + + OUT1_W1TS + 0x14 + GPIO_OUT1_W1TS + 32 + 0x00000000 + + + OUT1_DATA_W1TS + 0 + 8 + + + + + OUT1_W1TC + 0x18 + GPIO_OUT1_W1TC + 32 + 0x00000000 + + + OUT1_DATA_W1TC + 0 + 8 + + + + + SDIO_SELECT + 0x1c + GPIO_SDIO_SELECT + 32 + 0x00000000 + + + SDIO_SEL + 0 + 8 + + + + + ENABLE + 0x20 + GPIO_ENABLE + 32 + 0x00000000 + + + ENABLE_DATA + 0 + 32 + + + + + ENABLE_W1TS + 0x24 + GPIO_ENABLE_W1TS + 32 + 0x00000000 + + + ENABLE_DATA_W1TS + 0 + 32 + + + + + ENABLE_W1TC + 0x28 + GPIO_ENABLE_W1TC + 32 + 0x00000000 + + + ENABLE_DATA_W1TC + 0 + 32 + + + + + ENABLE1 + 0x2c + GPIO_ENABLE1 + 32 + 0x00000000 + + + ENABLE1_DATA + 0 + 8 + + + + + ENABLE1_W1TS + 0x30 + GPIO_ENABLE1_W1TS + 32 + 0x00000000 + + + ENABLE1_DATA_W1TS + 0 + 8 + + + + + ENABLE1_W1TC + 0x34 + GPIO_ENABLE1_W1TC + 32 + 0x00000000 + + + ENABLE1_DATA_W1TC + 0 + 8 + + + + + STRAP + 0x38 + GPIO_STRAP + 32 + 0x00000000 + + + STRAPPING + 0 + 16 + + + + + IN + 0x3c + GPIO_IN + 32 + 0x00000000 + + + IN_DATA + 0 + 32 + + + + + IN1 + 0x40 + GPIO_IN1 + 32 + 0x00000000 + + + IN1_DATA + 0 + 8 + + + + + STATUS + 0x44 + GPIO_STATUS + 32 + 0x00000000 + + + STATUS_INT + 0 + 32 + + + + + STATUS_W1TS + 0x48 + GPIO_STATUS_W1TS + 32 + 0x00000000 + + + STATUS_INT_W1TS + 0 + 32 + + + + + STATUS_W1TC + 0x4c + GPIO_STATUS_W1TC + 32 + 0x00000000 + + + STATUS_INT_W1TC + 0 + 32 + + + + + STATUS1 + 0x50 + GPIO_STATUS1 + 32 + 0x00000000 + + + STATUS1_INT + 0 + 8 + + + + + STATUS1_W1TS + 0x54 + GPIO_STATUS1_W1TS + 32 + 0x00000000 + + + STATUS1_INT_W1TS + 0 + 8 + + + + + STATUS1_W1TC + 0x58 + GPIO_STATUS1_W1TC + 32 + 0x00000000 + + + STATUS1_INT_W1TC + 0 + 8 + + + + + ACPU_INT + 0x60 + GPIO_ACPU_INT + 32 + 0x00000000 + + + APPCPU_INT + 0 + 32 + + + + + ACPU_NMI_INT + 0x64 + GPIO_ACPU_NMI_INT + 32 + 0x00000000 + + + APPCPU_NMI_INT + 0 + 32 + + + + + PCPU_INT + 0x68 + GPIO_PCPU_INT + 32 + 0x00000000 + + + PROCPU_INT + 0 + 32 + + + + + PCPU_NMI_INT + 0x6c + GPIO_PCPU_NMI_INT + 32 + 0x00000000 + + + PROCPU_NMI_INT + 0 + 32 + + + + + CPUSDIO_INT + 0x70 + GPIO_CPUSDIO_INT + 32 + 0x00000000 + + + SDIO_INT + 0 + 32 + + + + + ACPU_INT1 + 0x74 + GPIO_ACPU_INT1 + 32 + 0x00000000 + + + APPCPU_INT_H + 0 + 8 + + + + + ACPU_NMI_INT1 + 0x78 + GPIO_ACPU_NMI_INT1 + 32 + 0x00000000 + + + APPCPU_NMI_INT_H + 0 + 8 + + + + + PCPU_INT1 + 0x7c + GPIO_PCPU_INT1 + 32 + 0x00000000 + + + PROCPU_INT_H + 0 + 8 + + + + + PCPU_NMI_INT1 + 0x80 + GPIO_PCPU_NMI_INT1 + 32 + 0x00000000 + + + PROCPU_NMI_INT_H + 0 + 8 + + + + + CPUSDIO_INT1 + 0x84 + GPIO_CPUSDIO_INT1 + 32 + 0x00000000 + + + SDIO_INT_H + 0 + 8 + + + + + PIN0 + 0x88 + GPIO_PIN0 + 32 + 0x00000000 + + + PIN0_INT_ENA + 13 + 5 + + + PIN0_CONFIG + 11 + 2 + + + PIN0_WAKEUP_ENABLE + 10 + 1 + + + PIN0_INT_TYPE + 7 + 3 + + + PIN0_PAD_DRIVER + 2 + 1 + + + + + PIN1 + 0x8c + GPIO_PIN1 + 32 + 0x00000000 + + + PIN1_INT_ENA + 13 + 5 + + + PIN1_CONFIG + 11 + 2 + + + PIN1_WAKEUP_ENABLE + 10 + 1 + + + PIN1_INT_TYPE + 7 + 3 + + + PIN1_PAD_DRIVER + 2 + 1 + + + + + PIN2 + 0x90 + GPIO_PIN2 + 32 + 0x00000000 + + + PIN2_INT_ENA + 13 + 5 + + + PIN2_CONFIG + 11 + 2 + + + PIN2_WAKEUP_ENABLE + 10 + 1 + + + PIN2_INT_TYPE + 7 + 3 + + + PIN2_PAD_DRIVER + 2 + 1 + + + + + PIN3 + 0x94 + GPIO_PIN3 + 32 + 0x00000000 + + + PIN3_INT_ENA + 13 + 5 + + + PIN3_CONFIG + 11 + 2 + + + PIN3_WAKEUP_ENABLE + 10 + 1 + + + PIN3_INT_TYPE + 7 + 3 + + + PIN3_PAD_DRIVER + 2 + 1 + + + + + PIN4 + 0x98 + GPIO_PIN4 + 32 + 0x00000000 + + + PIN4_INT_ENA + 13 + 5 + + + PIN4_CONFIG + 11 + 2 + + + PIN4_WAKEUP_ENABLE + 10 + 1 + + + PIN4_INT_TYPE + 7 + 3 + + + PIN4_PAD_DRIVER + 2 + 1 + + + + + PIN5 + 0x9c + GPIO_PIN5 + 32 + 0x00000000 + + + PIN5_INT_ENA + 13 + 5 + + + PIN5_CONFIG + 11 + 2 + + + PIN5_WAKEUP_ENABLE + 10 + 1 + + + PIN5_INT_TYPE + 7 + 3 + + + PIN5_PAD_DRIVER + 2 + 1 + + + + + PIN6 + 0xa0 + GPIO_PIN6 + 32 + 0x00000000 + + + PIN6_INT_ENA + 13 + 5 + + + PIN6_CONFIG + 11 + 2 + + + PIN6_WAKEUP_ENABLE + 10 + 1 + + + PIN6_INT_TYPE + 7 + 3 + + + PIN6_PAD_DRIVER + 2 + 1 + + + + + PIN7 + 0xa4 + GPIO_PIN7 + 32 + 0x00000000 + + + PIN7_INT_ENA + 13 + 5 + + + PIN7_CONFIG + 11 + 2 + + + PIN7_WAKEUP_ENABLE + 10 + 1 + + + PIN7_INT_TYPE + 7 + 3 + + + PIN7_PAD_DRIVER + 2 + 1 + + + + + PIN8 + 0xa8 + GPIO_PIN8 + 32 + 0x00000000 + + + PIN8_INT_ENA + 13 + 5 + + + PIN8_CONFIG + 11 + 2 + + + PIN8_WAKEUP_ENABLE + 10 + 1 + + + PIN8_INT_TYPE + 7 + 3 + + + PIN8_PAD_DRIVER + 2 + 1 + + + + + PIN9 + 0xac + GPIO_PIN9 + 32 + 0x00000000 + + + PIN9_INT_ENA + 13 + 5 + + + PIN9_CONFIG + 11 + 2 + + + PIN9_WAKEUP_ENABLE + 10 + 1 + + + PIN9_INT_TYPE + 7 + 3 + + + PIN9_PAD_DRIVER + 2 + 1 + + + + + PIN10 + 0xb0 + GPIO_PIN10 + 32 + 0x00000000 + + + PIN10_INT_ENA + 13 + 5 + + + PIN10_CONFIG + 11 + 2 + + + PIN10_WAKEUP_ENABLE + 10 + 1 + + + PIN10_INT_TYPE + 7 + 3 + + + PIN10_PAD_DRIVER + 2 + 1 + + + + + PIN11 + 0xb4 + GPIO_PIN11 + 32 + 0x00000000 + + + PIN11_INT_ENA + 13 + 5 + + + PIN11_CONFIG + 11 + 2 + + + PIN11_WAKEUP_ENABLE + 10 + 1 + + + PIN11_INT_TYPE + 7 + 3 + + + PIN11_PAD_DRIVER + 2 + 1 + + + + + PIN12 + 0xb8 + GPIO_PIN12 + 32 + 0x00000000 + + + PIN12_INT_ENA + 13 + 5 + + + PIN12_CONFIG + 11 + 2 + + + PIN12_WAKEUP_ENABLE + 10 + 1 + + + PIN12_INT_TYPE + 7 + 3 + + + PIN12_PAD_DRIVER + 2 + 1 + + + + + PIN13 + 0xbc + GPIO_PIN13 + 32 + 0x00000000 + + + PIN13_INT_ENA + 13 + 5 + + + PIN13_CONFIG + 11 + 2 + + + PIN13_WAKEUP_ENABLE + 10 + 1 + + + PIN13_INT_TYPE + 7 + 3 + + + PIN13_PAD_DRIVER + 2 + 1 + + + + + PIN14 + 0xc0 + GPIO_PIN14 + 32 + 0x00000000 + + + PIN14_INT_ENA + 13 + 5 + + + PIN14_CONFIG + 11 + 2 + + + PIN14_WAKEUP_ENABLE + 10 + 1 + + + PIN14_INT_TYPE + 7 + 3 + + + PIN14_PAD_DRIVER + 2 + 1 + + + + + PIN15 + 0xc4 + GPIO_PIN15 + 32 + 0x00000000 + + + PIN15_INT_ENA + 13 + 5 + + + PIN15_CONFIG + 11 + 2 + + + PIN15_WAKEUP_ENABLE + 10 + 1 + + + PIN15_INT_TYPE + 7 + 3 + + + PIN15_PAD_DRIVER + 2 + 1 + + + + + PIN16 + 0xc8 + GPIO_PIN16 + 32 + 0x00000000 + + + PIN16_INT_ENA + 13 + 5 + + + PIN16_CONFIG + 11 + 2 + + + PIN16_WAKEUP_ENABLE + 10 + 1 + + + PIN16_INT_TYPE + 7 + 3 + + + PIN16_PAD_DRIVER + 2 + 1 + + + + + PIN17 + 0xcc + GPIO_PIN17 + 32 + 0x00000000 + + + PIN17_INT_ENA + 13 + 5 + + + PIN17_CONFIG + 11 + 2 + + + PIN17_WAKEUP_ENABLE + 10 + 1 + + + PIN17_INT_TYPE + 7 + 3 + + + PIN17_PAD_DRIVER + 2 + 1 + + + + + PIN18 + 0xd0 + GPIO_PIN18 + 32 + 0x00000000 + + + PIN18_INT_ENA + 13 + 5 + + + PIN18_CONFIG + 11 + 2 + + + PIN18_WAKEUP_ENABLE + 10 + 1 + + + PIN18_INT_TYPE + 7 + 3 + + + PIN18_PAD_DRIVER + 2 + 1 + + + + + PIN19 + 0xd4 + GPIO_PIN19 + 32 + 0x00000000 + + + PIN19_INT_ENA + 13 + 5 + + + PIN19_CONFIG + 11 + 2 + + + PIN19_WAKEUP_ENABLE + 10 + 1 + + + PIN19_INT_TYPE + 7 + 3 + + + PIN19_PAD_DRIVER + 2 + 1 + + + + + PIN20 + 0xd8 + GPIO_PIN20 + 32 + 0x00000000 + + + PIN20_INT_ENA + 13 + 5 + + + PIN20_CONFIG + 11 + 2 + + + PIN20_WAKEUP_ENABLE + 10 + 1 + + + PIN20_INT_TYPE + 7 + 3 + + + PIN20_PAD_DRIVER + 2 + 1 + + + + + PIN21 + 0xdc + GPIO_PIN21 + 32 + 0x00000000 + + + PIN21_INT_ENA + 13 + 5 + + + PIN21_CONFIG + 11 + 2 + + + PIN21_WAKEUP_ENABLE + 10 + 1 + + + PIN21_INT_TYPE + 7 + 3 + + + PIN21_PAD_DRIVER + 2 + 1 + + + + + PIN22 + 0xe0 + GPIO_PIN22 + 32 + 0x00000000 + + + PIN22_INT_ENA + 13 + 5 + + + PIN22_CONFIG + 11 + 2 + + + PIN22_WAKEUP_ENABLE + 10 + 1 + + + PIN22_INT_TYPE + 7 + 3 + + + PIN22_PAD_DRIVER + 2 + 1 + + + + + PIN23 + 0xe4 + GPIO_PIN23 + 32 + 0x00000000 + + + PIN23_INT_ENA + 13 + 5 + + + PIN23_CONFIG + 11 + 2 + + + PIN23_WAKEUP_ENABLE + 10 + 1 + + + PIN23_INT_TYPE + 7 + 3 + + + PIN23_PAD_DRIVER + 2 + 1 + + + + + PIN24 + 0xe8 + GPIO_PIN24 + 32 + 0x00000000 + + + PIN24_INT_ENA + 13 + 5 + + + PIN24_CONFIG + 11 + 2 + + + PIN24_WAKEUP_ENABLE + 10 + 1 + + + PIN24_INT_TYPE + 7 + 3 + + + PIN24_PAD_DRIVER + 2 + 1 + + + + + PIN25 + 0xec + GPIO_PIN25 + 32 + 0x00000000 + + + PIN25_INT_ENA + 13 + 5 + + + PIN25_CONFIG + 11 + 2 + + + PIN25_WAKEUP_ENABLE + 10 + 1 + + + PIN25_INT_TYPE + 7 + 3 + + + PIN25_PAD_DRIVER + 2 + 1 + + + + + PIN26 + 0xf0 + GPIO_PIN26 + 32 + 0x00000000 + + + PIN26_INT_ENA + 13 + 5 + + + PIN26_CONFIG + 11 + 2 + + + PIN26_WAKEUP_ENABLE + 10 + 1 + + + PIN26_INT_TYPE + 7 + 3 + + + PIN26_PAD_DRIVER + 2 + 1 + + + + + PIN27 + 0xf4 + GPIO_PIN27 + 32 + 0x00000000 + + + PIN27_INT_ENA + 13 + 5 + + + PIN27_CONFIG + 11 + 2 + + + PIN27_WAKEUP_ENABLE + 10 + 1 + + + PIN27_INT_TYPE + 7 + 3 + + + PIN27_PAD_DRIVER + 2 + 1 + + + + + PIN28 + 0xf8 + GPIO_PIN28 + 32 + 0x00000000 + + + PIN28_INT_ENA + 13 + 5 + + + PIN28_CONFIG + 11 + 2 + + + PIN28_WAKEUP_ENABLE + 10 + 1 + + + PIN28_INT_TYPE + 7 + 3 + + + PIN28_PAD_DRIVER + 2 + 1 + + + + + PIN29 + 0xfc + GPIO_PIN29 + 32 + 0x00000000 + + + PIN29_INT_ENA + 13 + 5 + + + PIN29_CONFIG + 11 + 2 + + + PIN29_WAKEUP_ENABLE + 10 + 1 + + + PIN29_INT_TYPE + 7 + 3 + + + PIN29_PAD_DRIVER + 2 + 1 + + + + + PIN30 + 0x100 + GPIO_PIN30 + 32 + 0x00000000 + + + PIN30_INT_ENA + 13 + 5 + + + PIN30_CONFIG + 11 + 2 + + + PIN30_WAKEUP_ENABLE + 10 + 1 + + + PIN30_INT_TYPE + 7 + 3 + + + PIN30_PAD_DRIVER + 2 + 1 + + + + + PIN31 + 0x104 + GPIO_PIN31 + 32 + 0x00000000 + + + PIN31_INT_ENA + 13 + 5 + + + PIN31_CONFIG + 11 + 2 + + + PIN31_WAKEUP_ENABLE + 10 + 1 + + + PIN31_INT_TYPE + 7 + 3 + + + PIN31_PAD_DRIVER + 2 + 1 + + + + + PIN32 + 0x108 + GPIO_PIN32 + 32 + 0x00000000 + + + PIN32_INT_ENA + 13 + 5 + + + PIN32_CONFIG + 11 + 2 + + + PIN32_WAKEUP_ENABLE + 10 + 1 + + + PIN32_INT_TYPE + 7 + 3 + + + PIN32_PAD_DRIVER + 2 + 1 + + + + + PIN33 + 0x10c + GPIO_PIN33 + 32 + 0x00000000 + + + PIN33_INT_ENA + 13 + 5 + + + PIN33_CONFIG + 11 + 2 + + + PIN33_WAKEUP_ENABLE + 10 + 1 + + + PIN33_INT_TYPE + 7 + 3 + + + PIN33_PAD_DRIVER + 2 + 1 + + + + + PIN34 + 0x110 + GPIO_PIN34 + 32 + 0x00000000 + + + PIN34_INT_ENA + 13 + 5 + + + PIN34_CONFIG + 11 + 2 + + + PIN34_WAKEUP_ENABLE + 10 + 1 + + + PIN34_INT_TYPE + 7 + 3 + + + PIN34_PAD_DRIVER + 2 + 1 + + + + + PIN35 + 0x114 + GPIO_PIN35 + 32 + 0x00000000 + + + PIN35_INT_ENA + 13 + 5 + + + PIN35_CONFIG + 11 + 2 + + + PIN35_WAKEUP_ENABLE + 10 + 1 + + + PIN35_INT_TYPE + 7 + 3 + + + PIN35_PAD_DRIVER + 2 + 1 + + + + + PIN36 + 0x118 + GPIO_PIN36 + 32 + 0x00000000 + + + PIN36_INT_ENA + 13 + 5 + + + PIN36_CONFIG + 11 + 2 + + + PIN36_WAKEUP_ENABLE + 10 + 1 + + + PIN36_INT_TYPE + 7 + 3 + + + PIN36_PAD_DRIVER + 2 + 1 + + + + + PIN37 + 0x11c + GPIO_PIN37 + 32 + 0x00000000 + + + PIN37_INT_ENA + 13 + 5 + + + PIN37_CONFIG + 11 + 2 + + + PIN37_WAKEUP_ENABLE + 10 + 1 + + + PIN37_INT_TYPE + 7 + 3 + + + PIN37_PAD_DRIVER + 2 + 1 + + + + + PIN38 + 0x120 + GPIO_PIN38 + 32 + 0x00000000 + + + PIN38_INT_ENA + 13 + 5 + + + PIN38_CONFIG + 11 + 2 + + + PIN38_WAKEUP_ENABLE + 10 + 1 + + + PIN38_INT_TYPE + 7 + 3 + + + PIN38_PAD_DRIVER + 2 + 1 + + + + + PIN39 + 0x124 + GPIO_PIN39 + 32 + 0x00000000 + + + PIN39_INT_ENA + 13 + 5 + + + PIN39_CONFIG + 11 + 2 + + + PIN39_WAKEUP_ENABLE + 10 + 1 + + + PIN39_INT_TYPE + 7 + 3 + + + PIN39_PAD_DRIVER + 2 + 1 + + + + + cali_conf + 0x128 + GPIO_cali_conf + 32 + 0x00000000 + + + CALI_START + 31 + 1 + + + CALI_RTC_MAX + 0 + 10 + + + + + cali_data + 0x12c + GPIO_cali_data + 32 + 0x00000000 + + + CALI_RDY_SYNC2 + 31 + 1 + + + CALI_RDY_REAL + 30 + 1 + + + CALI_VALUE_SYNC2 + 0 + 20 + + + + + FUNC0_IN_SEL_CFG + 0x130 + GPIO_FUNC0_IN_SEL_CFG + 32 + 0x00000000 + + + SIG0_IN_SEL + 7 + 1 + + + FUNC0_IN_INV_SEL + 6 + 1 + + + FUNC0_IN_SEL + 0 + 6 + + + + + FUNC1_IN_SEL_CFG + 0x134 + GPIO_FUNC1_IN_SEL_CFG + 32 + 0x00000000 + + + SIG1_IN_SEL + 7 + 1 + + + FUNC1_IN_INV_SEL + 6 + 1 + + + FUNC1_IN_SEL + 0 + 6 + + + + + FUNC2_IN_SEL_CFG + 0x138 + GPIO_FUNC2_IN_SEL_CFG + 32 + 0x00000000 + + + SIG2_IN_SEL + 7 + 1 + + + FUNC2_IN_INV_SEL + 6 + 1 + + + FUNC2_IN_SEL + 0 + 6 + + + + + FUNC3_IN_SEL_CFG + 0x13c + GPIO_FUNC3_IN_SEL_CFG + 32 + 0x00000000 + + + SIG3_IN_SEL + 7 + 1 + + + FUNC3_IN_INV_SEL + 6 + 1 + + + FUNC3_IN_SEL + 0 + 6 + + + + + FUNC4_IN_SEL_CFG + 0x140 + GPIO_FUNC4_IN_SEL_CFG + 32 + 0x00000000 + + + SIG4_IN_SEL + 7 + 1 + + + FUNC4_IN_INV_SEL + 6 + 1 + + + FUNC4_IN_SEL + 0 + 6 + + + + + FUNC5_IN_SEL_CFG + 0x144 + GPIO_FUNC5_IN_SEL_CFG + 32 + 0x00000000 + + + SIG5_IN_SEL + 7 + 1 + + + FUNC5_IN_INV_SEL + 6 + 1 + + + FUNC5_IN_SEL + 0 + 6 + + + + + FUNC6_IN_SEL_CFG + 0x148 + GPIO_FUNC6_IN_SEL_CFG + 32 + 0x00000000 + + + SIG6_IN_SEL + 7 + 1 + + + FUNC6_IN_INV_SEL + 6 + 1 + + + FUNC6_IN_SEL + 0 + 6 + + + + + FUNC7_IN_SEL_CFG + 0x14c + GPIO_FUNC7_IN_SEL_CFG + 32 + 0x00000000 + + + SIG7_IN_SEL + 7 + 1 + + + FUNC7_IN_INV_SEL + 6 + 1 + + + FUNC7_IN_SEL + 0 + 6 + + + + + FUNC8_IN_SEL_CFG + 0x150 + GPIO_FUNC8_IN_SEL_CFG + 32 + 0x00000000 + + + SIG8_IN_SEL + 7 + 1 + + + FUNC8_IN_INV_SEL + 6 + 1 + + + FUNC8_IN_SEL + 0 + 6 + + + + + FUNC9_IN_SEL_CFG + 0x154 + GPIO_FUNC9_IN_SEL_CFG + 32 + 0x00000000 + + + SIG9_IN_SEL + 7 + 1 + + + FUNC9_IN_INV_SEL + 6 + 1 + + + FUNC9_IN_SEL + 0 + 6 + + + + + FUNC10_IN_SEL_CFG + 0x158 + GPIO_FUNC10_IN_SEL_CFG + 32 + 0x00000000 + + + SIG10_IN_SEL + 7 + 1 + + + FUNC10_IN_INV_SEL + 6 + 1 + + + FUNC10_IN_SEL + 0 + 6 + + + + + FUNC11_IN_SEL_CFG + 0x15c + GPIO_FUNC11_IN_SEL_CFG + 32 + 0x00000000 + + + SIG11_IN_SEL + 7 + 1 + + + FUNC11_IN_INV_SEL + 6 + 1 + + + FUNC11_IN_SEL + 0 + 6 + + + + + FUNC12_IN_SEL_CFG + 0x160 + GPIO_FUNC12_IN_SEL_CFG + 32 + 0x00000000 + + + SIG12_IN_SEL + 7 + 1 + + + FUNC12_IN_INV_SEL + 6 + 1 + + + FUNC12_IN_SEL + 0 + 6 + + + + + FUNC13_IN_SEL_CFG + 0x164 + GPIO_FUNC13_IN_SEL_CFG + 32 + 0x00000000 + + + SIG13_IN_SEL + 7 + 1 + + + FUNC13_IN_INV_SEL + 6 + 1 + + + FUNC13_IN_SEL + 0 + 6 + + + + + FUNC14_IN_SEL_CFG + 0x168 + GPIO_FUNC14_IN_SEL_CFG + 32 + 0x00000000 + + + SIG14_IN_SEL + 7 + 1 + + + FUNC14_IN_INV_SEL + 6 + 1 + + + FUNC14_IN_SEL + 0 + 6 + + + + + FUNC15_IN_SEL_CFG + 0x16c + GPIO_FUNC15_IN_SEL_CFG + 32 + 0x00000000 + + + SIG15_IN_SEL + 7 + 1 + + + FUNC15_IN_INV_SEL + 6 + 1 + + + FUNC15_IN_SEL + 0 + 6 + + + + + FUNC16_IN_SEL_CFG + 0x170 + GPIO_FUNC16_IN_SEL_CFG + 32 + 0x00000000 + + + SIG16_IN_SEL + 7 + 1 + + + FUNC16_IN_INV_SEL + 6 + 1 + + + FUNC16_IN_SEL + 0 + 6 + + + + + FUNC17_IN_SEL_CFG + 0x174 + GPIO_FUNC17_IN_SEL_CFG + 32 + 0x00000000 + + + SIG17_IN_SEL + 7 + 1 + + + FUNC17_IN_INV_SEL + 6 + 1 + + + FUNC17_IN_SEL + 0 + 6 + + + + + FUNC18_IN_SEL_CFG + 0x178 + GPIO_FUNC18_IN_SEL_CFG + 32 + 0x00000000 + + + SIG18_IN_SEL + 7 + 1 + + + FUNC18_IN_INV_SEL + 6 + 1 + + + FUNC18_IN_SEL + 0 + 6 + + + + + FUNC19_IN_SEL_CFG + 0x17c + GPIO_FUNC19_IN_SEL_CFG + 32 + 0x00000000 + + + SIG19_IN_SEL + 7 + 1 + + + FUNC19_IN_INV_SEL + 6 + 1 + + + FUNC19_IN_SEL + 0 + 6 + + + + + FUNC20_IN_SEL_CFG + 0x180 + GPIO_FUNC20_IN_SEL_CFG + 32 + 0x00000000 + + + SIG20_IN_SEL + 7 + 1 + + + FUNC20_IN_INV_SEL + 6 + 1 + + + FUNC20_IN_SEL + 0 + 6 + + + + + FUNC21_IN_SEL_CFG + 0x184 + GPIO_FUNC21_IN_SEL_CFG + 32 + 0x00000000 + + + SIG21_IN_SEL + 7 + 1 + + + FUNC21_IN_INV_SEL + 6 + 1 + + + FUNC21_IN_SEL + 0 + 6 + + + + + FUNC22_IN_SEL_CFG + 0x188 + GPIO_FUNC22_IN_SEL_CFG + 32 + 0x00000000 + + + SIG22_IN_SEL + 7 + 1 + + + FUNC22_IN_INV_SEL + 6 + 1 + + + FUNC22_IN_SEL + 0 + 6 + + + + + FUNC23_IN_SEL_CFG + 0x18c + GPIO_FUNC23_IN_SEL_CFG + 32 + 0x00000000 + + + SIG23_IN_SEL + 7 + 1 + + + FUNC23_IN_INV_SEL + 6 + 1 + + + FUNC23_IN_SEL + 0 + 6 + + + + + FUNC24_IN_SEL_CFG + 0x190 + GPIO_FUNC24_IN_SEL_CFG + 32 + 0x00000000 + + + SIG24_IN_SEL + 7 + 1 + + + FUNC24_IN_INV_SEL + 6 + 1 + + + FUNC24_IN_SEL + 0 + 6 + + + + + FUNC25_IN_SEL_CFG + 0x194 + GPIO_FUNC25_IN_SEL_CFG + 32 + 0x00000000 + + + SIG25_IN_SEL + 7 + 1 + + + FUNC25_IN_INV_SEL + 6 + 1 + + + FUNC25_IN_SEL + 0 + 6 + + + + + FUNC26_IN_SEL_CFG + 0x198 + GPIO_FUNC26_IN_SEL_CFG + 32 + 0x00000000 + + + SIG26_IN_SEL + 7 + 1 + + + FUNC26_IN_INV_SEL + 6 + 1 + + + FUNC26_IN_SEL + 0 + 6 + + + + + FUNC27_IN_SEL_CFG + 0x19c + GPIO_FUNC27_IN_SEL_CFG + 32 + 0x00000000 + + + SIG27_IN_SEL + 7 + 1 + + + FUNC27_IN_INV_SEL + 6 + 1 + + + FUNC27_IN_SEL + 0 + 6 + + + + + FUNC28_IN_SEL_CFG + 0x1a0 + GPIO_FUNC28_IN_SEL_CFG + 32 + 0x00000000 + + + SIG28_IN_SEL + 7 + 1 + + + FUNC28_IN_INV_SEL + 6 + 1 + + + FUNC28_IN_SEL + 0 + 6 + + + + + FUNC29_IN_SEL_CFG + 0x1a4 + GPIO_FUNC29_IN_SEL_CFG + 32 + 0x00000000 + + + SIG29_IN_SEL + 7 + 1 + + + FUNC29_IN_INV_SEL + 6 + 1 + + + FUNC29_IN_SEL + 0 + 6 + + + + + FUNC30_IN_SEL_CFG + 0x1a8 + GPIO_FUNC30_IN_SEL_CFG + 32 + 0x00000000 + + + SIG30_IN_SEL + 7 + 1 + + + FUNC30_IN_INV_SEL + 6 + 1 + + + FUNC30_IN_SEL + 0 + 6 + + + + + FUNC31_IN_SEL_CFG + 0x1ac + GPIO_FUNC31_IN_SEL_CFG + 32 + 0x00000000 + + + SIG31_IN_SEL + 7 + 1 + + + FUNC31_IN_INV_SEL + 6 + 1 + + + FUNC31_IN_SEL + 0 + 6 + + + + + FUNC32_IN_SEL_CFG + 0x1b0 + GPIO_FUNC32_IN_SEL_CFG + 32 + 0x00000000 + + + SIG32_IN_SEL + 7 + 1 + + + FUNC32_IN_INV_SEL + 6 + 1 + + + FUNC32_IN_SEL + 0 + 6 + + + + + FUNC33_IN_SEL_CFG + 0x1b4 + GPIO_FUNC33_IN_SEL_CFG + 32 + 0x00000000 + + + SIG33_IN_SEL + 7 + 1 + + + FUNC33_IN_INV_SEL + 6 + 1 + + + FUNC33_IN_SEL + 0 + 6 + + + + + FUNC34_IN_SEL_CFG + 0x1b8 + GPIO_FUNC34_IN_SEL_CFG + 32 + 0x00000000 + + + SIG34_IN_SEL + 7 + 1 + + + FUNC34_IN_INV_SEL + 6 + 1 + + + FUNC34_IN_SEL + 0 + 6 + + + + + FUNC35_IN_SEL_CFG + 0x1bc + GPIO_FUNC35_IN_SEL_CFG + 32 + 0x00000000 + + + SIG35_IN_SEL + 7 + 1 + + + FUNC35_IN_INV_SEL + 6 + 1 + + + FUNC35_IN_SEL + 0 + 6 + + + + + FUNC36_IN_SEL_CFG + 0x1c0 + GPIO_FUNC36_IN_SEL_CFG + 32 + 0x00000000 + + + SIG36_IN_SEL + 7 + 1 + + + FUNC36_IN_INV_SEL + 6 + 1 + + + FUNC36_IN_SEL + 0 + 6 + + + + + FUNC37_IN_SEL_CFG + 0x1c4 + GPIO_FUNC37_IN_SEL_CFG + 32 + 0x00000000 + + + SIG37_IN_SEL + 7 + 1 + + + FUNC37_IN_INV_SEL + 6 + 1 + + + FUNC37_IN_SEL + 0 + 6 + + + + + FUNC38_IN_SEL_CFG + 0x1c8 + GPIO_FUNC38_IN_SEL_CFG + 32 + 0x00000000 + + + SIG38_IN_SEL + 7 + 1 + + + FUNC38_IN_INV_SEL + 6 + 1 + + + FUNC38_IN_SEL + 0 + 6 + + + + + FUNC39_IN_SEL_CFG + 0x1cc + GPIO_FUNC39_IN_SEL_CFG + 32 + 0x00000000 + + + SIG39_IN_SEL + 7 + 1 + + + FUNC39_IN_INV_SEL + 6 + 1 + + + FUNC39_IN_SEL + 0 + 6 + + + + + FUNC40_IN_SEL_CFG + 0x1d0 + GPIO_FUNC40_IN_SEL_CFG + 32 + 0x00000000 + + + SIG40_IN_SEL + 7 + 1 + + + FUNC40_IN_INV_SEL + 6 + 1 + + + FUNC40_IN_SEL + 0 + 6 + + + + + FUNC41_IN_SEL_CFG + 0x1d4 + GPIO_FUNC41_IN_SEL_CFG + 32 + 0x00000000 + + + SIG41_IN_SEL + 7 + 1 + + + FUNC41_IN_INV_SEL + 6 + 1 + + + FUNC41_IN_SEL + 0 + 6 + + + + + FUNC42_IN_SEL_CFG + 0x1d8 + GPIO_FUNC42_IN_SEL_CFG + 32 + 0x00000000 + + + SIG42_IN_SEL + 7 + 1 + + + FUNC42_IN_INV_SEL + 6 + 1 + + + FUNC42_IN_SEL + 0 + 6 + + + + + FUNC43_IN_SEL_CFG + 0x1dc + GPIO_FUNC43_IN_SEL_CFG + 32 + 0x00000000 + + + SIG43_IN_SEL + 7 + 1 + + + FUNC43_IN_INV_SEL + 6 + 1 + + + FUNC43_IN_SEL + 0 + 6 + + + + + FUNC44_IN_SEL_CFG + 0x1e0 + GPIO_FUNC44_IN_SEL_CFG + 32 + 0x00000000 + + + SIG44_IN_SEL + 7 + 1 + + + FUNC44_IN_INV_SEL + 6 + 1 + + + FUNC44_IN_SEL + 0 + 6 + + + + + FUNC45_IN_SEL_CFG + 0x1e4 + GPIO_FUNC45_IN_SEL_CFG + 32 + 0x00000000 + + + SIG45_IN_SEL + 7 + 1 + + + FUNC45_IN_INV_SEL + 6 + 1 + + + FUNC45_IN_SEL + 0 + 6 + + + + + FUNC46_IN_SEL_CFG + 0x1e8 + GPIO_FUNC46_IN_SEL_CFG + 32 + 0x00000000 + + + SIG46_IN_SEL + 7 + 1 + + + FUNC46_IN_INV_SEL + 6 + 1 + + + FUNC46_IN_SEL + 0 + 6 + + + + + FUNC47_IN_SEL_CFG + 0x1ec + GPIO_FUNC47_IN_SEL_CFG + 32 + 0x00000000 + + + SIG47_IN_SEL + 7 + 1 + + + FUNC47_IN_INV_SEL + 6 + 1 + + + FUNC47_IN_SEL + 0 + 6 + + + + + FUNC48_IN_SEL_CFG + 0x1f0 + GPIO_FUNC48_IN_SEL_CFG + 32 + 0x00000000 + + + SIG48_IN_SEL + 7 + 1 + + + FUNC48_IN_INV_SEL + 6 + 1 + + + FUNC48_IN_SEL + 0 + 6 + + + + + FUNC49_IN_SEL_CFG + 0x1f4 + GPIO_FUNC49_IN_SEL_CFG + 32 + 0x00000000 + + + SIG49_IN_SEL + 7 + 1 + + + FUNC49_IN_INV_SEL + 6 + 1 + + + FUNC49_IN_SEL + 0 + 6 + + + + + FUNC50_IN_SEL_CFG + 0x1f8 + GPIO_FUNC50_IN_SEL_CFG + 32 + 0x00000000 + + + SIG50_IN_SEL + 7 + 1 + + + FUNC50_IN_INV_SEL + 6 + 1 + + + FUNC50_IN_SEL + 0 + 6 + + + + + FUNC51_IN_SEL_CFG + 0x1fc + GPIO_FUNC51_IN_SEL_CFG + 32 + 0x00000000 + + + SIG51_IN_SEL + 7 + 1 + + + FUNC51_IN_INV_SEL + 6 + 1 + + + FUNC51_IN_SEL + 0 + 6 + + + + + FUNC52_IN_SEL_CFG + 0x200 + GPIO_FUNC52_IN_SEL_CFG + 32 + 0x00000000 + + + SIG52_IN_SEL + 7 + 1 + + + FUNC52_IN_INV_SEL + 6 + 1 + + + FUNC52_IN_SEL + 0 + 6 + + + + + FUNC53_IN_SEL_CFG + 0x204 + GPIO_FUNC53_IN_SEL_CFG + 32 + 0x00000000 + + + SIG53_IN_SEL + 7 + 1 + + + FUNC53_IN_INV_SEL + 6 + 1 + + + FUNC53_IN_SEL + 0 + 6 + + + + + FUNC54_IN_SEL_CFG + 0x208 + GPIO_FUNC54_IN_SEL_CFG + 32 + 0x00000000 + + + SIG54_IN_SEL + 7 + 1 + + + FUNC54_IN_INV_SEL + 6 + 1 + + + FUNC54_IN_SEL + 0 + 6 + + + + + FUNC55_IN_SEL_CFG + 0x20c + GPIO_FUNC55_IN_SEL_CFG + 32 + 0x00000000 + + + SIG55_IN_SEL + 7 + 1 + + + FUNC55_IN_INV_SEL + 6 + 1 + + + FUNC55_IN_SEL + 0 + 6 + + + + + FUNC56_IN_SEL_CFG + 0x210 + GPIO_FUNC56_IN_SEL_CFG + 32 + 0x00000000 + + + SIG56_IN_SEL + 7 + 1 + + + FUNC56_IN_INV_SEL + 6 + 1 + + + FUNC56_IN_SEL + 0 + 6 + + + + + FUNC57_IN_SEL_CFG + 0x214 + GPIO_FUNC57_IN_SEL_CFG + 32 + 0x00000000 + + + SIG57_IN_SEL + 7 + 1 + + + FUNC57_IN_INV_SEL + 6 + 1 + + + FUNC57_IN_SEL + 0 + 6 + + + + + FUNC58_IN_SEL_CFG + 0x218 + GPIO_FUNC58_IN_SEL_CFG + 32 + 0x00000000 + + + SIG58_IN_SEL + 7 + 1 + + + FUNC58_IN_INV_SEL + 6 + 1 + + + FUNC58_IN_SEL + 0 + 6 + + + + + FUNC59_IN_SEL_CFG + 0x21c + GPIO_FUNC59_IN_SEL_CFG + 32 + 0x00000000 + + + SIG59_IN_SEL + 7 + 1 + + + FUNC59_IN_INV_SEL + 6 + 1 + + + FUNC59_IN_SEL + 0 + 6 + + + + + FUNC60_IN_SEL_CFG + 0x220 + GPIO_FUNC60_IN_SEL_CFG + 32 + 0x00000000 + + + SIG60_IN_SEL + 7 + 1 + + + FUNC60_IN_INV_SEL + 6 + 1 + + + FUNC60_IN_SEL + 0 + 6 + + + + + FUNC61_IN_SEL_CFG + 0x224 + GPIO_FUNC61_IN_SEL_CFG + 32 + 0x00000000 + + + SIG61_IN_SEL + 7 + 1 + + + FUNC61_IN_INV_SEL + 6 + 1 + + + FUNC61_IN_SEL + 0 + 6 + + + + + FUNC62_IN_SEL_CFG + 0x228 + GPIO_FUNC62_IN_SEL_CFG + 32 + 0x00000000 + + + SIG62_IN_SEL + 7 + 1 + + + FUNC62_IN_INV_SEL + 6 + 1 + + + FUNC62_IN_SEL + 0 + 6 + + + + + FUNC63_IN_SEL_CFG + 0x22c + GPIO_FUNC63_IN_SEL_CFG + 32 + 0x00000000 + + + SIG63_IN_SEL + 7 + 1 + + + FUNC63_IN_INV_SEL + 6 + 1 + + + FUNC63_IN_SEL + 0 + 6 + + + + + FUNC64_IN_SEL_CFG + 0x230 + GPIO_FUNC64_IN_SEL_CFG + 32 + 0x00000000 + + + SIG64_IN_SEL + 7 + 1 + + + FUNC64_IN_INV_SEL + 6 + 1 + + + FUNC64_IN_SEL + 0 + 6 + + + + + FUNC65_IN_SEL_CFG + 0x234 + GPIO_FUNC65_IN_SEL_CFG + 32 + 0x00000000 + + + SIG65_IN_SEL + 7 + 1 + + + FUNC65_IN_INV_SEL + 6 + 1 + + + FUNC65_IN_SEL + 0 + 6 + + + + + FUNC66_IN_SEL_CFG + 0x238 + GPIO_FUNC66_IN_SEL_CFG + 32 + 0x00000000 + + + SIG66_IN_SEL + 7 + 1 + + + FUNC66_IN_INV_SEL + 6 + 1 + + + FUNC66_IN_SEL + 0 + 6 + + + + + FUNC67_IN_SEL_CFG + 0x23c + GPIO_FUNC67_IN_SEL_CFG + 32 + 0x00000000 + + + SIG67_IN_SEL + 7 + 1 + + + FUNC67_IN_INV_SEL + 6 + 1 + + + FUNC67_IN_SEL + 0 + 6 + + + + + FUNC68_IN_SEL_CFG + 0x240 + GPIO_FUNC68_IN_SEL_CFG + 32 + 0x00000000 + + + SIG68_IN_SEL + 7 + 1 + + + FUNC68_IN_INV_SEL + 6 + 1 + + + FUNC68_IN_SEL + 0 + 6 + + + + + FUNC69_IN_SEL_CFG + 0x244 + GPIO_FUNC69_IN_SEL_CFG + 32 + 0x00000000 + + + SIG69_IN_SEL + 7 + 1 + + + FUNC69_IN_INV_SEL + 6 + 1 + + + FUNC69_IN_SEL + 0 + 6 + + + + + FUNC70_IN_SEL_CFG + 0x248 + GPIO_FUNC70_IN_SEL_CFG + 32 + 0x00000000 + + + SIG70_IN_SEL + 7 + 1 + + + FUNC70_IN_INV_SEL + 6 + 1 + + + FUNC70_IN_SEL + 0 + 6 + + + + + FUNC71_IN_SEL_CFG + 0x24c + GPIO_FUNC71_IN_SEL_CFG + 32 + 0x00000000 + + + SIG71_IN_SEL + 7 + 1 + + + FUNC71_IN_INV_SEL + 6 + 1 + + + FUNC71_IN_SEL + 0 + 6 + + + + + FUNC72_IN_SEL_CFG + 0x250 + GPIO_FUNC72_IN_SEL_CFG + 32 + 0x00000000 + + + SIG72_IN_SEL + 7 + 1 + + + FUNC72_IN_INV_SEL + 6 + 1 + + + FUNC72_IN_SEL + 0 + 6 + + + + + FUNC73_IN_SEL_CFG + 0x254 + GPIO_FUNC73_IN_SEL_CFG + 32 + 0x00000000 + + + SIG73_IN_SEL + 7 + 1 + + + FUNC73_IN_INV_SEL + 6 + 1 + + + FUNC73_IN_SEL + 0 + 6 + + + + + FUNC74_IN_SEL_CFG + 0x258 + GPIO_FUNC74_IN_SEL_CFG + 32 + 0x00000000 + + + SIG74_IN_SEL + 7 + 1 + + + FUNC74_IN_INV_SEL + 6 + 1 + + + FUNC74_IN_SEL + 0 + 6 + + + + + FUNC75_IN_SEL_CFG + 0x25c + GPIO_FUNC75_IN_SEL_CFG + 32 + 0x00000000 + + + SIG75_IN_SEL + 7 + 1 + + + FUNC75_IN_INV_SEL + 6 + 1 + + + FUNC75_IN_SEL + 0 + 6 + + + + + FUNC76_IN_SEL_CFG + 0x260 + GPIO_FUNC76_IN_SEL_CFG + 32 + 0x00000000 + + + SIG76_IN_SEL + 7 + 1 + + + FUNC76_IN_INV_SEL + 6 + 1 + + + FUNC76_IN_SEL + 0 + 6 + + + + + FUNC77_IN_SEL_CFG + 0x264 + GPIO_FUNC77_IN_SEL_CFG + 32 + 0x00000000 + + + SIG77_IN_SEL + 7 + 1 + + + FUNC77_IN_INV_SEL + 6 + 1 + + + FUNC77_IN_SEL + 0 + 6 + + + + + FUNC78_IN_SEL_CFG + 0x268 + GPIO_FUNC78_IN_SEL_CFG + 32 + 0x00000000 + + + SIG78_IN_SEL + 7 + 1 + + + FUNC78_IN_INV_SEL + 6 + 1 + + + FUNC78_IN_SEL + 0 + 6 + + + + + FUNC79_IN_SEL_CFG + 0x26c + GPIO_FUNC79_IN_SEL_CFG + 32 + 0x00000000 + + + SIG79_IN_SEL + 7 + 1 + + + FUNC79_IN_INV_SEL + 6 + 1 + + + FUNC79_IN_SEL + 0 + 6 + + + + + FUNC80_IN_SEL_CFG + 0x270 + GPIO_FUNC80_IN_SEL_CFG + 32 + 0x00000000 + + + SIG80_IN_SEL + 7 + 1 + + + FUNC80_IN_INV_SEL + 6 + 1 + + + FUNC80_IN_SEL + 0 + 6 + + + + + FUNC81_IN_SEL_CFG + 0x274 + GPIO_FUNC81_IN_SEL_CFG + 32 + 0x00000000 + + + SIG81_IN_SEL + 7 + 1 + + + FUNC81_IN_INV_SEL + 6 + 1 + + + FUNC81_IN_SEL + 0 + 6 + + + + + FUNC82_IN_SEL_CFG + 0x278 + GPIO_FUNC82_IN_SEL_CFG + 32 + 0x00000000 + + + SIG82_IN_SEL + 7 + 1 + + + FUNC82_IN_INV_SEL + 6 + 1 + + + FUNC82_IN_SEL + 0 + 6 + + + + + FUNC83_IN_SEL_CFG + 0x27c + GPIO_FUNC83_IN_SEL_CFG + 32 + 0x00000000 + + + SIG83_IN_SEL + 7 + 1 + + + FUNC83_IN_INV_SEL + 6 + 1 + + + FUNC83_IN_SEL + 0 + 6 + + + + + FUNC84_IN_SEL_CFG + 0x280 + GPIO_FUNC84_IN_SEL_CFG + 32 + 0x00000000 + + + SIG84_IN_SEL + 7 + 1 + + + FUNC84_IN_INV_SEL + 6 + 1 + + + FUNC84_IN_SEL + 0 + 6 + + + + + FUNC85_IN_SEL_CFG + 0x284 + GPIO_FUNC85_IN_SEL_CFG + 32 + 0x00000000 + + + SIG85_IN_SEL + 7 + 1 + + + FUNC85_IN_INV_SEL + 6 + 1 + + + FUNC85_IN_SEL + 0 + 6 + + + + + FUNC86_IN_SEL_CFG + 0x288 + GPIO_FUNC86_IN_SEL_CFG + 32 + 0x00000000 + + + SIG86_IN_SEL + 7 + 1 + + + FUNC86_IN_INV_SEL + 6 + 1 + + + FUNC86_IN_SEL + 0 + 6 + + + + + FUNC87_IN_SEL_CFG + 0x28c + GPIO_FUNC87_IN_SEL_CFG + 32 + 0x00000000 + + + SIG87_IN_SEL + 7 + 1 + + + FUNC87_IN_INV_SEL + 6 + 1 + + + FUNC87_IN_SEL + 0 + 6 + + + + + FUNC88_IN_SEL_CFG + 0x290 + GPIO_FUNC88_IN_SEL_CFG + 32 + 0x00000000 + + + SIG88_IN_SEL + 7 + 1 + + + FUNC88_IN_INV_SEL + 6 + 1 + + + FUNC88_IN_SEL + 0 + 6 + + + + + FUNC89_IN_SEL_CFG + 0x294 + GPIO_FUNC89_IN_SEL_CFG + 32 + 0x00000000 + + + SIG89_IN_SEL + 7 + 1 + + + FUNC89_IN_INV_SEL + 6 + 1 + + + FUNC89_IN_SEL + 0 + 6 + + + + + FUNC90_IN_SEL_CFG + 0x298 + GPIO_FUNC90_IN_SEL_CFG + 32 + 0x00000000 + + + SIG90_IN_SEL + 7 + 1 + + + FUNC90_IN_INV_SEL + 6 + 1 + + + FUNC90_IN_SEL + 0 + 6 + + + + + FUNC91_IN_SEL_CFG + 0x29c + GPIO_FUNC91_IN_SEL_CFG + 32 + 0x00000000 + + + SIG91_IN_SEL + 7 + 1 + + + FUNC91_IN_INV_SEL + 6 + 1 + + + FUNC91_IN_SEL + 0 + 6 + + + + + FUNC92_IN_SEL_CFG + 0x2a0 + GPIO_FUNC92_IN_SEL_CFG + 32 + 0x00000000 + + + SIG92_IN_SEL + 7 + 1 + + + FUNC92_IN_INV_SEL + 6 + 1 + + + FUNC92_IN_SEL + 0 + 6 + + + + + FUNC93_IN_SEL_CFG + 0x2a4 + GPIO_FUNC93_IN_SEL_CFG + 32 + 0x00000000 + + + SIG93_IN_SEL + 7 + 1 + + + FUNC93_IN_INV_SEL + 6 + 1 + + + FUNC93_IN_SEL + 0 + 6 + + + + + FUNC94_IN_SEL_CFG + 0x2a8 + GPIO_FUNC94_IN_SEL_CFG + 32 + 0x00000000 + + + SIG94_IN_SEL + 7 + 1 + + + FUNC94_IN_INV_SEL + 6 + 1 + + + FUNC94_IN_SEL + 0 + 6 + + + + + FUNC95_IN_SEL_CFG + 0x2ac + GPIO_FUNC95_IN_SEL_CFG + 32 + 0x00000000 + + + SIG95_IN_SEL + 7 + 1 + + + FUNC95_IN_INV_SEL + 6 + 1 + + + FUNC95_IN_SEL + 0 + 6 + + + + + FUNC96_IN_SEL_CFG + 0x2b0 + GPIO_FUNC96_IN_SEL_CFG + 32 + 0x00000000 + + + SIG96_IN_SEL + 7 + 1 + + + FUNC96_IN_INV_SEL + 6 + 1 + + + FUNC96_IN_SEL + 0 + 6 + + + + + FUNC97_IN_SEL_CFG + 0x2b4 + GPIO_FUNC97_IN_SEL_CFG + 32 + 0x00000000 + + + SIG97_IN_SEL + 7 + 1 + + + FUNC97_IN_INV_SEL + 6 + 1 + + + FUNC97_IN_SEL + 0 + 6 + + + + + FUNC98_IN_SEL_CFG + 0x2b8 + GPIO_FUNC98_IN_SEL_CFG + 32 + 0x00000000 + + + SIG98_IN_SEL + 7 + 1 + + + FUNC98_IN_INV_SEL + 6 + 1 + + + FUNC98_IN_SEL + 0 + 6 + + + + + FUNC99_IN_SEL_CFG + 0x2bc + GPIO_FUNC99_IN_SEL_CFG + 32 + 0x00000000 + + + SIG99_IN_SEL + 7 + 1 + + + FUNC99_IN_INV_SEL + 6 + 1 + + + FUNC99_IN_SEL + 0 + 6 + + + + + FUNC100_IN_SEL_CFG + 0x2c0 + GPIO_FUNC100_IN_SEL_CFG + 32 + 0x00000000 + + + SIG100_IN_SEL + 7 + 1 + + + FUNC100_IN_INV_SEL + 6 + 1 + + + FUNC100_IN_SEL + 0 + 6 + + + + + FUNC101_IN_SEL_CFG + 0x2c4 + GPIO_FUNC101_IN_SEL_CFG + 32 + 0x00000000 + + + SIG101_IN_SEL + 7 + 1 + + + FUNC101_IN_INV_SEL + 6 + 1 + + + FUNC101_IN_SEL + 0 + 6 + + + + + FUNC102_IN_SEL_CFG + 0x2c8 + GPIO_FUNC102_IN_SEL_CFG + 32 + 0x00000000 + + + SIG102_IN_SEL + 7 + 1 + + + FUNC102_IN_INV_SEL + 6 + 1 + + + FUNC102_IN_SEL + 0 + 6 + + + + + FUNC103_IN_SEL_CFG + 0x2cc + GPIO_FUNC103_IN_SEL_CFG + 32 + 0x00000000 + + + SIG103_IN_SEL + 7 + 1 + + + FUNC103_IN_INV_SEL + 6 + 1 + + + FUNC103_IN_SEL + 0 + 6 + + + + + FUNC104_IN_SEL_CFG + 0x2d0 + GPIO_FUNC104_IN_SEL_CFG + 32 + 0x00000000 + + + SIG104_IN_SEL + 7 + 1 + + + FUNC104_IN_INV_SEL + 6 + 1 + + + FUNC104_IN_SEL + 0 + 6 + + + + + FUNC105_IN_SEL_CFG + 0x2d4 + GPIO_FUNC105_IN_SEL_CFG + 32 + 0x00000000 + + + SIG105_IN_SEL + 7 + 1 + + + FUNC105_IN_INV_SEL + 6 + 1 + + + FUNC105_IN_SEL + 0 + 6 + + + + + FUNC106_IN_SEL_CFG + 0x2d8 + GPIO_FUNC106_IN_SEL_CFG + 32 + 0x00000000 + + + SIG106_IN_SEL + 7 + 1 + + + FUNC106_IN_INV_SEL + 6 + 1 + + + FUNC106_IN_SEL + 0 + 6 + + + + + FUNC107_IN_SEL_CFG + 0x2dc + GPIO_FUNC107_IN_SEL_CFG + 32 + 0x00000000 + + + SIG107_IN_SEL + 7 + 1 + + + FUNC107_IN_INV_SEL + 6 + 1 + + + FUNC107_IN_SEL + 0 + 6 + + + + + FUNC108_IN_SEL_CFG + 0x2e0 + GPIO_FUNC108_IN_SEL_CFG + 32 + 0x00000000 + + + SIG108_IN_SEL + 7 + 1 + + + FUNC108_IN_INV_SEL + 6 + 1 + + + FUNC108_IN_SEL + 0 + 6 + + + + + FUNC109_IN_SEL_CFG + 0x2e4 + GPIO_FUNC109_IN_SEL_CFG + 32 + 0x00000000 + + + SIG109_IN_SEL + 7 + 1 + + + FUNC109_IN_INV_SEL + 6 + 1 + + + FUNC109_IN_SEL + 0 + 6 + + + + + FUNC110_IN_SEL_CFG + 0x2e8 + GPIO_FUNC110_IN_SEL_CFG + 32 + 0x00000000 + + + SIG110_IN_SEL + 7 + 1 + + + FUNC110_IN_INV_SEL + 6 + 1 + + + FUNC110_IN_SEL + 0 + 6 + + + + + FUNC111_IN_SEL_CFG + 0x2ec + GPIO_FUNC111_IN_SEL_CFG + 32 + 0x00000000 + + + SIG111_IN_SEL + 7 + 1 + + + FUNC111_IN_INV_SEL + 6 + 1 + + + FUNC111_IN_SEL + 0 + 6 + + + + + FUNC112_IN_SEL_CFG + 0x2f0 + GPIO_FUNC112_IN_SEL_CFG + 32 + 0x00000000 + + + SIG112_IN_SEL + 7 + 1 + + + FUNC112_IN_INV_SEL + 6 + 1 + + + FUNC112_IN_SEL + 0 + 6 + + + + + FUNC113_IN_SEL_CFG + 0x2f4 + GPIO_FUNC113_IN_SEL_CFG + 32 + 0x00000000 + + + SIG113_IN_SEL + 7 + 1 + + + FUNC113_IN_INV_SEL + 6 + 1 + + + FUNC113_IN_SEL + 0 + 6 + + + + + FUNC114_IN_SEL_CFG + 0x2f8 + GPIO_FUNC114_IN_SEL_CFG + 32 + 0x00000000 + + + SIG114_IN_SEL + 7 + 1 + + + FUNC114_IN_INV_SEL + 6 + 1 + + + FUNC114_IN_SEL + 0 + 6 + + + + + FUNC115_IN_SEL_CFG + 0x2fc + GPIO_FUNC115_IN_SEL_CFG + 32 + 0x00000000 + + + SIG115_IN_SEL + 7 + 1 + + + FUNC115_IN_INV_SEL + 6 + 1 + + + FUNC115_IN_SEL + 0 + 6 + + + + + FUNC116_IN_SEL_CFG + 0x300 + GPIO_FUNC116_IN_SEL_CFG + 32 + 0x00000000 + + + SIG116_IN_SEL + 7 + 1 + + + FUNC116_IN_INV_SEL + 6 + 1 + + + FUNC116_IN_SEL + 0 + 6 + + + + + FUNC117_IN_SEL_CFG + 0x304 + GPIO_FUNC117_IN_SEL_CFG + 32 + 0x00000000 + + + SIG117_IN_SEL + 7 + 1 + + + FUNC117_IN_INV_SEL + 6 + 1 + + + FUNC117_IN_SEL + 0 + 6 + + + + + FUNC118_IN_SEL_CFG + 0x308 + GPIO_FUNC118_IN_SEL_CFG + 32 + 0x00000000 + + + SIG118_IN_SEL + 7 + 1 + + + FUNC118_IN_INV_SEL + 6 + 1 + + + FUNC118_IN_SEL + 0 + 6 + + + + + FUNC119_IN_SEL_CFG + 0x30c + GPIO_FUNC119_IN_SEL_CFG + 32 + 0x00000000 + + + SIG119_IN_SEL + 7 + 1 + + + FUNC119_IN_INV_SEL + 6 + 1 + + + FUNC119_IN_SEL + 0 + 6 + + + + + FUNC120_IN_SEL_CFG + 0x310 + GPIO_FUNC120_IN_SEL_CFG + 32 + 0x00000000 + + + SIG120_IN_SEL + 7 + 1 + + + FUNC120_IN_INV_SEL + 6 + 1 + + + FUNC120_IN_SEL + 0 + 6 + + + + + FUNC121_IN_SEL_CFG + 0x314 + GPIO_FUNC121_IN_SEL_CFG + 32 + 0x00000000 + + + SIG121_IN_SEL + 7 + 1 + + + FUNC121_IN_INV_SEL + 6 + 1 + + + FUNC121_IN_SEL + 0 + 6 + + + + + FUNC122_IN_SEL_CFG + 0x318 + GPIO_FUNC122_IN_SEL_CFG + 32 + 0x00000000 + + + SIG122_IN_SEL + 7 + 1 + + + FUNC122_IN_INV_SEL + 6 + 1 + + + FUNC122_IN_SEL + 0 + 6 + + + + + FUNC123_IN_SEL_CFG + 0x31c + GPIO_FUNC123_IN_SEL_CFG + 32 + 0x00000000 + + + SIG123_IN_SEL + 7 + 1 + + + FUNC123_IN_INV_SEL + 6 + 1 + + + FUNC123_IN_SEL + 0 + 6 + + + + + FUNC124_IN_SEL_CFG + 0x320 + GPIO_FUNC124_IN_SEL_CFG + 32 + 0x00000000 + + + SIG124_IN_SEL + 7 + 1 + + + FUNC124_IN_INV_SEL + 6 + 1 + + + FUNC124_IN_SEL + 0 + 6 + + + + + FUNC125_IN_SEL_CFG + 0x324 + GPIO_FUNC125_IN_SEL_CFG + 32 + 0x00000000 + + + SIG125_IN_SEL + 7 + 1 + + + FUNC125_IN_INV_SEL + 6 + 1 + + + FUNC125_IN_SEL + 0 + 6 + + + + + FUNC126_IN_SEL_CFG + 0x328 + GPIO_FUNC126_IN_SEL_CFG + 32 + 0x00000000 + + + SIG126_IN_SEL + 7 + 1 + + + FUNC126_IN_INV_SEL + 6 + 1 + + + FUNC126_IN_SEL + 0 + 6 + + + + + FUNC127_IN_SEL_CFG + 0x32c + GPIO_FUNC127_IN_SEL_CFG + 32 + 0x00000000 + + + SIG127_IN_SEL + 7 + 1 + + + FUNC127_IN_INV_SEL + 6 + 1 + + + FUNC127_IN_SEL + 0 + 6 + + + + + FUNC128_IN_SEL_CFG + 0x330 + GPIO_FUNC128_IN_SEL_CFG + 32 + 0x00000000 + + + SIG128_IN_SEL + 7 + 1 + + + FUNC128_IN_INV_SEL + 6 + 1 + + + FUNC128_IN_SEL + 0 + 6 + + + + + FUNC129_IN_SEL_CFG + 0x334 + GPIO_FUNC129_IN_SEL_CFG + 32 + 0x00000000 + + + SIG129_IN_SEL + 7 + 1 + + + FUNC129_IN_INV_SEL + 6 + 1 + + + FUNC129_IN_SEL + 0 + 6 + + + + + FUNC130_IN_SEL_CFG + 0x338 + GPIO_FUNC130_IN_SEL_CFG + 32 + 0x00000000 + + + SIG130_IN_SEL + 7 + 1 + + + FUNC130_IN_INV_SEL + 6 + 1 + + + FUNC130_IN_SEL + 0 + 6 + + + + + FUNC131_IN_SEL_CFG + 0x33c + GPIO_FUNC131_IN_SEL_CFG + 32 + 0x00000000 + + + SIG131_IN_SEL + 7 + 1 + + + FUNC131_IN_INV_SEL + 6 + 1 + + + FUNC131_IN_SEL + 0 + 6 + + + + + FUNC132_IN_SEL_CFG + 0x340 + GPIO_FUNC132_IN_SEL_CFG + 32 + 0x00000000 + + + SIG132_IN_SEL + 7 + 1 + + + FUNC132_IN_INV_SEL + 6 + 1 + + + FUNC132_IN_SEL + 0 + 6 + + + + + FUNC133_IN_SEL_CFG + 0x344 + GPIO_FUNC133_IN_SEL_CFG + 32 + 0x00000000 + + + SIG133_IN_SEL + 7 + 1 + + + FUNC133_IN_INV_SEL + 6 + 1 + + + FUNC133_IN_SEL + 0 + 6 + + + + + FUNC134_IN_SEL_CFG + 0x348 + GPIO_FUNC134_IN_SEL_CFG + 32 + 0x00000000 + + + SIG134_IN_SEL + 7 + 1 + + + FUNC134_IN_INV_SEL + 6 + 1 + + + FUNC134_IN_SEL + 0 + 6 + + + + + FUNC135_IN_SEL_CFG + 0x34c + GPIO_FUNC135_IN_SEL_CFG + 32 + 0x00000000 + + + SIG135_IN_SEL + 7 + 1 + + + FUNC135_IN_INV_SEL + 6 + 1 + + + FUNC135_IN_SEL + 0 + 6 + + + + + FUNC136_IN_SEL_CFG + 0x350 + GPIO_FUNC136_IN_SEL_CFG + 32 + 0x00000000 + + + SIG136_IN_SEL + 7 + 1 + + + FUNC136_IN_INV_SEL + 6 + 1 + + + FUNC136_IN_SEL + 0 + 6 + + + + + FUNC137_IN_SEL_CFG + 0x354 + GPIO_FUNC137_IN_SEL_CFG + 32 + 0x00000000 + + + SIG137_IN_SEL + 7 + 1 + + + FUNC137_IN_INV_SEL + 6 + 1 + + + FUNC137_IN_SEL + 0 + 6 + + + + + FUNC138_IN_SEL_CFG + 0x358 + GPIO_FUNC138_IN_SEL_CFG + 32 + 0x00000000 + + + SIG138_IN_SEL + 7 + 1 + + + FUNC138_IN_INV_SEL + 6 + 1 + + + FUNC138_IN_SEL + 0 + 6 + + + + + FUNC139_IN_SEL_CFG + 0x35c + GPIO_FUNC139_IN_SEL_CFG + 32 + 0x00000000 + + + SIG139_IN_SEL + 7 + 1 + + + FUNC139_IN_INV_SEL + 6 + 1 + + + FUNC139_IN_SEL + 0 + 6 + + + + + FUNC140_IN_SEL_CFG + 0x360 + GPIO_FUNC140_IN_SEL_CFG + 32 + 0x00000000 + + + SIG140_IN_SEL + 7 + 1 + + + FUNC140_IN_INV_SEL + 6 + 1 + + + FUNC140_IN_SEL + 0 + 6 + + + + + FUNC141_IN_SEL_CFG + 0x364 + GPIO_FUNC141_IN_SEL_CFG + 32 + 0x00000000 + + + SIG141_IN_SEL + 7 + 1 + + + FUNC141_IN_INV_SEL + 6 + 1 + + + FUNC141_IN_SEL + 0 + 6 + + + + + FUNC142_IN_SEL_CFG + 0x368 + GPIO_FUNC142_IN_SEL_CFG + 32 + 0x00000000 + + + SIG142_IN_SEL + 7 + 1 + + + FUNC142_IN_INV_SEL + 6 + 1 + + + FUNC142_IN_SEL + 0 + 6 + + + + + FUNC143_IN_SEL_CFG + 0x36c + GPIO_FUNC143_IN_SEL_CFG + 32 + 0x00000000 + + + SIG143_IN_SEL + 7 + 1 + + + FUNC143_IN_INV_SEL + 6 + 1 + + + FUNC143_IN_SEL + 0 + 6 + + + + + FUNC144_IN_SEL_CFG + 0x370 + GPIO_FUNC144_IN_SEL_CFG + 32 + 0x00000000 + + + SIG144_IN_SEL + 7 + 1 + + + FUNC144_IN_INV_SEL + 6 + 1 + + + FUNC144_IN_SEL + 0 + 6 + + + + + FUNC145_IN_SEL_CFG + 0x374 + GPIO_FUNC145_IN_SEL_CFG + 32 + 0x00000000 + + + SIG145_IN_SEL + 7 + 1 + + + FUNC145_IN_INV_SEL + 6 + 1 + + + FUNC145_IN_SEL + 0 + 6 + + + + + FUNC146_IN_SEL_CFG + 0x378 + GPIO_FUNC146_IN_SEL_CFG + 32 + 0x00000000 + + + SIG146_IN_SEL + 7 + 1 + + + FUNC146_IN_INV_SEL + 6 + 1 + + + FUNC146_IN_SEL + 0 + 6 + + + + + FUNC147_IN_SEL_CFG + 0x37c + GPIO_FUNC147_IN_SEL_CFG + 32 + 0x00000000 + + + SIG147_IN_SEL + 7 + 1 + + + FUNC147_IN_INV_SEL + 6 + 1 + + + FUNC147_IN_SEL + 0 + 6 + + + + + FUNC148_IN_SEL_CFG + 0x380 + GPIO_FUNC148_IN_SEL_CFG + 32 + 0x00000000 + + + SIG148_IN_SEL + 7 + 1 + + + FUNC148_IN_INV_SEL + 6 + 1 + + + FUNC148_IN_SEL + 0 + 6 + + + + + FUNC149_IN_SEL_CFG + 0x384 + GPIO_FUNC149_IN_SEL_CFG + 32 + 0x00000000 + + + SIG149_IN_SEL + 7 + 1 + + + FUNC149_IN_INV_SEL + 6 + 1 + + + FUNC149_IN_SEL + 0 + 6 + + + + + FUNC150_IN_SEL_CFG + 0x388 + GPIO_FUNC150_IN_SEL_CFG + 32 + 0x00000000 + + + SIG150_IN_SEL + 7 + 1 + + + FUNC150_IN_INV_SEL + 6 + 1 + + + FUNC150_IN_SEL + 0 + 6 + + + + + FUNC151_IN_SEL_CFG + 0x38c + GPIO_FUNC151_IN_SEL_CFG + 32 + 0x00000000 + + + SIG151_IN_SEL + 7 + 1 + + + FUNC151_IN_INV_SEL + 6 + 1 + + + FUNC151_IN_SEL + 0 + 6 + + + + + FUNC152_IN_SEL_CFG + 0x390 + GPIO_FUNC152_IN_SEL_CFG + 32 + 0x00000000 + + + SIG152_IN_SEL + 7 + 1 + + + FUNC152_IN_INV_SEL + 6 + 1 + + + FUNC152_IN_SEL + 0 + 6 + + + + + FUNC153_IN_SEL_CFG + 0x394 + GPIO_FUNC153_IN_SEL_CFG + 32 + 0x00000000 + + + SIG153_IN_SEL + 7 + 1 + + + FUNC153_IN_INV_SEL + 6 + 1 + + + FUNC153_IN_SEL + 0 + 6 + + + + + FUNC154_IN_SEL_CFG + 0x398 + GPIO_FUNC154_IN_SEL_CFG + 32 + 0x00000000 + + + SIG154_IN_SEL + 7 + 1 + + + FUNC154_IN_INV_SEL + 6 + 1 + + + FUNC154_IN_SEL + 0 + 6 + + + + + FUNC155_IN_SEL_CFG + 0x39c + GPIO_FUNC155_IN_SEL_CFG + 32 + 0x00000000 + + + SIG155_IN_SEL + 7 + 1 + + + FUNC155_IN_INV_SEL + 6 + 1 + + + FUNC155_IN_SEL + 0 + 6 + + + + + FUNC156_IN_SEL_CFG + 0x3a0 + GPIO_FUNC156_IN_SEL_CFG + 32 + 0x00000000 + + + SIG156_IN_SEL + 7 + 1 + + + FUNC156_IN_INV_SEL + 6 + 1 + + + FUNC156_IN_SEL + 0 + 6 + + + + + FUNC157_IN_SEL_CFG + 0x3a4 + GPIO_FUNC157_IN_SEL_CFG + 32 + 0x00000000 + + + SIG157_IN_SEL + 7 + 1 + + + FUNC157_IN_INV_SEL + 6 + 1 + + + FUNC157_IN_SEL + 0 + 6 + + + + + FUNC158_IN_SEL_CFG + 0x3a8 + GPIO_FUNC158_IN_SEL_CFG + 32 + 0x00000000 + + + SIG158_IN_SEL + 7 + 1 + + + FUNC158_IN_INV_SEL + 6 + 1 + + + FUNC158_IN_SEL + 0 + 6 + + + + + FUNC159_IN_SEL_CFG + 0x3ac + GPIO_FUNC159_IN_SEL_CFG + 32 + 0x00000000 + + + SIG159_IN_SEL + 7 + 1 + + + FUNC159_IN_INV_SEL + 6 + 1 + + + FUNC159_IN_SEL + 0 + 6 + + + + + FUNC160_IN_SEL_CFG + 0x3b0 + GPIO_FUNC160_IN_SEL_CFG + 32 + 0x00000000 + + + SIG160_IN_SEL + 7 + 1 + + + FUNC160_IN_INV_SEL + 6 + 1 + + + FUNC160_IN_SEL + 0 + 6 + + + + + FUNC161_IN_SEL_CFG + 0x3b4 + GPIO_FUNC161_IN_SEL_CFG + 32 + 0x00000000 + + + SIG161_IN_SEL + 7 + 1 + + + FUNC161_IN_INV_SEL + 6 + 1 + + + FUNC161_IN_SEL + 0 + 6 + + + + + FUNC162_IN_SEL_CFG + 0x3b8 + GPIO_FUNC162_IN_SEL_CFG + 32 + 0x00000000 + + + SIG162_IN_SEL + 7 + 1 + + + FUNC162_IN_INV_SEL + 6 + 1 + + + FUNC162_IN_SEL + 0 + 6 + + + + + FUNC163_IN_SEL_CFG + 0x3bc + GPIO_FUNC163_IN_SEL_CFG + 32 + 0x00000000 + + + SIG163_IN_SEL + 7 + 1 + + + FUNC163_IN_INV_SEL + 6 + 1 + + + FUNC163_IN_SEL + 0 + 6 + + + + + FUNC164_IN_SEL_CFG + 0x3c0 + GPIO_FUNC164_IN_SEL_CFG + 32 + 0x00000000 + + + SIG164_IN_SEL + 7 + 1 + + + FUNC164_IN_INV_SEL + 6 + 1 + + + FUNC164_IN_SEL + 0 + 6 + + + + + FUNC165_IN_SEL_CFG + 0x3c4 + GPIO_FUNC165_IN_SEL_CFG + 32 + 0x00000000 + + + SIG165_IN_SEL + 7 + 1 + + + FUNC165_IN_INV_SEL + 6 + 1 + + + FUNC165_IN_SEL + 0 + 6 + + + + + FUNC166_IN_SEL_CFG + 0x3c8 + GPIO_FUNC166_IN_SEL_CFG + 32 + 0x00000000 + + + SIG166_IN_SEL + 7 + 1 + + + FUNC166_IN_INV_SEL + 6 + 1 + + + FUNC166_IN_SEL + 0 + 6 + + + + + FUNC167_IN_SEL_CFG + 0x3cc + GPIO_FUNC167_IN_SEL_CFG + 32 + 0x00000000 + + + SIG167_IN_SEL + 7 + 1 + + + FUNC167_IN_INV_SEL + 6 + 1 + + + FUNC167_IN_SEL + 0 + 6 + + + + + FUNC168_IN_SEL_CFG + 0x3d0 + GPIO_FUNC168_IN_SEL_CFG + 32 + 0x00000000 + + + SIG168_IN_SEL + 7 + 1 + + + FUNC168_IN_INV_SEL + 6 + 1 + + + FUNC168_IN_SEL + 0 + 6 + + + + + FUNC169_IN_SEL_CFG + 0x3d4 + GPIO_FUNC169_IN_SEL_CFG + 32 + 0x00000000 + + + SIG169_IN_SEL + 7 + 1 + + + FUNC169_IN_INV_SEL + 6 + 1 + + + FUNC169_IN_SEL + 0 + 6 + + + + + FUNC170_IN_SEL_CFG + 0x3d8 + GPIO_FUNC170_IN_SEL_CFG + 32 + 0x00000000 + + + SIG170_IN_SEL + 7 + 1 + + + FUNC170_IN_INV_SEL + 6 + 1 + + + FUNC170_IN_SEL + 0 + 6 + + + + + FUNC171_IN_SEL_CFG + 0x3dc + GPIO_FUNC171_IN_SEL_CFG + 32 + 0x00000000 + + + SIG171_IN_SEL + 7 + 1 + + + FUNC171_IN_INV_SEL + 6 + 1 + + + FUNC171_IN_SEL + 0 + 6 + + + + + FUNC172_IN_SEL_CFG + 0x3e0 + GPIO_FUNC172_IN_SEL_CFG + 32 + 0x00000000 + + + SIG172_IN_SEL + 7 + 1 + + + FUNC172_IN_INV_SEL + 6 + 1 + + + FUNC172_IN_SEL + 0 + 6 + + + + + FUNC173_IN_SEL_CFG + 0x3e4 + GPIO_FUNC173_IN_SEL_CFG + 32 + 0x00000000 + + + SIG173_IN_SEL + 7 + 1 + + + FUNC173_IN_INV_SEL + 6 + 1 + + + FUNC173_IN_SEL + 0 + 6 + + + + + FUNC174_IN_SEL_CFG + 0x3e8 + GPIO_FUNC174_IN_SEL_CFG + 32 + 0x00000000 + + + SIG174_IN_SEL + 7 + 1 + + + FUNC174_IN_INV_SEL + 6 + 1 + + + FUNC174_IN_SEL + 0 + 6 + + + + + FUNC175_IN_SEL_CFG + 0x3ec + GPIO_FUNC175_IN_SEL_CFG + 32 + 0x00000000 + + + SIG175_IN_SEL + 7 + 1 + + + FUNC175_IN_INV_SEL + 6 + 1 + + + FUNC175_IN_SEL + 0 + 6 + + + + + FUNC176_IN_SEL_CFG + 0x3f0 + GPIO_FUNC176_IN_SEL_CFG + 32 + 0x00000000 + + + SIG176_IN_SEL + 7 + 1 + + + FUNC176_IN_INV_SEL + 6 + 1 + + + FUNC176_IN_SEL + 0 + 6 + + + + + FUNC177_IN_SEL_CFG + 0x3f4 + GPIO_FUNC177_IN_SEL_CFG + 32 + 0x00000000 + + + SIG177_IN_SEL + 7 + 1 + + + FUNC177_IN_INV_SEL + 6 + 1 + + + FUNC177_IN_SEL + 0 + 6 + + + + + FUNC178_IN_SEL_CFG + 0x3f8 + GPIO_FUNC178_IN_SEL_CFG + 32 + 0x00000000 + + + SIG178_IN_SEL + 7 + 1 + + + FUNC178_IN_INV_SEL + 6 + 1 + + + FUNC178_IN_SEL + 0 + 6 + + + + + FUNC179_IN_SEL_CFG + 0x3fc + GPIO_FUNC179_IN_SEL_CFG + 32 + 0x00000000 + + + SIG179_IN_SEL + 7 + 1 + + + FUNC179_IN_INV_SEL + 6 + 1 + + + FUNC179_IN_SEL + 0 + 6 + + + + + FUNC180_IN_SEL_CFG + 0x400 + GPIO_FUNC180_IN_SEL_CFG + 32 + 0x00000000 + + + SIG180_IN_SEL + 7 + 1 + + + FUNC180_IN_INV_SEL + 6 + 1 + + + FUNC180_IN_SEL + 0 + 6 + + + + + FUNC181_IN_SEL_CFG + 0x404 + GPIO_FUNC181_IN_SEL_CFG + 32 + 0x00000000 + + + SIG181_IN_SEL + 7 + 1 + + + FUNC181_IN_INV_SEL + 6 + 1 + + + FUNC181_IN_SEL + 0 + 6 + + + + + FUNC182_IN_SEL_CFG + 0x408 + GPIO_FUNC182_IN_SEL_CFG + 32 + 0x00000000 + + + SIG182_IN_SEL + 7 + 1 + + + FUNC182_IN_INV_SEL + 6 + 1 + + + FUNC182_IN_SEL + 0 + 6 + + + + + FUNC183_IN_SEL_CFG + 0x40c + GPIO_FUNC183_IN_SEL_CFG + 32 + 0x00000000 + + + SIG183_IN_SEL + 7 + 1 + + + FUNC183_IN_INV_SEL + 6 + 1 + + + FUNC183_IN_SEL + 0 + 6 + + + + + FUNC184_IN_SEL_CFG + 0x410 + GPIO_FUNC184_IN_SEL_CFG + 32 + 0x00000000 + + + SIG184_IN_SEL + 7 + 1 + + + FUNC184_IN_INV_SEL + 6 + 1 + + + FUNC184_IN_SEL + 0 + 6 + + + + + FUNC185_IN_SEL_CFG + 0x414 + GPIO_FUNC185_IN_SEL_CFG + 32 + 0x00000000 + + + SIG185_IN_SEL + 7 + 1 + + + FUNC185_IN_INV_SEL + 6 + 1 + + + FUNC185_IN_SEL + 0 + 6 + + + + + FUNC186_IN_SEL_CFG + 0x418 + GPIO_FUNC186_IN_SEL_CFG + 32 + 0x00000000 + + + SIG186_IN_SEL + 7 + 1 + + + FUNC186_IN_INV_SEL + 6 + 1 + + + FUNC186_IN_SEL + 0 + 6 + + + + + FUNC187_IN_SEL_CFG + 0x41c + GPIO_FUNC187_IN_SEL_CFG + 32 + 0x00000000 + + + SIG187_IN_SEL + 7 + 1 + + + FUNC187_IN_INV_SEL + 6 + 1 + + + FUNC187_IN_SEL + 0 + 6 + + + + + FUNC188_IN_SEL_CFG + 0x420 + GPIO_FUNC188_IN_SEL_CFG + 32 + 0x00000000 + + + SIG188_IN_SEL + 7 + 1 + + + FUNC188_IN_INV_SEL + 6 + 1 + + + FUNC188_IN_SEL + 0 + 6 + + + + + FUNC189_IN_SEL_CFG + 0x424 + GPIO_FUNC189_IN_SEL_CFG + 32 + 0x00000000 + + + SIG189_IN_SEL + 7 + 1 + + + FUNC189_IN_INV_SEL + 6 + 1 + + + FUNC189_IN_SEL + 0 + 6 + + + + + FUNC190_IN_SEL_CFG + 0x428 + GPIO_FUNC190_IN_SEL_CFG + 32 + 0x00000000 + + + SIG190_IN_SEL + 7 + 1 + + + FUNC190_IN_INV_SEL + 6 + 1 + + + FUNC190_IN_SEL + 0 + 6 + + + + + FUNC191_IN_SEL_CFG + 0x42c + GPIO_FUNC191_IN_SEL_CFG + 32 + 0x00000000 + + + SIG191_IN_SEL + 7 + 1 + + + FUNC191_IN_INV_SEL + 6 + 1 + + + FUNC191_IN_SEL + 0 + 6 + + + + + FUNC192_IN_SEL_CFG + 0x430 + GPIO_FUNC192_IN_SEL_CFG + 32 + 0x00000000 + + + SIG192_IN_SEL + 7 + 1 + + + FUNC192_IN_INV_SEL + 6 + 1 + + + FUNC192_IN_SEL + 0 + 6 + + + + + FUNC193_IN_SEL_CFG + 0x434 + GPIO_FUNC193_IN_SEL_CFG + 32 + 0x00000000 + + + SIG193_IN_SEL + 7 + 1 + + + FUNC193_IN_INV_SEL + 6 + 1 + + + FUNC193_IN_SEL + 0 + 6 + + + + + FUNC194_IN_SEL_CFG + 0x438 + GPIO_FUNC194_IN_SEL_CFG + 32 + 0x00000000 + + + SIG194_IN_SEL + 7 + 1 + + + FUNC194_IN_INV_SEL + 6 + 1 + + + FUNC194_IN_SEL + 0 + 6 + + + + + FUNC195_IN_SEL_CFG + 0x43c + GPIO_FUNC195_IN_SEL_CFG + 32 + 0x00000000 + + + SIG195_IN_SEL + 7 + 1 + + + FUNC195_IN_INV_SEL + 6 + 1 + + + FUNC195_IN_SEL + 0 + 6 + + + + + FUNC196_IN_SEL_CFG + 0x440 + GPIO_FUNC196_IN_SEL_CFG + 32 + 0x00000000 + + + SIG196_IN_SEL + 7 + 1 + + + FUNC196_IN_INV_SEL + 6 + 1 + + + FUNC196_IN_SEL + 0 + 6 + + + + + FUNC197_IN_SEL_CFG + 0x444 + GPIO_FUNC197_IN_SEL_CFG + 32 + 0x00000000 + + + SIG197_IN_SEL + 7 + 1 + + + FUNC197_IN_INV_SEL + 6 + 1 + + + FUNC197_IN_SEL + 0 + 6 + + + + + FUNC198_IN_SEL_CFG + 0x448 + GPIO_FUNC198_IN_SEL_CFG + 32 + 0x00000000 + + + SIG198_IN_SEL + 7 + 1 + + + FUNC198_IN_INV_SEL + 6 + 1 + + + FUNC198_IN_SEL + 0 + 6 + + + + + FUNC199_IN_SEL_CFG + 0x44c + GPIO_FUNC199_IN_SEL_CFG + 32 + 0x00000000 + + + SIG199_IN_SEL + 7 + 1 + + + FUNC199_IN_INV_SEL + 6 + 1 + + + FUNC199_IN_SEL + 0 + 6 + + + + + FUNC200_IN_SEL_CFG + 0x450 + GPIO_FUNC200_IN_SEL_CFG + 32 + 0x00000000 + + + SIG200_IN_SEL + 7 + 1 + + + FUNC200_IN_INV_SEL + 6 + 1 + + + FUNC200_IN_SEL + 0 + 6 + + + + + FUNC201_IN_SEL_CFG + 0x454 + GPIO_FUNC201_IN_SEL_CFG + 32 + 0x00000000 + + + SIG201_IN_SEL + 7 + 1 + + + FUNC201_IN_INV_SEL + 6 + 1 + + + FUNC201_IN_SEL + 0 + 6 + + + + + FUNC202_IN_SEL_CFG + 0x458 + GPIO_FUNC202_IN_SEL_CFG + 32 + 0x00000000 + + + SIG202_IN_SEL + 7 + 1 + + + FUNC202_IN_INV_SEL + 6 + 1 + + + FUNC202_IN_SEL + 0 + 6 + + + + + FUNC203_IN_SEL_CFG + 0x45c + GPIO_FUNC203_IN_SEL_CFG + 32 + 0x00000000 + + + SIG203_IN_SEL + 7 + 1 + + + FUNC203_IN_INV_SEL + 6 + 1 + + + FUNC203_IN_SEL + 0 + 6 + + + + + FUNC204_IN_SEL_CFG + 0x460 + GPIO_FUNC204_IN_SEL_CFG + 32 + 0x00000000 + + + SIG204_IN_SEL + 7 + 1 + + + FUNC204_IN_INV_SEL + 6 + 1 + + + FUNC204_IN_SEL + 0 + 6 + + + + + FUNC205_IN_SEL_CFG + 0x464 + GPIO_FUNC205_IN_SEL_CFG + 32 + 0x00000000 + + + SIG205_IN_SEL + 7 + 1 + + + FUNC205_IN_INV_SEL + 6 + 1 + + + FUNC205_IN_SEL + 0 + 6 + + + + + FUNC206_IN_SEL_CFG + 0x468 + GPIO_FUNC206_IN_SEL_CFG + 32 + 0x00000000 + + + SIG206_IN_SEL + 7 + 1 + + + FUNC206_IN_INV_SEL + 6 + 1 + + + FUNC206_IN_SEL + 0 + 6 + + + + + FUNC207_IN_SEL_CFG + 0x46c + GPIO_FUNC207_IN_SEL_CFG + 32 + 0x00000000 + + + SIG207_IN_SEL + 7 + 1 + + + FUNC207_IN_INV_SEL + 6 + 1 + + + FUNC207_IN_SEL + 0 + 6 + + + + + FUNC208_IN_SEL_CFG + 0x470 + GPIO_FUNC208_IN_SEL_CFG + 32 + 0x00000000 + + + SIG208_IN_SEL + 7 + 1 + + + FUNC208_IN_INV_SEL + 6 + 1 + + + FUNC208_IN_SEL + 0 + 6 + + + + + FUNC209_IN_SEL_CFG + 0x474 + GPIO_FUNC209_IN_SEL_CFG + 32 + 0x00000000 + + + SIG209_IN_SEL + 7 + 1 + + + FUNC209_IN_INV_SEL + 6 + 1 + + + FUNC209_IN_SEL + 0 + 6 + + + + + FUNC210_IN_SEL_CFG + 0x478 + GPIO_FUNC210_IN_SEL_CFG + 32 + 0x00000000 + + + SIG210_IN_SEL + 7 + 1 + + + FUNC210_IN_INV_SEL + 6 + 1 + + + FUNC210_IN_SEL + 0 + 6 + + + + + FUNC211_IN_SEL_CFG + 0x47c + GPIO_FUNC211_IN_SEL_CFG + 32 + 0x00000000 + + + SIG211_IN_SEL + 7 + 1 + + + FUNC211_IN_INV_SEL + 6 + 1 + + + FUNC211_IN_SEL + 0 + 6 + + + + + FUNC212_IN_SEL_CFG + 0x480 + GPIO_FUNC212_IN_SEL_CFG + 32 + 0x00000000 + + + SIG212_IN_SEL + 7 + 1 + + + FUNC212_IN_INV_SEL + 6 + 1 + + + FUNC212_IN_SEL + 0 + 6 + + + + + FUNC213_IN_SEL_CFG + 0x484 + GPIO_FUNC213_IN_SEL_CFG + 32 + 0x00000000 + + + SIG213_IN_SEL + 7 + 1 + + + FUNC213_IN_INV_SEL + 6 + 1 + + + FUNC213_IN_SEL + 0 + 6 + + + + + FUNC214_IN_SEL_CFG + 0x488 + GPIO_FUNC214_IN_SEL_CFG + 32 + 0x00000000 + + + SIG214_IN_SEL + 7 + 1 + + + FUNC214_IN_INV_SEL + 6 + 1 + + + FUNC214_IN_SEL + 0 + 6 + + + + + FUNC215_IN_SEL_CFG + 0x48c + GPIO_FUNC215_IN_SEL_CFG + 32 + 0x00000000 + + + SIG215_IN_SEL + 7 + 1 + + + FUNC215_IN_INV_SEL + 6 + 1 + + + FUNC215_IN_SEL + 0 + 6 + + + + + FUNC216_IN_SEL_CFG + 0x490 + GPIO_FUNC216_IN_SEL_CFG + 32 + 0x00000000 + + + SIG216_IN_SEL + 7 + 1 + + + FUNC216_IN_INV_SEL + 6 + 1 + + + FUNC216_IN_SEL + 0 + 6 + + + + + FUNC217_IN_SEL_CFG + 0x494 + GPIO_FUNC217_IN_SEL_CFG + 32 + 0x00000000 + + + SIG217_IN_SEL + 7 + 1 + + + FUNC217_IN_INV_SEL + 6 + 1 + + + FUNC217_IN_SEL + 0 + 6 + + + + + FUNC218_IN_SEL_CFG + 0x498 + GPIO_FUNC218_IN_SEL_CFG + 32 + 0x00000000 + + + SIG218_IN_SEL + 7 + 1 + + + FUNC218_IN_INV_SEL + 6 + 1 + + + FUNC218_IN_SEL + 0 + 6 + + + + + FUNC219_IN_SEL_CFG + 0x49c + GPIO_FUNC219_IN_SEL_CFG + 32 + 0x00000000 + + + SIG219_IN_SEL + 7 + 1 + + + FUNC219_IN_INV_SEL + 6 + 1 + + + FUNC219_IN_SEL + 0 + 6 + + + + + FUNC220_IN_SEL_CFG + 0x4a0 + GPIO_FUNC220_IN_SEL_CFG + 32 + 0x00000000 + + + SIG220_IN_SEL + 7 + 1 + + + FUNC220_IN_INV_SEL + 6 + 1 + + + FUNC220_IN_SEL + 0 + 6 + + + + + FUNC221_IN_SEL_CFG + 0x4a4 + GPIO_FUNC221_IN_SEL_CFG + 32 + 0x00000000 + + + SIG221_IN_SEL + 7 + 1 + + + FUNC221_IN_INV_SEL + 6 + 1 + + + FUNC221_IN_SEL + 0 + 6 + + + + + FUNC222_IN_SEL_CFG + 0x4a8 + GPIO_FUNC222_IN_SEL_CFG + 32 + 0x00000000 + + + SIG222_IN_SEL + 7 + 1 + + + FUNC222_IN_INV_SEL + 6 + 1 + + + FUNC222_IN_SEL + 0 + 6 + + + + + FUNC223_IN_SEL_CFG + 0x4ac + GPIO_FUNC223_IN_SEL_CFG + 32 + 0x00000000 + + + SIG223_IN_SEL + 7 + 1 + + + FUNC223_IN_INV_SEL + 6 + 1 + + + FUNC223_IN_SEL + 0 + 6 + + + + + FUNC224_IN_SEL_CFG + 0x4b0 + GPIO_FUNC224_IN_SEL_CFG + 32 + 0x00000000 + + + SIG224_IN_SEL + 7 + 1 + + + FUNC224_IN_INV_SEL + 6 + 1 + + + FUNC224_IN_SEL + 0 + 6 + + + + + FUNC225_IN_SEL_CFG + 0x4b4 + GPIO_FUNC225_IN_SEL_CFG + 32 + 0x00000000 + + + SIG225_IN_SEL + 7 + 1 + + + FUNC225_IN_INV_SEL + 6 + 1 + + + FUNC225_IN_SEL + 0 + 6 + + + + + FUNC226_IN_SEL_CFG + 0x4b8 + GPIO_FUNC226_IN_SEL_CFG + 32 + 0x00000000 + + + SIG226_IN_SEL + 7 + 1 + + + FUNC226_IN_INV_SEL + 6 + 1 + + + FUNC226_IN_SEL + 0 + 6 + + + + + FUNC227_IN_SEL_CFG + 0x4bc + GPIO_FUNC227_IN_SEL_CFG + 32 + 0x00000000 + + + SIG227_IN_SEL + 7 + 1 + + + FUNC227_IN_INV_SEL + 6 + 1 + + + FUNC227_IN_SEL + 0 + 6 + + + + + FUNC228_IN_SEL_CFG + 0x4c0 + GPIO_FUNC228_IN_SEL_CFG + 32 + 0x00000000 + + + SIG228_IN_SEL + 7 + 1 + + + FUNC228_IN_INV_SEL + 6 + 1 + + + FUNC228_IN_SEL + 0 + 6 + + + + + FUNC229_IN_SEL_CFG + 0x4c4 + GPIO_FUNC229_IN_SEL_CFG + 32 + 0x00000000 + + + SIG229_IN_SEL + 7 + 1 + + + FUNC229_IN_INV_SEL + 6 + 1 + + + FUNC229_IN_SEL + 0 + 6 + + + + + FUNC230_IN_SEL_CFG + 0x4c8 + GPIO_FUNC230_IN_SEL_CFG + 32 + 0x00000000 + + + SIG230_IN_SEL + 7 + 1 + + + FUNC230_IN_INV_SEL + 6 + 1 + + + FUNC230_IN_SEL + 0 + 6 + + + + + FUNC231_IN_SEL_CFG + 0x4cc + GPIO_FUNC231_IN_SEL_CFG + 32 + 0x00000000 + + + SIG231_IN_SEL + 7 + 1 + + + FUNC231_IN_INV_SEL + 6 + 1 + + + FUNC231_IN_SEL + 0 + 6 + + + + + FUNC232_IN_SEL_CFG + 0x4d0 + GPIO_FUNC232_IN_SEL_CFG + 32 + 0x00000000 + + + SIG232_IN_SEL + 7 + 1 + + + FUNC232_IN_INV_SEL + 6 + 1 + + + FUNC232_IN_SEL + 0 + 6 + + + + + FUNC233_IN_SEL_CFG + 0x4d4 + GPIO_FUNC233_IN_SEL_CFG + 32 + 0x00000000 + + + SIG233_IN_SEL + 7 + 1 + + + FUNC233_IN_INV_SEL + 6 + 1 + + + FUNC233_IN_SEL + 0 + 6 + + + + + FUNC234_IN_SEL_CFG + 0x4d8 + GPIO_FUNC234_IN_SEL_CFG + 32 + 0x00000000 + + + SIG234_IN_SEL + 7 + 1 + + + FUNC234_IN_INV_SEL + 6 + 1 + + + FUNC234_IN_SEL + 0 + 6 + + + + + FUNC235_IN_SEL_CFG + 0x4dc + GPIO_FUNC235_IN_SEL_CFG + 32 + 0x00000000 + + + SIG235_IN_SEL + 7 + 1 + + + FUNC235_IN_INV_SEL + 6 + 1 + + + FUNC235_IN_SEL + 0 + 6 + + + + + FUNC236_IN_SEL_CFG + 0x4e0 + GPIO_FUNC236_IN_SEL_CFG + 32 + 0x00000000 + + + SIG236_IN_SEL + 7 + 1 + + + FUNC236_IN_INV_SEL + 6 + 1 + + + FUNC236_IN_SEL + 0 + 6 + + + + + FUNC237_IN_SEL_CFG + 0x4e4 + GPIO_FUNC237_IN_SEL_CFG + 32 + 0x00000000 + + + SIG237_IN_SEL + 7 + 1 + + + FUNC237_IN_INV_SEL + 6 + 1 + + + FUNC237_IN_SEL + 0 + 6 + + + + + FUNC238_IN_SEL_CFG + 0x4e8 + GPIO_FUNC238_IN_SEL_CFG + 32 + 0x00000000 + + + SIG238_IN_SEL + 7 + 1 + + + FUNC238_IN_INV_SEL + 6 + 1 + + + FUNC238_IN_SEL + 0 + 6 + + + + + FUNC239_IN_SEL_CFG + 0x4ec + GPIO_FUNC239_IN_SEL_CFG + 32 + 0x00000000 + + + SIG239_IN_SEL + 7 + 1 + + + FUNC239_IN_INV_SEL + 6 + 1 + + + FUNC239_IN_SEL + 0 + 6 + + + + + FUNC240_IN_SEL_CFG + 0x4f0 + GPIO_FUNC240_IN_SEL_CFG + 32 + 0x00000000 + + + SIG240_IN_SEL + 7 + 1 + + + FUNC240_IN_INV_SEL + 6 + 1 + + + FUNC240_IN_SEL + 0 + 6 + + + + + FUNC241_IN_SEL_CFG + 0x4f4 + GPIO_FUNC241_IN_SEL_CFG + 32 + 0x00000000 + + + SIG241_IN_SEL + 7 + 1 + + + FUNC241_IN_INV_SEL + 6 + 1 + + + FUNC241_IN_SEL + 0 + 6 + + + + + FUNC242_IN_SEL_CFG + 0x4f8 + GPIO_FUNC242_IN_SEL_CFG + 32 + 0x00000000 + + + SIG242_IN_SEL + 7 + 1 + + + FUNC242_IN_INV_SEL + 6 + 1 + + + FUNC242_IN_SEL + 0 + 6 + + + + + FUNC243_IN_SEL_CFG + 0x4fc + GPIO_FUNC243_IN_SEL_CFG + 32 + 0x00000000 + + + SIG243_IN_SEL + 7 + 1 + + + FUNC243_IN_INV_SEL + 6 + 1 + + + FUNC243_IN_SEL + 0 + 6 + + + + + FUNC244_IN_SEL_CFG + 0x500 + GPIO_FUNC244_IN_SEL_CFG + 32 + 0x00000000 + + + SIG244_IN_SEL + 7 + 1 + + + FUNC244_IN_INV_SEL + 6 + 1 + + + FUNC244_IN_SEL + 0 + 6 + + + + + FUNC245_IN_SEL_CFG + 0x504 + GPIO_FUNC245_IN_SEL_CFG + 32 + 0x00000000 + + + SIG245_IN_SEL + 7 + 1 + + + FUNC245_IN_INV_SEL + 6 + 1 + + + FUNC245_IN_SEL + 0 + 6 + + + + + FUNC246_IN_SEL_CFG + 0x508 + GPIO_FUNC246_IN_SEL_CFG + 32 + 0x00000000 + + + SIG246_IN_SEL + 7 + 1 + + + FUNC246_IN_INV_SEL + 6 + 1 + + + FUNC246_IN_SEL + 0 + 6 + + + + + FUNC247_IN_SEL_CFG + 0x50c + GPIO_FUNC247_IN_SEL_CFG + 32 + 0x00000000 + + + SIG247_IN_SEL + 7 + 1 + + + FUNC247_IN_INV_SEL + 6 + 1 + + + FUNC247_IN_SEL + 0 + 6 + + + + + FUNC248_IN_SEL_CFG + 0x510 + GPIO_FUNC248_IN_SEL_CFG + 32 + 0x00000000 + + + SIG248_IN_SEL + 7 + 1 + + + FUNC248_IN_INV_SEL + 6 + 1 + + + FUNC248_IN_SEL + 0 + 6 + + + + + FUNC249_IN_SEL_CFG + 0x514 + GPIO_FUNC249_IN_SEL_CFG + 32 + 0x00000000 + + + SIG249_IN_SEL + 7 + 1 + + + FUNC249_IN_INV_SEL + 6 + 1 + + + FUNC249_IN_SEL + 0 + 6 + + + + + FUNC250_IN_SEL_CFG + 0x518 + GPIO_FUNC250_IN_SEL_CFG + 32 + 0x00000000 + + + SIG250_IN_SEL + 7 + 1 + + + FUNC250_IN_INV_SEL + 6 + 1 + + + FUNC250_IN_SEL + 0 + 6 + + + + + FUNC251_IN_SEL_CFG + 0x51c + GPIO_FUNC251_IN_SEL_CFG + 32 + 0x00000000 + + + SIG251_IN_SEL + 7 + 1 + + + FUNC251_IN_INV_SEL + 6 + 1 + + + FUNC251_IN_SEL + 0 + 6 + + + + + FUNC252_IN_SEL_CFG + 0x520 + GPIO_FUNC252_IN_SEL_CFG + 32 + 0x00000000 + + + SIG252_IN_SEL + 7 + 1 + + + FUNC252_IN_INV_SEL + 6 + 1 + + + FUNC252_IN_SEL + 0 + 6 + + + + + FUNC253_IN_SEL_CFG + 0x524 + GPIO_FUNC253_IN_SEL_CFG + 32 + 0x00000000 + + + SIG253_IN_SEL + 7 + 1 + + + FUNC253_IN_INV_SEL + 6 + 1 + + + FUNC253_IN_SEL + 0 + 6 + + + + + FUNC254_IN_SEL_CFG + 0x528 + GPIO_FUNC254_IN_SEL_CFG + 32 + 0x00000000 + + + SIG254_IN_SEL + 7 + 1 + + + FUNC254_IN_INV_SEL + 6 + 1 + + + FUNC254_IN_SEL + 0 + 6 + + + + + FUNC255_IN_SEL_CFG + 0x52c + GPIO_FUNC255_IN_SEL_CFG + 32 + 0x00000000 + + + SIG255_IN_SEL + 7 + 1 + + + FUNC255_IN_INV_SEL + 6 + 1 + + + FUNC255_IN_SEL + 0 + 6 + + + + + FUNC0_OUT_SEL_CFG + 0x530 + GPIO_FUNC0_OUT_SEL_CFG + 32 + 0x00000000 + + + FUNC0_OEN_INV_SEL + 11 + 1 + + + FUNC0_OEN_SEL + 10 + 1 + + + FUNC0_OUT_INV_SEL + 9 + 1 + + + FUNC0_OUT_SEL + 0 + 9 + + + + + FUNC1_OUT_SEL_CFG + 0x534 + GPIO_FUNC1_OUT_SEL_CFG + 32 + 0x00000000 + + + FUNC1_OEN_INV_SEL + 11 + 1 + + + FUNC1_OEN_SEL + 10 + 1 + + + FUNC1_OUT_INV_SEL + 9 + 1 + + + FUNC1_OUT_SEL + 0 + 9 + + + + + FUNC2_OUT_SEL_CFG + 0x538 + GPIO_FUNC2_OUT_SEL_CFG + 32 + 0x00000000 + + + FUNC2_OEN_INV_SEL + 11 + 1 + + + FUNC2_OEN_SEL + 10 + 1 + + + FUNC2_OUT_INV_SEL + 9 + 1 + + + FUNC2_OUT_SEL + 0 + 9 + + + + + FUNC3_OUT_SEL_CFG + 0x53c + GPIO_FUNC3_OUT_SEL_CFG + 32 + 0x00000000 + + + FUNC3_OEN_INV_SEL + 11 + 1 + + + FUNC3_OEN_SEL + 10 + 1 + + + FUNC3_OUT_INV_SEL + 9 + 1 + + + FUNC3_OUT_SEL + 0 + 9 + + + + + FUNC4_OUT_SEL_CFG + 0x540 + GPIO_FUNC4_OUT_SEL_CFG + 32 + 0x00000000 + + + FUNC4_OEN_INV_SEL + 11 + 1 + + + FUNC4_OEN_SEL + 10 + 1 + + + FUNC4_OUT_INV_SEL + 9 + 1 + + + FUNC4_OUT_SEL + 0 + 9 + + + + + FUNC5_OUT_SEL_CFG + 0x544 + GPIO_FUNC5_OUT_SEL_CFG + 32 + 0x00000000 + + + FUNC5_OEN_INV_SEL + 11 + 1 + + + FUNC5_OEN_SEL + 10 + 1 + + + FUNC5_OUT_INV_SEL + 9 + 1 + + + FUNC5_OUT_SEL + 0 + 9 + + + + + FUNC6_OUT_SEL_CFG + 0x548 + GPIO_FUNC6_OUT_SEL_CFG + 32 + 0x00000000 + + + FUNC6_OEN_INV_SEL + 11 + 1 + + + FUNC6_OEN_SEL + 10 + 1 + + + FUNC6_OUT_INV_SEL + 9 + 1 + + + FUNC6_OUT_SEL + 0 + 9 + + + + + FUNC7_OUT_SEL_CFG + 0x54c + GPIO_FUNC7_OUT_SEL_CFG + 32 + 0x00000000 + + + FUNC7_OEN_INV_SEL + 11 + 1 + + + FUNC7_OEN_SEL + 10 + 1 + + + FUNC7_OUT_INV_SEL + 9 + 1 + + + FUNC7_OUT_SEL + 0 + 9 + + + + + FUNC8_OUT_SEL_CFG + 0x550 + GPIO_FUNC8_OUT_SEL_CFG + 32 + 0x00000000 + + + FUNC8_OEN_INV_SEL + 11 + 1 + + + FUNC8_OEN_SEL + 10 + 1 + + + FUNC8_OUT_INV_SEL + 9 + 1 + + + FUNC8_OUT_SEL + 0 + 9 + + + + + FUNC9_OUT_SEL_CFG + 0x554 + GPIO_FUNC9_OUT_SEL_CFG + 32 + 0x00000000 + + + FUNC9_OEN_INV_SEL + 11 + 1 + + + FUNC9_OEN_SEL + 10 + 1 + + + FUNC9_OUT_INV_SEL + 9 + 1 + + + FUNC9_OUT_SEL + 0 + 9 + + + + + FUNC10_OUT_SEL_CFG + 0x558 + GPIO_FUNC10_OUT_SEL_CFG + 32 + 0x00000000 + + + FUNC10_OEN_INV_SEL + 11 + 1 + + + FUNC10_OEN_SEL + 10 + 1 + + + FUNC10_OUT_INV_SEL + 9 + 1 + + + FUNC10_OUT_SEL + 0 + 9 + + + + + FUNC11_OUT_SEL_CFG + 0x55c + GPIO_FUNC11_OUT_SEL_CFG + 32 + 0x00000000 + + + FUNC11_OEN_INV_SEL + 11 + 1 + + + FUNC11_OEN_SEL + 10 + 1 + + + FUNC11_OUT_INV_SEL + 9 + 1 + + + FUNC11_OUT_SEL + 0 + 9 + + + + + FUNC12_OUT_SEL_CFG + 0x560 + GPIO_FUNC12_OUT_SEL_CFG + 32 + 0x00000000 + + + FUNC12_OEN_INV_SEL + 11 + 1 + + + FUNC12_OEN_SEL + 10 + 1 + + + FUNC12_OUT_INV_SEL + 9 + 1 + + + FUNC12_OUT_SEL + 0 + 9 + + + + + FUNC13_OUT_SEL_CFG + 0x564 + GPIO_FUNC13_OUT_SEL_CFG + 32 + 0x00000000 + + + FUNC13_OEN_INV_SEL + 11 + 1 + + + FUNC13_OEN_SEL + 10 + 1 + + + FUNC13_OUT_INV_SEL + 9 + 1 + + + FUNC13_OUT_SEL + 0 + 9 + + + + + FUNC14_OUT_SEL_CFG + 0x568 + GPIO_FUNC14_OUT_SEL_CFG + 32 + 0x00000000 + + + FUNC14_OEN_INV_SEL + 11 + 1 + + + FUNC14_OEN_SEL + 10 + 1 + + + FUNC14_OUT_INV_SEL + 9 + 1 + + + FUNC14_OUT_SEL + 0 + 9 + + + + + FUNC15_OUT_SEL_CFG + 0x56c + GPIO_FUNC15_OUT_SEL_CFG + 32 + 0x00000000 + + + FUNC15_OEN_INV_SEL + 11 + 1 + + + FUNC15_OEN_SEL + 10 + 1 + + + FUNC15_OUT_INV_SEL + 9 + 1 + + + FUNC15_OUT_SEL + 0 + 9 + + + + + FUNC16_OUT_SEL_CFG + 0x570 + GPIO_FUNC16_OUT_SEL_CFG + 32 + 0x00000000 + + + FUNC16_OEN_INV_SEL + 11 + 1 + + + FUNC16_OEN_SEL + 10 + 1 + + + FUNC16_OUT_INV_SEL + 9 + 1 + + + FUNC16_OUT_SEL + 0 + 9 + + + + + FUNC17_OUT_SEL_CFG + 0x574 + GPIO_FUNC17_OUT_SEL_CFG + 32 + 0x00000000 + + + FUNC17_OEN_INV_SEL + 11 + 1 + + + FUNC17_OEN_SEL + 10 + 1 + + + FUNC17_OUT_INV_SEL + 9 + 1 + + + FUNC17_OUT_SEL + 0 + 9 + + + + + FUNC18_OUT_SEL_CFG + 0x578 + GPIO_FUNC18_OUT_SEL_CFG + 32 + 0x00000000 + + + FUNC18_OEN_INV_SEL + 11 + 1 + + + FUNC18_OEN_SEL + 10 + 1 + + + FUNC18_OUT_INV_SEL + 9 + 1 + + + FUNC18_OUT_SEL + 0 + 9 + + + + + FUNC19_OUT_SEL_CFG + 0x57c + GPIO_FUNC19_OUT_SEL_CFG + 32 + 0x00000000 + + + FUNC19_OEN_INV_SEL + 11 + 1 + + + FUNC19_OEN_SEL + 10 + 1 + + + FUNC19_OUT_INV_SEL + 9 + 1 + + + FUNC19_OUT_SEL + 0 + 9 + + + + + FUNC20_OUT_SEL_CFG + 0x580 + GPIO_FUNC20_OUT_SEL_CFG + 32 + 0x00000000 + + + FUNC20_OEN_INV_SEL + 11 + 1 + + + FUNC20_OEN_SEL + 10 + 1 + + + FUNC20_OUT_INV_SEL + 9 + 1 + + + FUNC20_OUT_SEL + 0 + 9 + + + + + FUNC21_OUT_SEL_CFG + 0x584 + GPIO_FUNC21_OUT_SEL_CFG + 32 + 0x00000000 + + + FUNC21_OEN_INV_SEL + 11 + 1 + + + FUNC21_OEN_SEL + 10 + 1 + + + FUNC21_OUT_INV_SEL + 9 + 1 + + + FUNC21_OUT_SEL + 0 + 9 + + + + + FUNC22_OUT_SEL_CFG + 0x588 + GPIO_FUNC22_OUT_SEL_CFG + 32 + 0x00000000 + + + FUNC22_OEN_INV_SEL + 11 + 1 + + + FUNC22_OEN_SEL + 10 + 1 + + + FUNC22_OUT_INV_SEL + 9 + 1 + + + FUNC22_OUT_SEL + 0 + 9 + + + + + FUNC23_OUT_SEL_CFG + 0x58c + GPIO_FUNC23_OUT_SEL_CFG + 32 + 0x00000000 + + + FUNC23_OEN_INV_SEL + 11 + 1 + + + FUNC23_OEN_SEL + 10 + 1 + + + FUNC23_OUT_INV_SEL + 9 + 1 + + + FUNC23_OUT_SEL + 0 + 9 + + + + + FUNC24_OUT_SEL_CFG + 0x590 + GPIO_FUNC24_OUT_SEL_CFG + 32 + 0x00000000 + + + FUNC24_OEN_INV_SEL + 11 + 1 + + + FUNC24_OEN_SEL + 10 + 1 + + + FUNC24_OUT_INV_SEL + 9 + 1 + + + FUNC24_OUT_SEL + 0 + 9 + + + + + FUNC25_OUT_SEL_CFG + 0x594 + GPIO_FUNC25_OUT_SEL_CFG + 32 + 0x00000000 + + + FUNC25_OEN_INV_SEL + 11 + 1 + + + FUNC25_OEN_SEL + 10 + 1 + + + FUNC25_OUT_INV_SEL + 9 + 1 + + + FUNC25_OUT_SEL + 0 + 9 + + + + + FUNC26_OUT_SEL_CFG + 0x598 + GPIO_FUNC26_OUT_SEL_CFG + 32 + 0x00000000 + + + FUNC26_OEN_INV_SEL + 11 + 1 + + + FUNC26_OEN_SEL + 10 + 1 + + + FUNC26_OUT_INV_SEL + 9 + 1 + + + FUNC26_OUT_SEL + 0 + 9 + + + + + FUNC27_OUT_SEL_CFG + 0x59c + GPIO_FUNC27_OUT_SEL_CFG + 32 + 0x00000000 + + + FUNC27_OEN_INV_SEL + 11 + 1 + + + FUNC27_OEN_SEL + 10 + 1 + + + FUNC27_OUT_INV_SEL + 9 + 1 + + + FUNC27_OUT_SEL + 0 + 9 + + + + + FUNC28_OUT_SEL_CFG + 0x5a0 + GPIO_FUNC28_OUT_SEL_CFG + 32 + 0x00000000 + + + FUNC28_OEN_INV_SEL + 11 + 1 + + + FUNC28_OEN_SEL + 10 + 1 + + + FUNC28_OUT_INV_SEL + 9 + 1 + + + FUNC28_OUT_SEL + 0 + 9 + + + + + FUNC29_OUT_SEL_CFG + 0x5a4 + GPIO_FUNC29_OUT_SEL_CFG + 32 + 0x00000000 + + + FUNC29_OEN_INV_SEL + 11 + 1 + + + FUNC29_OEN_SEL + 10 + 1 + + + FUNC29_OUT_INV_SEL + 9 + 1 + + + FUNC29_OUT_SEL + 0 + 9 + + + + + FUNC30_OUT_SEL_CFG + 0x5a8 + GPIO_FUNC30_OUT_SEL_CFG + 32 + 0x00000000 + + + FUNC30_OEN_INV_SEL + 11 + 1 + + + FUNC30_OEN_SEL + 10 + 1 + + + FUNC30_OUT_INV_SEL + 9 + 1 + + + FUNC30_OUT_SEL + 0 + 9 + + + + + FUNC31_OUT_SEL_CFG + 0x5ac + GPIO_FUNC31_OUT_SEL_CFG + 32 + 0x00000000 + + + FUNC31_OEN_INV_SEL + 11 + 1 + + + FUNC31_OEN_SEL + 10 + 1 + + + FUNC31_OUT_INV_SEL + 9 + 1 + + + FUNC31_OUT_SEL + 0 + 9 + + + + + FUNC32_OUT_SEL_CFG + 0x5b0 + GPIO_FUNC32_OUT_SEL_CFG + 32 + 0x00000000 + + + FUNC32_OEN_INV_SEL + 11 + 1 + + + FUNC32_OEN_SEL + 10 + 1 + + + FUNC32_OUT_INV_SEL + 9 + 1 + + + FUNC32_OUT_SEL + 0 + 9 + + + + + FUNC33_OUT_SEL_CFG + 0x5b4 + GPIO_FUNC33_OUT_SEL_CFG + 32 + 0x00000000 + + + FUNC33_OEN_INV_SEL + 11 + 1 + + + FUNC33_OEN_SEL + 10 + 1 + + + FUNC33_OUT_INV_SEL + 9 + 1 + + + FUNC33_OUT_SEL + 0 + 9 + + + + + FUNC34_OUT_SEL_CFG + 0x5b8 + GPIO_FUNC34_OUT_SEL_CFG + 32 + 0x00000000 + + + FUNC34_OEN_INV_SEL + 11 + 1 + + + FUNC34_OEN_SEL + 10 + 1 + + + FUNC34_OUT_INV_SEL + 9 + 1 + + + FUNC34_OUT_SEL + 0 + 9 + + + + + FUNC35_OUT_SEL_CFG + 0x5bc + GPIO_FUNC35_OUT_SEL_CFG + 32 + 0x00000000 + + + FUNC35_OEN_INV_SEL + 11 + 1 + + + FUNC35_OEN_SEL + 10 + 1 + + + FUNC35_OUT_INV_SEL + 9 + 1 + + + FUNC35_OUT_SEL + 0 + 9 + + + + + FUNC36_OUT_SEL_CFG + 0x5c0 + GPIO_FUNC36_OUT_SEL_CFG + 32 + 0x00000000 + + + FUNC36_OEN_INV_SEL + 11 + 1 + + + FUNC36_OEN_SEL + 10 + 1 + + + FUNC36_OUT_INV_SEL + 9 + 1 + + + FUNC36_OUT_SEL + 0 + 9 + + + + + FUNC37_OUT_SEL_CFG + 0x5c4 + GPIO_FUNC37_OUT_SEL_CFG + 32 + 0x00000000 + + + FUNC37_OEN_INV_SEL + 11 + 1 + + + FUNC37_OEN_SEL + 10 + 1 + + + FUNC37_OUT_INV_SEL + 9 + 1 + + + FUNC37_OUT_SEL + 0 + 9 + + + + + FUNC38_OUT_SEL_CFG + 0x5c8 + GPIO_FUNC38_OUT_SEL_CFG + 32 + 0x00000000 + + + FUNC38_OEN_INV_SEL + 11 + 1 + + + FUNC38_OEN_SEL + 10 + 1 + + + FUNC38_OUT_INV_SEL + 9 + 1 + + + FUNC38_OUT_SEL + 0 + 9 + + + + + FUNC39_OUT_SEL_CFG + 0x5cc + GPIO_FUNC39_OUT_SEL_CFG + 32 + 0x00000000 + + + FUNC39_OEN_INV_SEL + 11 + 1 + + + FUNC39_OEN_SEL + 10 + 1 + + + FUNC39_OUT_INV_SEL + 9 + 1 + + + FUNC39_OUT_SEL + 0 + 9 + + + + + GPIO_INTRinterrupt of GPIO, level22 + GPIO_NMIinterrupt of GPIO, NMI23 + + + FRC_TIMER + 0x3ff47000 + + 0 + 0x00000000 + registers + + + + + UHCI + 0x0 + + 0 + 0x00000620 + registers + + + + CONF0 + 0x0 + UHCI_CONF0 + 32 + 0x00000000 + + + UART_RX_BRK_EOF_EN + 23 + 1 + + + CLK_EN + 22 + 1 + + + ENCODE_CRC_EN + 21 + 1 + + + LEN_EOF_EN + 20 + 1 + + + UART_IDLE_EOF_EN + 19 + 1 + + + CRC_REC_EN + 18 + 1 + + + HEAD_EN + 17 + 1 + + + SEPER_EN + 16 + 1 + + + MEM_TRANS_EN + 15 + 1 + + + OUT_DATA_BURST_EN + 14 + 1 + + + INDSCR_BURST_EN + 13 + 1 + + + OUTDSCR_BURST_EN + 12 + 1 + + + UART2_CE + 11 + 1 + + + UART1_CE + 10 + 1 + + + UART0_CE + 9 + 1 + + + OUT_EOF_MODE + 8 + 1 + + + OUT_NO_RESTART_CLR + 7 + 1 + + + OUT_AUTO_WRBACK + 6 + 1 + + + OUT_LOOP_TEST + 5 + 1 + + + IN_LOOP_TEST + 4 + 1 + + + AHBM_RST + 3 + 1 + + + AHBM_FIFO_RST + 2 + 1 + + + OUT_RST + 1 + 1 + + + IN_RST + 0 + 1 + + + + + INT_RAW + 0x4 + UHCI_INT_RAW + 32 + 0x00000000 + + + DMA_INFIFO_FULL_WM_INT_RAW + 16 + 1 + + + SEND_A_Q_INT_RAW + 15 + 1 + + + SEND_S_Q_INT_RAW + 14 + 1 + + + OUT_TOTAL_EOF_INT_RAW + 13 + 1 + + + OUTLINK_EOF_ERR_INT_RAW + 12 + 1 + + + IN_DSCR_EMPTY_INT_RAW + 11 + 1 + + + OUT_DSCR_ERR_INT_RAW + 10 + 1 + + + IN_DSCR_ERR_INT_RAW + 9 + 1 + + + OUT_EOF_INT_RAW + 8 + 1 + + + OUT_DONE_INT_RAW + 7 + 1 + + + IN_ERR_EOF_INT_RAW + 6 + 1 + + + IN_SUC_EOF_INT_RAW + 5 + 1 + + + IN_DONE_INT_RAW + 4 + 1 + + + TX_HUNG_INT_RAW + 3 + 1 + + + RX_HUNG_INT_RAW + 2 + 1 + + + TX_START_INT_RAW + 1 + 1 + + + RX_START_INT_RAW + 0 + 1 + + + + + INT_ST + 0x8 + UHCI_INT_ST + 32 + 0x00000000 + + + DMA_INFIFO_FULL_WM_INT_ST + 16 + 1 + + + SEND_A_Q_INT_ST + 15 + 1 + + + SEND_S_Q_INT_ST + 14 + 1 + + + OUT_TOTAL_EOF_INT_ST + 13 + 1 + + + OUTLINK_EOF_ERR_INT_ST + 12 + 1 + + + IN_DSCR_EMPTY_INT_ST + 11 + 1 + + + OUT_DSCR_ERR_INT_ST + 10 + 1 + + + IN_DSCR_ERR_INT_ST + 9 + 1 + + + OUT_EOF_INT_ST + 8 + 1 + + + OUT_DONE_INT_ST + 7 + 1 + + + IN_ERR_EOF_INT_ST + 6 + 1 + + + IN_SUC_EOF_INT_ST + 5 + 1 + + + IN_DONE_INT_ST + 4 + 1 + + + TX_HUNG_INT_ST + 3 + 1 + + + RX_HUNG_INT_ST + 2 + 1 + + + TX_START_INT_ST + 1 + 1 + + + RX_START_INT_ST + 0 + 1 + + + + + INT_ENA + 0xc + UHCI_INT_ENA + 32 + 0x00000000 + + + DMA_INFIFO_FULL_WM_INT_ENA + 16 + 1 + + + SEND_A_Q_INT_ENA + 15 + 1 + + + SEND_S_Q_INT_ENA + 14 + 1 + + + OUT_TOTAL_EOF_INT_ENA + 13 + 1 + + + OUTLINK_EOF_ERR_INT_ENA + 12 + 1 + + + IN_DSCR_EMPTY_INT_ENA + 11 + 1 + + + OUT_DSCR_ERR_INT_ENA + 10 + 1 + + + IN_DSCR_ERR_INT_ENA + 9 + 1 + + + OUT_EOF_INT_ENA + 8 + 1 + + + OUT_DONE_INT_ENA + 7 + 1 + + + IN_ERR_EOF_INT_ENA + 6 + 1 + + + IN_SUC_EOF_INT_ENA + 5 + 1 + + + IN_DONE_INT_ENA + 4 + 1 + + + TX_HUNG_INT_ENA + 3 + 1 + + + RX_HUNG_INT_ENA + 2 + 1 + + + TX_START_INT_ENA + 1 + 1 + + + RX_START_INT_ENA + 0 + 1 + + + + + INT_CLR + 0x10 + UHCI_INT_CLR + 32 + 0x00000000 + + + DMA_INFIFO_FULL_WM_INT_CLR + 16 + 1 + + + SEND_A_Q_INT_CLR + 15 + 1 + + + SEND_S_Q_INT_CLR + 14 + 1 + + + OUT_TOTAL_EOF_INT_CLR + 13 + 1 + + + OUTLINK_EOF_ERR_INT_CLR + 12 + 1 + + + IN_DSCR_EMPTY_INT_CLR + 11 + 1 + + + OUT_DSCR_ERR_INT_CLR + 10 + 1 + + + IN_DSCR_ERR_INT_CLR + 9 + 1 + + + OUT_EOF_INT_CLR + 8 + 1 + + + OUT_DONE_INT_CLR + 7 + 1 + + + IN_ERR_EOF_INT_CLR + 6 + 1 + + + IN_SUC_EOF_INT_CLR + 5 + 1 + + + IN_DONE_INT_CLR + 4 + 1 + + + TX_HUNG_INT_CLR + 3 + 1 + + + RX_HUNG_INT_CLR + 2 + 1 + + + TX_START_INT_CLR + 1 + 1 + + + RX_START_INT_CLR + 0 + 1 + + + + + DMA_OUT_STATUS + 0x14 + UHCI_DMA_OUT_STATUS + 32 + 0x00000000 + + + OUT_EMPTY + 1 + 1 + + + OUT_FULL + 0 + 1 + + + + + DMA_OUT_PUSH + 0x18 + UHCI_DMA_OUT_PUSH + 32 + 0x00000000 + + + OUTFIFO_PUSH + 16 + 1 + + + OUTFIFO_WDATA + 0 + 9 + + + + + DMA_IN_STATUS + 0x1c + UHCI_DMA_IN_STATUS + 32 + 0x00000000 + + + RX_ERR_CAUSE + 4 + 3 + + + IN_EMPTY + 1 + 1 + + + IN_FULL + 0 + 1 + + + + + DMA_IN_POP + 0x20 + UHCI_DMA_IN_POP + 32 + 0x00000000 + + + INFIFO_POP + 16 + 1 + + + INFIFO_RDATA + 0 + 12 + + + + + DMA_OUT_LINK + 0x24 + UHCI_DMA_OUT_LINK + 32 + 0x00000000 + + + OUTLINK_PARK + 31 + 1 + + + OUTLINK_RESTART + 30 + 1 + + + OUTLINK_START + 29 + 1 + + + OUTLINK_STOP + 28 + 1 + + + OUTLINK_ADDR + 0 + 20 + + + + + DMA_IN_LINK + 0x28 + UHCI_DMA_IN_LINK + 32 + 0x00000000 + + + INLINK_PARK + 31 + 1 + + + INLINK_RESTART + 30 + 1 + + + INLINK_START + 29 + 1 + + + INLINK_STOP + 28 + 1 + + + INLINK_AUTO_RET + 20 + 1 + + + INLINK_ADDR + 0 + 20 + + + + + CONF1 + 0x2c + UHCI_CONF1 + 32 + 0x00000000 + + + DMA_INFIFO_FULL_THRS + 9 + 12 + + + SW_START + 8 + 1 + + + WAIT_SW_START + 7 + 1 + + + CHECK_OWNER + 6 + 1 + + + TX_ACK_NUM_RE + 5 + 1 + + + TX_CHECK_SUM_RE + 4 + 1 + + + SAVE_HEAD + 3 + 1 + + + CRC_DISABLE + 2 + 1 + + + CHECK_SEQ_EN + 1 + 1 + + + CHECK_SUM_EN + 0 + 1 + + + + + STATE0 + 0x30 + UHCI_STATE0 + 32 + 0x00000000 + + + STATE0 + 0 + 32 + + + + + STATE1 + 0x34 + UHCI_STATE1 + 32 + 0x00000000 + + + STATE1 + 0 + 32 + + + + + DMA_OUT_EOF_DES_ADDR + 0x38 + UHCI_DMA_OUT_EOF_DES_ADDR + 32 + 0x00000000 + + + OUT_EOF_DES_ADDR + 0 + 32 + + + + + DMA_IN_SUC_EOF_DES_ADDR + 0x3c + UHCI_DMA_IN_SUC_EOF_DES_ADDR + 32 + 0x00000000 + + + IN_SUC_EOF_DES_ADDR + 0 + 32 + + + + + DMA_IN_ERR_EOF_DES_ADDR + 0x40 + UHCI_DMA_IN_ERR_EOF_DES_ADDR + 32 + 0x00000000 + + + IN_ERR_EOF_DES_ADDR + 0 + 32 + + + + + DMA_OUT_EOF_BFR_DES_ADDR + 0x44 + UHCI_DMA_OUT_EOF_BFR_DES_ADDR + 32 + 0x00000000 + + + OUT_EOF_BFR_DES_ADDR + 0 + 32 + + + + + AHB_TEST + 0x48 + UHCI_AHB_TEST + 32 + 0x00000000 + + + AHB_TESTADDR + 4 + 2 + + + AHB_TESTMODE + 0 + 3 + + + + + DMA_IN_DSCR + 0x4c + UHCI_DMA_IN_DSCR + 32 + 0x00000000 + + + INLINK_DSCR + 0 + 32 + + + + + DMA_IN_DSCR_BF0 + 0x50 + UHCI_DMA_IN_DSCR_BF0 + 32 + 0x00000000 + + + INLINK_DSCR_BF0 + 0 + 32 + + + + + DMA_IN_DSCR_BF1 + 0x54 + UHCI_DMA_IN_DSCR_BF1 + 32 + 0x00000000 + + + INLINK_DSCR_BF1 + 0 + 32 + + + + + DMA_OUT_DSCR + 0x58 + UHCI_DMA_OUT_DSCR + 32 + 0x00000000 + + + OUTLINK_DSCR + 0 + 32 + + + + + DMA_OUT_DSCR_BF0 + 0x5c + UHCI_DMA_OUT_DSCR_BF0 + 32 + 0x00000000 + + + OUTLINK_DSCR_BF0 + 0 + 32 + + + + + DMA_OUT_DSCR_BF1 + 0x60 + UHCI_DMA_OUT_DSCR_BF1 + 32 + 0x00000000 + + + OUTLINK_DSCR_BF1 + 0 + 32 + + + + + ESCAPE_CONF + 0x64 + UHCI_ESCAPE_CONF + 32 + 0x00000000 + + + RX_13_ESC_EN + 7 + 1 + + + RX_11_ESC_EN + 6 + 1 + + + RX_DB_ESC_EN + 5 + 1 + + + RX_C0_ESC_EN + 4 + 1 + + + TX_13_ESC_EN + 3 + 1 + + + TX_11_ESC_EN + 2 + 1 + + + TX_DB_ESC_EN + 1 + 1 + + + TX_C0_ESC_EN + 0 + 1 + + + + + HUNG_CONF + 0x68 + UHCI_HUNG_CONF + 32 + 0x00000000 + + + RXFIFO_TIMEOUT_ENA + 23 + 1 + + + RXFIFO_TIMEOUT_SHIFT + 20 + 3 + + + RXFIFO_TIMEOUT + 12 + 8 + + + TXFIFO_TIMEOUT_ENA + 11 + 1 + + + TXFIFO_TIMEOUT_SHIFT + 8 + 3 + + + TXFIFO_TIMEOUT + 0 + 8 + + + + + RX_HEAD + 0x70 + UHCI_RX_HEAD + 32 + 0x00000000 + + + RX_HEAD + 0 + 32 + + + + + QUICK_SENT + 0x74 + UHCI_QUICK_SENT + 32 + 0x00000000 + + + ALWAYS_SEND_EN + 7 + 1 + + + ALWAYS_SEND_NUM + 4 + 3 + + + SINGLE_SEND_EN + 3 + 1 + + + SINGLE_SEND_NUM + 0 + 3 + + + + + Q0_WORD0 + 0x78 + UHCI_Q0_WORD0 + 32 + 0x00000000 + + + SEND_Q0_WORD0 + 0 + 32 + + + + + Q0_WORD1 + 0x7c + UHCI_Q0_WORD1 + 32 + 0x00000000 + + + SEND_Q0_WORD1 + 0 + 32 + + + + + Q1_WORD0 + 0x80 + UHCI_Q1_WORD0 + 32 + 0x00000000 + + + SEND_Q1_WORD0 + 0 + 32 + + + + + Q1_WORD1 + 0x84 + UHCI_Q1_WORD1 + 32 + 0x00000000 + + + SEND_Q1_WORD1 + 0 + 32 + + + + + Q2_WORD0 + 0x88 + UHCI_Q2_WORD0 + 32 + 0x00000000 + + + SEND_Q2_WORD0 + 0 + 32 + + + + + Q2_WORD1 + 0x8c + UHCI_Q2_WORD1 + 32 + 0x00000000 + + + SEND_Q2_WORD1 + 0 + 32 + + + + + Q3_WORD0 + 0x90 + UHCI_Q3_WORD0 + 32 + 0x00000000 + + + SEND_Q3_WORD0 + 0 + 32 + + + + + Q3_WORD1 + 0x94 + UHCI_Q3_WORD1 + 32 + 0x00000000 + + + SEND_Q3_WORD1 + 0 + 32 + + + + + Q4_WORD0 + 0x98 + UHCI_Q4_WORD0 + 32 + 0x00000000 + + + SEND_Q4_WORD0 + 0 + 32 + + + + + Q4_WORD1 + 0x9c + UHCI_Q4_WORD1 + 32 + 0x00000000 + + + SEND_Q4_WORD1 + 0 + 32 + + + + + Q5_WORD0 + 0xa0 + UHCI_Q5_WORD0 + 32 + 0x00000000 + + + SEND_Q5_WORD0 + 0 + 32 + + + + + Q5_WORD1 + 0xa4 + UHCI_Q5_WORD1 + 32 + 0x00000000 + + + SEND_Q5_WORD1 + 0 + 32 + + + + + Q6_WORD0 + 0xa8 + UHCI_Q6_WORD0 + 32 + 0x00000000 + + + SEND_Q6_WORD0 + 0 + 32 + + + + + Q6_WORD1 + 0xac + UHCI_Q6_WORD1 + 32 + 0x00000000 + + + SEND_Q6_WORD1 + 0 + 32 + + + + + ESC_CONF0 + 0xb0 + UHCI_ESC_CONF0 + 32 + 0x00000000 + + + SEPER_ESC_CHAR1 + 16 + 8 + + + SEPER_ESC_CHAR0 + 8 + 8 + + + SEPER_CHAR + 0 + 8 + + + + + ESC_CONF1 + 0xb4 + UHCI_ESC_CONF1 + 32 + 0x00000000 + + + ESC_SEQ0_CHAR1 + 16 + 8 + + + ESC_SEQ0_CHAR0 + 8 + 8 + + + ESC_SEQ0 + 0 + 8 + + + + + ESC_CONF2 + 0xb8 + UHCI_ESC_CONF2 + 32 + 0x00000000 + + + ESC_SEQ1_CHAR1 + 16 + 8 + + + ESC_SEQ1_CHAR0 + 8 + 8 + + + ESC_SEQ1 + 0 + 8 + + + + + ESC_CONF3 + 0xbc + UHCI_ESC_CONF3 + 32 + 0x00000000 + + + ESC_SEQ2_CHAR1 + 16 + 8 + + + ESC_SEQ2_CHAR0 + 8 + 8 + + + ESC_SEQ2 + 0 + 8 + + + + + PKT_THRES + 0xc0 + UHCI_PKT_THRES + 32 + 0x00000000 + + + PKT_THRS + 0 + 13 + + + + + DATE + 0xfc + UHCI_DATE + 32 + 0x00000000 + + + DATE + 0 + 32 + + + + + UHCI0_INTRinterrupt of UHCI0, level12 + UHCI1_INTRinterrupt of UHCI1, level13 + + + SLCHOST + 0x3ff55000 + + 0 + 0x00000800 + registers + + + + HOST_SLCHOST_FUNC2_0 + 0x10 + HOST_SLCHOST_FUNC2_0 + 32 + 0x00000000 + + + HOST_SLC_FUNC2_INT + 24 + 1 + + + + + HOST_SLCHOST_FUNC2_1 + 0x14 + HOST_SLCHOST_FUNC2_1 + 32 + 0x00000000 + + + HOST_SLC_FUNC2_INT_EN + 0 + 1 + + + + + HOST_SLCHOST_FUNC2_2 + 0x20 + HOST_SLCHOST_FUNC2_2 + 32 + 0x00000000 + + + HOST_SLC_FUNC1_MDSTAT + 0 + 1 + + + + + HOST_SLCHOST_GPIO_STATUS0 + 0x34 + HOST_SLCHOST_GPIO_STATUS0 + 32 + 0x00000000 + + + HOST_GPIO_SDIO_INT0 + 0 + 32 + + + + + HOST_SLCHOST_GPIO_STATUS1 + 0x38 + HOST_SLCHOST_GPIO_STATUS1 + 32 + 0x00000000 + + + HOST_GPIO_SDIO_INT1 + 0 + 8 + + + + + HOST_SLCHOST_GPIO_IN0 + 0x3c + HOST_SLCHOST_GPIO_IN0 + 32 + 0x00000000 + + + HOST_GPIO_SDIO_IN0 + 0 + 32 + + + + + HOST_SLCHOST_GPIO_IN1 + 0x40 + HOST_SLCHOST_GPIO_IN1 + 32 + 0x00000000 + + + HOST_GPIO_SDIO_IN1 + 0 + 8 + + + + + HOST_SLC0HOST_TOKEN_RDATA + 0x44 + HOST_SLC0HOST_TOKEN_RDATA + 32 + 0x00000000 + + + HOST_SLC0_RX_PF_EOF + 28 + 4 + + + HOST_HOSTSLC0_TOKEN1 + 16 + 12 + + + HOST_SLC0_RX_PF_VALID + 12 + 1 + + + HOST_SLC0_TOKEN0 + 0 + 12 + + + + + HOST_SLC0_HOST_PF + 0x48 + HOST_SLC0_HOST_PF + 32 + 0x00000000 + + + HOST_SLC0_PF_DATA + 0 + 32 + + + + + HOST_SLC1_HOST_PF + 0x4c + HOST_SLC1_HOST_PF + 32 + 0x00000000 + + + HOST_SLC1_PF_DATA + 0 + 32 + + + + + HOST_SLC0HOST_INT_RAW + 0x50 + HOST_SLC0HOST_INT_RAW + 32 + 0x00000000 + + + HOST_GPIO_SDIO_INT_RAW + 25 + 1 + + + HOST_SLC0_HOST_RD_RETRY_INT_RAW + 24 + 1 + + + HOST_SLC0_RX_NEW_PACKET_INT_RAW + 23 + 1 + + + HOST_SLC0_EXT_BIT3_INT_RAW + 22 + 1 + + + HOST_SLC0_EXT_BIT2_INT_RAW + 21 + 1 + + + HOST_SLC0_EXT_BIT1_INT_RAW + 20 + 1 + + + HOST_SLC0_EXT_BIT0_INT_RAW + 19 + 1 + + + HOST_SLC0_RX_PF_VALID_INT_RAW + 18 + 1 + + + HOST_SLC0_TX_OVF_INT_RAW + 17 + 1 + + + HOST_SLC0_RX_UDF_INT_RAW + 16 + 1 + + + HOST_SLC0HOST_TX_START_INT_RAW + 15 + 1 + + + HOST_SLC0HOST_RX_START_INT_RAW + 14 + 1 + + + HOST_SLC0HOST_RX_EOF_INT_RAW + 13 + 1 + + + HOST_SLC0HOST_RX_SOF_INT_RAW + 12 + 1 + + + HOST_SLC0_TOKEN1_0TO1_INT_RAW + 11 + 1 + + + HOST_SLC0_TOKEN0_0TO1_INT_RAW + 10 + 1 + + + HOST_SLC0_TOKEN1_1TO0_INT_RAW + 9 + 1 + + + HOST_SLC0_TOKEN0_1TO0_INT_RAW + 8 + 1 + + + HOST_SLC0_TOHOST_BIT7_INT_RAW + 7 + 1 + + + HOST_SLC0_TOHOST_BIT6_INT_RAW + 6 + 1 + + + HOST_SLC0_TOHOST_BIT5_INT_RAW + 5 + 1 + + + HOST_SLC0_TOHOST_BIT4_INT_RAW + 4 + 1 + + + HOST_SLC0_TOHOST_BIT3_INT_RAW + 3 + 1 + + + HOST_SLC0_TOHOST_BIT2_INT_RAW + 2 + 1 + + + HOST_SLC0_TOHOST_BIT1_INT_RAW + 1 + 1 + + + HOST_SLC0_TOHOST_BIT0_INT_RAW + 0 + 1 + + + + + HOST_SLC1HOST_INT_RAW + 0x54 + HOST_SLC1HOST_INT_RAW + 32 + 0x00000000 + + + HOST_SLC1_BT_RX_NEW_PACKET_INT_RAW + 25 + 1 + + + HOST_SLC1_HOST_RD_RETRY_INT_RAW + 24 + 1 + + + HOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW + 23 + 1 + + + HOST_SLC1_EXT_BIT3_INT_RAW + 22 + 1 + + + HOST_SLC1_EXT_BIT2_INT_RAW + 21 + 1 + + + HOST_SLC1_EXT_BIT1_INT_RAW + 20 + 1 + + + HOST_SLC1_EXT_BIT0_INT_RAW + 19 + 1 + + + HOST_SLC1_RX_PF_VALID_INT_RAW + 18 + 1 + + + HOST_SLC1_TX_OVF_INT_RAW + 17 + 1 + + + HOST_SLC1_RX_UDF_INT_RAW + 16 + 1 + + + HOST_SLC1HOST_TX_START_INT_RAW + 15 + 1 + + + HOST_SLC1HOST_RX_START_INT_RAW + 14 + 1 + + + HOST_SLC1HOST_RX_EOF_INT_RAW + 13 + 1 + + + HOST_SLC1HOST_RX_SOF_INT_RAW + 12 + 1 + + + HOST_SLC1_TOKEN1_0TO1_INT_RAW + 11 + 1 + + + HOST_SLC1_TOKEN0_0TO1_INT_RAW + 10 + 1 + + + HOST_SLC1_TOKEN1_1TO0_INT_RAW + 9 + 1 + + + HOST_SLC1_TOKEN0_1TO0_INT_RAW + 8 + 1 + + + HOST_SLC1_TOHOST_BIT7_INT_RAW + 7 + 1 + + + HOST_SLC1_TOHOST_BIT6_INT_RAW + 6 + 1 + + + HOST_SLC1_TOHOST_BIT5_INT_RAW + 5 + 1 + + + HOST_SLC1_TOHOST_BIT4_INT_RAW + 4 + 1 + + + HOST_SLC1_TOHOST_BIT3_INT_RAW + 3 + 1 + + + HOST_SLC1_TOHOST_BIT2_INT_RAW + 2 + 1 + + + HOST_SLC1_TOHOST_BIT1_INT_RAW + 1 + 1 + + + HOST_SLC1_TOHOST_BIT0_INT_RAW + 0 + 1 + + + + + HOST_SLC0HOST_INT_ST + 0x58 + HOST_SLC0HOST_INT_ST + 32 + 0x00000000 + + + HOST_GPIO_SDIO_INT_ST + 25 + 1 + + + HOST_SLC0_HOST_RD_RETRY_INT_ST + 24 + 1 + + + HOST_SLC0_RX_NEW_PACKET_INT_ST + 23 + 1 + + + HOST_SLC0_EXT_BIT3_INT_ST + 22 + 1 + + + HOST_SLC0_EXT_BIT2_INT_ST + 21 + 1 + + + HOST_SLC0_EXT_BIT1_INT_ST + 20 + 1 + + + HOST_SLC0_EXT_BIT0_INT_ST + 19 + 1 + + + HOST_SLC0_RX_PF_VALID_INT_ST + 18 + 1 + + + HOST_SLC0_TX_OVF_INT_ST + 17 + 1 + + + HOST_SLC0_RX_UDF_INT_ST + 16 + 1 + + + HOST_SLC0HOST_TX_START_INT_ST + 15 + 1 + + + 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21 + 1 + + + HOST_FN2_SLC0_EXT_BIT1_INT_ENA + 20 + 1 + + + HOST_FN2_SLC0_EXT_BIT0_INT_ENA + 19 + 1 + + + HOST_FN2_SLC0_RX_PF_VALID_INT_ENA + 18 + 1 + + + HOST_FN2_SLC0_TX_OVF_INT_ENA + 17 + 1 + + + HOST_FN2_SLC0_RX_UDF_INT_ENA + 16 + 1 + + + HOST_FN2_SLC0HOST_TX_START_INT_ENA + 15 + 1 + + + HOST_FN2_SLC0HOST_RX_START_INT_ENA + 14 + 1 + + + HOST_FN2_SLC0HOST_RX_EOF_INT_ENA + 13 + 1 + + + HOST_FN2_SLC0HOST_RX_SOF_INT_ENA + 12 + 1 + + + HOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA + 11 + 1 + + + HOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA + 10 + 1 + + + HOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA + 9 + 1 + + + HOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA + 8 + 1 + + + HOST_FN2_SLC0_TOHOST_BIT7_INT_ENA + 7 + 1 + + + HOST_FN2_SLC0_TOHOST_BIT6_INT_ENA + 6 + 1 + + + HOST_FN2_SLC0_TOHOST_BIT5_INT_ENA + 5 + 1 + + + HOST_FN2_SLC0_TOHOST_BIT4_INT_ENA + 4 + 1 + + + HOST_FN2_SLC0_TOHOST_BIT3_INT_ENA + 3 + 1 + + + HOST_FN2_SLC0_TOHOST_BIT2_INT_ENA + 2 + 1 + + + HOST_FN2_SLC0_TOHOST_BIT1_INT_ENA + 1 + 1 + + + HOST_FN2_SLC0_TOHOST_BIT0_INT_ENA + 0 + 1 + + + + + HOST_SLC1HOST_FUNC2_INT_ENA + 0xe8 + HOST_SLC1HOST_FUNC2_INT_ENA + 32 + 0x00000000 + + + HOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA + 25 + 1 + + + HOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA + 24 + 1 + + + HOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA + 23 + 1 + + + HOST_FN2_SLC1_EXT_BIT3_INT_ENA + 22 + 1 + + + HOST_FN2_SLC1_EXT_BIT2_INT_ENA + 21 + 1 + + + HOST_FN2_SLC1_EXT_BIT1_INT_ENA + 20 + 1 + + + HOST_FN2_SLC1_EXT_BIT0_INT_ENA + 19 + 1 + + + HOST_FN2_SLC1_RX_PF_VALID_INT_ENA + 18 + 1 + + + HOST_FN2_SLC1_TX_OVF_INT_ENA + 17 + 1 + + + HOST_FN2_SLC1_RX_UDF_INT_ENA + 16 + 1 + + + HOST_FN2_SLC1HOST_TX_START_INT_ENA + 15 + 1 + + + HOST_FN2_SLC1HOST_RX_START_INT_ENA + 14 + 1 + + + HOST_FN2_SLC1HOST_RX_EOF_INT_ENA + 13 + 1 + + + HOST_FN2_SLC1HOST_RX_SOF_INT_ENA + 12 + 1 + + + HOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA + 11 + 1 + + + HOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA + 10 + 1 + + + HOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA + 9 + 1 + + + HOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA + 8 + 1 + + + HOST_FN2_SLC1_TOHOST_BIT7_INT_ENA + 7 + 1 + + + HOST_FN2_SLC1_TOHOST_BIT6_INT_ENA + 6 + 1 + + + HOST_FN2_SLC1_TOHOST_BIT5_INT_ENA + 5 + 1 + + + HOST_FN2_SLC1_TOHOST_BIT4_INT_ENA + 4 + 1 + + + HOST_FN2_SLC1_TOHOST_BIT3_INT_ENA + 3 + 1 + + + HOST_FN2_SLC1_TOHOST_BIT2_INT_ENA + 2 + 1 + + + HOST_FN2_SLC1_TOHOST_BIT1_INT_ENA + 1 + 1 + + + HOST_FN2_SLC1_TOHOST_BIT0_INT_ENA + 0 + 1 + + + + + HOST_SLC0HOST_INT_ENA + 0xec + HOST_SLC0HOST_INT_ENA + 32 + 0x00000000 + + + HOST_GPIO_SDIO_INT_ENA + 25 + 1 + + + HOST_SLC0_HOST_RD_RETRY_INT_ENA + 24 + 1 + + + HOST_SLC0_RX_NEW_PACKET_INT_ENA + 23 + 1 + + + HOST_SLC0_EXT_BIT3_INT_ENA + 22 + 1 + + + HOST_SLC0_EXT_BIT2_INT_ENA + 21 + 1 + + + HOST_SLC0_EXT_BIT1_INT_ENA + 20 + 1 + + + HOST_SLC0_EXT_BIT0_INT_ENA + 19 + 1 + + + HOST_SLC0_RX_PF_VALID_INT_ENA + 18 + 1 + + + HOST_SLC0_TX_OVF_INT_ENA + 17 + 1 + + + HOST_SLC0_RX_UDF_INT_ENA + 16 + 1 + + + HOST_SLC0HOST_TX_START_INT_ENA + 15 + 1 + + + HOST_SLC0HOST_RX_START_INT_ENA + 14 + 1 + + + HOST_SLC0HOST_RX_EOF_INT_ENA + 13 + 1 + + + HOST_SLC0HOST_RX_SOF_INT_ENA + 12 + 1 + + + HOST_SLC0_TOKEN1_0TO1_INT_ENA + 11 + 1 + + + HOST_SLC0_TOKEN0_0TO1_INT_ENA + 10 + 1 + + + HOST_SLC0_TOKEN1_1TO0_INT_ENA + 9 + 1 + + + HOST_SLC0_TOKEN0_1TO0_INT_ENA + 8 + 1 + + + HOST_SLC0_TOHOST_BIT7_INT_ENA + 7 + 1 + + + HOST_SLC0_TOHOST_BIT6_INT_ENA + 6 + 1 + + + HOST_SLC0_TOHOST_BIT5_INT_ENA + 5 + 1 + + + HOST_SLC0_TOHOST_BIT4_INT_ENA + 4 + 1 + + + HOST_SLC0_TOHOST_BIT3_INT_ENA + 3 + 1 + + + HOST_SLC0_TOHOST_BIT2_INT_ENA + 2 + 1 + + + HOST_SLC0_TOHOST_BIT1_INT_ENA + 1 + 1 + + + HOST_SLC0_TOHOST_BIT0_INT_ENA + 0 + 1 + + + + + HOST_SLC1HOST_INT_ENA + 0xf0 + HOST_SLC1HOST_INT_ENA + 32 + 0x00000000 + + + HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA + 25 + 1 + + + HOST_SLC1_HOST_RD_RETRY_INT_ENA + 24 + 1 + + + HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA + 23 + 1 + + + HOST_SLC1_EXT_BIT3_INT_ENA + 22 + 1 + + + HOST_SLC1_EXT_BIT2_INT_ENA + 21 + 1 + + + HOST_SLC1_EXT_BIT1_INT_ENA + 20 + 1 + + + HOST_SLC1_EXT_BIT0_INT_ENA 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0xf8 + HOST_SLC1HOST_RX_INFOR + 32 + 0x00000000 + + + HOST_SLC1HOST_RX_INFOR + 0 + 20 + + + + + HOST_SLC0HOST_LEN_WD + 0xfc + HOST_SLC0HOST_LEN_WD + 32 + 0x00000000 + + + HOST_SLC0HOST_LEN_WD + 0 + 32 + + + + + HOST_SLC_APBWIN_WDATA + 0x100 + HOST_SLC_APBWIN_WDATA + 32 + 0x00000000 + + + HOST_SLC_APBWIN_WDATA + 0 + 32 + + + + + HOST_SLC_APBWIN_CONF + 0x104 + HOST_SLC_APBWIN_CONF + 32 + 0x00000000 + + + HOST_SLC_APBWIN_START + 29 + 1 + + + HOST_SLC_APBWIN_WR + 28 + 1 + + + HOST_SLC_APBWIN_ADDR + 0 + 28 + + + + + HOST_SLC_APBWIN_RDATA + 0x108 + HOST_SLC_APBWIN_RDATA + 32 + 0x00000000 + + + HOST_SLC_APBWIN_RDATA + 0 + 32 + + + + + HOST_SLCHOST_RDCLR0 + 0x10c + HOST_SLCHOST_RDCLR0 + 32 + 0x00000000 + + + HOST_SLCHOST_SLC0_BIT6_CLRADDR + 9 + 9 + + + HOST_SLCHOST_SLC0_BIT7_CLRADDR + 0 + 9 + + + + + HOST_SLCHOST_RDCLR1 + 0x110 + HOST_SLCHOST_RDCLR1 + 32 + 0x00000000 + + + HOST_SLCHOST_SLC1_BIT6_CLRADDR + 9 + 9 + + + HOST_SLCHOST_SLC1_BIT7_CLRADDR + 0 + 9 + + + + + HOST_SLC0HOST_INT_ENA1 + 0x114 + HOST_SLC0HOST_INT_ENA1 + 32 + 0x00000000 + + + HOST_GPIO_SDIO_INT_ENA1 + 25 + 1 + + + HOST_SLC0_HOST_RD_RETRY_INT_ENA1 + 24 + 1 + + + HOST_SLC0_RX_NEW_PACKET_INT_ENA1 + 23 + 1 + + + HOST_SLC0_EXT_BIT3_INT_ENA1 + 22 + 1 + + + HOST_SLC0_EXT_BIT2_INT_ENA1 + 21 + 1 + + + HOST_SLC0_EXT_BIT1_INT_ENA1 + 20 + 1 + + + HOST_SLC0_EXT_BIT0_INT_ENA1 + 19 + 1 + + + HOST_SLC0_RX_PF_VALID_INT_ENA1 + 18 + 1 + + + HOST_SLC0_TX_OVF_INT_ENA1 + 17 + 1 + + + HOST_SLC0_RX_UDF_INT_ENA1 + 16 + 1 + + + HOST_SLC0HOST_TX_START_INT_ENA1 + 15 + 1 + + + HOST_SLC0HOST_RX_START_INT_ENA1 + 14 + 1 + + + HOST_SLC0HOST_RX_EOF_INT_ENA1 + 13 + 1 + + + HOST_SLC0HOST_RX_SOF_INT_ENA1 + 12 + 1 + + + HOST_SLC0_TOKEN1_0TO1_INT_ENA1 + 11 + 1 + + + HOST_SLC0_TOKEN0_0TO1_INT_ENA1 + 10 + 1 + + + HOST_SLC0_TOKEN1_1TO0_INT_ENA1 + 9 + 1 + + + HOST_SLC0_TOKEN0_1TO0_INT_ENA1 + 8 + 1 + + + HOST_SLC0_TOHOST_BIT7_INT_ENA1 + 7 + 1 + + + HOST_SLC0_TOHOST_BIT6_INT_ENA1 + 6 + 1 + + + HOST_SLC0_TOHOST_BIT5_INT_ENA1 + 5 + 1 + + + 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HOST_SLC1_TOKEN0_0TO1_INT_ENA1 + 10 + 1 + + + HOST_SLC1_TOKEN1_1TO0_INT_ENA1 + 9 + 1 + + + HOST_SLC1_TOKEN0_1TO0_INT_ENA1 + 8 + 1 + + + HOST_SLC1_TOHOST_BIT7_INT_ENA1 + 7 + 1 + + + HOST_SLC1_TOHOST_BIT6_INT_ENA1 + 6 + 1 + + + HOST_SLC1_TOHOST_BIT5_INT_ENA1 + 5 + 1 + + + HOST_SLC1_TOHOST_BIT4_INT_ENA1 + 4 + 1 + + + HOST_SLC1_TOHOST_BIT3_INT_ENA1 + 3 + 1 + + + HOST_SLC1_TOHOST_BIT2_INT_ENA1 + 2 + 1 + + + HOST_SLC1_TOHOST_BIT1_INT_ENA1 + 1 + 1 + + + HOST_SLC1_TOHOST_BIT0_INT_ENA1 + 0 + 1 + + + + + HOST_SLCHOSTDATE + 0x178 + HOST_SLCHOSTDATE + 32 + 0x00000000 + + + HOST_SLCHOST_DATE + 0 + 32 + + + + + HOST_SLCHOSTID + 0x17c + HOST_SLCHOSTID + 32 + 0x00000000 + + + HOST_SLCHOST_ID + 0 + 32 + + + + + HOST_SLCHOST_CONF + 0x1f0 + HOST_SLCHOST_CONF + 32 + 0x00000000 + + + HOST_HSPEED_CON_EN + 27 + 1 + + + HOST_SDIO_PAD_PULLUP + 26 + 1 + + + HOST_SDIO20_INT_DELAY + 25 + 1 + + + HOST_FRC_QUICK_IN + 20 + 5 + + + HOST_FRC_POS_SAMP + 15 + 5 + + + HOST_FRC_NEG_SAMP + 10 + 5 + + + HOST_FRC_SDIO20 + 5 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SLC0_RX_PUSH_DSCR_ADDR + 0 + 32 + + + + + 0_DONE_DSCR_ADDR + 0x12c + SLC_0_DONE_DSCR_ADDR + 32 + 0x00000000 + + + SLC0_RX_DONE_DSCR_ADDR + 0 + 32 + + + + + 0_SUB_START_DES + 0x130 + SLC_0_SUB_START_DES + 32 + 0x00000000 + + + SLC0_SUB_PAC_START_DSCR_ADDR + 0 + 32 + + + + + 0_DSCR_CNT + 0x134 + SLC_0_DSCR_CNT + 32 + 0x00000000 + + + SLC0_RX_GET_EOF_OCC + 16 + 1 + + + SLC0_RX_DSCR_CNT_LAT + 0 + 10 + + + + + 0_LEN_LIM_CONF + 0x138 + SLC_0_LEN_LIM_CONF + 32 + 0x00000000 + + + SLC0_LEN_LIM + 0 + 20 + + + + + 0INT_ST1 + 0x13c + SLC_0INT_ST1 + 32 + 0x00000000 + + + SLC0_RX_QUICK_EOF_INT_ST1 + 26 + 1 + + + CMD_DTC_INT_ST1 + 25 + 1 + + + SLC0_TX_ERR_EOF_INT_ST1 + 24 + 1 + + + SLC0_WR_RETRY_DONE_INT_ST1 + 23 + 1 + + + SLC0_HOST_RD_ACK_INT_ST1 + 22 + 1 + + + SLC0_TX_DSCR_EMPTY_INT_ST1 + 21 + 1 + + + SLC0_RX_DSCR_ERR_INT_ST1 + 20 + 1 + + + SLC0_TX_DSCR_ERR_INT_ST1 + 19 + 1 + + + SLC0_TOHOST_INT_ST1 + 18 + 1 + + + SLC0_RX_EOF_INT_ST1 + 17 + 1 + + + SLC0_RX_DONE_INT_ST1 + 16 + 1 + + + SLC0_TX_SUC_EOF_INT_ST1 + 15 + 1 + + + SLC0_TX_DONE_INT_ST1 + 14 + 1 + + + SLC0_TOKEN1_1TO0_INT_ST1 + 13 + 1 + + + SLC0_TOKEN0_1TO0_INT_ST1 + 12 + 1 + + + SLC0_TX_OVF_INT_ST1 + 11 + 1 + + + SLC0_RX_UDF_INT_ST1 + 10 + 1 + + + SLC0_TX_START_INT_ST1 + 9 + 1 + + + SLC0_RX_START_INT_ST1 + 8 + 1 + + + FRHOST_BIT7_INT_ST1 + 7 + 1 + + + FRHOST_BIT6_INT_ST1 + 6 + 1 + + + FRHOST_BIT5_INT_ST1 + 5 + 1 + + + FRHOST_BIT4_INT_ST1 + 4 + 1 + + + FRHOST_BIT3_INT_ST1 + 3 + 1 + + + FRHOST_BIT2_INT_ST1 + 2 + 1 + + + FRHOST_BIT1_INT_ST1 + 1 + 1 + + + FRHOST_BIT0_INT_ST1 + 0 + 1 + + + + + 0INT_ENA1 + 0x140 + SLC_0INT_ENA1 + 32 + 0x00000000 + + + SLC0_RX_QUICK_EOF_INT_ENA1 + 26 + 1 + + + CMD_DTC_INT_ENA1 + 25 + 1 + + + SLC0_TX_ERR_EOF_INT_ENA1 + 24 + 1 + + + SLC0_WR_RETRY_DONE_INT_ENA1 + 23 + 1 + + + SLC0_HOST_RD_ACK_INT_ENA1 + 22 + 1 + + + SLC0_TX_DSCR_EMPTY_INT_ENA1 + 21 + 1 + + + SLC0_RX_DSCR_ERR_INT_ENA1 + 20 + 1 + + + SLC0_TX_DSCR_ERR_INT_ENA1 + 19 + 1 + + + SLC0_TOHOST_INT_ENA1 + 18 + 1 + + + SLC0_RX_EOF_INT_ENA1 + 17 + 1 + + + SLC0_RX_DONE_INT_ENA1 + 16 + 1 + + + SLC0_TX_SUC_EOF_INT_ENA1 + 15 + 1 + + + SLC0_TX_DONE_INT_ENA1 + 14 + 1 + + + SLC0_TOKEN1_1TO0_INT_ENA1 + 13 + 1 + + + SLC0_TOKEN0_1TO0_INT_ENA1 + 12 + 1 + + + SLC0_TX_OVF_INT_ENA1 + 11 + 1 + + + SLC0_RX_UDF_INT_ENA1 + 10 + 1 + + + SLC0_TX_START_INT_ENA1 + 9 + 1 + + + SLC0_RX_START_INT_ENA1 + 8 + 1 + + + FRHOST_BIT7_INT_ENA1 + 7 + 1 + + + FRHOST_BIT6_INT_ENA1 + 6 + 1 + + + FRHOST_BIT5_INT_ENA1 + 5 + 1 + + + FRHOST_BIT4_INT_ENA1 + 4 + 1 + + + FRHOST_BIT3_INT_ENA1 + 3 + 1 + + + FRHOST_BIT2_INT_ENA1 + 2 + 1 + + + FRHOST_BIT1_INT_ENA1 + 1 + 1 + + + FRHOST_BIT0_INT_ENA1 + 0 + 1 + + + + + 1INT_ST1 + 0x144 + SLC_1INT_ST1 + 32 + 0x00000000 + + + SLC1_TX_ERR_EOF_INT_ST1 + 24 + 1 + + + SLC1_WR_RETRY_DONE_INT_ST1 + 23 + 1 + + + SLC1_HOST_RD_ACK_INT_ST1 + 22 + 1 + + + SLC1_TX_DSCR_EMPTY_INT_ST1 + 21 + 1 + + + SLC1_RX_DSCR_ERR_INT_ST1 + 20 + 1 + + + SLC1_TX_DSCR_ERR_INT_ST1 + 19 + 1 + + + SLC1_TOHOST_INT_ST1 + 18 + 1 + + + SLC1_RX_EOF_INT_ST1 + 17 + 1 + + + SLC1_RX_DONE_INT_ST1 + 16 + 1 + + + SLC1_TX_SUC_EOF_INT_ST1 + 15 + 1 + + + SLC1_TX_DONE_INT_ST1 + 14 + 1 + + + SLC1_TOKEN1_1TO0_INT_ST1 + 13 + 1 + + + SLC1_TOKEN0_1TO0_INT_ST1 + 12 + 1 + + + SLC1_TX_OVF_INT_ST1 + 11 + 1 + + + SLC1_RX_UDF_INT_ST1 + 10 + 1 + + + SLC1_TX_START_INT_ST1 + 9 + 1 + + + SLC1_RX_START_INT_ST1 + 8 + 1 + + + FRHOST_BIT15_INT_ST1 + 7 + 1 + + + FRHOST_BIT14_INT_ST1 + 6 + 1 + + + FRHOST_BIT13_INT_ST1 + 5 + 1 + + + FRHOST_BIT12_INT_ST1 + 4 + 1 + + + FRHOST_BIT11_INT_ST1 + 3 + 1 + + + FRHOST_BIT10_INT_ST1 + 2 + 1 + + + FRHOST_BIT9_INT_ST1 + 1 + 1 + + + FRHOST_BIT8_INT_ST1 + 0 + 1 + + + + + 1INT_ENA1 + 0x148 + SLC_1INT_ENA1 + 32 + 0x00000000 + + + SLC1_TX_ERR_EOF_INT_ENA1 + 24 + 1 + + + SLC1_WR_RETRY_DONE_INT_ENA1 + 23 + 1 + + + SLC1_HOST_RD_ACK_INT_ENA1 + 22 + 1 + + + SLC1_TX_DSCR_EMPTY_INT_ENA1 + 21 + 1 + + + SLC1_RX_DSCR_ERR_INT_ENA1 + 20 + 1 + + + SLC1_TX_DSCR_ERR_INT_ENA1 + 19 + 1 + + + SLC1_TOHOST_INT_ENA1 + 18 + 1 + + + SLC1_RX_EOF_INT_ENA1 + 17 + 1 + + + SLC1_RX_DONE_INT_ENA1 + 16 + 1 + + + SLC1_TX_SUC_EOF_INT_ENA1 + 15 + 1 + + + SLC1_TX_DONE_INT_ENA1 + 14 + 1 + + + SLC1_TOKEN1_1TO0_INT_ENA1 + 13 + 1 + + + SLC1_TOKEN0_1TO0_INT_ENA1 + 12 + 1 + + + SLC1_TX_OVF_INT_ENA1 + 11 + 1 + + + SLC1_RX_UDF_INT_ENA1 + 10 + 1 + + + SLC1_TX_START_INT_ENA1 + 9 + 1 + + + SLC1_RX_START_INT_ENA1 + 8 + 1 + + + FRHOST_BIT15_INT_ENA1 + 7 + 1 + + + FRHOST_BIT14_INT_ENA1 + 6 + 1 + + + FRHOST_BIT13_INT_ENA1 + 5 + 1 + + + FRHOST_BIT12_INT_ENA1 + 4 + 1 + + + FRHOST_BIT11_INT_ENA1 + 3 + 1 + + + FRHOST_BIT10_INT_ENA1 + 2 + 1 + + + FRHOST_BIT9_INT_ENA1 + 1 + 1 + + + FRHOST_BIT8_INT_ENA1 + 0 + 1 + + + + + DATE + 0x1f8 + SLC_DATE + 32 + 0x00000000 + + + DATE + 0 + 32 + + + + + ID + 0x1fc + SLC_ID + 32 + 0x00000000 + + + ID + 0 + 32 + + + + + SLC0_INTRinterrupt of SLC0, level10 + SLC1_INTRinterrupt of SLC1, level11 + + + RTCMEM0 + 0x3ff61000 + + 0 + 0x00000000 + registers + + + + + TIMG1 + 0x3ff60000 + + + SHA + 0x3ff03000 + + 0 + 0x00000000 + registers + + + + + PWM1 + 0x3ff6c000 + + + RTCCNTL + 0x3ff48000 + + + OPTIONS0 + 0x0 + RTC_CNTL_OPTIONS0 + 32 + 0x00000000 + + + SW_SYS_RST + 31 + 1 + + + DG_WRAP_FORCE_NORST + 30 + 1 + + + DG_WRAP_FORCE_RST + 29 + 1 + + + ANALOG_FORCE_NOISO + 28 + 1 + + + PLL_FORCE_NOISO + 27 + 1 + + + XTL_FORCE_NOISO + 26 + 1 + + + ANALOG_FORCE_ISO + 25 + 1 + + + PLL_FORCE_ISO + 24 + 1 + + + XTL_FORCE_ISO + 23 + 1 + + + BIAS_CORE_FORCE_PU + 22 + 1 + + + BIAS_CORE_FORCE_PD + 21 + 1 + + + BIAS_CORE_FOLW_8M + 20 + 1 + + + BIAS_I2C_FORCE_PU + 19 + 1 + + + BIAS_I2C_FORCE_PD + 18 + 1 + + + BIAS_I2C_FOLW_8M + 17 + 1 + + + BIAS_FORCE_NOSLEEP + 16 + 1 + + + BIAS_FORCE_SLEEP + 15 + 1 + + + BIAS_SLEEP_FOLW_8M + 14 + 1 + + + XTL_FORCE_PU + 13 + 1 + + + XTL_FORCE_PD + 12 + 1 + + + BBPLL_FORCE_PU + 11 + 1 + + + BBPLL_FORCE_PD + 10 + 1 + + + BBPLL_I2C_FORCE_PU + 9 + 1 + + + BBPLL_I2C_FORCE_PD + 8 + 1 + + + BB_I2C_FORCE_PU + 7 + 1 + + + BB_I2C_FORCE_PD + 6 + 1 + + + SW_PROCPU_RST + 5 + 1 + + + SW_APPCPU_RST + 4 + 1 + + + SW_STALL_PROCPU_C0 + 2 + 2 + + + SW_STALL_APPCPU_C0 + 0 + 2 + + + + + SLP_TIMER0 + 0x4 + RTC_CNTL_SLP_TIMER0 + 32 + 0x00000000 + + + SLP_VAL_LO + 0 + 32 + + + + + SLP_TIMER1 + 0x8 + RTC_CNTL_SLP_TIMER1 + 32 + 0x00000000 + + + MAIN_TIMER_ALARM_EN + 16 + 1 + + + SLP_VAL_HI + 0 + 16 + + + + + TIME_UPDATE + 0xc + RTC_CNTL_TIME_UPDATE + 32 + 0x00000000 + + + TIME_UPDATE + 31 + 1 + + + TIME_VALID + 30 + 1 + + + + + TIME0 + 0x10 + RTC_CNTL_TIME0 + 32 + 0x00000000 + + + TIME_LO + 0 + 32 + + + + + TIME1 + 0x14 + RTC_CNTL_TIME1 + 32 + 0x00000000 + + + TIME_HI + 0 + 16 + + + + + STATE0 + 0x18 + RTC_CNTL_STATE0 + 32 + 0x00000000 + + + SLEEP_EN + 31 + 1 + + + SLP_REJECT + 30 + 1 + + + SLP_WAKEUP + 29 + 1 + + + SDIO_ACTIVE_IND + 28 + 1 + + + ULP_CP_SLP_TIMER_EN + 24 + 1 + + + TOUCH_SLP_TIMER_EN + 23 + 1 + + + APB2RTC_BRIDGE_SEL + 22 + 1 + + + ULP_CP_WAKEUP_FORCE_EN + 21 + 1 + + + TOUCH_WAKEUP_FORCE_EN + 20 + 1 + + + + + TIMER1 + 0x1c + RTC_CNTL_TIMER1 + 32 + 0x00000000 + + + PLL_BUF_WAIT + 24 + 8 + + + XTL_BUF_WAIT + 14 + 10 + + + CK8M_WAIT + 6 + 8 + + + CPU_STALL_WAIT + 1 + 5 + + + CPU_STALL_EN + 0 + 1 + + + + + TIMER2 + 0x20 + RTC_CNTL_TIMER2 + 32 + 0x00000000 + + + MIN_TIME_CK8M_OFF + 24 + 8 + + + ULPCP_TOUCH_START_WAIT + 15 + 9 + + + + + TIMER3 + 0x24 + RTC_CNTL_TIMER3 + 32 + 0x00000000 + + + ROM_RAM_POWERUP_TIMER + 25 + 7 + + + ROM_RAM_WAIT_TIMER + 16 + 9 + + + WIFI_POWERUP_TIMER + 9 + 7 + + + WIFI_WAIT_TIMER + 0 + 9 + + + + + TIMER4 + 0x28 + RTC_CNTL_TIMER4 + 32 + 0x00000000 + + + DG_WRAP_POWERUP_TIMER + 25 + 7 + + + DG_WRAP_WAIT_TIMER + 16 + 9 + + + POWERUP_TIMER + 9 + 7 + + + WAIT_TIMER + 0 + 9 + + + + + TIMER5 + 0x2c + RTC_CNTL_TIMER5 + 32 + 0x00000000 + + + RTCMEM_POWERUP_TIMER + 25 + 7 + + + RTCMEM_WAIT_TIMER + 16 + 9 + + + MIN_SLP_VAL + 8 + 8 + + + ULP_CP_SUBTIMER_PREDIV + 0 + 8 + + + + + ANA_CONF + 0x30 + RTC_CNTL_ANA_CONF + 32 + 0x00000000 + + + PLL_I2C_PU + 31 + 1 + + + CKGEN_I2C_PU + 30 + 1 + + + RFRX_PBUS_PU + 28 + 1 + + + TXRF_I2C_PU + 27 + 1 + + + PVTMON_PU + 26 + 1 + + + BBPLL_CAL_SLP_START + 25 + 1 + + + PLLA_FORCE_PU + 24 + 1 + + + PLLA_FORCE_PD + 23 + 1 + + + + + RESET_STATE + 0x34 + RTC_CNTL_RESET_STATE + 32 + 0x00000000 + + + PROCPU_STAT_VECTOR_SEL + 13 + 1 + + + APPCPU_STAT_VECTOR_SEL + 12 + 1 + + + RESET_CAUSE_APPCPU + 6 + 6 + + + RESET_CAUSE_PROCPU + 0 + 6 + + + + + WAKEUP_STATE + 0x38 + RTC_CNTL_WAKEUP_STATE + 32 + 0x00000000 + + + GPIO_WAKEUP_FILTER + 22 + 1 + + + WAKEUP_ENA + 11 + 11 + + + WAKEUP_CAUSE + 0 + 11 + + + + + INT_ENA + 0x3c + RTC_CNTL_INT_ENA + 32 + 0x00000000 + + + MAIN_TIMER_INT_ENA + 8 + 1 + + + BROWN_OUT_INT_ENA + 7 + 1 + + + TOUCH_INT_ENA + 6 + 1 + + + ULP_CP_INT_ENA + 5 + 1 + + + TIME_VALID_INT_ENA + 4 + 1 + + + WDT_INT_ENA + 3 + 1 + + + SDIO_IDLE_INT_ENA + 2 + 1 + + + SLP_REJECT_INT_ENA + 1 + 1 + + + SLP_WAKEUP_INT_ENA + 0 + 1 + + + + + INT_RAW + 0x40 + RTC_CNTL_INT_RAW + 32 + 0x00000000 + + + MAIN_TIMER_INT_RAW + 8 + 1 + + + BROWN_OUT_INT_RAW + 7 + 1 + + + TOUCH_INT_RAW + 6 + 1 + + + ULP_CP_INT_RAW + 5 + 1 + + + TIME_VALID_INT_RAW + 4 + 1 + + + WDT_INT_RAW + 3 + 1 + + + SDIO_IDLE_INT_RAW + 2 + 1 + + + SLP_REJECT_INT_RAW + 1 + 1 + + + SLP_WAKEUP_INT_RAW + 0 + 1 + + + + + INT_ST + 0x44 + RTC_CNTL_INT_ST + 32 + 0x00000000 + + + MAIN_TIMER_INT_ST + 8 + 1 + + + BROWN_OUT_INT_ST + 7 + 1 + + + TOUCH_INT_ST + 6 + 1 + + + SAR_INT_ST + 5 + 1 + + + TIME_VALID_INT_ST + 4 + 1 + + + WDT_INT_ST + 3 + 1 + + + SDIO_IDLE_INT_ST + 2 + 1 + + + SLP_REJECT_INT_ST + 1 + 1 + + + SLP_WAKEUP_INT_ST + 0 + 1 + + + + + INT_CLR + 0x48 + RTC_CNTL_INT_CLR + 32 + 0x00000000 + + + MAIN_TIMER_INT_CLR + 8 + 1 + + + BROWN_OUT_INT_CLR + 7 + 1 + + + TOUCH_INT_CLR + 6 + 1 + + + SAR_INT_CLR + 5 + 1 + + + TIME_VALID_INT_CLR + 4 + 1 + + + WDT_INT_CLR + 3 + 1 + + + SDIO_IDLE_INT_CLR + 2 + 1 + + + SLP_REJECT_INT_CLR + 1 + 1 + + + SLP_WAKEUP_INT_CLR + 0 + 1 + + + + + STORE0 + 0x4c + RTC_CNTL_STORE0 + 32 + 0x00000000 + + + SCRATCH0 + 0 + 32 + + + + + STORE1 + 0x50 + RTC_CNTL_STORE1 + 32 + 0x00000000 + + + SCRATCH1 + 0 + 32 + + + + + STORE2 + 0x54 + RTC_CNTL_STORE2 + 32 + 0x00000000 + + + SCRATCH2 + 0 + 32 + + + + + STORE3 + 0x58 + RTC_CNTL_STORE3 + 32 + 0x00000000 + + + SCRATCH3 + 0 + 32 + + + + + EXT_XTL_CONF + 0x5c + RTC_CNTL_EXT_XTL_CONF + 32 + 0x00000000 + + + XTL_EXT_CTR_EN + 31 + 1 + + + XTL_EXT_CTR_LV + 30 + 1 + + + + + EXT_WAKEUP_CONF + 0x60 + RTC_CNTL_EXT_WAKEUP_CONF + 32 + 0x00000000 + + + EXT_WAKEUP1_LV + 31 + 1 + + + EXT_WAKEUP0_LV + 30 + 1 + + + + + SLP_REJECT_CONF + 0x64 + RTC_CNTL_SLP_REJECT_CONF + 32 + 0x00000000 + + + REJECT_CAUSE + 28 + 4 + + + DEEP_SLP_REJECT_EN + 27 + 1 + + + LIGHT_SLP_REJECT_EN + 26 + 1 + + + SDIO_REJECT_EN + 25 + 1 + + + GPIO_REJECT_EN + 24 + 1 + + + + + CPU_PERIOD_CONF + 0x68 + RTC_CNTL_CPU_PERIOD_CONF + 32 + 0x00000000 + + + CPUPERIOD_SEL + 30 + 2 + + + CPUSEL_CONF + 29 + 1 + + + + + SDIO_ACT_CONF + 0x6c + RTC_CNTL_SDIO_ACT_CONF + 32 + 0x00000000 + + + SDIO_ACT_DNUM + 22 + 10 + + + + + CLK_CONF + 0x70 + RTC_CNTL_CLK_CONF + 32 + 0x00000000 + + + ANA_CLK_RTC_SEL + 30 + 2 + ANA_CLK_RTC_SELread-writeSLOW_CKSelect slow clock0CK_XTAL_32KSelect XTAL_32K1CK8M_D256_OUTInternal 8 MHz RC oscillator, divided by 2562 + + + FAST_CLK_RTC_SEL + 29 + 1 + FAST_CLK_RTC_SELread-writeXTALSelect XTAL0CK8MSelect CK8M1 + + + SOC_CLK_SEL + 27 + 2 + SOC_CLK_SELread-writeXTALSelect XTAL clock0PLLSelect PLL clock1CK8MSelect CK8M clock2APLLSelect APLL clock3 + + + CK8M_FORCE_PU + 26 + 1 + CK8M_FORCE_PUread-writeClearDon't force power up0ForceForce power up1 + + + CK8M_FORCE_PD + 25 + 1 + CK8M_FORCE_PDread-writeClearDon't force power down0ForceForce power down1 + + + CK8M_DFREQ + 17 + 8 + + + CK8M_FORCE_NOGATING + 16 + 1 + + + XTAL_FORCE_NOGATING + 15 + 1 + + + CK8M_DIV_SEL + 12 + 3 + + + CK8M_DFREQ_FORCE + 11 + 1 + + + DIG_CLK8M_EN + 10 + 1 + DIG_CLK8M_ENread-writeDisableDisable CK8M0EnableEnable CK8M for digital core (no relation to RTC core)1 + + + DIG_CLK8M_D256_EN + 9 + 1 + DIG_CLK8M_D256_ENread-writeDisableDisable CK8M_D256_OUT0EnableEnable CK8M_D256_OUT for digital core (no relation to RTC core)1 + + + DIG_XTAL32K_EN + 8 + 1 + DIG_XTAL32K_ENread-writeDisableDisable CK_XTAL_32K0EnableEnable CK_XTAL_32K for digital core(no relation to RTC core)1 + + + ENB_CK8M_DIV + 7 + 1 + + + ENB_CK8M + 6 + 1 + + + CK8M_DIV + 4 + 2 + CK8M_DIVread-writediv128div1280div256div2561div512div5122div1024div10243 + + + + + SDIO_CONF + 0x74 + RTC_CNTL_SDIO_CONF + 32 + 0x00000000 + + + XPD_SDIO_REG + 31 + 1 + + + DREFH_SDIO + 29 + 2 + + + DREFM_SDIO + 27 + 2 + + + DREFL_SDIO + 25 + 2 + + + REG1P8_READY + 24 + 1 + + + SDIO_TIEH + 23 + 1 + + + SDIO_FORCE + 22 + 1 + + + SDIO_PD_EN + 21 + 1 + + + + + BIAS_CONF + 0x78 + RTC_CNTL_BIAS_CONF + 32 + 0x00000000 + + + RST_BIAS_I2C + 31 + 1 + + + DEC_HEARTBEAT_WIDTH + 30 + 1 + + + INC_HEARTBEAT_PERIOD + 29 + 1 + + + DEC_HEARTBEAT_PERIOD + 28 + 1 + + + INC_HEARTBEAT_REFRESH + 27 + 1 + + + ENB_SCK_XTAL + 26 + 1 + + + DBG_ATTEN + 24 + 2 + + + FORCE_PU + 31 + 1 + + + FORCE_PD + 30 + 1 + + + DBOOST_FORCE_PU + 29 + 1 + + + DBOOST_FORCE_PD + 28 + 1 + + + DBIAS_WAK + 25 + 3 + + + DBIAS_SLP + 22 + 3 + + + SCK_DCAP + 14 + 8 + + + DIG_DBIAS_WAK + 11 + 3 + + + DIG_DBIAS_SLP + 8 + 3 + + + SCK_DCAP_FORCE + 7 + 1 + + + + + PWC + 0x80 + RTC_CNTL_PWC + 32 + 0x00000000 + + + PD_EN + 20 + 1 + + + FORCE_PU + 19 + 1 + + + FORCE_PD + 18 + 1 + + + SLOWMEM_PD_EN + 17 + 1 + + + SLOWMEM_FORCE_PU + 16 + 1 + + + SLOWMEM_FORCE_PD + 15 + 1 + + + FASTMEM_PD_EN + 14 + 1 + + + FASTMEM_FORCE_PU + 13 + 1 + + + FASTMEM_FORCE_PD + 12 + 1 + + + SLOWMEM_FORCE_LPU + 11 + 1 + + + SLOWMEM_FORCE_LPD + 10 + 1 + + + SLOWMEM_FOLW_CPU + 9 + 1 + + + FASTMEM_FORCE_LPU + 8 + 1 + + + FASTMEM_FORCE_LPD + 7 + 1 + + + FASTMEM_FOLW_CPU + 6 + 1 + + + FORCE_NOISO + 5 + 1 + + + FORCE_ISO + 4 + 1 + + + SLOWMEM_FORCE_ISO + 3 + 1 + + + SLOWMEM_FORCE_NOISO + 2 + 1 + + + FASTMEM_FORCE_ISO + 1 + 1 + + + FASTMEM_FORCE_NOISO + 0 + 1 + + + + + DIG_PWC + 0x84 + RTC_CNTL_DIG_PWC + 32 + 0x00000000 + + + DG_WRAP_PD_EN + 31 + 1 + + + WIFI_PD_EN + 30 + 1 + + + INTER_RAM4_PD_EN + 29 + 1 + + + INTER_RAM3_PD_EN + 28 + 1 + + + INTER_RAM2_PD_EN + 27 + 1 + + + INTER_RAM1_PD_EN + 26 + 1 + + + INTER_RAM0_PD_EN + 25 + 1 + + + ROM0_PD_EN + 24 + 1 + + + DG_WRAP_FORCE_PU + 20 + 1 + + + DG_WRAP_FORCE_PD + 19 + 1 + + + WIFI_FORCE_PU + 18 + 1 + + + WIFI_FORCE_PD + 17 + 1 + + + INTER_RAM4_FORCE_PU + 16 + 1 + + + INTER_RAM4_FORCE_PD + 15 + 1 + + + INTER_RAM3_FORCE_PU + 14 + 1 + + + INTER_RAM3_FORCE_PD + 13 + 1 + + + INTER_RAM2_FORCE_PU + 12 + 1 + + + INTER_RAM2_FORCE_PD + 11 + 1 + + + INTER_RAM1_FORCE_PU + 10 + 1 + + + INTER_RAM1_FORCE_PD + 9 + 1 + + + INTER_RAM0_FORCE_PU + 8 + 1 + + + INTER_RAM0_FORCE_PD + 7 + 1 + + + ROM0_FORCE_PU + 6 + 1 + + + ROM0_FORCE_PD + 5 + 1 + + + LSLP_MEM_FORCE_PU + 4 + 1 + + + LSLP_MEM_FORCE_PD + 3 + 1 + + + + + DIG_ISO + 0x88 + RTC_CNTL_DIG_ISO + 32 + 0x00000000 + + + DG_WRAP_FORCE_NOISO + 31 + 1 + + + DG_WRAP_FORCE_ISO + 30 + 1 + + + WIFI_FORCE_NOISO + 29 + 1 + + + WIFI_FORCE_ISO + 28 + 1 + + + INTER_RAM4_FORCE_NOISO + 27 + 1 + + + INTER_RAM4_FORCE_ISO + 26 + 1 + + + INTER_RAM3_FORCE_NOISO + 25 + 1 + + + INTER_RAM3_FORCE_ISO + 24 + 1 + + + INTER_RAM2_FORCE_NOISO + 23 + 1 + + + INTER_RAM2_FORCE_ISO + 22 + 1 + + + INTER_RAM1_FORCE_NOISO + 21 + 1 + + + INTER_RAM1_FORCE_ISO + 20 + 1 + + + INTER_RAM0_FORCE_NOISO + 19 + 1 + + + INTER_RAM0_FORCE_ISO + 18 + 1 + + + ROM0_FORCE_NOISO + 17 + 1 + + + ROM0_FORCE_ISO + 16 + 1 + + + DG_PAD_FORCE_HOLD + 15 + 1 + + + DG_PAD_FORCE_UNHOLD + 14 + 1 + + + DG_PAD_FORCE_ISO + 13 + 1 + + + DG_PAD_FORCE_NOISO + 12 + 1 + + + DG_PAD_AUTOHOLD_EN + 11 + 1 + + + CLR_DG_PAD_AUTOHOLD + 10 + 1 + + + DG_PAD_AUTOHOLD + 9 + 1 + + + DIG_ISO_FORCE_ON + 8 + 1 + + + DIG_ISO_FORCE_OFF + 7 + 1 + + + + + WDTCONFIG0 + 0x8c + RTC_CNTL_WDTCONFIG0 + 32 + 0x00000000 + + + WDT_EN + 31 + 1 + + + WDT_STG0 + 28 + 3 + WDT_STG0read-writeDisableDisabled0InterruptTrigger an interrupt1ResetCPUReset CPU core2ResetSystemReset System, but not RTC3ResetRTCReset System & RTC4 + + + WDT_STG1 + 25 + 3 + + + + WDT_STG2 + 22 + 3 + + + + WDT_STG3 + 19 + 3 + + + + WDT_EDGE_INT_EN + 18 + 1 + + + WDT_LEVEL_INT_EN + 17 + 1 + + + WDT_CPU_RESET_LENGTH + 14 + 3 + WDT_CPU_RESET_LENGTHread-writeT100ns100ns0T200ns200ns1T300ns300ns2T400ns400ns3T500ns500ns4T800ns800ns5T1600ns1600ns6T3200ns3200ns7 + + + WDT_SYS_RESET_LENGTH + 11 + 3 + + + + WDT_FLASHBOOT_MOD_EN + 10 + 1 + + + WDT_PROCPU_RESET_EN + 9 + 1 + + + WDT_APPCPU_RESET_EN + 8 + 1 + + + WDT_PAUSE_IN_SLP + 7 + 1 + + + + + WDTCONFIG1 + 0x90 + RTC_CNTL_WDTCONFIG1 + 32 + 0x00000000 + + + WDT_STG0_HOLD + 0 + 32 + + + + + WDTCONFIG2 + 0x94 + RTC_CNTL_WDTCONFIG2 + 32 + 0x00000000 + + + WDT_STG1_HOLD + 0 + 32 + + + + + WDTCONFIG3 + 0x98 + RTC_CNTL_WDTCONFIG3 + 32 + 0x00000000 + + + WDT_STG2_HOLD + 0 + 32 + + + + + WDTCONFIG4 + 0x9c + RTC_CNTL_WDTCONFIG4 + 32 + 0x00000000 + + + WDT_STG3_HOLD + 0 + 32 + + + + + WDTFEED + 0xa0 + RTC_CNTL_WDTFEED + 32 + 0x00000000 + + + WDT_FEED + 31 + 1 + + + + + WDTWPROTECT + 0xa4 + RTC_CNTL_WDTWPROTECT + 32 + 0x00000000 + + + WDT_WKEY + 0 + 32 + + + + + TEST_MUX + 0xa8 + RTC_CNTL_TEST_MUX + 32 + 0x00000000 + + + DTEST_RTC + 30 + 2 + + + ENT_RTC + 29 + 1 + + + + + SW_CPU_STALL + 0xac + RTC_CNTL_SW_CPU_STALL + 32 + 0x00000000 + + + SW_STALL_PROCPU_C1 + 26 + 6 + + + SW_STALL_APPCPU_C1 + 20 + 6 + + + + + STORE4 + 0xb0 + RTC_CNTL_STORE4 + 32 + 0x00000000 + + + SCRATCH4 + 0 + 32 + + + + + STORE5 + 0xb4 + RTC_CNTL_STORE5 + 32 + 0x00000000 + + + SCRATCH5 + 0 + 32 + + + + + STORE6 + 0xb8 + RTC_CNTL_STORE6 + 32 + 0x00000000 + + + SCRATCH6 + 0 + 32 + + + + + STORE7 + 0xbc + RTC_CNTL_STORE7 + 32 + 0x00000000 + + + SCRATCH7 + 0 + 32 + + + + + DIAG1 + 0xc4 + RTC_CNTL_DIAG1 + 32 + 0x00000000 + + + LOW_POWER_DIAG1 + 0 + 32 + + + + + HOLD_FORCE + 0xc8 + RTC_CNTL_HOLD_FORCE + 32 + 0x00000000 + + + X32N_HOLD_FORCE + 17 + 1 + + + X32P_HOLD_FORCE + 16 + 1 + + + TOUCH_PAD7_HOLD_FORCE + 15 + 1 + + + TOUCH_PAD6_HOLD_FORCE + 14 + 1 + + + TOUCH_PAD5_HOLD_FORCE + 13 + 1 + + + TOUCH_PAD4_HOLD_FORCE + 12 + 1 + + + TOUCH_PAD3_HOLD_FORCE + 11 + 1 + + + TOUCH_PAD2_HOLD_FORCE + 10 + 1 + + + TOUCH_PAD1_HOLD_FORCE + 9 + 1 + + + TOUCH_PAD0_HOLD_FORCE + 8 + 1 + + + SENSE4_HOLD_FORCE + 7 + 1 + + + SENSE3_HOLD_FORCE + 6 + 1 + + + SENSE2_HOLD_FORCE + 5 + 1 + + + SENSE1_HOLD_FORCE + 4 + 1 + + + PDAC2_HOLD_FORCE + 3 + 1 + + + PDAC1_HOLD_FORCE + 2 + 1 + + + ADC2_HOLD_FORCE + 1 + 1 + + + ADC1_HOLD_FORCE + 0 + 1 + + + + + EXT_WAKEUP1 + 0xcc + RTC_CNTL_EXT_WAKEUP1 + 32 + 0x00000000 + + + EXT_WAKEUP1_STATUS_CLR + 18 + 1 + + + EXT_WAKEUP1_SEL + 0 + 18 + + + + + EXT_WAKEUP1_STATUS + 0xd0 + RTC_CNTL_EXT_WAKEUP1_STATUS + 32 + 0x00000000 + + + EXT_WAKEUP1_STATUS + 0 + 18 + + + + + BROWN_OUT + 0xd4 + RTC_CNTL_BROWN_OUT + 32 + 0x00000000 + + + BROWN_OUT_DET + 31 + 1 + + + BROWN_OUT_ENA + 30 + 1 + + + DBROWN_OUT_THRES + 27 + 3 + + + BROWN_OUT_RST_ENA + 26 + 1 + + + BROWN_OUT_RST_WAIT + 16 + 10 + + + BROWN_OUT_PD_RF_ENA + 15 + 1 + + + BROWN_OUT_CLOSE_FLASH_ENA + 14 + 1 + + + + + DATE + 0x13c + RTC_CNTL_DATE + 32 + 0x00000000 + + + CNTL_DATE + 0 + 28 + + + + CNTLFORCE_PUForce RTC power up311 + FORCE_PDForce RTC power down (decrease voltage to 0.8V or lower)301 + FORCE_DBOOST_PUForce DBOOST power up291 + FORCE_DBOOST_PDForce DBOOST power down281 + DBIAS_WAKRTC DBIAS during wakeup253DBIAS_WAKread-writeBIAS_0V90Core voltage 0.90V0BIAS_0V95Core voltage 0.95V1BIAS_1V00Core voltage 1.00V2BIAS_1V05Core voltage 1.05V3BIAS_1V10Core voltage 1.10V4BIAS_1V15Core voltage 1.15V5BIAS_1V20Core voltage 1.20V6BIAS_1V25Core voltage 1.25V7 + + DBIAS_SLPRTC DBIAS during sleep223 + + SCK_DCAP150kHz oscillator tuning148 + DIG_DBIAS_WAKDBIAS during wakeup113 + + DIG_DBIAS_SLPDBIAS during wakeup83 + + SCK_DCAP_FORCE150kHz tuning force71 + RTC Control Register12432read-write0 + APLLBLOCKBlock08 + ADDRAddress88 + DATAData168 + WRITEWrite241 + BUSYReady251 + APLL I2C Register53768193232read-write0 + PLLBLOCKBlock08 + ADDRAddress88 + DATAData168 + WRITEWrite241 + BUSYReady251 + PLL I2C Register53768193632read-write0 + + 01696RTC CNTL registers5376819204Internal I2C registersRTC_CORE_INTRinterrupt of rtc core, level, include rtc watchdog46 + + + PWM2 + 0x3ff6f000 + + + UHCI0 + 0x3ff54000 + + + SENS + 0x3ff48800 + + 0 + 0x00000540 + registers + + + + SAR_READ_CTRL + 0x0 + SENS_SAR_READ_CTRL + 32 + 0x00000000 + + + SAR1_DATA_INV + 28 + 1 + + + SAR1_DIG_FORCE + 27 + 1 + + + SAR1_SAMPLE_NUM + 19 + 8 + + + SAR1_CLK_GATED + 18 + 1 + + + SAR1_SAMPLE_BIT + 16 + 2 + + + SAR1_SAMPLE_CYCLE + 8 + 8 + + + SAR1_CLK_DIV + 0 + 8 + + + + + SAR_READ_STATUS1 + 0x4 + SENS_SAR_READ_STATUS1 + 32 + 0x00000000 + + + SAR1_READER_STATUS + 0 + 32 + + + + + SAR_MEAS_WAIT1 + 0x8 + SENS_SAR_MEAS_WAIT1 + 32 + 0x00000000 + + + SAR_AMP_WAIT2 + 16 + 16 + + + SAR_AMP_WAIT1 + 0 + 16 + + + + + SAR_MEAS_WAIT2 + 0xc + SENS_SAR_MEAS_WAIT2 + 32 + 0x00000000 + + + SAR2_RSTB_WAIT + 20 + 8 + + + FORCE_XPD_SAR + 18 + 2 + + + FORCE_XPD_AMP + 16 + 2 + + + SAR_AMP_WAIT3 + 0 + 16 + + + + + SAR_MEAS_CTRL + 0x10 + SENS_SAR_MEAS_CTRL + 32 + 0x00000000 + + + SAR2_XPD_WAIT + 24 + 8 + + + SAR_RSTB_FSM + 20 + 4 + + + XPD_SAR_FSM + 16 + 4 + + + AMP_SHORT_REF_GND_FSM + 12 + 4 + + + AMP_SHORT_REF_FSM + 8 + 4 + + + AMP_RST_FB_FSM + 4 + 4 + + + XPD_SAR_AMP_FSM + 0 + 4 + + + + + SAR_READ_STATUS2 + 0x14 + SENS_SAR_READ_STATUS2 + 32 + 0x00000000 + + + SAR2_READER_STATUS + 0 + 32 + + + + + ULP_CP_SLEEP_CYC0 + 0x18 + SENS_ULP_CP_SLEEP_CYC0 + 32 + 0x00000000 + + + SLEEP_CYCLES_S0 + 0 + 32 + + + + + ULP_CP_SLEEP_CYC1 + 0x1c + SENS_ULP_CP_SLEEP_CYC1 + 32 + 0x00000000 + + + SLEEP_CYCLES_S1 + 0 + 32 + + + + + ULP_CP_SLEEP_CYC2 + 0x20 + SENS_ULP_CP_SLEEP_CYC2 + 32 + 0x00000000 + + + SLEEP_CYCLES_S2 + 0 + 32 + + + + + ULP_CP_SLEEP_CYC3 + 0x24 + SENS_ULP_CP_SLEEP_CYC3 + 32 + 0x00000000 + + + SLEEP_CYCLES_S3 + 0 + 32 + + + + + ULP_CP_SLEEP_CYC4 + 0x28 + SENS_ULP_CP_SLEEP_CYC4 + 32 + 0x00000000 + + + SLEEP_CYCLES_S4 + 0 + 32 + + + + + SAR_START_FORCE + 0x2c + SENS_SAR_START_FORCE + 32 + 0x00000000 + + + SAR2_PWDET_EN + 24 + 1 + + + SAR1_STOP + 23 + 1 + + + SAR2_STOP + 22 + 1 + + + PC_INIT + 11 + 11 + + + SARCLK_EN + 10 + 1 + + + ULP_CP_START_TOP + 9 + 1 + + + ULP_CP_FORCE_START_TOP + 8 + 1 + + + SAR2_PWDET_CCT + 5 + 3 + + + SAR2_EN_TEST + 4 + 1 + + + SAR2_BIT_WIDTH + 2 + 2 + + + SAR1_BIT_WIDTH + 0 + 2 + + + + + SAR_MEM_WR_CTRL + 0x30 + SENS_SAR_MEM_WR_CTRL + 32 + 0x00000000 + + + RTC_MEM_WR_OFFST_CLR + 22 + 1 + + + MEM_WR_ADDR_SIZE + 11 + 11 + + + MEM_WR_ADDR_INIT + 0 + 11 + + + + + SAR_ATTEN1 + 0x34 + SENS_SAR_ATTEN1 + 32 + 0x00000000 + + + SAR1_ATTEN + 0 + 32 + + + + + SAR_ATTEN2 + 0x38 + SENS_SAR_ATTEN2 + 32 + 0x00000000 + + + SAR2_ATTEN + 0 + 32 + + + + + SAR_SLAVE_ADDR1 + 0x3c + SENS_SAR_SLAVE_ADDR1 + 32 + 0x00000000 + + + MEAS_STATUS + 22 + 8 + + + I2C_SLAVE_ADDR0 + 11 + 11 + + + I2C_SLAVE_ADDR1 + 0 + 11 + + + + + SAR_SLAVE_ADDR2 + 0x40 + SENS_SAR_SLAVE_ADDR2 + 32 + 0x00000000 + + + I2C_SLAVE_ADDR2 + 11 + 11 + + + I2C_SLAVE_ADDR3 + 0 + 11 + + + + + SAR_SLAVE_ADDR3 + 0x44 + SENS_SAR_SLAVE_ADDR3 + 32 + 0x00000000 + + + TSENS_RDY_OUT + 30 + 1 + + + TSENS_OUT + 22 + 8 + + + I2C_SLAVE_ADDR4 + 11 + 11 + + + I2C_SLAVE_ADDR5 + 0 + 11 + + + + + SAR_SLAVE_ADDR4 + 0x48 + SENS_SAR_SLAVE_ADDR4 + 32 + 0x00000000 + + + I2C_DONE + 30 + 1 + + + I2C_RDATA + 22 + 8 + + + I2C_SLAVE_ADDR6 + 11 + 11 + + + I2C_SLAVE_ADDR7 + 0 + 11 + + + + + SAR_TSENS_CTRL + 0x4c + SENS_SAR_TSENS_CTRL + 32 + 0x00000000 + + + TSENS_DUMP_OUT + 26 + 1 + + + TSENS_POWER_UP_FORCE + 25 + 1 + + + TSENS_POWER_UP + 24 + 1 + + + TSENS_CLK_DIV + 16 + 8 + + + TSENS_IN_INV + 15 + 1 + + + TSENS_CLK_GATED + 14 + 1 + + + TSENS_CLK_INV + 13 + 1 + + + TSENS_XPD_FORCE + 12 + 1 + + + TSENS_XPD_WAIT + 0 + 12 + + + + + SAR_I2C_CTRL + 0x50 + SENS_SAR_I2C_CTRL + 32 + 0x00000000 + + + SAR_I2C_START_FORCE + 29 + 1 + + + SAR_I2C_START + 28 + 1 + + + SAR_I2C_CTRL + 0 + 28 + + + + + SAR_MEAS_START1 + 0x54 + SENS_SAR_MEAS_START1 + 32 + 0x00000000 + + + SAR1_EN_PAD_FORCE + 31 + 1 + + + SAR1_EN_PAD + 19 + 12 + + + MEAS1_START_FORCE + 18 + 1 + + + MEAS1_START_SAR + 17 + 1 + + + MEAS1_DONE_SAR + 16 + 1 + + + MEAS1_DATA_SAR + 0 + 16 + + + + + SAR_TOUCH_CTRL1 + 0x58 + SENS_SAR_TOUCH_CTRL1 + 32 + 0x00000000 + + + HALL_PHASE_FORCE + 27 + 1 + + + XPD_HALL_FORCE + 26 + 1 + + + TOUCH_OUT_1EN + 25 + 1 + + + TOUCH_OUT_SEL + 24 + 1 + + + TOUCH_XPD_WAIT + 16 + 8 + + + TOUCH_MEAS_DELAY + 0 + 16 + + + + + SAR_TOUCH_THRES1 + 0x5c + SENS_SAR_TOUCH_THRES1 + 32 + 0x00000000 + + + TOUCH_OUT_TH0 + 16 + 16 + + + TOUCH_OUT_TH1 + 0 + 16 + + + + + SAR_TOUCH_THRES2 + 0x60 + SENS_SAR_TOUCH_THRES2 + 32 + 0x00000000 + + + TOUCH_OUT_TH2 + 16 + 16 + + + TOUCH_OUT_TH3 + 0 + 16 + + + + + SAR_TOUCH_THRES3 + 0x64 + SENS_SAR_TOUCH_THRES3 + 32 + 0x00000000 + + + TOUCH_OUT_TH4 + 16 + 16 + + + TOUCH_OUT_TH5 + 0 + 16 + + + + + SAR_TOUCH_THRES4 + 0x68 + SENS_SAR_TOUCH_THRES4 + 32 + 0x00000000 + + + TOUCH_OUT_TH6 + 16 + 16 + + + TOUCH_OUT_TH7 + 0 + 16 + + + + + SAR_TOUCH_THRES5 + 0x6c + SENS_SAR_TOUCH_THRES5 + 32 + 0x00000000 + + + TOUCH_OUT_TH8 + 16 + 16 + + + TOUCH_OUT_TH9 + 0 + 16 + + + + + SAR_TOUCH_OUT1 + 0x70 + SENS_SAR_TOUCH_OUT1 + 32 + 0x00000000 + + + TOUCH_MEAS_OUT0 + 16 + 16 + + + TOUCH_MEAS_OUT1 + 0 + 16 + + + + + SAR_TOUCH_OUT2 + 0x74 + SENS_SAR_TOUCH_OUT2 + 32 + 0x00000000 + + + TOUCH_MEAS_OUT2 + 16 + 16 + + + TOUCH_MEAS_OUT3 + 0 + 16 + + + + + SAR_TOUCH_OUT3 + 0x78 + SENS_SAR_TOUCH_OUT3 + 32 + 0x00000000 + + + TOUCH_MEAS_OUT4 + 16 + 16 + + + TOUCH_MEAS_OUT5 + 0 + 16 + + + + + SAR_TOUCH_OUT4 + 0x7c + SENS_SAR_TOUCH_OUT4 + 32 + 0x00000000 + + + TOUCH_MEAS_OUT6 + 16 + 16 + + + TOUCH_MEAS_OUT7 + 0 + 16 + + + + + SAR_TOUCH_OUT5 + 0x80 + SENS_SAR_TOUCH_OUT5 + 32 + 0x00000000 + + + TOUCH_MEAS_OUT8 + 16 + 16 + + + TOUCH_MEAS_OUT9 + 0 + 16 + + + + + SAR_TOUCH_CTRL2 + 0x84 + SENS_SAR_TOUCH_CTRL2 + 32 + 0x00000000 + + + TOUCH_MEAS_EN_CLR + 30 + 1 + + + TOUCH_SLEEP_CYCLES + 14 + 16 + + + TOUCH_START_FORCE + 13 + 1 + + + TOUCH_START_EN + 12 + 1 + + + TOUCH_START_FSM_EN + 11 + 1 + + + TOUCH_MEAS_DONE + 10 + 1 + + + TOUCH_MEAS_EN + 0 + 10 + + + + + SAR_TOUCH_ENABLE + 0x8c + SENS_SAR_TOUCH_ENABLE + 32 + 0x00000000 + + + TOUCH_PAD_OUTEN1 + 20 + 10 + + + TOUCH_PAD_OUTEN2 + 10 + 10 + + + TOUCH_PAD_WORKEN + 0 + 10 + + + + + SAR_READ_CTRL2 + 0x90 + SENS_SAR_READ_CTRL2 + 32 + 0x00000000 + + + SAR2_DATA_INV + 29 + 1 + + + SAR2_DIG_FORCE + 28 + 1 + + + SAR2_PWDET_FORCE + 27 + 1 + + + SAR2_SAMPLE_NUM + 19 + 8 + + + SAR2_CLK_GATED + 18 + 1 + + + SAR2_SAMPLE_BIT + 16 + 2 + + + SAR2_SAMPLE_CYCLE + 8 + 8 + + + SAR2_CLK_DIV + 0 + 8 + + + + + SAR_MEAS_START2 + 0x94 + SENS_SAR_MEAS_START2 + 32 + 0x00000000 + + + SAR2_EN_PAD_FORCE + 31 + 1 + + + SAR2_EN_PAD + 19 + 12 + + + MEAS2_START_FORCE + 18 + 1 + + + MEAS2_START_SAR + 17 + 1 + + + MEAS2_DONE_SAR + 16 + 1 + + + MEAS2_DATA_SAR + 0 + 16 + + + + + SAR_DAC_CTRL1 + 0x98 + SENS_SAR_DAC_CTRL1 + 32 + 0x00000000 + + + DAC_CLK_INV + 25 + 1 + + + DAC_CLK_FORCE_HIGH + 24 + 1 + + + DAC_CLK_FORCE_LOW + 23 + 1 + + + DAC_DIG_FORCE + 22 + 1 + + + DEBUG_BIT_SEL + 17 + 5 + + + SW_TONE_EN + 16 + 1 + + + SW_FSTEP + 0 + 16 + + + + + SAR_DAC_CTRL2 + 0x9c + SENS_SAR_DAC_CTRL2 + 32 + 0x00000000 + + + DAC_CW_EN2 + 25 + 1 + + + DAC_CW_EN1 + 24 + 1 + + + DAC_INV2 + 22 + 2 + + + DAC_INV1 + 20 + 2 + + + DAC_SCALE2 + 18 + 2 + + + DAC_SCALE1 + 16 + 2 + + + DAC_DC2 + 8 + 8 + + + DAC_DC1 + 0 + 8 + + + + + SAR_MEAS_CTRL2 + 0xa0 + SENS_SAR_MEAS_CTRL2 + 32 + 0x00000000 + + + AMP_SHORT_REF_GND_FORCE + 17 + 2 + + + AMP_SHORT_REF_FORCE + 15 + 2 + + + AMP_RST_FB_FORCE + 13 + 2 + + + SAR2_RSTB_FORCE + 11 + 2 + + + SAR_RSTB_FSM_IDLE + 10 + 1 + + + XPD_SAR_FSM_IDLE + 9 + 1 + + + AMP_SHORT_REF_GND_FSM_IDLE + 8 + 1 + + + AMP_SHORT_REF_FSM_IDLE + 7 + 1 + + + AMP_RST_FB_FSM_IDLE + 6 + 1 + + + XPD_SAR_AMP_FSM_IDLE + 5 + 1 + + + SAR1_DAC_XPD_FSM_IDLE + 4 + 1 + + + SAR1_DAC_XPD_FSM + 0 + 4 + + + + + SAR_NOUSE + 0xf8 + SENS_SAR_NOUSE + 32 + 0x00000000 + + + SAR_NOUSE + 0 + 32 + + + + + SARDATE + 0xfc + SENS_SARDATE + 32 + 0x00000000 + + + SAR_DATE + 0 + 28 + + + + + + + NRX + 0x3ff5cc00 + + 0 + 0x00000000 + registers + + + + + RTCIO + 0x3ff48400 + + 0 + 0x00000660 + registers + + + + RTC_GPIO_OUT + 0x0 + RTC_GPIO_OUT + 32 + 0x00000000 + + + RTC_GPIO_OUT_DATA + 14 + 18 + + + + + RTC_GPIO_OUT_W1TS + 0x4 + RTC_GPIO_OUT_W1TS + 32 + 0x00000000 + + + RTC_GPIO_OUT_DATA_W1TS + 14 + 18 + + + + + RTC_GPIO_OUT_W1TC + 0x8 + RTC_GPIO_OUT_W1TC + 32 + 0x00000000 + + + RTC_GPIO_OUT_DATA_W1TC + 14 + 18 + + + + + RTC_GPIO_ENABLE + 0xc + RTC_GPIO_ENABLE + 32 + 0x00000000 + + + RTC_GPIO_ENABLE + 14 + 18 + + + + + RTC_GPIO_ENABLE_W1TS + 0x10 + RTC_GPIO_ENABLE_W1TS + 32 + 0x00000000 + + + RTC_GPIO_ENABLE_W1TS + 14 + 18 + + + + + RTC_GPIO_ENABLE_W1TC + 0x14 + RTC_GPIO_ENABLE_W1TC + 32 + 0x00000000 + + + RTC_GPIO_ENABLE_W1TC + 14 + 18 + + + + + RTC_GPIO_STATUS + 0x18 + RTC_GPIO_STATUS + 32 + 0x00000000 + + + RTC_GPIO_STATUS_INT + 14 + 18 + + + + + RTC_GPIO_STATUS_W1TS + 0x1c + RTC_GPIO_STATUS_W1TS + 32 + 0x00000000 + + + RTC_GPIO_STATUS_INT_W1TS + 14 + 18 + + + + + RTC_GPIO_STATUS_W1TC + 0x20 + RTC_GPIO_STATUS_W1TC + 32 + 0x00000000 + + + RTC_GPIO_STATUS_INT_W1TC + 14 + 18 + + + + + RTC_GPIO_IN + 0x24 + RTC_GPIO_IN + 32 + 0x00000000 + + + RTC_GPIO_IN_NEXT + 14 + 18 + + + + + RTC_GPIO_PIN0 + 0x28 + RTC_GPIO_PIN0 + 32 + 0x00000000 + + + RTC_GPIO_PIN0_WAKEUP_ENABLE + 10 + 1 + + + RTC_GPIO_PIN0_INT_TYPE + 7 + 3 + + + RTC_GPIO_PIN0_PAD_DRIVER + 2 + 1 + + + + + RTC_GPIO_PIN1 + 0x2c + RTC_GPIO_PIN1 + 32 + 0x00000000 + + + RTC_GPIO_PIN1_WAKEUP_ENABLE + 10 + 1 + + + RTC_GPIO_PIN1_INT_TYPE + 7 + 3 + + + RTC_GPIO_PIN1_PAD_DRIVER + 2 + 1 + + + + + RTC_GPIO_PIN2 + 0x30 + RTC_GPIO_PIN2 + 32 + 0x00000000 + + + RTC_GPIO_PIN2_WAKEUP_ENABLE + 10 + 1 + + + RTC_GPIO_PIN2_INT_TYPE + 7 + 3 + + + RTC_GPIO_PIN2_PAD_DRIVER + 2 + 1 + + + + + RTC_GPIO_PIN3 + 0x34 + RTC_GPIO_PIN3 + 32 + 0x00000000 + + + RTC_GPIO_PIN3_WAKEUP_ENABLE + 10 + 1 + + + RTC_GPIO_PIN3_INT_TYPE + 7 + 3 + + + RTC_GPIO_PIN3_PAD_DRIVER + 2 + 1 + + + + + RTC_GPIO_PIN4 + 0x38 + RTC_GPIO_PIN4 + 32 + 0x00000000 + + + RTC_GPIO_PIN4_WAKEUP_ENABLE + 10 + 1 + + + RTC_GPIO_PIN4_INT_TYPE + 7 + 3 + + + RTC_GPIO_PIN4_PAD_DRIVER + 2 + 1 + + + + + RTC_GPIO_PIN5 + 0x3c + RTC_GPIO_PIN5 + 32 + 0x00000000 + + + RTC_GPIO_PIN5_WAKEUP_ENABLE + 10 + 1 + + + RTC_GPIO_PIN5_INT_TYPE + 7 + 3 + + + RTC_GPIO_PIN5_PAD_DRIVER + 2 + 1 + + + + + RTC_GPIO_PIN6 + 0x40 + RTC_GPIO_PIN6 + 32 + 0x00000000 + + + RTC_GPIO_PIN6_WAKEUP_ENABLE + 10 + 1 + + + RTC_GPIO_PIN6_INT_TYPE + 7 + 3 + + + RTC_GPIO_PIN6_PAD_DRIVER + 2 + 1 + + + + + RTC_GPIO_PIN7 + 0x44 + RTC_GPIO_PIN7 + 32 + 0x00000000 + + + RTC_GPIO_PIN7_WAKEUP_ENABLE + 10 + 1 + + + RTC_GPIO_PIN7_INT_TYPE + 7 + 3 + + + RTC_GPIO_PIN7_PAD_DRIVER + 2 + 1 + + + + + RTC_GPIO_PIN8 + 0x48 + RTC_GPIO_PIN8 + 32 + 0x00000000 + + + RTC_GPIO_PIN8_WAKEUP_ENABLE + 10 + 1 + + + RTC_GPIO_PIN8_INT_TYPE + 7 + 3 + + + RTC_GPIO_PIN8_PAD_DRIVER + 2 + 1 + + + + + RTC_GPIO_PIN9 + 0x4c + RTC_GPIO_PIN9 + 32 + 0x00000000 + + + RTC_GPIO_PIN9_WAKEUP_ENABLE + 10 + 1 + + + RTC_GPIO_PIN9_INT_TYPE + 7 + 3 + + + RTC_GPIO_PIN9_PAD_DRIVER + 2 + 1 + + + + + RTC_GPIO_PIN10 + 0x50 + RTC_GPIO_PIN10 + 32 + 0x00000000 + + + RTC_GPIO_PIN10_WAKEUP_ENABLE + 10 + 1 + + + RTC_GPIO_PIN10_INT_TYPE + 7 + 3 + + + RTC_GPIO_PIN10_PAD_DRIVER + 2 + 1 + + + + + RTC_GPIO_PIN11 + 0x54 + RTC_GPIO_PIN11 + 32 + 0x00000000 + + + RTC_GPIO_PIN11_WAKEUP_ENABLE + 10 + 1 + + + RTC_GPIO_PIN11_INT_TYPE + 7 + 3 + + + RTC_GPIO_PIN11_PAD_DRIVER + 2 + 1 + + + + + RTC_GPIO_PIN12 + 0x58 + RTC_GPIO_PIN12 + 32 + 0x00000000 + + + RTC_GPIO_PIN12_WAKEUP_ENABLE + 10 + 1 + + + RTC_GPIO_PIN12_INT_TYPE + 7 + 3 + + + RTC_GPIO_PIN12_PAD_DRIVER + 2 + 1 + + + + + RTC_GPIO_PIN13 + 0x5c + RTC_GPIO_PIN13 + 32 + 0x00000000 + + + RTC_GPIO_PIN13_WAKEUP_ENABLE + 10 + 1 + + + RTC_GPIO_PIN13_INT_TYPE + 7 + 3 + + + RTC_GPIO_PIN13_PAD_DRIVER + 2 + 1 + + + + + RTC_GPIO_PIN14 + 0x60 + RTC_GPIO_PIN14 + 32 + 0x00000000 + + + RTC_GPIO_PIN14_WAKEUP_ENABLE + 10 + 1 + + + RTC_GPIO_PIN14_INT_TYPE + 7 + 3 + + + RTC_GPIO_PIN14_PAD_DRIVER + 2 + 1 + + + + + RTC_GPIO_PIN15 + 0x64 + RTC_GPIO_PIN15 + 32 + 0x00000000 + + + RTC_GPIO_PIN15_WAKEUP_ENABLE + 10 + 1 + + + RTC_GPIO_PIN15_INT_TYPE + 7 + 3 + + + RTC_GPIO_PIN15_PAD_DRIVER + 2 + 1 + + + + + RTC_GPIO_PIN16 + 0x68 + RTC_GPIO_PIN16 + 32 + 0x00000000 + + + RTC_GPIO_PIN16_WAKEUP_ENABLE + 10 + 1 + + + RTC_GPIO_PIN16_INT_TYPE + 7 + 3 + + + RTC_GPIO_PIN16_PAD_DRIVER + 2 + 1 + + + + + RTC_GPIO_PIN17 + 0x6c + RTC_GPIO_PIN17 + 32 + 0x00000000 + + + RTC_GPIO_PIN17_WAKEUP_ENABLE + 10 + 1 + + + RTC_GPIO_PIN17_INT_TYPE + 7 + 3 + + + RTC_GPIO_PIN17_PAD_DRIVER + 2 + 1 + + + + + RTC_IO_RTC_DEBUG_SEL + 0x70 + RTC_IO_RTC_DEBUG_SEL + 32 + 0x00000000 + + + RTC_IO_DEBUG_12M_NO_GATING + 25 + 1 + + + RTC_IO_DEBUG_SEL4 + 20 + 5 + + + RTC_IO_DEBUG_SEL3 + 15 + 5 + + + RTC_IO_DEBUG_SEL2 + 10 + 5 + + + RTC_IO_DEBUG_SEL1 + 5 + 5 + + + RTC_IO_DEBUG_SEL0 + 0 + 5 + + + + + RTC_IO_DIG_PAD_HOLD + 0x74 + RTC_IO_DIG_PAD_HOLD + 32 + 0x00000000 + + + RTC_IO_DIG_PAD_HOLD + 0 + 32 + + + + + RTC_IO_HALL_SENS + 0x78 + RTC_IO_HALL_SENS + 32 + 0x00000000 + + + RTC_IO_XPD_HALL + 31 + 1 + + + RTC_IO_HALL_PHASE + 30 + 1 + + + + + RTC_IO_SENSOR_PADS + 0x7c + RTC_IO_SENSOR_PADS + 32 + 0x00000000 + + + RTC_IO_SENSE1_HOLD + 31 + 1 + + + RTC_IO_SENSE2_HOLD + 30 + 1 + + + RTC_IO_SENSE3_HOLD + 29 + 1 + + + RTC_IO_SENSE4_HOLD + 28 + 1 + + + RTC_IO_SENSE1_MUX_SEL + 27 + 1 + + + RTC_IO_SENSE2_MUX_SEL + 26 + 1 + + + RTC_IO_SENSE3_MUX_SEL + 25 + 1 + + + RTC_IO_SENSE4_MUX_SEL + 24 + 1 + + + RTC_IO_SENSE1_FUN_SEL + 22 + 2 + + + RTC_IO_SENSE1_SLP_SEL + 21 + 1 + + + RTC_IO_SENSE1_SLP_IE + 20 + 1 + + + RTC_IO_SENSE1_FUN_IE + 19 + 1 + + + RTC_IO_SENSE2_FUN_SEL + 17 + 2 + + + RTC_IO_SENSE2_SLP_SEL + 16 + 1 + + + RTC_IO_SENSE2_SLP_IE + 15 + 1 + + + RTC_IO_SENSE2_FUN_IE + 14 + 1 + + + RTC_IO_SENSE3_FUN_SEL + 12 + 2 + + + RTC_IO_SENSE3_SLP_SEL + 11 + 1 + + + RTC_IO_SENSE3_SLP_IE + 10 + 1 + + + RTC_IO_SENSE3_FUN_IE + 9 + 1 + + + RTC_IO_SENSE4_FUN_SEL + 7 + 2 + + + RTC_IO_SENSE4_SLP_SEL + 6 + 1 + + + RTC_IO_SENSE4_SLP_IE + 5 + 1 + + + RTC_IO_SENSE4_FUN_IE + 4 + 1 + + + + + RTC_IO_ADC_PAD + 0x80 + RTC_IO_ADC_PAD + 32 + 0x00000000 + + + RTC_IO_ADC1_HOLD + 31 + 1 + + + RTC_IO_ADC2_HOLD + 30 + 1 + + + RTC_IO_ADC1_MUX_SEL + 29 + 1 + + + RTC_IO_ADC2_MUX_SEL + 28 + 1 + + + RTC_IO_ADC1_FUN_SEL + 26 + 2 + + + RTC_IO_ADC1_SLP_SEL + 25 + 1 + + + RTC_IO_ADC1_SLP_IE + 24 + 1 + + + RTC_IO_ADC1_FUN_IE + 23 + 1 + + + RTC_IO_ADC2_FUN_SEL + 21 + 2 + + + RTC_IO_ADC2_SLP_SEL + 20 + 1 + + + RTC_IO_ADC2_SLP_IE + 19 + 1 + + + RTC_IO_ADC2_FUN_IE + 18 + 1 + + + + + RTC_IO_PAD_DAC1 + 0x84 + RTC_IO_PAD_DAC1 + 32 + 0x00000000 + + + RTC_IO_PDAC1_DRV + 30 + 2 + + + RTC_IO_PDAC1_HOLD + 29 + 1 + + + RTC_IO_PDAC1_RDE + 28 + 1 + + + RTC_IO_PDAC1_RUE + 27 + 1 + + + RTC_IO_PDAC1_DAC + 19 + 8 + + + RTC_IO_PDAC1_XPD_DAC + 18 + 1 + + + RTC_IO_PDAC1_MUX_SEL + 17 + 1 + + + RTC_IO_PDAC1_FUN_SEL + 15 + 2 + + + RTC_IO_PDAC1_SLP_SEL + 14 + 1 + + + RTC_IO_PDAC1_SLP_IE + 13 + 1 + + + RTC_IO_PDAC1_SLP_OE + 12 + 1 + + + RTC_IO_PDAC1_FUN_IE + 11 + 1 + + + RTC_IO_PDAC1_DAC_XPD_FORCE + 10 + 1 + + + + + RTC_IO_PAD_DAC2 + 0x88 + RTC_IO_PAD_DAC2 + 32 + 0x00000000 + + + RTC_IO_PDAC2_DRV + 30 + 2 + + + RTC_IO_PDAC2_HOLD + 29 + 1 + + + RTC_IO_PDAC2_RDE + 28 + 1 + + + RTC_IO_PDAC2_RUE + 27 + 1 + + + RTC_IO_PDAC2_DAC + 19 + 8 + + + RTC_IO_PDAC2_XPD_DAC + 18 + 1 + + + RTC_IO_PDAC2_MUX_SEL + 17 + 1 + + + RTC_IO_PDAC2_FUN_SEL + 15 + 2 + + + RTC_IO_PDAC2_SLP_SEL + 14 + 1 + + + RTC_IO_PDAC2_SLP_IE + 13 + 1 + + + RTC_IO_PDAC2_SLP_OE + 12 + 1 + + + RTC_IO_PDAC2_FUN_IE + 11 + 1 + + + RTC_IO_PDAC2_DAC_XPD_FORCE + 10 + 1 + + + + + RTC_IO_XTAL_32K_PAD + 0x8c + RTC_IO_XTAL_32K_PAD + 32 + 0x00000000 + + + RTC_IO_X32N_DRV + 30 + 2 + + + RTC_IO_X32N_HOLD + 29 + 1 + + + RTC_IO_X32N_RDE + 28 + 1 + + + RTC_IO_X32N_RUE + 27 + 1 + + + RTC_IO_X32P_DRV + 25 + 2 + + + RTC_IO_X32P_HOLD + 24 + 1 + + + RTC_IO_X32P_RDE + 23 + 1 + + + RTC_IO_X32P_RUE + 22 + 1 + + + RTC_IO_DAC_XTAL_32K + 20 + 2 + + + RTC_IO_XPD_XTAL_32K + 19 + 1 + + + RTC_IO_X32N_MUX_SEL + 18 + 1 + + + RTC_IO_X32P_MUX_SEL + 17 + 1 + + + RTC_IO_X32N_FUN_SEL + 15 + 2 + + + RTC_IO_X32N_SLP_SEL + 14 + 1 + + + RTC_IO_X32N_SLP_IE + 13 + 1 + + + RTC_IO_X32N_SLP_OE + 12 + 1 + + + RTC_IO_X32N_FUN_IE + 11 + 1 + + + RTC_IO_X32P_FUN_SEL + 9 + 2 + + + RTC_IO_X32P_SLP_SEL + 8 + 1 + + + RTC_IO_X32P_SLP_IE + 7 + 1 + + + RTC_IO_X32P_SLP_OE + 6 + 1 + + + RTC_IO_X32P_FUN_IE + 5 + 1 + + + RTC_IO_DRES_XTAL_32K + 3 + 2 + + + RTC_IO_DBIAS_XTAL_32K + 1 + 2 + + + + + RTC_IO_TOUCH_CFG + 0x90 + RTC_IO_TOUCH_CFG + 32 + 0x00000000 + + + RTC_IO_TOUCH_XPD_BIAS + 31 + 1 + + + RTC_IO_TOUCH_DREFH + 29 + 2 + + + RTC_IO_TOUCH_DREFL + 27 + 2 + + + RTC_IO_TOUCH_DRANGE + 25 + 2 + + + RTC_IO_TOUCH_DCUR + 23 + 2 + + + + + RTC_IO_TOUCH_PAD0 + 0x94 + RTC_IO_TOUCH_PAD0 + 32 + 0x00000000 + + + RTC_IO_TOUCH_PAD0_HOLD + 31 + 1 + + + RTC_IO_TOUCH_PAD0_DRV + 29 + 2 + + + RTC_IO_TOUCH_PAD0_RDE + 28 + 1 + + + RTC_IO_TOUCH_PAD0_RUE + 27 + 1 + + + RTC_IO_TOUCH_PAD0_DAC + 23 + 3 + + + RTC_IO_TOUCH_PAD0_START + 22 + 1 + + + RTC_IO_TOUCH_PAD0_TIE_OPT + 21 + 1 + + + RTC_IO_TOUCH_PAD0_XPD + 20 + 1 + + + RTC_IO_TOUCH_PAD0_MUX_SEL + 19 + 1 + + + RTC_IO_TOUCH_PAD0_FUN_SEL + 17 + 2 + + + RTC_IO_TOUCH_PAD0_SLP_SEL + 16 + 1 + + + RTC_IO_TOUCH_PAD0_SLP_IE + 15 + 1 + + + RTC_IO_TOUCH_PAD0_SLP_OE + 14 + 1 + + + RTC_IO_TOUCH_PAD0_FUN_IE + 13 + 1 + + + RTC_IO_TOUCH_PAD0_TO_GPIO + 12 + 1 + + + + + RTC_IO_TOUCH_PAD1 + 0x98 + RTC_IO_TOUCH_PAD1 + 32 + 0x00000000 + + + RTC_IO_TOUCH_PAD1_HOLD + 31 + 1 + + + RTC_IO_TOUCH_PAD1_DRV + 29 + 2 + + + RTC_IO_TOUCH_PAD1_RDE + 28 + 1 + + + RTC_IO_TOUCH_PAD1_RUE + 27 + 1 + + + RTC_IO_TOUCH_PAD1_DAC + 23 + 3 + + + RTC_IO_TOUCH_PAD1_START + 22 + 1 + + + RTC_IO_TOUCH_PAD1_TIE_OPT + 21 + 1 + + + RTC_IO_TOUCH_PAD1_XPD + 20 + 1 + + + RTC_IO_TOUCH_PAD1_MUX_SEL + 19 + 1 + + + RTC_IO_TOUCH_PAD1_FUN_SEL + 17 + 2 + + + RTC_IO_TOUCH_PAD1_SLP_SEL + 16 + 1 + + + RTC_IO_TOUCH_PAD1_SLP_IE + 15 + 1 + + + RTC_IO_TOUCH_PAD1_SLP_OE + 14 + 1 + + + RTC_IO_TOUCH_PAD1_FUN_IE + 13 + 1 + + + RTC_IO_TOUCH_PAD1_TO_GPIO + 12 + 1 + + + + + RTC_IO_TOUCH_PAD2 + 0x9c + RTC_IO_TOUCH_PAD2 + 32 + 0x00000000 + + + RTC_IO_TOUCH_PAD2_HOLD + 31 + 1 + + + RTC_IO_TOUCH_PAD2_DRV + 29 + 2 + + + RTC_IO_TOUCH_PAD2_RDE + 28 + 1 + + + RTC_IO_TOUCH_PAD2_RUE + 27 + 1 + + + RTC_IO_TOUCH_PAD2_DAC + 23 + 3 + + + RTC_IO_TOUCH_PAD2_START + 22 + 1 + + + RTC_IO_TOUCH_PAD2_TIE_OPT + 21 + 1 + + + RTC_IO_TOUCH_PAD2_XPD + 20 + 1 + + + RTC_IO_TOUCH_PAD2_MUX_SEL + 19 + 1 + + + RTC_IO_TOUCH_PAD2_FUN_SEL + 17 + 2 + + + RTC_IO_TOUCH_PAD2_SLP_SEL + 16 + 1 + + + RTC_IO_TOUCH_PAD2_SLP_IE + 15 + 1 + + + RTC_IO_TOUCH_PAD2_SLP_OE + 14 + 1 + + + RTC_IO_TOUCH_PAD2_FUN_IE + 13 + 1 + + + RTC_IO_TOUCH_PAD2_TO_GPIO + 12 + 1 + + + + + RTC_IO_TOUCH_PAD3 + 0xa0 + RTC_IO_TOUCH_PAD3 + 32 + 0x00000000 + + + RTC_IO_TOUCH_PAD3_HOLD + 31 + 1 + + + RTC_IO_TOUCH_PAD3_DRV + 29 + 2 + + + RTC_IO_TOUCH_PAD3_RDE + 28 + 1 + + + RTC_IO_TOUCH_PAD3_RUE + 27 + 1 + + + RTC_IO_TOUCH_PAD3_DAC + 23 + 3 + + + RTC_IO_TOUCH_PAD3_START + 22 + 1 + + + RTC_IO_TOUCH_PAD3_TIE_OPT + 21 + 1 + + + RTC_IO_TOUCH_PAD3_XPD + 20 + 1 + + + RTC_IO_TOUCH_PAD3_MUX_SEL + 19 + 1 + + + RTC_IO_TOUCH_PAD3_FUN_SEL + 17 + 2 + + + RTC_IO_TOUCH_PAD3_SLP_SEL + 16 + 1 + + + RTC_IO_TOUCH_PAD3_SLP_IE + 15 + 1 + + + RTC_IO_TOUCH_PAD3_SLP_OE + 14 + 1 + + + RTC_IO_TOUCH_PAD3_FUN_IE + 13 + 1 + + + RTC_IO_TOUCH_PAD3_TO_GPIO + 12 + 1 + + + + + RTC_IO_TOUCH_PAD4 + 0xa4 + RTC_IO_TOUCH_PAD4 + 32 + 0x00000000 + + + RTC_IO_TOUCH_PAD4_HOLD + 31 + 1 + + + RTC_IO_TOUCH_PAD4_DRV + 29 + 2 + + + RTC_IO_TOUCH_PAD4_RDE + 28 + 1 + + + RTC_IO_TOUCH_PAD4_RUE + 27 + 1 + + + RTC_IO_TOUCH_PAD4_DAC + 23 + 3 + + + RTC_IO_TOUCH_PAD4_START + 22 + 1 + + + RTC_IO_TOUCH_PAD4_TIE_OPT + 21 + 1 + + + RTC_IO_TOUCH_PAD4_XPD + 20 + 1 + + + RTC_IO_TOUCH_PAD4_MUX_SEL + 19 + 1 + + + RTC_IO_TOUCH_PAD4_FUN_SEL + 17 + 2 + + + RTC_IO_TOUCH_PAD4_SLP_SEL + 16 + 1 + + + RTC_IO_TOUCH_PAD4_SLP_IE + 15 + 1 + + + RTC_IO_TOUCH_PAD4_SLP_OE + 14 + 1 + + + RTC_IO_TOUCH_PAD4_FUN_IE + 13 + 1 + + + RTC_IO_TOUCH_PAD4_TO_GPIO + 12 + 1 + + + + + RTC_IO_TOUCH_PAD5 + 0xa8 + RTC_IO_TOUCH_PAD5 + 32 + 0x00000000 + + + RTC_IO_TOUCH_PAD5_HOLD + 31 + 1 + + + RTC_IO_TOUCH_PAD5_DRV + 29 + 2 + + + RTC_IO_TOUCH_PAD5_RDE + 28 + 1 + + + RTC_IO_TOUCH_PAD5_RUE + 27 + 1 + + + RTC_IO_TOUCH_PAD5_DAC + 23 + 3 + + + RTC_IO_TOUCH_PAD5_START + 22 + 1 + + + RTC_IO_TOUCH_PAD5_TIE_OPT + 21 + 1 + + + RTC_IO_TOUCH_PAD5_XPD + 20 + 1 + + + RTC_IO_TOUCH_PAD5_MUX_SEL + 19 + 1 + + + RTC_IO_TOUCH_PAD5_FUN_SEL + 17 + 2 + + + RTC_IO_TOUCH_PAD5_SLP_SEL + 16 + 1 + + + RTC_IO_TOUCH_PAD5_SLP_IE + 15 + 1 + + + RTC_IO_TOUCH_PAD5_SLP_OE + 14 + 1 + + + RTC_IO_TOUCH_PAD5_FUN_IE + 13 + 1 + + + RTC_IO_TOUCH_PAD5_TO_GPIO + 12 + 1 + + + + + RTC_IO_TOUCH_PAD6 + 0xac + RTC_IO_TOUCH_PAD6 + 32 + 0x00000000 + + + RTC_IO_TOUCH_PAD6_HOLD + 31 + 1 + + + RTC_IO_TOUCH_PAD6_DRV + 29 + 2 + + + RTC_IO_TOUCH_PAD6_RDE + 28 + 1 + + + RTC_IO_TOUCH_PAD6_RUE + 27 + 1 + + + RTC_IO_TOUCH_PAD6_DAC + 23 + 3 + + + RTC_IO_TOUCH_PAD6_START + 22 + 1 + + + RTC_IO_TOUCH_PAD6_TIE_OPT + 21 + 1 + + + RTC_IO_TOUCH_PAD6_XPD + 20 + 1 + + + RTC_IO_TOUCH_PAD6_MUX_SEL + 19 + 1 + + + RTC_IO_TOUCH_PAD6_FUN_SEL + 17 + 2 + + + RTC_IO_TOUCH_PAD6_SLP_SEL + 16 + 1 + + + RTC_IO_TOUCH_PAD6_SLP_IE + 15 + 1 + + + RTC_IO_TOUCH_PAD6_SLP_OE + 14 + 1 + + + RTC_IO_TOUCH_PAD6_FUN_IE + 13 + 1 + + + RTC_IO_TOUCH_PAD6_TO_GPIO + 12 + 1 + + + + + RTC_IO_TOUCH_PAD7 + 0xb0 + RTC_IO_TOUCH_PAD7 + 32 + 0x00000000 + + + RTC_IO_TOUCH_PAD7_HOLD + 31 + 1 + + + RTC_IO_TOUCH_PAD7_DRV + 29 + 2 + + + RTC_IO_TOUCH_PAD7_RDE + 28 + 1 + + + RTC_IO_TOUCH_PAD7_RUE + 27 + 1 + + + RTC_IO_TOUCH_PAD7_DAC + 23 + 3 + + + RTC_IO_TOUCH_PAD7_START + 22 + 1 + + + RTC_IO_TOUCH_PAD7_TIE_OPT + 21 + 1 + + + RTC_IO_TOUCH_PAD7_XPD + 20 + 1 + + + RTC_IO_TOUCH_PAD7_MUX_SEL + 19 + 1 + + + RTC_IO_TOUCH_PAD7_FUN_SEL + 17 + 2 + + + RTC_IO_TOUCH_PAD7_SLP_SEL + 16 + 1 + + + RTC_IO_TOUCH_PAD7_SLP_IE + 15 + 1 + + + RTC_IO_TOUCH_PAD7_SLP_OE + 14 + 1 + + + RTC_IO_TOUCH_PAD7_FUN_IE + 13 + 1 + + + RTC_IO_TOUCH_PAD7_TO_GPIO + 12 + 1 + + + + + RTC_IO_TOUCH_PAD8 + 0xb4 + RTC_IO_TOUCH_PAD8 + 32 + 0x00000000 + + + RTC_IO_TOUCH_PAD8_DAC + 23 + 3 + + + RTC_IO_TOUCH_PAD8_START + 22 + 1 + + + RTC_IO_TOUCH_PAD8_TIE_OPT + 21 + 1 + + + RTC_IO_TOUCH_PAD8_XPD + 20 + 1 + + + RTC_IO_TOUCH_PAD8_TO_GPIO + 19 + 1 + + + + + RTC_IO_TOUCH_PAD9 + 0xb8 + RTC_IO_TOUCH_PAD9 + 32 + 0x00000000 + + + RTC_IO_TOUCH_PAD9_DAC + 23 + 3 + + + RTC_IO_TOUCH_PAD9_START + 22 + 1 + + + RTC_IO_TOUCH_PAD9_TIE_OPT + 21 + 1 + + + RTC_IO_TOUCH_PAD9_XPD + 20 + 1 + + + RTC_IO_TOUCH_PAD9_TO_GPIO + 19 + 1 + + + + + RTC_IO_EXT_WAKEUP0 + 0xbc + RTC_IO_EXT_WAKEUP0 + 32 + 0x00000000 + + + RTC_IO_EXT_WAKEUP0_SEL + 27 + 5 + + + + + RTC_IO_XTL_EXT_CTR + 0xc0 + RTC_IO_XTL_EXT_CTR + 32 + 0x00000000 + + + RTC_IO_XTL_EXT_CTR_SEL + 27 + 5 + + + + + RTC_IO_SAR_I2C_IO + 0xc4 + RTC_IO_SAR_I2C_IO + 32 + 0x00000000 + + + RTC_IO_SAR_I2C_SDA_SEL + 30 + 2 + + + RTC_IO_SAR_I2C_SCL_SEL + 28 + 2 + + + RTC_IO_SAR_DEBUG_BIT_SEL + 23 + 5 + + + + + RTC_IO_DATE + 0xc8 + RTC_IO_DATE + 32 + 0x00000000 + + + RTC_IO_IO_DATE + 0 + 28 + + + + + + + FE + 0x3ff46000 + + 0 + 0x00000000 + registers + + + + + BB + 0x3ff5d000 + + 0 + 0x00000000 + registers + + + + + DPORT + 0x3ff00000 + + 0 + 0x00002de0 + registers + + + + PRO_BOOT_REMAP_CTRL + 0x0 + DPORT_PRO_BOOT_REMAP_CTRL + 32 + 0x00000000 + + + PRO_BOOT_REMAP + 0 + 1 + + + + + APP_BOOT_REMAP_CTRL + 0x4 + DPORT_APP_BOOT_REMAP_CTRL + 32 + 0x00000000 + + + APP_BOOT_REMAP + 0 + 1 + + + + + ACCESS_CHECK + 0x8 + DPORT_ACCESS_CHECK + 32 + 0x00000000 + + + ACCESS_CHECK_APP + 8 + 1 + + + ACCESS_CHECK_PRO + 0 + 1 + + + + + PRO_DPORT_APB_MASK0 + 0xc + DPORT_PRO_DPORT_APB_MASK0 + 32 + 0x00000000 + + + PRODPORT_APB_MASK0 + 0 + 32 + + + + + PRO_DPORT_APB_MASK1 + 0x10 + DPORT_PRO_DPORT_APB_MASK1 + 32 + 0x00000000 + + + PRODPORT_APB_MASK1 + 0 + 32 + + + + + APP_DPORT_APB_MASK0 + 0x14 + DPORT_APP_DPORT_APB_MASK0 + 32 + 0x00000000 + + + APPDPORT_APB_MASK0 + 0 + 32 + + + + + APP_DPORT_APB_MASK1 + 0x18 + DPORT_APP_DPORT_APB_MASK1 + 32 + 0x00000000 + + + APPDPORT_APB_MASK1 + 0 + 32 + + + + + PERI_CLK_EN + 0x1c + DPORT_PERI_CLK_EN + 32 + 0x00000000 + + + PERI_CLK_EN + 0 + 32 + + DIGITAL_SIGNATURE41 + SECURE_BOOT31 + RSA_ACCELERATOR21 + SHA_ACCELERATOR11 + AES_ACCELERATOR01 + + + + PERI_RST_EN + 0x20 + DPORT_PERI_RST_EN + 32 + 0x00000000 + + + PERI_RST_EN + 0 + 32 + + DIGITAL_SIGNATURE41 + SECURE_BOOT31 + RSA_ACCELERATOR21 + SHA_ACCELERATOR11 + AES_ACCELERATOR01 + + + + WIFI_BB_CFG + 0x24 + DPORT_WIFI_BB_CFG + 32 + 0x00000000 + + + WIFI_BB_CFG + 0 + 32 + + + + + WIFI_BB_CFG_2 + 0x28 + DPORT_WIFI_BB_CFG_2 + 32 + 0x00000000 + + + WIFI_BB_CFG_2 + 0 + 32 + + + + + APPCPU_CTRL_A + 0x2c + DPORT_APPCPU_CTRL_A + 32 + 0x00000000 + + + APPCPU_RESETTING + 0 + 1 + + + + + APPCPU_CTRL_B + 0x30 + DPORT_APPCPU_CTRL_B + 32 + 0x00000000 + + + APPCPU_CLKGATE_EN + 0 + 1 + + + + + APPCPU_CTRL_C + 0x34 + DPORT_APPCPU_CTRL_C + 32 + 0x00000000 + + + APPCPU_RUNSTALL + 0 + 1 + + + + + APPCPU_CTRL_D + 0x38 + DPORT_APPCPU_CTRL_D + 32 + 0x00000000 + + + APPCPU_BOOT_ADDR + 0 + 32 + + + + + CPU_PER_CONF + 0x3c + DPORT_CPU_PER_CONF + 32 + 0x00000000 + + + FAST_CLK_RTC_SEL + 3 + 1 + + + LOWSPEED_CLK_SEL + 2 + 1 + + + CPUPERIOD_SEL + 0 + 2 + CPUPERIOD_SELread-writeSEL_80Select 80 MHz clock0SEL_160Select 160 MHz clock1SEL_240Select 240 MHz clock2 + + + + + PRO_CACHE_CTRL + 0x40 + DPORT_PRO_CACHE_CTRL + 32 + 0x00000000 + + + PRO_DRAM_HL + 16 + 1 + + + SLAVE_REQ + 15 + 1 + + + AHB_SPI_REQ + 14 + 1 + + + PRO_SLAVE_REQ + 13 + 1 + + + PRO_AHB_SPI_REQ + 12 + 1 + + + PRO_DRAM_SPLIT + 11 + 1 + + + PRO_SINGLE_IRAM_ENA + 10 + 1 + + + PRO_CACHE_LOCK_3_EN + 9 + 1 + + + PRO_CACHE_LOCK_2_EN + 8 + 1 + + + PRO_CACHE_LOCK_1_EN + 7 + 1 + + + PRO_CACHE_LOCK_0_EN + 6 + 1 + + + PRO_CACHE_FLUSH_DONE + 5 + 1 + + + PRO_CACHE_FLUSH_ENA + 4 + 1 + + + PRO_CACHE_ENABLE + 3 + 1 + + + PRO_CACHE_MODE + 2 + 1 + + + + + PRO_CACHE_CTRL1 + 0x44 + DPORT_PRO_CACHE_CTRL1 + 32 + 0x00000000 + + + PRO_CACHE_MMU_IA_CLR + 13 + 1 + + + PRO_CMMU_PD + 12 + 1 + + + PRO_CMMU_FORCE_ON + 11 + 1 + + + PRO_CMMU_FLASH_PAGE_MODE + 9 + 2 + + + PRO_CMMU_SRAM_PAGE_MODE + 6 + 3 + + + PRO_CACHE_MASK_OPSDRAM + 5 + 1 + + + PRO_CACHE_MASK_DROM0 + 4 + 1 + + + PRO_CACHE_MASK_DRAM1 + 3 + 1 + + + PRO_CACHE_MASK_IROM0 + 2 + 1 + + + PRO_CACHE_MASK_IRAM1 + 1 + 1 + + + PRO_CACHE_MASK_IRAM0 + 0 + 1 + + + + + PRO_CACHE_LOCK_0_ADDR + 0x48 + DPORT_PRO_CACHE_LOCK_0_ADDR + 32 + 0x00000000 + + + PRO_CACHE_LOCK_0_ADDR_MAX + 18 + 4 + + + PRO_CACHE_LOCK_0_ADDR_MIN + 14 + 4 + + + PRO_CACHE_LOCK_0_ADDR_PRE + 0 + 14 + + + + + PRO_CACHE_LOCK_1_ADDR + 0x4c + DPORT_PRO_CACHE_LOCK_1_ADDR + 32 + 0x00000000 + + + PRO_CACHE_LOCK_1_ADDR_MAX + 18 + 4 + + + PRO_CACHE_LOCK_1_ADDR_MIN + 14 + 4 + + + PRO_CACHE_LOCK_1_ADDR_PRE + 0 + 14 + + + + + PRO_CACHE_LOCK_2_ADDR + 0x50 + DPORT_PRO_CACHE_LOCK_2_ADDR + 32 + 0x00000000 + + + PRO_CACHE_LOCK_2_ADDR_MAX + 18 + 4 + + + PRO_CACHE_LOCK_2_ADDR_MIN + 14 + 4 + + + PRO_CACHE_LOCK_2_ADDR_PRE + 0 + 14 + + + + + PRO_CACHE_LOCK_3_ADDR + 0x54 + DPORT_PRO_CACHE_LOCK_3_ADDR + 32 + 0x00000000 + + + PRO_CACHE_LOCK_3_ADDR_MAX + 18 + 4 + + + PRO_CACHE_LOCK_3_ADDR_MIN + 14 + 4 + + + PRO_CACHE_LOCK_3_ADDR_PRE + 0 + 14 + + + + + APP_CACHE_CTRL + 0x58 + DPORT_APP_CACHE_CTRL + 32 + 0x00000000 + + + APP_DRAM_HL + 14 + 1 + + + APP_SLAVE_REQ + 13 + 1 + + + APP_AHB_SPI_REQ + 12 + 1 + + + APP_DRAM_SPLIT + 11 + 1 + + + APP_SINGLE_IRAM_ENA + 10 + 1 + + + APP_CACHE_LOCK_3_EN + 9 + 1 + + + APP_CACHE_LOCK_2_EN + 8 + 1 + + + APP_CACHE_LOCK_1_EN + 7 + 1 + + + APP_CACHE_LOCK_0_EN + 6 + 1 + + + APP_CACHE_FLUSH_DONE + 5 + 1 + + + APP_CACHE_FLUSH_ENA + 4 + 1 + + + APP_CACHE_ENABLE + 3 + 1 + + + APP_CACHE_MODE + 2 + 1 + + + + + APP_CACHE_CTRL1 + 0x5c + DPORT_APP_CACHE_CTRL1 + 32 + 0x00000000 + + + APP_CACHE_MMU_IA_CLR + 13 + 1 + + + APP_CMMU_PD + 12 + 1 + + + APP_CMMU_FORCE_ON + 11 + 1 + + + APP_CMMU_FLASH_PAGE_MODE + 9 + 2 + + + APP_CMMU_SRAM_PAGE_MODE + 6 + 3 + + + APP_CACHE_MASK_OPSDRAM + 5 + 1 + + + APP_CACHE_MASK_DROM0 + 4 + 1 + + + APP_CACHE_MASK_DRAM1 + 3 + 1 + + + APP_CACHE_MASK_IROM0 + 2 + 1 + + + APP_CACHE_MASK_IRAM1 + 1 + 1 + + + APP_CACHE_MASK_IRAM0 + 0 + 1 + + + + + APP_CACHE_LOCK_0_ADDR + 0x60 + DPORT_APP_CACHE_LOCK_0_ADDR + 32 + 0x00000000 + + + APP_CACHE_LOCK_0_ADDR_MAX + 18 + 4 + + + APP_CACHE_LOCK_0_ADDR_MIN + 14 + 4 + + + APP_CACHE_LOCK_0_ADDR_PRE + 0 + 14 + + + + + APP_CACHE_LOCK_1_ADDR + 0x64 + DPORT_APP_CACHE_LOCK_1_ADDR + 32 + 0x00000000 + + + APP_CACHE_LOCK_1_ADDR_MAX + 18 + 4 + + + APP_CACHE_LOCK_1_ADDR_MIN + 14 + 4 + + + APP_CACHE_LOCK_1_ADDR_PRE + 0 + 14 + + + + + APP_CACHE_LOCK_2_ADDR + 0x68 + DPORT_APP_CACHE_LOCK_2_ADDR + 32 + 0x00000000 + + + APP_CACHE_LOCK_2_ADDR_MAX + 18 + 4 + + + APP_CACHE_LOCK_2_ADDR_MIN + 14 + 4 + + + APP_CACHE_LOCK_2_ADDR_PRE + 0 + 14 + + + + + APP_CACHE_LOCK_3_ADDR + 0x6c + DPORT_APP_CACHE_LOCK_3_ADDR + 32 + 0x00000000 + + + APP_CACHE_LOCK_3_ADDR_MAX + 18 + 4 + + + APP_CACHE_LOCK_3_ADDR_MIN + 14 + 4 + + + APP_CACHE_LOCK_3_ADDR_PRE + 0 + 14 + + + + + TRACEMEM_MUX_MODE + 0x70 + DPORT_TRACEMEM_MUX_MODE + 32 + 0x00000000 + + + TRACEMEM_MUX_MODE + 0 + 2 + + + + + PRO_TRACEMEM_ENA + 0x74 + DPORT_PRO_TRACEMEM_ENA + 32 + 0x00000000 + + + PRO_TRACEMEM_ENA + 0 + 1 + + + + + APP_TRACEMEM_ENA + 0x78 + DPORT_APP_TRACEMEM_ENA + 32 + 0x00000000 + + + APP_TRACEMEM_ENA + 0 + 1 + + + + + CACHE_MUX_MODE + 0x7c + DPORT_CACHE_MUX_MODE + 32 + 0x00000000 + + + CACHE_MUX_MODE + 0 + 2 + + + + + IMMU_PAGE_MODE + 0x80 + DPORT_IMMU_PAGE_MODE + 32 + 0x00000000 + + + IMMU_PAGE_MODE + 1 + 2 + + + INTERNAL_SRAM_IMMU_ENA + 0 + 1 + + + + + DMMU_PAGE_MODE + 0x84 + DPORT_DMMU_PAGE_MODE + 32 + 0x00000000 + + + DMMU_PAGE_MODE + 1 + 2 + + + INTERNAL_SRAM_DMMU_ENA + 0 + 1 + + + + + ROM_MPU_ENA + 0x88 + DPORT_ROM_MPU_ENA + 32 + 0x00000000 + + + APP_ROM_MPU_ENA + 2 + 1 + + + PRO_ROM_MPU_ENA + 1 + 1 + + + SHARE_ROM_MPU_ENA + 0 + 1 + + + + + MEM_PD_MASK + 0x8c + DPORT_MEM_PD_MASK + 32 + 0x00000000 + + + LSLP_MEM_PD_MASK + 0 + 1 + + + + + ROM_PD_CTRL + 0x90 + DPORT_ROM_PD_CTRL + 32 + 0x00000000 + + + SHARE_ROM_PD + 2 + 6 + + + APP_ROM_PD + 1 + 1 + + + PRO_ROM_PD + 0 + 1 + + + + + ROM_FO_CTRL + 0x94 + DPORT_ROM_FO_CTRL + 32 + 0x00000000 + + + SHARE_ROM_FO + 2 + 6 + + + APP_ROM_FO + 1 + 1 + + + PRO_ROM_FO + 0 + 1 + + + + + SRAM_PD_CTRL_0 + 0x98 + DPORT_SRAM_PD_CTRL_0 + 32 + 0x00000000 + + + SRAM_PD_0 + 0 + 32 + + + + + SRAM_PD_CTRL_1 + 0x9c + DPORT_SRAM_PD_CTRL_1 + 32 + 0x00000000 + + + SRAM_PD_1 + 0 + 1 + + + + + SRAM_FO_CTRL_0 + 0xa0 + DPORT_SRAM_FO_CTRL_0 + 32 + 0x00000000 + + + SRAM_FO_0 + 0 + 32 + + + + + SRAM_FO_CTRL_1 + 0xa4 + DPORT_SRAM_FO_CTRL_1 + 32 + 0x00000000 + + + SRAM_FO_1 + 0 + 1 + + + + + IRAM_DRAM_AHB_SEL + 0xa8 + DPORT_IRAM_DRAM_AHB_SEL + 32 + 0x00000000 + + + MAC_DUMP_MODE + 5 + 2 + + + MASK_AHB + 4 + 1 + + + MASK_APP_DRAM + 3 + 1 + + + MASK_PRO_DRAM + 2 + 1 + + + MASK_APP_IRAM + 1 + 1 + + + MASK_PRO_IRAM + 0 + 1 + + + + + TAG_FO_CTRL + 0xac + DPORT_TAG_FO_CTRL + 32 + 0x00000000 + + + APP_CACHE_TAG_PD + 9 + 1 + + + APP_CACHE_TAG_FORCE_ON + 8 + 1 + + + PRO_CACHE_TAG_PD + 1 + 1 + + + PRO_CACHE_TAG_FORCE_ON + 0 + 1 + + + + + AHB_LITE_MASK + 0xb0 + DPORT_AHB_LITE_MASK + 32 + 0x00000000 + + + AHB_LITE_SDHOST_PID_REG + 11 + 3 + + + AHB_LITE_MASK_APPDPORT + 10 + 1 + + + AHB_LITE_MASK_PRODPORT + 9 + 1 + + + AHB_LITE_MASK_SDIO + 8 + 1 + + + AHB_LITE_MASK_APP + 4 + 1 + + + AHB_LITE_MASK_PRO + 0 + 1 + + + + + AHB_MPU_TABLE_0 + 0xb4 + DPORT_AHB_MPU_TABLE_0 + 32 + 0x00000000 + + + AHB_ACCESS_GRANT_0 + 0 + 32 + + + + + AHB_MPU_TABLE_1 + 0xb8 + DPORT_AHB_MPU_TABLE_1 + 32 + 0x00000000 + + + AHB_ACCESS_GRANT_1 + 0 + 9 + + + + + HOST_INF_SEL + 0xbc + DPORT_HOST_INF_SEL + 32 + 0x00000000 + + + LINK_DEVICE_SEL + 8 + 8 + + + PERI_IO_SWAP + 0 + 8 + + + + + PERIP_CLK_EN + 0xc0 + DPORT_PERIP_CLK_EN + 32 + 0x00000000 + + + PERIP_CLK_EN + 0 + 32 + + PWM3261 + PWM2251 + UART_MEM241 + UART2231 + SPI_DMA221 + I2S1211 + PWM1201 + CAN191 + I2C1181 + PWM0171 + SPI3161 + TIMER_GROUP1151 + EFUSE141 + TIMER_GROUP0131 + UHCI1121 + LED_PWM111 + PULSE_CNT101 + REMOTE_CONTROLLER91 + UHCI081 + I2C071 + SPI261 + UART151 + I2S041 + WDG31 + UART021 + SPI011 + TIMERS01 + + + + PERIP_RST_EN + 0xc4 + DPORT_PERIP_RST_EN + 32 + 0x00000000 + + + PERIP_RST + 0 + 32 + + + SPI_DECRYPT_ENABLE + 12 + 1 + + + SPI_ENCRYPT_ENABLE + 8 + 1 + + + SLAVE_SPI_MASK_APP + 4 + 1 + + + SLAVE_SPI_MASK_PRO + 0 + 1 + + PWM3261 + PWM2251 + UART_MEM241 + UART2231 + SPI_DMA221 + I2S1211 + PWM1201 + CAN191 + I2C1181 + PWM0171 + SPI3161 + TIMER_GROUP1151 + EFUSE141 + TIMER_GROUP0131 + UHCI1121 + LED_PWM111 + PULSE_CNT101 + REMOTE_CONTROLLER91 + UHCI081 + I2C071 + SPI261 + UART151 + I2S041 + WDG31 + UART021 + SPI011 + TIMERS01 + + + + WIFI_CLK_EN + 0xcc + DPORT_WIFI_CLK_EN + 32 + 0x00000000 + + + WIFI_CLK_EN + 0 + 32 + + + + + CORE_RST_EN + 0xd0 + DPORT_CORE_RST_EN + 32 + 0x00000000 + + + CORE_RST + 0 + 32 + + + + + BT_LPCK_DIV_INT + 0xd4 + DPORT_BT_LPCK_DIV_INT + 32 + 0x00000000 + + + BTEXTWAKEUP_REQ + 12 + 1 + + + BT_LPCK_DIV_NUM + 0 + 12 + + + + + BT_LPCK_DIV_FRAC + 0xd8 + DPORT_BT_LPCK_DIV_FRAC + 32 + 0x00000000 + + + LPCLK_SEL_XTAL32K + 27 + 1 + + + LPCLK_SEL_XTAL + 26 + 1 + + + LPCLK_SEL_8M + 25 + 1 + + + LPCLK_SEL_RTC_SLOW + 24 + 1 + + + BT_LPCK_DIV_A + 12 + 12 + + + BT_LPCK_DIV_B + 0 + 12 + + + + + CPU_INTR_FROM_CPU_0 + 0xdc + DPORT_CPU_INTR_FROM_CPU_0 + 32 + 0x00000000 + + + CPU_INTR_FROM_CPU_0 + 0 + 1 + + + + + CPU_INTR_FROM_CPU_1 + 0xe0 + DPORT_CPU_INTR_FROM_CPU_1 + 32 + 0x00000000 + + + CPU_INTR_FROM_CPU_1 + 0 + 1 + + + + + CPU_INTR_FROM_CPU_2 + 0xe4 + DPORT_CPU_INTR_FROM_CPU_2 + 32 + 0x00000000 + + + CPU_INTR_FROM_CPU_2 + 0 + 1 + + + + + CPU_INTR_FROM_CPU_3 + 0xe8 + DPORT_CPU_INTR_FROM_CPU_3 + 32 + 0x00000000 + + + CPU_INTR_FROM_CPU_3 + 0 + 1 + + + + + PRO_INTR_STATUS_0 + 0xec + DPORT_PRO_INTR_STATUS_0 + 32 + 0x00000000 + + + PRO_INTR_STATUS_0 + 0 + 32 + + + + + PRO_INTR_STATUS_1 + 0xf0 + DPORT_PRO_INTR_STATUS_1 + 32 + 0x00000000 + + + PRO_INTR_STATUS_1 + 0 + 32 + + + + + PRO_INTR_STATUS_2 + 0xf4 + DPORT_PRO_INTR_STATUS_2 + 32 + 0x00000000 + + + PRO_INTR_STATUS_2 + 0 + 32 + + + + + APP_INTR_STATUS_0 + 0xf8 + DPORT_APP_INTR_STATUS_0 + 32 + 0x00000000 + + + APP_INTR_STATUS_0 + 0 + 32 + + + + + APP_INTR_STATUS_1 + 0xfc + DPORT_APP_INTR_STATUS_1 + 32 + 0x00000000 + + + APP_INTR_STATUS_1 + 0 + 32 + + + + + APP_INTR_STATUS_2 + 0x100 + DPORT_APP_INTR_STATUS_2 + 32 + 0x00000000 + + + APP_INTR_STATUS_2 + 0 + 32 + + + + + PRO_MAC_INTR_MAP + 0x104 + DPORT_PRO_MAC_INTR_MAP + 32 + 0x00000000 + + + PRO_MAC_INTR_MAP + 0 + 5 + + + + + PRO_MAC_NMI_MAP + 0x108 + DPORT_PRO_MAC_NMI_MAP + 32 + 0x00000000 + + + PRO_MAC_NMI_MAP + 0 + 5 + + + + + PRO_BB_INT_MAP + 0x10c + DPORT_PRO_BB_INT_MAP + 32 + 0x00000000 + + + PRO_BB_INT_MAP + 0 + 5 + + + + + PRO_BT_MAC_INT_MAP + 0x110 + DPORT_PRO_BT_MAC_INT_MAP + 32 + 0x00000000 + + + PRO_BT_MAC_INT_MAP + 0 + 5 + + + + + PRO_BT_BB_INT_MAP + 0x114 + DPORT_PRO_BT_BB_INT_MAP + 32 + 0x00000000 + + + PRO_BT_BB_INT_MAP + 0 + 5 + + + + + PRO_BT_BB_NMI_MAP + 0x118 + DPORT_PRO_BT_BB_NMI_MAP + 32 + 0x00000000 + + + PRO_BT_BB_NMI_MAP + 0 + 5 + + + + + PRO_RWBT_IRQ_MAP + 0x11c + DPORT_PRO_RWBT_IRQ_MAP + 32 + 0x00000000 + + + PRO_RWBT_IRQ_MAP + 0 + 5 + + + + + PRO_RWBLE_IRQ_MAP + 0x120 + DPORT_PRO_RWBLE_IRQ_MAP + 32 + 0x00000000 + + + PRO_RWBLE_IRQ_MAP + 0 + 5 + + + + + PRO_RWBT_NMI_MAP + 0x124 + DPORT_PRO_RWBT_NMI_MAP + 32 + 0x00000000 + + + PRO_RWBT_NMI_MAP + 0 + 5 + + + + + PRO_RWBLE_NMI_MAP + 0x128 + DPORT_PRO_RWBLE_NMI_MAP + 32 + 0x00000000 + + + PRO_RWBLE_NMI_MAP + 0 + 5 + + + + + PRO_SLC0_INTR_MAP + 0x12c + DPORT_PRO_SLC0_INTR_MAP + 32 + 0x00000000 + + + PRO_SLC0_INTR_MAP + 0 + 5 + + + + + PRO_SLC1_INTR_MAP + 0x130 + DPORT_PRO_SLC1_INTR_MAP + 32 + 0x00000000 + + + PRO_SLC1_INTR_MAP + 0 + 5 + + + + + PRO_UHCI0_INTR_MAP + 0x134 + DPORT_PRO_UHCI0_INTR_MAP + 32 + 0x00000000 + + + PRO_UHCI0_INTR_MAP + 0 + 5 + + + + + PRO_UHCI1_INTR_MAP + 0x138 + DPORT_PRO_UHCI1_INTR_MAP + 32 + 0x00000000 + + + PRO_UHCI1_INTR_MAP + 0 + 5 + + + + + PRO_TG_T0_LEVEL_INT_MAP + 0x13c + DPORT_PRO_TG_T0_LEVEL_INT_MAP + 32 + 0x00000000 + + + PRO_TG_T0_LEVEL_INT_MAP + 0 + 5 + + + + + PRO_TG_T1_LEVEL_INT_MAP + 0x140 + DPORT_PRO_TG_T1_LEVEL_INT_MAP + 32 + 0x00000000 + + + PRO_TG_T1_LEVEL_INT_MAP + 0 + 5 + + + + + PRO_TG_WDT_LEVEL_INT_MAP + 0x144 + DPORT_PRO_TG_WDT_LEVEL_INT_MAP + 32 + 0x00000000 + + + PRO_TG_WDT_LEVEL_INT_MAP + 0 + 5 + + + + + PRO_TG_LACT_LEVEL_INT_MAP + 0x148 + DPORT_PRO_TG_LACT_LEVEL_INT_MAP + 32 + 0x00000000 + + + PRO_TG_LACT_LEVEL_INT_MAP + 0 + 5 + + + + + PRO_TG1_T0_LEVEL_INT_MAP + 0x14c + DPORT_PRO_TG1_T0_LEVEL_INT_MAP + 32 + 0x00000000 + + + PRO_TG1_T0_LEVEL_INT_MAP + 0 + 5 + + + + + PRO_TG1_T1_LEVEL_INT_MAP + 0x150 + DPORT_PRO_TG1_T1_LEVEL_INT_MAP + 32 + 0x00000000 + + + PRO_TG1_T1_LEVEL_INT_MAP + 0 + 5 + + + + + PRO_TG1_WDT_LEVEL_INT_MAP + 0x154 + DPORT_PRO_TG1_WDT_LEVEL_INT_MAP + 32 + 0x00000000 + + + PRO_TG1_WDT_LEVEL_INT_MAP + 0 + 5 + + + + + PRO_TG1_LACT_LEVEL_INT_MAP + 0x158 + DPORT_PRO_TG1_LACT_LEVEL_INT_MAP + 32 + 0x00000000 + + + PRO_TG1_LACT_LEVEL_INT_MAP + 0 + 5 + + + + + PRO_GPIO_INTERRUPT_MAP + 0x15c + DPORT_PRO_GPIO_INTERRUPT_MAP + 32 + 0x00000000 + + + PRO_GPIO_INTERRUPT_PRO_MAP + 0 + 5 + + + + + PRO_GPIO_INTERRUPT_NMI_MAP + 0x160 + DPORT_PRO_GPIO_INTERRUPT_NMI_MAP + 32 + 0x00000000 + + + PRO_GPIO_INTERRUPT_PRO_NMI_MAP + 0 + 5 + + + + + PRO_CPU_INTR_FROM_CPU_0_MAP + 0x164 + DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP + 32 + 0x00000000 + + + PRO_CPU_INTR_FROM_CPU_0_MAP + 0 + 5 + + + + + PRO_CPU_INTR_FROM_CPU_1_MAP + 0x168 + DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP + 32 + 0x00000000 + + + PRO_CPU_INTR_FROM_CPU_1_MAP + 0 + 5 + + + + + PRO_CPU_INTR_FROM_CPU_2_MAP + 0x16c + DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP + 32 + 0x00000000 + + + PRO_CPU_INTR_FROM_CPU_2_MAP + 0 + 5 + + + + + PRO_CPU_INTR_FROM_CPU_3_MAP + 0x170 + DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP + 32 + 0x00000000 + + + PRO_CPU_INTR_FROM_CPU_3_MAP + 0 + 5 + + + + + PRO_SPI_INTR_0_MAP + 0x174 + DPORT_PRO_SPI_INTR_0_MAP + 32 + 0x00000000 + + + PRO_SPI_INTR_0_MAP + 0 + 5 + + + + + PRO_SPI_INTR_1_MAP + 0x178 + DPORT_PRO_SPI_INTR_1_MAP + 32 + 0x00000000 + + + PRO_SPI_INTR_1_MAP + 0 + 5 + + + + + PRO_SPI_INTR_2_MAP + 0x17c + DPORT_PRO_SPI_INTR_2_MAP + 32 + 0x00000000 + + + PRO_SPI_INTR_2_MAP + 0 + 5 + + + + + PRO_SPI_INTR_3_MAP + 0x180 + DPORT_PRO_SPI_INTR_3_MAP + 32 + 0x00000000 + + + PRO_SPI_INTR_3_MAP + 0 + 5 + + + + + PRO_I2S0_INT_MAP + 0x184 + DPORT_PRO_I2S0_INT_MAP + 32 + 0x00000000 + + + PRO_I2S0_INT_MAP + 0 + 5 + + + + + PRO_I2S1_INT_MAP + 0x188 + DPORT_PRO_I2S1_INT_MAP + 32 + 0x00000000 + + + PRO_I2S1_INT_MAP + 0 + 5 + + + + + PRO_UART_INTR_MAP + 0x18c + DPORT_PRO_UART_INTR_MAP + 32 + 0x00000000 + + + PRO_UART_INTR_MAP + 0 + 5 + + + + + PRO_UART1_INTR_MAP + 0x190 + DPORT_PRO_UART1_INTR_MAP + 32 + 0x00000000 + + + PRO_UART1_INTR_MAP + 0 + 5 + + + + + PRO_UART2_INTR_MAP + 0x194 + DPORT_PRO_UART2_INTR_MAP + 32 + 0x00000000 + + + PRO_UART2_INTR_MAP + 0 + 5 + + + + + PRO_SDIO_HOST_INTERRUPT_MAP + 0x198 + DPORT_PRO_SDIO_HOST_INTERRUPT_MAP + 32 + 0x00000000 + + + PRO_SDIO_HOST_INTERRUPT_MAP + 0 + 5 + + + + + PRO_EMAC_INT_MAP + 0x19c + DPORT_PRO_EMAC_INT_MAP + 32 + 0x00000000 + + + PRO_EMAC_INT_MAP + 0 + 5 + + + + + PRO_PWM0_INTR_MAP + 0x1a0 + DPORT_PRO_PWM0_INTR_MAP + 32 + 0x00000000 + + + PRO_PWM0_INTR_MAP + 0 + 5 + + + + + PRO_PWM1_INTR_MAP + 0x1a4 + DPORT_PRO_PWM1_INTR_MAP + 32 + 0x00000000 + + + PRO_PWM1_INTR_MAP + 0 + 5 + + + + + PRO_PWM2_INTR_MAP + 0x1a8 + DPORT_PRO_PWM2_INTR_MAP + 32 + 0x00000000 + + + PRO_PWM2_INTR_MAP + 0 + 5 + + + + + PRO_PWM3_INTR_MAP + 0x1ac + DPORT_PRO_PWM3_INTR_MAP + 32 + 0x00000000 + + + PRO_PWM3_INTR_MAP + 0 + 5 + + + + + PRO_LEDC_INT_MAP + 0x1b0 + DPORT_PRO_LEDC_INT_MAP + 32 + 0x00000000 + + + PRO_LEDC_INT_MAP + 0 + 5 + + + + + PRO_EFUSE_INT_MAP + 0x1b4 + DPORT_PRO_EFUSE_INT_MAP + 32 + 0x00000000 + + + PRO_EFUSE_INT_MAP + 0 + 5 + + + + + PRO_CAN_INT_MAP + 0x1b8 + DPORT_PRO_CAN_INT_MAP + 32 + 0x00000000 + + + PRO_CAN_INT_MAP + 0 + 5 + + + + + PRO_RTC_CORE_INTR_MAP + 0x1bc + DPORT_PRO_RTC_CORE_INTR_MAP + 32 + 0x00000000 + + + PRO_RTC_CORE_INTR_MAP + 0 + 5 + + + + + PRO_RMT_INTR_MAP + 0x1c0 + DPORT_PRO_RMT_INTR_MAP + 32 + 0x00000000 + + + PRO_RMT_INTR_MAP + 0 + 5 + + + + + PRO_PCNT_INTR_MAP + 0x1c4 + DPORT_PRO_PCNT_INTR_MAP + 32 + 0x00000000 + + + PRO_PCNT_INTR_MAP + 0 + 5 + + + + + PRO_I2C_EXT0_INTR_MAP + 0x1c8 + DPORT_PRO_I2C_EXT0_INTR_MAP + 32 + 0x00000000 + + + PRO_I2C_EXT0_INTR_MAP + 0 + 5 + + + + + PRO_I2C_EXT1_INTR_MAP + 0x1cc + DPORT_PRO_I2C_EXT1_INTR_MAP + 32 + 0x00000000 + + + PRO_I2C_EXT1_INTR_MAP + 0 + 5 + + + + + PRO_RSA_INTR_MAP + 0x1d0 + DPORT_PRO_RSA_INTR_MAP + 32 + 0x00000000 + + + PRO_RSA_INTR_MAP + 0 + 5 + + + + + PRO_SPI1_DMA_INT_MAP + 0x1d4 + DPORT_PRO_SPI1_DMA_INT_MAP + 32 + 0x00000000 + + + PRO_SPI1_DMA_INT_MAP + 0 + 5 + + + + + PRO_SPI2_DMA_INT_MAP + 0x1d8 + DPORT_PRO_SPI2_DMA_INT_MAP + 32 + 0x00000000 + + + PRO_SPI2_DMA_INT_MAP + 0 + 5 + + + + + PRO_SPI3_DMA_INT_MAP + 0x1dc + DPORT_PRO_SPI3_DMA_INT_MAP + 32 + 0x00000000 + + + PRO_SPI3_DMA_INT_MAP + 0 + 5 + + + + + PRO_WDG_INT_MAP + 0x1e0 + DPORT_PRO_WDG_INT_MAP + 32 + 0x00000000 + + + PRO_WDG_INT_MAP + 0 + 5 + + + + + PRO_TIMER_INT1_MAP + 0x1e4 + DPORT_PRO_TIMER_INT1_MAP + 32 + 0x00000000 + + + PRO_TIMER_INT1_MAP + 0 + 5 + + + + + PRO_TIMER_INT2_MAP + 0x1e8 + DPORT_PRO_TIMER_INT2_MAP + 32 + 0x00000000 + + + PRO_TIMER_INT2_MAP + 0 + 5 + + + + + PRO_TG_T0_EDGE_INT_MAP + 0x1ec + DPORT_PRO_TG_T0_EDGE_INT_MAP + 32 + 0x00000000 + + + PRO_TG_T0_EDGE_INT_MAP + 0 + 5 + + + + + PRO_TG_T1_EDGE_INT_MAP + 0x1f0 + DPORT_PRO_TG_T1_EDGE_INT_MAP + 32 + 0x00000000 + + + PRO_TG_T1_EDGE_INT_MAP + 0 + 5 + + + + + PRO_TG_WDT_EDGE_INT_MAP + 0x1f4 + DPORT_PRO_TG_WDT_EDGE_INT_MAP + 32 + 0x00000000 + + + PRO_TG_WDT_EDGE_INT_MAP + 0 + 5 + + + + + PRO_TG_LACT_EDGE_INT_MAP + 0x1f8 + DPORT_PRO_TG_LACT_EDGE_INT_MAP + 32 + 0x00000000 + + + PRO_TG_LACT_EDGE_INT_MAP + 0 + 5 + + + + + PRO_TG1_T0_EDGE_INT_MAP + 0x1fc + DPORT_PRO_TG1_T0_EDGE_INT_MAP + 32 + 0x00000000 + + + PRO_TG1_T0_EDGE_INT_MAP + 0 + 5 + + + + + PRO_TG1_T1_EDGE_INT_MAP + 0x200 + DPORT_PRO_TG1_T1_EDGE_INT_MAP + 32 + 0x00000000 + + + PRO_TG1_T1_EDGE_INT_MAP + 0 + 5 + + + + + PRO_TG1_WDT_EDGE_INT_MAP + 0x204 + DPORT_PRO_TG1_WDT_EDGE_INT_MAP + 32 + 0x00000000 + + + PRO_TG1_WDT_EDGE_INT_MAP + 0 + 5 + + + + + PRO_TG1_LACT_EDGE_INT_MAP + 0x208 + DPORT_PRO_TG1_LACT_EDGE_INT_MAP + 32 + 0x00000000 + + + PRO_TG1_LACT_EDGE_INT_MAP + 0 + 5 + + + + + PRO_MMU_IA_INT_MAP + 0x20c + DPORT_PRO_MMU_IA_INT_MAP + 32 + 0x00000000 + + + PRO_MMU_IA_INT_MAP + 0 + 5 + + + + + PRO_MPU_IA_INT_MAP + 0x210 + DPORT_PRO_MPU_IA_INT_MAP + 32 + 0x00000000 + + + PRO_MPU_IA_INT_MAP + 0 + 5 + + + + + PRO_CACHE_IA_INT_MAP + 0x214 + DPORT_PRO_CACHE_IA_INT_MAP + 32 + 0x00000000 + + + PRO_CACHE_IA_INT_MAP + 0 + 5 + + + + + APP_MAC_INTR_MAP + 0x218 + DPORT_APP_MAC_INTR_MAP + 32 + 0x00000000 + + + APP_MAC_INTR_MAP + 0 + 5 + + + + + APP_MAC_NMI_MAP + 0x21c + DPORT_APP_MAC_NMI_MAP + 32 + 0x00000000 + + + APP_MAC_NMI_MAP + 0 + 5 + + + + + APP_BB_INT_MAP + 0x220 + DPORT_APP_BB_INT_MAP + 32 + 0x00000000 + + + APP_BB_INT_MAP + 0 + 5 + + + + + APP_BT_MAC_INT_MAP + 0x224 + DPORT_APP_BT_MAC_INT_MAP + 32 + 0x00000000 + + + APP_BT_MAC_INT_MAP + 0 + 5 + + + + + APP_BT_BB_INT_MAP + 0x228 + DPORT_APP_BT_BB_INT_MAP + 32 + 0x00000000 + + + APP_BT_BB_INT_MAP + 0 + 5 + + + + + APP_BT_BB_NMI_MAP + 0x22c + DPORT_APP_BT_BB_NMI_MAP + 32 + 0x00000000 + + + APP_BT_BB_NMI_MAP + 0 + 5 + + + + + APP_RWBT_IRQ_MAP + 0x230 + DPORT_APP_RWBT_IRQ_MAP + 32 + 0x00000000 + + + APP_RWBT_IRQ_MAP + 0 + 5 + + + + + APP_RWBLE_IRQ_MAP + 0x234 + DPORT_APP_RWBLE_IRQ_MAP + 32 + 0x00000000 + + + APP_RWBLE_IRQ_MAP + 0 + 5 + + + + + APP_RWBT_NMI_MAP + 0x238 + DPORT_APP_RWBT_NMI_MAP + 32 + 0x00000000 + + + APP_RWBT_NMI_MAP + 0 + 5 + + + + + APP_RWBLE_NMI_MAP + 0x23c + DPORT_APP_RWBLE_NMI_MAP + 32 + 0x00000000 + + + APP_RWBLE_NMI_MAP + 0 + 5 + + + + + APP_SLC0_INTR_MAP + 0x240 + DPORT_APP_SLC0_INTR_MAP + 32 + 0x00000000 + + + APP_SLC0_INTR_MAP + 0 + 5 + + + + + APP_SLC1_INTR_MAP + 0x244 + DPORT_APP_SLC1_INTR_MAP + 32 + 0x00000000 + + + APP_SLC1_INTR_MAP + 0 + 5 + + + + + APP_UHCI0_INTR_MAP + 0x248 + DPORT_APP_UHCI0_INTR_MAP + 32 + 0x00000000 + + + APP_UHCI0_INTR_MAP + 0 + 5 + + + + + APP_UHCI1_INTR_MAP + 0x24c + DPORT_APP_UHCI1_INTR_MAP + 32 + 0x00000000 + + + APP_UHCI1_INTR_MAP + 0 + 5 + + + + + APP_TG_T0_LEVEL_INT_MAP + 0x250 + DPORT_APP_TG_T0_LEVEL_INT_MAP + 32 + 0x00000000 + + + APP_TG_T0_LEVEL_INT_MAP + 0 + 5 + + + + + APP_TG_T1_LEVEL_INT_MAP + 0x254 + DPORT_APP_TG_T1_LEVEL_INT_MAP + 32 + 0x00000000 + + + APP_TG_T1_LEVEL_INT_MAP + 0 + 5 + + + + + APP_TG_WDT_LEVEL_INT_MAP + 0x258 + DPORT_APP_TG_WDT_LEVEL_INT_MAP + 32 + 0x00000000 + + + APP_TG_WDT_LEVEL_INT_MAP + 0 + 5 + + + + + APP_TG_LACT_LEVEL_INT_MAP + 0x25c + DPORT_APP_TG_LACT_LEVEL_INT_MAP + 32 + 0x00000000 + + + APP_TG_LACT_LEVEL_INT_MAP + 0 + 5 + + + + + APP_TG1_T0_LEVEL_INT_MAP + 0x260 + DPORT_APP_TG1_T0_LEVEL_INT_MAP + 32 + 0x00000000 + + + APP_TG1_T0_LEVEL_INT_MAP + 0 + 5 + + + + + APP_TG1_T1_LEVEL_INT_MAP + 0x264 + DPORT_APP_TG1_T1_LEVEL_INT_MAP + 32 + 0x00000000 + + + APP_TG1_T1_LEVEL_INT_MAP + 0 + 5 + + + + + APP_TG1_WDT_LEVEL_INT_MAP + 0x268 + DPORT_APP_TG1_WDT_LEVEL_INT_MAP + 32 + 0x00000000 + + + APP_TG1_WDT_LEVEL_INT_MAP + 0 + 5 + + + + + APP_TG1_LACT_LEVEL_INT_MAP + 0x26c + DPORT_APP_TG1_LACT_LEVEL_INT_MAP + 32 + 0x00000000 + + + APP_TG1_LACT_LEVEL_INT_MAP + 0 + 5 + + + + + APP_GPIO_INTERRUPT_MAP + 0x270 + DPORT_APP_GPIO_INTERRUPT_MAP + 32 + 0x00000000 + + + APP_GPIO_INTERRUPT_APP_MAP + 0 + 5 + + + + + APP_GPIO_INTERRUPT_NMI_MAP + 0x274 + DPORT_APP_GPIO_INTERRUPT_NMI_MAP + 32 + 0x00000000 + + + APP_GPIO_INTERRUPT_APP_NMI_MAP + 0 + 5 + + + + + APP_CPU_INTR_FROM_CPU_0_MAP + 0x278 + DPORT_APP_CPU_INTR_FROM_CPU_0_MAP + 32 + 0x00000000 + + + APP_CPU_INTR_FROM_CPU_0_MAP + 0 + 5 + + + + + APP_CPU_INTR_FROM_CPU_1_MAP + 0x27c + DPORT_APP_CPU_INTR_FROM_CPU_1_MAP + 32 + 0x00000000 + + + APP_CPU_INTR_FROM_CPU_1_MAP + 0 + 5 + + + + + APP_CPU_INTR_FROM_CPU_2_MAP + 0x280 + DPORT_APP_CPU_INTR_FROM_CPU_2_MAP + 32 + 0x00000000 + + + APP_CPU_INTR_FROM_CPU_2_MAP + 0 + 5 + + + + + APP_CPU_INTR_FROM_CPU_3_MAP + 0x284 + DPORT_APP_CPU_INTR_FROM_CPU_3_MAP + 32 + 0x00000000 + + + APP_CPU_INTR_FROM_CPU_3_MAP + 0 + 5 + + + + + APP_SPI_INTR_0_MAP + 0x288 + DPORT_APP_SPI_INTR_0_MAP + 32 + 0x00000000 + + + APP_SPI_INTR_0_MAP + 0 + 5 + + + + + APP_SPI_INTR_1_MAP + 0x28c + DPORT_APP_SPI_INTR_1_MAP + 32 + 0x00000000 + + + APP_SPI_INTR_1_MAP + 0 + 5 + + + + + APP_SPI_INTR_2_MAP + 0x290 + DPORT_APP_SPI_INTR_2_MAP + 32 + 0x00000000 + + + APP_SPI_INTR_2_MAP + 0 + 5 + + + + + APP_SPI_INTR_3_MAP + 0x294 + DPORT_APP_SPI_INTR_3_MAP + 32 + 0x00000000 + + + APP_SPI_INTR_3_MAP + 0 + 5 + + + + + APP_I2S0_INT_MAP + 0x298 + DPORT_APP_I2S0_INT_MAP + 32 + 0x00000000 + + + APP_I2S0_INT_MAP + 0 + 5 + + + + + APP_I2S1_INT_MAP + 0x29c + DPORT_APP_I2S1_INT_MAP + 32 + 0x00000000 + + + APP_I2S1_INT_MAP + 0 + 5 + + + + + APP_UART_INTR_MAP + 0x2a0 + DPORT_APP_UART_INTR_MAP + 32 + 0x00000000 + + + APP_UART_INTR_MAP + 0 + 5 + + + + + APP_UART1_INTR_MAP + 0x2a4 + DPORT_APP_UART1_INTR_MAP + 32 + 0x00000000 + + + APP_UART1_INTR_MAP + 0 + 5 + + + + + APP_UART2_INTR_MAP + 0x2a8 + DPORT_APP_UART2_INTR_MAP + 32 + 0x00000000 + + + APP_UART2_INTR_MAP + 0 + 5 + + + + + APP_SDIO_HOST_INTERRUPT_MAP + 0x2ac + DPORT_APP_SDIO_HOST_INTERRUPT_MAP + 32 + 0x00000000 + + + APP_SDIO_HOST_INTERRUPT_MAP + 0 + 5 + + + + + APP_EMAC_INT_MAP + 0x2b0 + DPORT_APP_EMAC_INT_MAP + 32 + 0x00000000 + + + APP_EMAC_INT_MAP + 0 + 5 + + + + + APP_PWM0_INTR_MAP + 0x2b4 + DPORT_APP_PWM0_INTR_MAP + 32 + 0x00000000 + + + APP_PWM0_INTR_MAP + 0 + 5 + + + + + APP_PWM1_INTR_MAP + 0x2b8 + DPORT_APP_PWM1_INTR_MAP + 32 + 0x00000000 + + + APP_PWM1_INTR_MAP + 0 + 5 + + + + + APP_PWM2_INTR_MAP + 0x2bc + DPORT_APP_PWM2_INTR_MAP + 32 + 0x00000000 + + + APP_PWM2_INTR_MAP + 0 + 5 + + + + + APP_PWM3_INTR_MAP + 0x2c0 + DPORT_APP_PWM3_INTR_MAP + 32 + 0x00000000 + + + APP_PWM3_INTR_MAP + 0 + 5 + + + + + APP_LEDC_INT_MAP + 0x2c4 + DPORT_APP_LEDC_INT_MAP + 32 + 0x00000000 + + + APP_LEDC_INT_MAP + 0 + 5 + + + + + APP_EFUSE_INT_MAP + 0x2c8 + DPORT_APP_EFUSE_INT_MAP + 32 + 0x00000000 + + + APP_EFUSE_INT_MAP + 0 + 5 + + + + + APP_CAN_INT_MAP + 0x2cc + DPORT_APP_CAN_INT_MAP + 32 + 0x00000000 + + + APP_CAN_INT_MAP + 0 + 5 + + + + + APP_RTC_CORE_INTR_MAP + 0x2d0 + DPORT_APP_RTC_CORE_INTR_MAP + 32 + 0x00000000 + + + APP_RTC_CORE_INTR_MAP + 0 + 5 + + + + + APP_RMT_INTR_MAP + 0x2d4 + DPORT_APP_RMT_INTR_MAP + 32 + 0x00000000 + + + APP_RMT_INTR_MAP + 0 + 5 + + + + + APP_PCNT_INTR_MAP + 0x2d8 + DPORT_APP_PCNT_INTR_MAP + 32 + 0x00000000 + + + APP_PCNT_INTR_MAP + 0 + 5 + + + + + APP_I2C_EXT0_INTR_MAP + 0x2dc + DPORT_APP_I2C_EXT0_INTR_MAP + 32 + 0x00000000 + + + APP_I2C_EXT0_INTR_MAP + 0 + 5 + + + + + APP_I2C_EXT1_INTR_MAP + 0x2e0 + DPORT_APP_I2C_EXT1_INTR_MAP + 32 + 0x00000000 + + + APP_I2C_EXT1_INTR_MAP + 0 + 5 + + + + + APP_RSA_INTR_MAP + 0x2e4 + DPORT_APP_RSA_INTR_MAP + 32 + 0x00000000 + + + APP_RSA_INTR_MAP + 0 + 5 + + + + + APP_SPI1_DMA_INT_MAP + 0x2e8 + DPORT_APP_SPI1_DMA_INT_MAP + 32 + 0x00000000 + + + APP_SPI1_DMA_INT_MAP + 0 + 5 + + + + + APP_SPI2_DMA_INT_MAP + 0x2ec + DPORT_APP_SPI2_DMA_INT_MAP + 32 + 0x00000000 + + + APP_SPI2_DMA_INT_MAP + 0 + 5 + + + + + APP_SPI3_DMA_INT_MAP + 0x2f0 + DPORT_APP_SPI3_DMA_INT_MAP + 32 + 0x00000000 + + + APP_SPI3_DMA_INT_MAP + 0 + 5 + + + + + APP_WDG_INT_MAP + 0x2f4 + DPORT_APP_WDG_INT_MAP + 32 + 0x00000000 + + + APP_WDG_INT_MAP + 0 + 5 + + + + + APP_TIMER_INT1_MAP + 0x2f8 + DPORT_APP_TIMER_INT1_MAP + 32 + 0x00000000 + + + APP_TIMER_INT1_MAP + 0 + 5 + + + + + APP_TIMER_INT2_MAP + 0x2fc + DPORT_APP_TIMER_INT2_MAP + 32 + 0x00000000 + + + APP_TIMER_INT2_MAP + 0 + 5 + + + + + APP_TG_T0_EDGE_INT_MAP + 0x300 + DPORT_APP_TG_T0_EDGE_INT_MAP + 32 + 0x00000000 + + + APP_TG_T0_EDGE_INT_MAP + 0 + 5 + + + + + APP_TG_T1_EDGE_INT_MAP + 0x304 + DPORT_APP_TG_T1_EDGE_INT_MAP + 32 + 0x00000000 + + + APP_TG_T1_EDGE_INT_MAP + 0 + 5 + + + + + APP_TG_WDT_EDGE_INT_MAP + 0x308 + DPORT_APP_TG_WDT_EDGE_INT_MAP + 32 + 0x00000000 + + + APP_TG_WDT_EDGE_INT_MAP + 0 + 5 + + + + + APP_TG_LACT_EDGE_INT_MAP + 0x30c + DPORT_APP_TG_LACT_EDGE_INT_MAP + 32 + 0x00000000 + + + APP_TG_LACT_EDGE_INT_MAP + 0 + 5 + + + + + APP_TG1_T0_EDGE_INT_MAP + 0x310 + DPORT_APP_TG1_T0_EDGE_INT_MAP + 32 + 0x00000000 + + + APP_TG1_T0_EDGE_INT_MAP + 0 + 5 + + + + + APP_TG1_T1_EDGE_INT_MAP + 0x314 + DPORT_APP_TG1_T1_EDGE_INT_MAP + 32 + 0x00000000 + + + APP_TG1_T1_EDGE_INT_MAP + 0 + 5 + + + + + APP_TG1_WDT_EDGE_INT_MAP + 0x318 + DPORT_APP_TG1_WDT_EDGE_INT_MAP + 32 + 0x00000000 + + + APP_TG1_WDT_EDGE_INT_MAP + 0 + 5 + + + + + APP_TG1_LACT_EDGE_INT_MAP + 0x31c + DPORT_APP_TG1_LACT_EDGE_INT_MAP + 32 + 0x00000000 + + + APP_TG1_LACT_EDGE_INT_MAP + 0 + 5 + + + + + APP_MMU_IA_INT_MAP + 0x320 + DPORT_APP_MMU_IA_INT_MAP + 32 + 0x00000000 + + + APP_MMU_IA_INT_MAP + 0 + 5 + + + + + APP_MPU_IA_INT_MAP + 0x324 + DPORT_APP_MPU_IA_INT_MAP + 32 + 0x00000000 + + + APP_MPU_IA_INT_MAP + 0 + 5 + + + + + APP_CACHE_IA_INT_MAP + 0x328 + DPORT_APP_CACHE_IA_INT_MAP + 32 + 0x00000000 + + + APP_CACHE_IA_INT_MAP + 0 + 5 + + + + + AHBLITE_MPU_TABLE_UART + 0x32c + DPORT_AHBLITE_MPU_TABLE_UART + 32 + 0x00000000 + + + UART_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_SPI1 + 0x330 + DPORT_AHBLITE_MPU_TABLE_SPI1 + 32 + 0x00000000 + + + SPI1_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_SPI0 + 0x334 + DPORT_AHBLITE_MPU_TABLE_SPI0 + 32 + 0x00000000 + + + SPI0_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_GPIO + 0x338 + DPORT_AHBLITE_MPU_TABLE_GPIO + 32 + 0x00000000 + + + GPIO_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_FE2 + 0x33c + DPORT_AHBLITE_MPU_TABLE_FE2 + 32 + 0x00000000 + + + FE2_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_FE + 0x340 + DPORT_AHBLITE_MPU_TABLE_FE + 32 + 0x00000000 + + + FE_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_TIMER + 0x344 + DPORT_AHBLITE_MPU_TABLE_TIMER + 32 + 0x00000000 + + + TIMER_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_RTC + 0x348 + DPORT_AHBLITE_MPU_TABLE_RTC + 32 + 0x00000000 + + + RTC_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_IO_MUX + 0x34c + DPORT_AHBLITE_MPU_TABLE_IO_MUX + 32 + 0x00000000 + + + IOMUX_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_WDG + 0x350 + DPORT_AHBLITE_MPU_TABLE_WDG + 32 + 0x00000000 + + + WDG_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_HINF + 0x354 + DPORT_AHBLITE_MPU_TABLE_HINF + 32 + 0x00000000 + + + HINF_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_UHCI1 + 0x358 + DPORT_AHBLITE_MPU_TABLE_UHCI1 + 32 + 0x00000000 + + + UHCI1_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_MISC + 0x35c + DPORT_AHBLITE_MPU_TABLE_MISC + 32 + 0x00000000 + + + MISC_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_I2C + 0x360 + DPORT_AHBLITE_MPU_TABLE_I2C + 32 + 0x00000000 + + + I2C_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_I2S0 + 0x364 + DPORT_AHBLITE_MPU_TABLE_I2S0 + 32 + 0x00000000 + + + I2S0_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_UART1 + 0x368 + DPORT_AHBLITE_MPU_TABLE_UART1 + 32 + 0x00000000 + + + UART1_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_BT + 0x36c + DPORT_AHBLITE_MPU_TABLE_BT + 32 + 0x00000000 + + + BT_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_BT_BUFFER + 0x370 + DPORT_AHBLITE_MPU_TABLE_BT_BUFFER + 32 + 0x00000000 + + + BTBUFFER_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_I2C_EXT0 + 0x374 + DPORT_AHBLITE_MPU_TABLE_I2C_EXT0 + 32 + 0x00000000 + + + I2CEXT0_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_UHCI0 + 0x378 + DPORT_AHBLITE_MPU_TABLE_UHCI0 + 32 + 0x00000000 + + + UHCI0_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_SLCHOST + 0x37c + DPORT_AHBLITE_MPU_TABLE_SLCHOST + 32 + 0x00000000 + + + SLCHOST_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_RMT + 0x380 + DPORT_AHBLITE_MPU_TABLE_RMT + 32 + 0x00000000 + + + RMT_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_PCNT + 0x384 + DPORT_AHBLITE_MPU_TABLE_PCNT + 32 + 0x00000000 + + + PCNT_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_SLC + 0x388 + DPORT_AHBLITE_MPU_TABLE_SLC + 32 + 0x00000000 + + + SLC_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_LEDC + 0x38c + DPORT_AHBLITE_MPU_TABLE_LEDC + 32 + 0x00000000 + + + LEDC_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_EFUSE + 0x390 + DPORT_AHBLITE_MPU_TABLE_EFUSE + 32 + 0x00000000 + + + EFUSE_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_SPI_ENCRYPT + 0x394 + DPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT + 32 + 0x00000000 + + + SPI_ENCRYPY_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_BB + 0x398 + DPORT_AHBLITE_MPU_TABLE_BB + 32 + 0x00000000 + + + BB_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_PWM0 + 0x39c + DPORT_AHBLITE_MPU_TABLE_PWM0 + 32 + 0x00000000 + + + PWM0_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_TIMERGROUP + 0x3a0 + DPORT_AHBLITE_MPU_TABLE_TIMERGROUP + 32 + 0x00000000 + + + TIMERGROUP_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_TIMERGROUP1 + 0x3a4 + DPORT_AHBLITE_MPU_TABLE_TIMERGROUP1 + 32 + 0x00000000 + + + TIMERGROUP1_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_SPI2 + 0x3a8 + DPORT_AHBLITE_MPU_TABLE_SPI2 + 32 + 0x00000000 + + + SPI2_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_SPI3 + 0x3ac + DPORT_AHBLITE_MPU_TABLE_SPI3 + 32 + 0x00000000 + + + SPI3_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_APB_CTRL + 0x3b0 + DPORT_AHBLITE_MPU_TABLE_APB_CTRL + 32 + 0x00000000 + + + APBCTRL_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_I2C_EXT1 + 0x3b4 + DPORT_AHBLITE_MPU_TABLE_I2C_EXT1 + 32 + 0x00000000 + + + I2CEXT1_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_SDIO_HOST + 0x3b8 + DPORT_AHBLITE_MPU_TABLE_SDIO_HOST + 32 + 0x00000000 + + + SDIOHOST_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_EMAC + 0x3bc + DPORT_AHBLITE_MPU_TABLE_EMAC + 32 + 0x00000000 + + + EMAC_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_CAN + 0x3c0 + DPORT_AHBLITE_MPU_TABLE_CAN + 32 + 0x00000000 + + + CAN_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_PWM1 + 0x3c4 + DPORT_AHBLITE_MPU_TABLE_PWM1 + 32 + 0x00000000 + + + PWM1_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_I2S1 + 0x3c8 + DPORT_AHBLITE_MPU_TABLE_I2S1 + 32 + 0x00000000 + + + I2S1_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_UART2 + 0x3cc + DPORT_AHBLITE_MPU_TABLE_UART2 + 32 + 0x00000000 + + + UART2_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_PWM2 + 0x3d0 + DPORT_AHBLITE_MPU_TABLE_PWM2 + 32 + 0x00000000 + + + PWM2_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_PWM3 + 0x3d4 + DPORT_AHBLITE_MPU_TABLE_PWM3 + 32 + 0x00000000 + + + PWM3_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_RWBT + 0x3d8 + DPORT_AHBLITE_MPU_TABLE_RWBT + 32 + 0x00000000 + + + RWBT_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_BTMAC + 0x3dc + DPORT_AHBLITE_MPU_TABLE_BTMAC + 32 + 0x00000000 + + + BTMAC_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_WIFIMAC + 0x3e0 + DPORT_AHBLITE_MPU_TABLE_WIFIMAC + 32 + 0x00000000 + + + WIFIMAC_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + AHBLITE_MPU_TABLE_PWR + 0x3e4 + DPORT_AHBLITE_MPU_TABLE_PWR + 32 + 0x00000000 + + + PWR_ACCESS_GRANT_CONFIG + 0 + 6 + + + + + MEM_ACCESS_DBUG0 + 0x3e8 + DPORT_MEM_ACCESS_DBUG0 + 32 + 0x00000000 + + + INTERNAL_SRAM_MMU_MULTI_HIT + 26 + 4 + + + INTERNAL_SRAM_IA + 14 + 12 + + + INTERNAL_SRAM_MMU_AD + 10 + 4 + + + SHARE_ROM_IA + 6 + 4 + + + SHARE_ROM_MPU_AD + 4 + 2 + + + APP_ROM_IA + 3 + 1 + + + APP_ROM_MPU_AD + 2 + 1 + + + PRO_ROM_IA + 1 + 1 + + + PRO_ROM_MPU_AD + 0 + 1 + + + + + MEM_ACCESS_DBUG1 + 0x3ec + DPORT_MEM_ACCESS_DBUG1 + 32 + 0x00000000 + + + AHBLITE_IA + 10 + 1 + + + AHBLITE_ACCESS_DENY + 9 + 1 + + + AHB_ACCESS_DENY + 8 + 1 + + + PIDGEN_IA + 6 + 2 + + + ARB_IA + 4 + 2 + + + INTERNAL_SRAM_MMU_MISS + 0 + 4 + + + + + PRO_DCACHE_DBUG0 + 0x3f0 + DPORT_PRO_DCACHE_DBUG0 + 32 + 0x00000000 + + + PRO_RX_END + 23 + 1 + + + PRO_SLAVE_WDATA_V + 22 + 1 + + + PRO_SLAVE_WR + 21 + 1 + + + PRO_TX_END + 20 + 1 + + + PRO_WR_BAK_TO_READ + 19 + 1 + + + PRO_CACHE_STATE + 7 + 12 + + + PRO_CACHE_IA + 1 + 6 + + + PRO_CACHE_MMU_IA + 0 + 1 + + + + + PRO_DCACHE_DBUG1 + 0x3f4 + DPORT_PRO_DCACHE_DBUG1 + 32 + 0x00000000 + + + PRO_CTAG_RAM_RDATA + 0 + 32 + + + + + PRO_DCACHE_DBUG2 + 0x3f8 + DPORT_PRO_DCACHE_DBUG2 + 32 + 0x00000000 + + + PRO_CACHE_VADDR + 0 + 27 + + + + + PRO_DCACHE_DBUG3 + 0x3fc + DPORT_PRO_DCACHE_DBUG3 + 32 + 0x00000000 + + + PRO_CACHE_IRAM0_PID_ERROR + 15 + 1 + + + PRO_CPU_DISABLED_CACHE_IA + 9 + 6 + + + + + PRO_DCACHE_DBUG4 + 0x400 + DPORT_PRO_DCACHE_DBUG4 + 32 + 0x00000000 + + + PRO_DRAM1ADDR0_IA + 0 + 20 + + + + + PRO_DCACHE_DBUG5 + 0x404 + DPORT_PRO_DCACHE_DBUG5 + 32 + 0x00000000 + + + PRO_DROM0ADDR0_IA + 0 + 20 + + + + + PRO_DCACHE_DBUG6 + 0x408 + DPORT_PRO_DCACHE_DBUG6 + 32 + 0x00000000 + + + PRO_IRAM0ADDR_IA + 0 + 20 + + + + + PRO_DCACHE_DBUG7 + 0x40c + DPORT_PRO_DCACHE_DBUG7 + 32 + 0x00000000 + + + PRO_IRAM1ADDR_IA + 0 + 20 + + + + + PRO_DCACHE_DBUG8 + 0x410 + DPORT_PRO_DCACHE_DBUG8 + 32 + 0x00000000 + + + PRO_IROM0ADDR_IA + 0 + 20 + + + + + PRO_DCACHE_DBUG9 + 0x414 + DPORT_PRO_DCACHE_DBUG9 + 32 + 0x00000000 + + + PRO_OPSDRAMADDR_IA + 0 + 20 + + + + + APP_DCACHE_DBUG0 + 0x418 + DPORT_APP_DCACHE_DBUG0 + 32 + 0x00000000 + + + APP_RX_END + 23 + 1 + + + APP_SLAVE_WDATA_V + 22 + 1 + + + APP_SLAVE_WR + 21 + 1 + + + APP_TX_END + 20 + 1 + + + APP_WR_BAK_TO_READ + 19 + 1 + + + APP_CACHE_STATE + 7 + 12 + + + APP_CACHE_IA + 1 + 6 + + + APP_CACHE_MMU_IA + 0 + 1 + + + + + APP_DCACHE_DBUG1 + 0x41c + DPORT_APP_DCACHE_DBUG1 + 32 + 0x00000000 + + + APP_CTAG_RAM_RDATA + 0 + 32 + + + + + APP_DCACHE_DBUG2 + 0x420 + DPORT_APP_DCACHE_DBUG2 + 32 + 0x00000000 + + + APP_CACHE_VADDR + 0 + 27 + + + + + APP_DCACHE_DBUG3 + 0x424 + DPORT_APP_DCACHE_DBUG3 + 32 + 0x00000000 + + + APP_CACHE_IRAM0_PID_ERROR + 15 + 1 + + + APP_CPU_DISABLED_CACHE_IA + 9 + 6 + + + + + APP_DCACHE_DBUG4 + 0x428 + DPORT_APP_DCACHE_DBUG4 + 32 + 0x00000000 + + + APP_DRAM1ADDR0_IA + 0 + 20 + + + + + APP_DCACHE_DBUG5 + 0x42c + DPORT_APP_DCACHE_DBUG5 + 32 + 0x00000000 + + + APP_DROM0ADDR0_IA + 0 + 20 + + + + + APP_DCACHE_DBUG6 + 0x430 + DPORT_APP_DCACHE_DBUG6 + 32 + 0x00000000 + + + APP_IRAM0ADDR_IA + 0 + 20 + + + + + APP_DCACHE_DBUG7 + 0x434 + DPORT_APP_DCACHE_DBUG7 + 32 + 0x00000000 + + + APP_IRAM1ADDR_IA + 0 + 20 + + + + + APP_DCACHE_DBUG8 + 0x438 + DPORT_APP_DCACHE_DBUG8 + 32 + 0x00000000 + + + APP_IROM0ADDR_IA + 0 + 20 + + + + + APP_DCACHE_DBUG9 + 0x43c + DPORT_APP_DCACHE_DBUG9 + 32 + 0x00000000 + + + APP_OPSDRAMADDR_IA + 0 + 20 + + + + + PRO_CPU_RECORD_CTRL + 0x440 + DPORT_PRO_CPU_RECORD_CTRL + 32 + 0x00000000 + + + PRO_CPU_PDEBUG_ENABLE + 8 + 1 + + + PRO_CPU_RECORD_DISABLE + 4 + 1 + + + PRO_CPU_RECORD_ENABLE + 0 + 1 + + + + + PRO_CPU_RECORD_STATUS + 0x444 + DPORT_PRO_CPU_RECORD_STATUS + 32 + 0x00000000 + + + PRO_CPU_RECORDING + 0 + 1 + + + + + PRO_CPU_RECORD_PID + 0x448 + DPORT_PRO_CPU_RECORD_PID + 32 + 0x00000000 + + + RECORD_PRO_PID + 0 + 3 + + + + + PRO_CPU_RECORD_PDEBUGINST + 0x44c + DPORT_PRO_CPU_RECORD_PDEBUGINST + 32 + 0x00000000 + + + RECORD_PRO_PDEBUGINST + 0 + 32 + + + + + PRO_CPU_RECORD_PDEBUGSTATUS + 0x450 + DPORT_PRO_CPU_RECORD_PDEBUGSTATUS + 32 + 0x00000000 + + + RECORD_PRO_PDEBUGSTATUS + 0 + 8 + + + + + PRO_CPU_RECORD_PDEBUGDATA + 0x454 + DPORT_PRO_CPU_RECORD_PDEBUGDATA + 32 + 0x00000000 + + + RECORD_PRO_PDEBUGDATA + 0 + 32 + + + + + PRO_CPU_RECORD_PDEBUGPC + 0x458 + DPORT_PRO_CPU_RECORD_PDEBUGPC + 32 + 0x00000000 + + + RECORD_PRO_PDEBUGPC + 0 + 32 + + + + + PRO_CPU_RECORD_PDEBUGLS0STAT + 0x45c + DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT + 32 + 0x00000000 + + + RECORD_PRO_PDEBUGLS0STAT + 0 + 32 + + + + + PRO_CPU_RECORD_PDEBUGLS0ADDR + 0x460 + DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR + 32 + 0x00000000 + + + RECORD_PRO_PDEBUGLS0ADDR + 0 + 32 + + + + + PRO_CPU_RECORD_PDEBUGLS0DATA + 0x464 + DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA + 32 + 0x00000000 + + + RECORD_PRO_PDEBUGLS0DATA + 0 + 32 + + + + + APP_CPU_RECORD_CTRL + 0x468 + DPORT_APP_CPU_RECORD_CTRL + 32 + 0x00000000 + + + APP_CPU_PDEBUG_ENABLE + 8 + 1 + + + APP_CPU_RECORD_DISABLE + 4 + 1 + + + APP_CPU_RECORD_ENABLE + 0 + 1 + + + + + APP_CPU_RECORD_STATUS + 0x46c + DPORT_APP_CPU_RECORD_STATUS + 32 + 0x00000000 + + + APP_CPU_RECORDING + 0 + 1 + + + + + APP_CPU_RECORD_PID + 0x470 + DPORT_APP_CPU_RECORD_PID + 32 + 0x00000000 + + + RECORD_APP_PID + 0 + 3 + + + + + APP_CPU_RECORD_PDEBUGINST + 0x474 + DPORT_APP_CPU_RECORD_PDEBUGINST + 32 + 0x00000000 + + + RECORD_APP_PDEBUGINST + 0 + 32 + + + + + APP_CPU_RECORD_PDEBUGSTATUS + 0x478 + DPORT_APP_CPU_RECORD_PDEBUGSTATUS + 32 + 0x00000000 + + + RECORD_APP_PDEBUGSTATUS + 0 + 8 + + + + + APP_CPU_RECORD_PDEBUGDATA + 0x47c + DPORT_APP_CPU_RECORD_PDEBUGDATA + 32 + 0x00000000 + + + RECORD_APP_PDEBUGDATA + 0 + 32 + + + + + APP_CPU_RECORD_PDEBUGPC + 0x480 + DPORT_APP_CPU_RECORD_PDEBUGPC + 32 + 0x00000000 + + + RECORD_APP_PDEBUGPC + 0 + 32 + + + + + APP_CPU_RECORD_PDEBUGLS0STAT + 0x484 + DPORT_APP_CPU_RECORD_PDEBUGLS0STAT + 32 + 0x00000000 + + + RECORD_APP_PDEBUGLS0STAT + 0 + 32 + + + + + APP_CPU_RECORD_PDEBUGLS0ADDR + 0x488 + DPORT_APP_CPU_RECORD_PDEBUGLS0ADDR + 32 + 0x00000000 + + + RECORD_APP_PDEBUGLS0ADDR + 0 + 32 + + + + + APP_CPU_RECORD_PDEBUGLS0DATA + 0x48c + DPORT_APP_CPU_RECORD_PDEBUGLS0DATA + 32 + 0x00000000 + + + RECORD_APP_PDEBUGLS0DATA + 0 + 32 + + + + + RSA_PD_CTRL + 0x490 + DPORT_RSA_PD_CTRL + 32 + 0x00000000 + + + RSA_PD + 0 + 1 + + + + + ROM_MPU_TABLE0 + 0x494 + DPORT_ROM_MPU_TABLE0 + 32 + 0x00000000 + + + ROM_MPU_TABLE0 + 0 + 2 + + + + + ROM_MPU_TABLE1 + 0x498 + DPORT_ROM_MPU_TABLE1 + 32 + 0x00000000 + + + ROM_MPU_TABLE1 + 0 + 2 + + + + + ROM_MPU_TABLE2 + 0x49c + DPORT_ROM_MPU_TABLE2 + 32 + 0x00000000 + + + ROM_MPU_TABLE2 + 0 + 2 + + + + + ROM_MPU_TABLE3 + 0x4a0 + DPORT_ROM_MPU_TABLE3 + 32 + 0x00000000 + + + ROM_MPU_TABLE3 + 0 + 2 + + + + + SHROM_MPU_TABLE0 + 0x4a4 + DPORT_SHROM_MPU_TABLE0 + 32 + 0x00000000 + + + SHROM_MPU_TABLE0 + 0 + 2 + + + + + SHROM_MPU_TABLE1 + 0x4a8 + DPORT_SHROM_MPU_TABLE1 + 32 + 0x00000000 + + + SHROM_MPU_TABLE1 + 0 + 2 + + + + + SHROM_MPU_TABLE2 + 0x4ac + DPORT_SHROM_MPU_TABLE2 + 32 + 0x00000000 + + + SHROM_MPU_TABLE2 + 0 + 2 + + + + + SHROM_MPU_TABLE3 + 0x4b0 + DPORT_SHROM_MPU_TABLE3 + 32 + 0x00000000 + + + SHROM_MPU_TABLE3 + 0 + 2 + + + + + SHROM_MPU_TABLE4 + 0x4b4 + DPORT_SHROM_MPU_TABLE4 + 32 + 0x00000000 + + + SHROM_MPU_TABLE4 + 0 + 2 + + + + + SHROM_MPU_TABLE5 + 0x4b8 + DPORT_SHROM_MPU_TABLE5 + 32 + 0x00000000 + + + SHROM_MPU_TABLE5 + 0 + 2 + + + + + SHROM_MPU_TABLE6 + 0x4bc + DPORT_SHROM_MPU_TABLE6 + 32 + 0x00000000 + + + SHROM_MPU_TABLE6 + 0 + 2 + + + + + SHROM_MPU_TABLE7 + 0x4c0 + DPORT_SHROM_MPU_TABLE7 + 32 + 0x00000000 + + + SHROM_MPU_TABLE7 + 0 + 2 + + + + + SHROM_MPU_TABLE8 + 0x4c4 + DPORT_SHROM_MPU_TABLE8 + 32 + 0x00000000 + + + SHROM_MPU_TABLE8 + 0 + 2 + + + + + SHROM_MPU_TABLE9 + 0x4c8 + DPORT_SHROM_MPU_TABLE9 + 32 + 0x00000000 + + + SHROM_MPU_TABLE9 + 0 + 2 + + + + + SHROM_MPU_TABLE10 + 0x4cc + DPORT_SHROM_MPU_TABLE10 + 32 + 0x00000000 + + + SHROM_MPU_TABLE10 + 0 + 2 + + + + + SHROM_MPU_TABLE11 + 0x4d0 + DPORT_SHROM_MPU_TABLE11 + 32 + 0x00000000 + + + SHROM_MPU_TABLE11 + 0 + 2 + + + + + SHROM_MPU_TABLE12 + 0x4d4 + DPORT_SHROM_MPU_TABLE12 + 32 + 0x00000000 + + + SHROM_MPU_TABLE12 + 0 + 2 + + + + + SHROM_MPU_TABLE13 + 0x4d8 + DPORT_SHROM_MPU_TABLE13 + 32 + 0x00000000 + + + SHROM_MPU_TABLE13 + 0 + 2 + + + + + SHROM_MPU_TABLE14 + 0x4dc + DPORT_SHROM_MPU_TABLE14 + 32 + 0x00000000 + + + SHROM_MPU_TABLE14 + 0 + 2 + + + + + SHROM_MPU_TABLE15 + 0x4e0 + DPORT_SHROM_MPU_TABLE15 + 32 + 0x00000000 + + + SHROM_MPU_TABLE15 + 0 + 2 + + + + + SHROM_MPU_TABLE16 + 0x4e4 + DPORT_SHROM_MPU_TABLE16 + 32 + 0x00000000 + + + SHROM_MPU_TABLE16 + 0 + 2 + + + + + SHROM_MPU_TABLE17 + 0x4e8 + DPORT_SHROM_MPU_TABLE17 + 32 + 0x00000000 + + + SHROM_MPU_TABLE17 + 0 + 2 + + + + + SHROM_MPU_TABLE18 + 0x4ec + DPORT_SHROM_MPU_TABLE18 + 32 + 0x00000000 + + + SHROM_MPU_TABLE18 + 0 + 2 + + + + + SHROM_MPU_TABLE19 + 0x4f0 + DPORT_SHROM_MPU_TABLE19 + 32 + 0x00000000 + + + SHROM_MPU_TABLE19 + 0 + 2 + + + + + SHROM_MPU_TABLE20 + 0x4f4 + DPORT_SHROM_MPU_TABLE20 + 32 + 0x00000000 + + + SHROM_MPU_TABLE20 + 0 + 2 + + + + + SHROM_MPU_TABLE21 + 0x4f8 + DPORT_SHROM_MPU_TABLE21 + 32 + 0x00000000 + + + SHROM_MPU_TABLE21 + 0 + 2 + + + + + SHROM_MPU_TABLE22 + 0x4fc + DPORT_SHROM_MPU_TABLE22 + 32 + 0x00000000 + + + SHROM_MPU_TABLE22 + 0 + 2 + + + + + SHROM_MPU_TABLE23 + 0x500 + DPORT_SHROM_MPU_TABLE23 + 32 + 0x00000000 + + + SHROM_MPU_TABLE23 + 0 + 2 + + + + + IMMU_TABLE0 + 0x504 + DPORT_IMMU_TABLE0 + 32 + 0x00000000 + + + IMMU_TABLE0 + 0 + 7 + + + + + IMMU_TABLE1 + 0x508 + DPORT_IMMU_TABLE1 + 32 + 0x00000000 + + + IMMU_TABLE1 + 0 + 7 + + + + + IMMU_TABLE2 + 0x50c + DPORT_IMMU_TABLE2 + 32 + 0x00000000 + + + IMMU_TABLE2 + 0 + 7 + + + + + IMMU_TABLE3 + 0x510 + DPORT_IMMU_TABLE3 + 32 + 0x00000000 + + + IMMU_TABLE3 + 0 + 7 + + + + + IMMU_TABLE4 + 0x514 + DPORT_IMMU_TABLE4 + 32 + 0x00000000 + + + IMMU_TABLE4 + 0 + 7 + + + + + IMMU_TABLE5 + 0x518 + DPORT_IMMU_TABLE5 + 32 + 0x00000000 + + + IMMU_TABLE5 + 0 + 7 + + + + + IMMU_TABLE6 + 0x51c + DPORT_IMMU_TABLE6 + 32 + 0x00000000 + + + IMMU_TABLE6 + 0 + 7 + + + + + IMMU_TABLE7 + 0x520 + DPORT_IMMU_TABLE7 + 32 + 0x00000000 + + + IMMU_TABLE7 + 0 + 7 + + + + + IMMU_TABLE8 + 0x524 + DPORT_IMMU_TABLE8 + 32 + 0x00000000 + + + IMMU_TABLE8 + 0 + 7 + + + + + IMMU_TABLE9 + 0x528 + DPORT_IMMU_TABLE9 + 32 + 0x00000000 + + + IMMU_TABLE9 + 0 + 7 + + + + + IMMU_TABLE10 + 0x52c + DPORT_IMMU_TABLE10 + 32 + 0x00000000 + + + IMMU_TABLE10 + 0 + 7 + + + + + IMMU_TABLE11 + 0x530 + DPORT_IMMU_TABLE11 + 32 + 0x00000000 + + + IMMU_TABLE11 + 0 + 7 + + + + + IMMU_TABLE12 + 0x534 + DPORT_IMMU_TABLE12 + 32 + 0x00000000 + + + IMMU_TABLE12 + 0 + 7 + + + + + IMMU_TABLE13 + 0x538 + DPORT_IMMU_TABLE13 + 32 + 0x00000000 + + + IMMU_TABLE13 + 0 + 7 + + + + + IMMU_TABLE14 + 0x53c + DPORT_IMMU_TABLE14 + 32 + 0x00000000 + + + IMMU_TABLE14 + 0 + 7 + + + + + IMMU_TABLE15 + 0x540 + DPORT_IMMU_TABLE15 + 32 + 0x00000000 + + + IMMU_TABLE15 + 0 + 7 + + + + + DMMU_TABLE0 + 0x544 + DPORT_DMMU_TABLE0 + 32 + 0x00000000 + + + DMMU_TABLE0 + 0 + 7 + + + + + DMMU_TABLE1 + 0x548 + DPORT_DMMU_TABLE1 + 32 + 0x00000000 + + + DMMU_TABLE1 + 0 + 7 + + + + + DMMU_TABLE2 + 0x54c + DPORT_DMMU_TABLE2 + 32 + 0x00000000 + + + DMMU_TABLE2 + 0 + 7 + + + + + DMMU_TABLE3 + 0x550 + DPORT_DMMU_TABLE3 + 32 + 0x00000000 + + + DMMU_TABLE3 + 0 + 7 + + + + + DMMU_TABLE4 + 0x554 + DPORT_DMMU_TABLE4 + 32 + 0x00000000 + + + DMMU_TABLE4 + 0 + 7 + + + + + DMMU_TABLE5 + 0x558 + DPORT_DMMU_TABLE5 + 32 + 0x00000000 + + + DMMU_TABLE5 + 0 + 7 + + + + + DMMU_TABLE6 + 0x55c + DPORT_DMMU_TABLE6 + 32 + 0x00000000 + + + DMMU_TABLE6 + 0 + 7 + + + + + DMMU_TABLE7 + 0x560 + DPORT_DMMU_TABLE7 + 32 + 0x00000000 + + + DMMU_TABLE7 + 0 + 7 + + + + + DMMU_TABLE8 + 0x564 + DPORT_DMMU_TABLE8 + 32 + 0x00000000 + + + DMMU_TABLE8 + 0 + 7 + + + + + DMMU_TABLE9 + 0x568 + DPORT_DMMU_TABLE9 + 32 + 0x00000000 + + + DMMU_TABLE9 + 0 + 7 + + + + + DMMU_TABLE10 + 0x56c + DPORT_DMMU_TABLE10 + 32 + 0x00000000 + + + DMMU_TABLE10 + 0 + 7 + + + + + DMMU_TABLE11 + 0x570 + DPORT_DMMU_TABLE11 + 32 + 0x00000000 + + + DMMU_TABLE11 + 0 + 7 + + + + + DMMU_TABLE12 + 0x574 + DPORT_DMMU_TABLE12 + 32 + 0x00000000 + + + DMMU_TABLE12 + 0 + 7 + + + + + DMMU_TABLE13 + 0x578 + DPORT_DMMU_TABLE13 + 32 + 0x00000000 + + + DMMU_TABLE13 + 0 + 7 + + + + + DMMU_TABLE14 + 0x57c + DPORT_DMMU_TABLE14 + 32 + 0x00000000 + + + DMMU_TABLE14 + 0 + 7 + + + + + DMMU_TABLE15 + 0x580 + DPORT_DMMU_TABLE15 + 32 + 0x00000000 + + + DMMU_TABLE15 + 0 + 7 + + + + + PRO_INTRUSION_CTRL + 0x584 + DPORT_PRO_INTRUSION_CTRL + 32 + 0x00000000 + + + PRO_INTRUSION_RECORD_RESET_N + 0 + 1 + + + + + PRO_INTRUSION_STATUS + 0x588 + DPORT_PRO_INTRUSION_STATUS + 32 + 0x00000000 + + + PRO_INTRUSION_RECORD + 0 + 4 + + + + + APP_INTRUSION_CTRL + 0x58c + DPORT_APP_INTRUSION_CTRL + 32 + 0x00000000 + + + APP_INTRUSION_RECORD_RESET_N + 0 + 1 + + + + + APP_INTRUSION_STATUS + 0x590 + DPORT_APP_INTRUSION_STATUS + 32 + 0x00000000 + + + APP_INTRUSION_RECORD + 0 + 4 + + + + + FRONT_END_MEM_PD + 0x594 + DPORT_FRONT_END_MEM_PD + 32 + 0x00000000 + + + PBUS_MEM_FORCE_PD + 3 + 1 + + + PBUS_MEM_FORCE_PU + 2 + 1 + + + AGC_MEM_FORCE_PD + 1 + 1 + + + AGC_MEM_FORCE_PU + 0 + 1 + + + + + MMU_IA_INT_EN + 0x598 + DPORT_MMU_IA_INT_EN + 32 + 0x00000000 + + + MMU_IA_INT_EN + 0 + 24 + + + + + MPU_IA_INT_EN + 0x59c + DPORT_MPU_IA_INT_EN + 32 + 0x00000000 + + + MPU_IA_INT_EN + 0 + 17 + + + + + CACHE_IA_INT_EN + 0x5a0 + DPORT_CACHE_IA_INT_EN + 32 + 0x00000000 + + + CACHE_IA_INT_EN + 0 + 28 + + + CACHE_IA_INT_PRO_OPPOSITE + 19 + 1 + + + CACHE_IA_INT_PRO_DRAM1 + 18 + 1 + + + CACHE_IA_INT_PRO_IROM0 + 17 + 1 + + + CACHE_IA_INT_PRO_IRAM1 + 16 + 1 + + + CACHE_IA_INT_PRO_IRAM0 + 15 + 1 + + + CACHE_IA_INT_PRO_DROM0 + 14 + 1 + + + CACHE_IA_INT_APP_OPPOSITE + 5 + 1 + + + CACHE_IA_INT_APP_IROM0 + 3 + 1 + + + CACHE_IA_INT_APP_IRAM1 + 2 + 1 + + + CACHE_IA_INT_APP_IRAM0 + 1 + 1 + + + CACHE_IA_INT_APP_DROM0 + 0 + 1 + + + + + SECURE_BOOT_CTRL + 0x5a4 + DPORT_SECURE_BOOT_CTRL + 32 + 0x00000000 + + + SW_BOOTLOADER_SEL + 0 + 1 + + + + + SPI_DMA_CHAN_SEL + 0x5a8 + DPORT_SPI_DMA_CHAN_SEL + 32 + 0x00000000 + + + SPI3_DMA_CHAN_SEL + 4 + 2 + + + SPI2_DMA_CHAN_SEL + 2 + 2 + + + SPI1_DMA_CHAN_SEL + 0 + 2 + + + + + PRO_VECBASE_CTRL + 0x5ac + DPORT_PRO_VECBASE_CTRL + 32 + 0x00000000 + + + PRO_OUT_VECBASE_SEL + 0 + 2 + + + + + PRO_VECBASE_SET + 0x5b0 + DPORT_PRO_VECBASE_SET + 32 + 0x00000000 + + + PRO_OUT_VECBASE_REG + 0 + 22 + + + + + APP_VECBASE_CTRL + 0x5b4 + DPORT_APP_VECBASE_CTRL + 32 + 0x00000000 + + + APP_OUT_VECBASE_SEL + 0 + 2 + + + + + APP_VECBASE_SET + 0x5b8 + DPORT_APP_VECBASE_SET + 32 + 0x00000000 + + + APP_OUT_VECBASE_REG + 0 + 22 + + + + + DATE + 0xffc + DPORT_DATE + 32 + 0x00000000 + + + DATE + 0 + 28 + + + + + + + SPI3 + 0x3ff65000 + + + UART2 + 0x3ff6e000 + + + TIMG + 0x0 + + 0 + 0x00000580 + registers + + + + T0CONFIG + 0x0 + TIMG_T0CONFIG + 32 + 0x00000000 + + + T0_EN + 31 + 1 + + + T0_INCREASE + 30 + 1 + + + T0_AUTORELOAD + 29 + 1 + + + T0_DIVIDER + 13 + 16 + + + T0_EDGE_INT_EN + 12 + 1 + + + T0_LEVEL_INT_EN + 11 + 1 + + + T0_ALARM_EN + 10 + 1 + + + + + T0LO + 0x4 + TIMG_T0LO + 32 + 0x00000000 + + + T0_LO + 0 + 32 + + + + + T0HI + 0x8 + TIMG_T0HI + 32 + 0x00000000 + + + T0_HI + 0 + 32 + + + + + T0UPDATE + 0xc + TIMG_T0UPDATE + 32 + 0x00000000 + + + T0_UPDATE + 0 + 32 + + + + + T0ALARMLO + 0x10 + TIMG_T0ALARMLO + 32 + 0x00000000 + + + T0_ALARM_LO + 0 + 32 + + + + + T0ALARMHI + 0x14 + TIMG_T0ALARMHI + 32 + 0x00000000 + + + T0_ALARM_HI + 0 + 32 + + + + + T0LOADLO + 0x18 + TIMG_T0LOADLO + 32 + 0x00000000 + + + T0_LOAD_LO + 0 + 32 + + + + + T0LOADHI + 0x1c + TIMG_T0LOADHI + 32 + 0x00000000 + + + T0_LOAD_HI + 0 + 32 + + + + + T0LOAD + 0x20 + TIMG_T0LOAD + 32 + 0x00000000 + + + T0_LOAD + 0 + 32 + + + + + T1CONFIG + 0x24 + TIMG_T1CONFIG + 32 + 0x00000000 + + + T1_EN + 31 + 1 + + + T1_INCREASE + 30 + 1 + + + T1_AUTORELOAD + 29 + 1 + + + T1_DIVIDER + 13 + 16 + + + T1_EDGE_INT_EN + 12 + 1 + + + T1_LEVEL_INT_EN + 11 + 1 + + + T1_ALARM_EN + 10 + 1 + + + + + T1LO + 0x28 + TIMG_T1LO + 32 + 0x00000000 + + + T1_LO + 0 + 32 + + + + + T1HI + 0x2c + TIMG_T1HI + 32 + 0x00000000 + + + T1_HI + 0 + 32 + + + + + T1UPDATE + 0x30 + TIMG_T1UPDATE + 32 + 0x00000000 + + + T1_UPDATE + 0 + 32 + + + + + T1ALARMLO + 0x34 + TIMG_T1ALARMLO + 32 + 0x00000000 + + + T1_ALARM_LO + 0 + 32 + + + + + T1ALARMHI + 0x38 + TIMG_T1ALARMHI + 32 + 0x00000000 + + + T1_ALARM_HI + 0 + 32 + + + + + T1LOADLO + 0x3c + TIMG_T1LOADLO + 32 + 0x00000000 + + + T1_LOAD_LO + 0 + 32 + + + + + T1LOADHI + 0x40 + TIMG_T1LOADHI + 32 + 0x00000000 + + + T1_LOAD_HI + 0 + 32 + + + + + T1LOAD + 0x44 + TIMG_T1LOAD + 32 + 0x00000000 + + + T1_LOAD + 0 + 32 + + + + + WDTCONFIG0 + 0x48 + TIMG_WDTCONFIG0 + 32 + 0x00000000 + + + WDT_EN + 31 + 1 + + + WDT_STG0 + 29 + 2 + WDT_STG0read-writeDisableDisabled0InterruptTrigger an interrupt1ResetCPUReset CPU core2ResetSystemReset System3 + + + WDT_STG1 + 27 + 2 + + + + WDT_STG2 + 25 + 2 + + + + WDT_STG3 + 23 + 2 + + + + WDT_EDGE_INT_EN + 22 + 1 + + + WDT_LEVEL_INT_EN + 21 + 1 + + + WDT_CPU_RESET_LENGTH + 18 + 3 + WDT_CPU_RESET_LENGTHread-writeT100ns100ns0T200ns200ns1T300ns300ns2T400ns400ns3T500ns500ns4T800ns800ns5T1600ns1600ns6T3200ns3200ns7 + + + WDT_SYS_RESET_LENGTH + 15 + 3 + + + + WDT_FLASHBOOT_MOD_EN + 14 + 1 + + + + + WDTCONFIG1 + 0x4c + TIMG_WDTCONFIG1 + 32 + 0x00000000 + + + WDT_CLK_PRESCALE + 16 + 16 + + + + + WDTCONFIG2 + 0x50 + TIMG_WDTCONFIG2 + 32 + 0x00000000 + + + WDT_STG0_HOLD + 0 + 32 + + + + + WDTCONFIG3 + 0x54 + TIMG_WDTCONFIG3 + 32 + 0x00000000 + + + WDT_STG1_HOLD + 0 + 32 + + + + + WDTCONFIG4 + 0x58 + TIMG_WDTCONFIG4 + 32 + 0x00000000 + + + WDT_STG2_HOLD + 0 + 32 + + + + + WDTCONFIG5 + 0x5c + TIMG_WDTCONFIG5 + 32 + 0x00000000 + + + WDT_STG3_HOLD + 0 + 32 + + + + + WDTFEED + 0x60 + TIMG_WDTFEED + 32 + 0x00000000 + + + WDT_FEED + 0 + 32 + + + + + WDTWPROTECT + 0x64 + TIMG_WDTWPROTECT + 32 + 0x00000000 + + + WDT_WKEY + 0 + 32 + + + + + RTCCALICFG + 0x68 + TIMG_RTCCALICFG + 32 + 0x00000000 + + + START + 31 + 1 + + + MAX + 16 + 15 + + + RDY + 15 + 1 + + + CLK_SEL + 13 + 2 + CLK_SELread-writeRTC_MUXSelect RTC slow clock0CK8M_D256Internal 8 MHz RC oscillator, divided by 2561XTAL32KSelect XTAL_32K2 + + + START_CYCLING + 12 + 1 + + + + + RTCCALICFG1 + 0x6c + TIMG_RTCCALICFG1 + 32 + 0x00000000 + + + VALUE + 7 + 25 + + + + + LACTCONFIG + 0x70 + TIMG_LACTCONFIG + 32 + 0x00000000 + + + LACT_EN + 31 + 1 + + + LACT_INCREASE + 30 + 1 + + + LACT_AUTORELOAD + 29 + 1 + + + LACT_DIVIDER + 13 + 16 + + + LACT_EDGE_INT_EN + 12 + 1 + + + LACT_LEVEL_INT_EN + 11 + 1 + + + LACT_ALARM_EN + 10 + 1 + + + LACT_LAC_EN + 9 + 1 + + + LACT_CPST_EN + 8 + 1 + + + LACT_RTC_ONLY + 7 + 1 + + + + + LACTRTC + 0x74 + TIMG_LACTRTC + 32 + 0x00000000 + + + LACT_RTC_STEP_LEN + 6 + 26 + + + + + LACTLO + 0x78 + TIMG_LACTLO + 32 + 0x00000000 + + + LACT_LO + 0 + 32 + + + + + LACTHI + 0x7c + TIMG_LACTHI + 32 + 0x00000000 + + + LACT_HI + 0 + 32 + + + + + LACTUPDATE + 0x80 + TIMG_LACTUPDATE + 32 + 0x00000000 + + + LACT_UPDATE + 0 + 32 + + + + + LACTALARMLO + 0x84 + TIMG_LACTALARMLO + 32 + 0x00000000 + + + LACT_ALARM_LO + 0 + 32 + + + + + LACTALARMHI + 0x88 + TIMG_LACTALARMHI + 32 + 0x00000000 + + + LACT_ALARM_HI + 0 + 32 + + + + + LACTLOADLO + 0x8c + TIMG_LACTLOADLO + 32 + 0x00000000 + + + LACT_LOAD_LO + 0 + 32 + + + + + LACTLOADHI + 0x90 + TIMG_LACTLOADHI + 32 + 0x00000000 + + + LACT_LOAD_HI + 0 + 32 + + + + + LACTLOAD + 0x94 + TIMG_LACTLOAD + 32 + 0x00000000 + + + LACT_LOAD + 0 + 32 + + + + + INT_ENA_TIMERS + 0x98 + TIMG_INT_ENA_TIMERS + 32 + 0x00000000 + + + LACT_INT_ENA + 3 + 1 + + + WDT_INT_ENA + 2 + 1 + + + T1_INT_ENA + 1 + 1 + + + T0_INT_ENA + 0 + 1 + + + + + INT_RAW_TIMERS + 0x9c + TIMG_INT_RAW_TIMERS + 32 + 0x00000000 + + + LACT_INT_RAW + 3 + 1 + + + WDT_INT_RAW + 2 + 1 + + + T1_INT_RAW + 1 + 1 + + + T0_INT_RAW + 0 + 1 + + + + + INT_ST_TIMERS + 0xa0 + TIMG_INT_ST_TIMERS + 32 + 0x00000000 + + + LACT_INT_ST + 3 + 1 + + + WDT_INT_ST + 2 + 1 + + + T1_INT_ST + 1 + 1 + + + T0_INT_ST + 0 + 1 + + + + + INT_CLR_TIMERS + 0xa4 + TIMG_INT_CLR_TIMERS + 32 + 0x00000000 + + + LACT_INT_CLR + 3 + 1 + + + WDT_INT_CLR + 2 + 1 + + + T1_INT_CLR + 1 + 1 + + + T0_INT_CLR + 0 + 1 + + + + + NTIMERS_DATE + 0xf8 + TIMG_NTIMERS_DATE + 32 + 0x00000000 + + + NTIMERS_DATE + 0 + 28 + + + + + TIMGCLK + 0xfc + TIMGCLK + 32 + 0x00000000 + + + CLK_EN + 31 + 1 + + + + + TG0_T0_LEVEL_INTRinterrupt of TIMER_GROUP0, TIMER0, level, we would like use EDGE for timer if permission14 + TG0_T1_LEVEL_INTRinterrupt of TIMER_GROUP0, TIMER1, level, we would like use EDGE for timer if permission15 + TG0_WDT_LEVEL_INTRinterrupt of TIMER_GROUP0, WATCHDOG, level16 + TG0_LACT_LEVEL_INTRinterrupt of TIMER_GROUP0, LACT, level17 + TG1_T0_LEVEL_INTRinterrupt of TIMER_GROUP1, TIMER0, level, we would like use EDGE for timer if permission18 + TG1_T1_LEVEL_INTRinterrupt of TIMER_GROUP1, TIMER1, level, we would like use EDGE for timer if permission19 + TG1_WDT_LEVEL_INTRinterrupt of TIMER_GROUP1, WATCHDOG, level20 + TG1_LACT_LEVEL_INTRinterrupt of TIMER_GROUP1, LACT, level21 + TG0_T0_EDGE_INTRinterrupt of TIMER_GROUP0, TIMER0, EDGE58 + TG0_T1_EDGE_INTRinterrupt of TIMER_GROUP0, TIMER1, EDGE59 + TG0_WDT_EDGE_INTRinterrupt of TIMER_GROUP0, WATCH DOG, EDGE60 + TG0_LACT_EDGE_INTRinterrupt of TIMER_GROUP0, LACT, EDGE61 + TG1_T0_EDGE_INTRinterrupt of TIMER_GROUP1, TIMER0, EDGE62 + TG1_T1_EDGE_INTRinterrupt of TIMER_GROUP1, TIMER1, EDGE63 + TG1_WDT_EDGE_INTRinterrupt of TIMER_GROUP1, WATCHDOG, EDGE64 + TG1_LACT_EDGE_INTRinterrupt of TIMER_GROUP0, LACT, EDGE65 + + + PWM3 + 0x3ff70000 + + + TIMG0 + 0x3ff5f000 + + + SPI_ENCRYPT + 0x3ff5b000 + + 0 + 0x00000000 + registers + + + + + GPIO_SD + 0x3ff44f00 + + 0 + 0x00000160 + registers + + + + SIGMADELTA0 + 0x0 + GPIO_SIGMADELTA0 + 32 + 0x00000000 + + + SD0_PRESCALE + 8 + 8 + + + SD0_IN + 0 + 8 + + + + + SIGMADELTA1 + 0x4 + GPIO_SIGMADELTA1 + 32 + 0x00000000 + + + SD1_PRESCALE + 8 + 8 + + + SD1_IN + 0 + 8 + + + + + SIGMADELTA2 + 0x8 + GPIO_SIGMADELTA2 + 32 + 0x00000000 + + + SD2_PRESCALE + 8 + 8 + + + SD2_IN + 0 + 8 + + + + + SIGMADELTA3 + 0xc + GPIO_SIGMADELTA3 + 32 + 0x00000000 + + + SD3_PRESCALE + 8 + 8 + + + SD3_IN + 0 + 8 + + + + + SIGMADELTA4 + 0x10 + GPIO_SIGMADELTA4 + 32 + 0x00000000 + + + SD4_PRESCALE + 8 + 8 + + + SD4_IN + 0 + 8 + + + + + SIGMADELTA5 + 0x14 + GPIO_SIGMADELTA5 + 32 + 0x00000000 + + + SD5_PRESCALE + 8 + 8 + + + SD5_IN + 0 + 8 + + + + + SIGMADELTA6 + 0x18 + GPIO_SIGMADELTA6 + 32 + 0x00000000 + + + SD6_PRESCALE + 8 + 8 + + + SD6_IN + 0 + 8 + + + + + SIGMADELTA7 + 0x1c + GPIO_SIGMADELTA7 + 32 + 0x00000000 + + + SD7_PRESCALE + 8 + 8 + + + SD7_IN + 0 + 8 + + + + + SIGMADELTA_CG + 0x20 + GPIO_SIGMADELTA_CG + 32 + 0x00000000 + + + SD_CLK_EN + 31 + 1 + + + + + SIGMADELTA_MISC + 0x24 + GPIO_SIGMADELTA_MISC + 32 + 0x00000000 + + + SPI_SWAP + 31 + 1 + + + + + SIGMADELTA_VERSION + 0x28 + GPIO_SIGMADELTA_VERSION + 32 + 0x00000000 + + + SD_DATE + 0 + 28 + + + + + + + SPI0 + 0x3ff43000 + + + SDMMC + 0x3ff68000 + + 0 + 0x00000000 + registers + + + + + PWM0 + 0x3ff5e000 + + + UHCI1 + 0x3ff4c000 + + + IO_MUX + 0x3ff49000 + + 0 + 0x00000000 + registers + + PIN_CTRLPIN_CTRL_CLK383 + PIN_CTRL_CLK243 + PIN_CTRL_CLK103 + configures clock source and clock output pins3200 + GPIO36MCU_SELconfigures IO_MUX function122 + FUN_DRVconfigures drive strength102 + FUN_IEconfigures input enable91 + FUN_WPUconfigures pull up81 + FUN_WPDconfigures pull down71 + MCU_DRVconfigures drive strength during sleep mode52 + MCU_IEconfigures input enable during sleep mode41 + MCU_WPUconfigures pull up during sleep mode31 + MCU_WPDconfigures pull down during sleep mode21 + SLP_SELconfigures sleep mode selection11 + MCU_OEconfigures output enable during sleep mode01 + configures IO_MUX for GPIO363242048 + GPIO37MCU_SELconfigures IO_MUX function122 + FUN_DRVconfigures drive strength102 + FUN_IEconfigures input enable91 + FUN_WPUconfigures pull up81 + FUN_WPDconfigures pull down71 + MCU_DRVconfigures drive strength during sleep mode52 + MCU_IEconfigures input enable during sleep mode41 + MCU_WPUconfigures pull up during sleep mode31 + MCU_WPDconfigures pull down during sleep mode21 + SLP_SELconfigures sleep mode selection11 + MCU_OEconfigures output enable during sleep mode01 + configures IO_MUX for GPIO373282048 + GPIO38MCU_SELconfigures IO_MUX function122 + FUN_DRVconfigures drive strength102 + FUN_IEconfigures input enable91 + FUN_WPUconfigures pull up81 + FUN_WPDconfigures pull down71 + MCU_DRVconfigures drive strength during sleep mode52 + MCU_IEconfigures input enable during sleep mode41 + MCU_WPUconfigures pull up during sleep mode31 + MCU_WPDconfigures pull down during sleep mode21 + SLP_SELconfigures sleep mode selection11 + MCU_OEconfigures output enable during sleep mode01 + configures IO_MUX for GPIO3832122048 + GPIO39MCU_SELconfigures IO_MUX function122 + FUN_DRVconfigures drive strength102 + FUN_IEconfigures input enable91 + FUN_WPUconfigures pull up81 + FUN_WPDconfigures pull down71 + MCU_DRVconfigures drive strength during sleep mode52 + MCU_IEconfigures input enable during sleep mode41 + MCU_WPUconfigures pull up during sleep mode31 + MCU_WPDconfigures pull down during sleep mode21 + SLP_SELconfigures sleep mode selection11 + MCU_OEconfigures output enable during sleep mode01 + configures IO_MUX for GPIO3932162048 + GPIO34MCU_SELconfigures IO_MUX function122 + FUN_DRVconfigures drive strength102 + FUN_IEconfigures input enable91 + FUN_WPUconfigures pull up81 + FUN_WPDconfigures pull down71 + MCU_DRVconfigures drive strength during sleep mode52 + MCU_IEconfigures drive strength during sleep mode41 + MCU_WPUconfigures pull up during sleep mode31 + MCU_WPDconfigures pull down during sleep mode21 + SLP_SELconfigures sleep mode selection11 + MCU_OEconfigures output enable during sleep mode01 + configures IO_MUX for GPIO3432202048 + GPIO35MCU_SELconfigures IO_MUX function122 + FUN_DRVconfigures drive strength102 + FUN_IEconfigures input enable91 + FUN_WPUconfigures pull up81 + FUN_WPDconfigures pull down71 + MCU_DRVconfigures drive strength during sleep mode52 + MCU_IEconfigures input enable during sleep mode41 + MCU_WPUconfigures pull up during sleep mode31 + MCU_WPDconfigures pull down during sleep mode21 + SLP_SELconfigures sleep mode selection11 + MCU_OEconfigures output enable during sleep mode01 + configures IO_MUX for GPIO3532242048 + GPIO32MCU_SELconfigures IO_MUX function122 + FUN_DRVconfigures drive strength102 + FUN_IEconfigures input enable91 + FUN_WPUconfigures pull up81 + FUN_WPDconfigures pull down71 + MCU_DRVconfigures drive strength during sleep mode52 + MCU_IEconfigures input enable during sleep mode41 + MCU_WPUconfigures pull up during sleep mode31 + MCU_WPDconfigures pull down during sleep mode21 + SLP_SELconfigures sleep mode selection11 + MCU_OEconfigures output enable during sleep mode01 + configures IO_MUX for GPIO3232282048 + GPIO33MCU_SELconfigures IO_MUX function122 + FUN_DRVconfigures drive strength102 + FUN_IEconfigures input enable91 + FUN_WPUconfigures pull up81 + FUN_WPDconfigures pull down71 + MCU_DRVconfigures drive strength during sleep mode52 + MCU_IEconfigures input enable during sleep mode41 + MCU_WPUconfigures pull up during sleep mode31 + MCU_WPDconfigures pull down during sleep mode21 + SLP_SELconfigures sleep mode selection11 + MCU_OEconfigures output enable during sleep mode01 + configures IO_MUX for GPIO3332322048 + GPIO25MCU_SELconfigures IO_MUX function122 + FUN_DRVconfigures drive strength102 + FUN_IEconfigures input enable91 + FUN_WPUconfigures pull up81 + FUN_WPDconfigures pull down71 + MCU_DRVconfigures drive strength during sleep mode52 + MCU_IEconfigures input enable during sleep mode41 + MCU_WPUconfigures pull up during sleep mode31 + MCU_WPDconfigures pull down during sleep mode21 + SLP_SELconfigures sleep mode selection11 + MCU_OEconfigures output enable during sleep mode01 + configures IO_MUX for GPIO2532362048 + GPIO26MCU_SELconfigures IO_MUX function122 + FUN_DRVconfigures drive strength102 + FUN_IEconfigures input enable91 + FUN_WPUconfigures pull up81 + FUN_WPDconfigures pull down71 + MCU_DRVconfigures drive strength during sleep mode52 + MCU_IEconfigures input enable during sleep mode41 + MCU_WPUconfigures pull up during sleep mode31 + MCU_WPDconfigures pull down during sleep mode21 + SLP_SELconfigures sleep mode selection11 + MCU_OEconfigures output enable during sleep mode01 + configures IO_MUX for GPIO2632402048 + GPIO27MCU_SELconfigures IO_MUX function122 + FUN_DRVconfigures drive strength102 + FUN_IEconfigures input enable91 + FUN_WPUconfigures pull up81 + FUN_WPDconfigures pull down71 + MCU_DRVconfigures drive strength during sleep mode52 + MCU_IEconfigures input enable during sleep mode41 + MCU_WPUconfigures pull up during sleep mode31 + MCU_WPDconfigures pull down during sleep mode21 + SLP_SELconfigures sleep mode selection11 + MCU_OEconfigures output enable during sleep mode01 + configures IO_MUX for GPIO2732442560 + MTMSMCU_SELconfigures IO_MUX function122 + FUN_DRVconfigures drive strength102 + FUN_IEconfigures input enable91 + FUN_WPUconfigures pull up81 + FUN_WPDconfigures pull down71 + MCU_DRVconfigures drive strength during sleep mode52 + MCU_IEconfigures input enable during sleep mode41 + MCU_WPUconfigures pull up during sleep mode31 + MCU_WPDconfigures pull down during sleep mode21 + SLP_SELconfigures sleep mode selection11 + MCU_OEconfigures output enable during sleep mode01 + configures IO_MUX for MTMS32482560 + MTDIMCU_SELconfigures IO_MUX function122 + FUN_DRVconfigures drive strength102 + FUN_IEconfigures input enable91 + FUN_WPUconfigures pull up81 + FUN_WPDconfigures pull down71 + MCU_DRVconfigures drive strength during sleep mode52 + MCU_IEconfigures input enable during sleep mode41 + MCU_WPUconfigures pull up during sleep mode31 + MCU_WPDconfigures pull down during sleep mode21 + SLP_SELconfigures sleep mode selection11 + MCU_OEconfigures output enable during sleep mode01 + configures IO_MUX for MTDI32522688 + MTCKMCU_SELconfigures IO_MUX function122 + FUN_DRVconfigures drive strength102 + FUN_IEconfigures input enable91 + FUN_WPUconfigures pull up81 + FUN_WPDconfigures pull down71 + MCU_DRVconfigures drive strength during sleep mode52 + MCU_IEconfigures input enable during sleep mode41 + MCU_WPUconfigures pull up during sleep mode31 + MCU_WPDconfigures pull down during sleep mode21 + SLP_SELconfigures sleep mode selection11 + MCU_OEconfigures output enable during sleep mode01 + configures IO_MUX for MTCK32562560 + MTDOMCU_SELconfigures IO_MUX function122 + FUN_DRVconfigures drive strength102 + FUN_IEconfigures input enable91 + FUN_WPUconfigures pull up81 + FUN_WPDconfigures pull down71 + MCU_DRVconfigures drive strength during sleep mode52 + MCU_IEconfigures input enable during sleep mode41 + MCU_WPUconfigures pull up during sleep mode31 + MCU_WPDconfigures pull down during sleep mode21 + SLP_SELconfigures sleep mode selection11 + MCU_OEconfigures output enable during sleep mode01 + configures IO_MUX for MTDO32602816 + GPIO2MCU_SELconfigures IO_MUX function122 + FUN_DRVconfigures drive strength102 + FUN_IEconfigures input enable91 + FUN_WPUconfigures pull up81 + FUN_WPDconfigures pull down71 + MCU_DRVconfigures drive strength during sleep mode52 + MCU_IEconfigures input enable during sleep mode41 + MCU_WPUconfigures pull up during sleep mode31 + MCU_WPDconfigures pull down during sleep mode21 + SLP_SELconfigures sleep mode selection11 + MCU_OEconfigures output enable during sleep mode01 + configures IO_MUX for GPIO232642688 + GPIO0MCU_SELconfigures IO_MUX function122 + FUN_DRVconfigures drive strength102 + FUN_IEconfigures input enable91 + FUN_WPUconfigures pull up81 + FUN_WPDconfigures pull down71 + MCU_DRVconfigures drive strength during sleep mode52 + MCU_IEconfigures input enable during sleep mode41 + MCU_WPUconfigures pull up during sleep mode31 + MCU_WPDconfigures pull down during sleep mode21 + SLP_SELconfigures sleep mode selection11 + MCU_OEconfigures output enable during sleep mode01 + configures IO_MUX for GPIO032682816 + GPIO4MCU_SELconfigures IO_MUX function122 + FUN_DRVconfigures drive strength102 + FUN_IEconfigures input enable91 + FUN_WPUconfigures pull up81 + FUN_WPDconfigures pull down71 + MCU_DRVconfigures drive strength during sleep mode52 + MCU_IEconfigures input enable during sleep mode41 + MCU_WPUconfigures pull up during sleep mode31 + MCU_WPDconfigures pull down during sleep mode21 + SLP_SELconfigures sleep mode selection11 + MCU_OEconfigures output enable during sleep mode01 + configures IO_MUX for GPIO432722688 + GPIO16MCU_SELconfigures IO_MUX function122 + FUN_DRVconfigures drive strength102 + FUN_IEconfigures input enable91 + FUN_WPUconfigures pull up81 + FUN_WPDconfigures pull down71 + MCU_DRVconfigures drive strength during sleep mode52 + MCU_IEconfigures input enable during sleep mode41 + MCU_WPUconfigures pull up during sleep mode31 + MCU_WPDconfigures pull down during sleep mode21 + SLP_SELconfigures sleep mode selection11 + MCU_OEconfigures output enable during sleep mode01 + configures IO_MUX for GPIO1632762560 + GPIO17MCU_SELconfigures IO_MUX function122 + FUN_DRVconfigures drive strength102 + FUN_IEconfigures input enable91 + FUN_WPUconfigures pull up81 + FUN_WPDconfigures pull down71 + MCU_DRVconfigures drive strength during sleep mode52 + MCU_IEconfigures input enable during sleep mode41 + MCU_WPUconfigures pull up during sleep mode31 + MCU_WPDconfigures pull down during sleep mode21 + SLP_SELconfigures sleep mode selection11 + MCU_OEconfigures output enable during sleep mode01 + configures IO_MUX for GPIO1732802560 + SD_DATA2MCU_SELconfigures IO_MUX function122 + FUN_DRVconfigures drive strength102 + FUN_IEconfigures input enable91 + FUN_WPUconfigures pull up81 + FUN_WPDconfigures pull down71 + MCU_DRVconfigures drive strength during sleep mode52 + MCU_IEconfigures input enable during sleep mode41 + MCU_WPUconfigures pull up during sleep mode31 + MCU_WPDconfigures pull down during sleep mode21 + SLP_SELconfigures sleep mode selection11 + MCU_OEconfigures output enable during sleep mode01 + configures IO_MUX for SD_DATA232842816 + SD_DATA3MCU_SELconfigures IO_MUX function122 + FUN_DRVconfigures drive strength102 + FUN_IEconfigures input enable91 + FUN_WPUconfigures pull up81 + FUN_WPDconfigures pull down71 + MCU_DRVconfigures drive strength during sleep mode52 + MCU_IEconfigures input enable during sleep mode41 + MCU_WPUconfigures pull up during sleep mode31 + MCU_WPDconfigures pull down during sleep mode21 + SLP_SELconfigures sleep mode selection11 + MCU_OEconfigures output enable during sleep mode01 + configures IO_MUX for SD_DATA332882816 + SD_CMDMCU_SELconfigures IO_MUX function122 + FUN_DRVconfigures drive strength102 + FUN_IEconfigures input enable91 + FUN_WPUconfigures pull up81 + FUN_WPDconfigures pull down71 + MCU_DRVconfigures drive strength during sleep mode52 + MCU_IEconfigures input enable during sleep mode41 + MCU_WPUconfigures pull up during sleep mode31 + MCU_WPDconfigures pull down during sleep mode21 + SLP_SELconfigures sleep mode selection11 + MCU_OEconfigures output enable during sleep mode01 + configures IO_MUX for SD_CMD32926912 + SD_CLKMCU_SELconfigures IO_MUX function122 + FUN_DRVconfigures drive strength102 + FUN_IEconfigures input enable91 + FUN_WPUconfigures pull up81 + FUN_WPDconfigures pull down71 + MCU_DRVconfigures drive strength during sleep mode52 + MCU_IEconfigures input enable during sleep mode41 + MCU_WPUconfigures pull up during sleep mode31 + MCU_WPDconfigures pull down during sleep mode21 + SLP_SELconfigures sleep mode selection11 + MCU_OEconfigures output enable during sleep mode01 + configures IO_MUX for SD_CLK32965888 + SD_DATA0MCU_SELconfigures IO_MUX function122 + FUN_DRVconfigures drive strength102 + FUN_IEconfigures input enable91 + FUN_WPUconfigures pull up81 + FUN_WPDconfigures pull down71 + MCU_DRVconfigures drive strength during sleep mode52 + MCU_IEconfigures input enable during sleep mode41 + MCU_WPUconfigures pull up during sleep mode31 + MCU_WPDconfigures pull down during sleep mode21 + SLP_SELconfigures sleep mode selection11 + MCU_OEconfigures output enable during sleep mode01 + configures IO_MUX for SD_DATA0321006912 + SD_DATA1MCU_SELconfigures IO_MUX function122 + FUN_DRVconfigures drive strength102 + FUN_IEconfigures input enable91 + FUN_WPUconfigures pull up81 + FUN_WPDconfigures pull down71 + MCU_DRVconfigures drive strength during sleep mode52 + MCU_IEconfigures input enable during sleep mode41 + MCU_WPUconfigures pull up during sleep mode31 + MCU_WPDconfigures pull down during sleep mode21 + SLP_SELconfigures sleep mode selection11 + MCU_OEconfigures output enable during sleep mode01 + configures IO_MUX for SD_DATA1321046912 + GPIO5MCU_SELconfigures IO_MUX function122 + FUN_DRVconfigures drive strength102 + FUN_IEconfigures input enable91 + FUN_WPUconfigures pull up81 + FUN_WPDconfigures pull down71 + MCU_DRVconfigures drive strength during sleep mode52 + MCU_IEconfigures input enable during sleep mode41 + MCU_WPUconfigures pull up during sleep mode31 + MCU_WPDconfigures pull down during sleep mode21 + SLP_SELconfigures sleep mode selection11 + MCU_OEconfigures output enable during sleep mode01 + configures IO_MUX for GPIO5321082816 + GPIO18MCU_SELconfigures IO_MUX function122 + FUN_DRVconfigures drive strength102 + FUN_IEconfigures input enable91 + FUN_WPUconfigures pull up81 + FUN_WPDconfigures pull down71 + MCU_DRVconfigures drive strength during sleep mode52 + MCU_IEconfigures input enable during sleep mode41 + MCU_WPUconfigures pull up during sleep mode31 + MCU_WPDconfigures pull down during sleep mode21 + SLP_SELconfigures sleep mode selection11 + MCU_OEconfigures output enable during sleep mode01 + configures IO_MUX for GPIO18321122560 + GPIO19MCU_SELconfigures IO_MUX function122 + FUN_DRVconfigures drive strength102 + FUN_IEconfigures input enable91 + FUN_WPUconfigures pull up81 + FUN_WPDconfigures pull down71 + MCU_DRVconfigures drive strength during sleep mode52 + MCU_IEconfigures input enable during sleep mode41 + MCU_WPUconfigures pull up during sleep mode31 + MCU_WPDconfigures pull down during sleep mode21 + SLP_SELconfigures sleep mode selection11 + MCU_OEconfigures output enable during sleep mode01 + configures IO_MUX for GPIO19321162560 + GPIO20MCU_SELconfigures IO_MUX function122 + FUN_DRVconfigures drive strength102 + FUN_IEconfigures input enable91 + FUN_WPUconfigures pull up81 + FUN_WPDconfigures pull down71 + MCU_DRVconfigures drive strength during sleep mode52 + MCU_IEconfigures input enable during sleep mode41 + MCU_WPUconfigures pull up during sleep mode31 + MCU_WPDconfigures pull down during sleep mode21 + SLP_SELconfigures sleep mode selection11 + MCU_OEconfigures output enable during sleep mode01 + configures IO_MUX for GPIO20321202560 + GPIO21MCU_SELconfigures IO_MUX function122 + FUN_DRVconfigures drive strength102 + FUN_IEconfigures input enable91 + FUN_WPUconfigures pull up81 + FUN_WPDconfigures pull down71 + MCU_DRVconfigures drive strength during sleep mode52 + MCU_IEconfigures input enable during sleep mode41 + MCU_WPUconfigures pull up during sleep mode31 + MCU_WPDconfigures pull down during sleep mode21 + SLP_SELconfigures sleep mode selection11 + MCU_OEconfigures output enable during sleep mode01 + configures IO_MUX for GPIO21321242560 + GPIO22MCU_SELconfigures IO_MUX function122 + FUN_DRVconfigures drive strength102 + FUN_IEconfigures input enable91 + FUN_WPUconfigures pull up81 + FUN_WPDconfigures pull down71 + MCU_DRVconfigures drive strength during sleep mode52 + MCU_IEconfigures input enable during sleep mode41 + MCU_WPUconfigures pull up during sleep mode31 + MCU_WPDconfigures pull down during sleep mode21 + SLP_SELconfigures sleep mode selection11 + MCU_OEconfigures output enable during sleep mode01 + configures IO_MUX for GPIO22321282560 + U0RXDMCU_SELconfigures IO_MUX function122 + FUN_DRVconfigures drive strength102 + FUN_IEconfigures input enable91 + FUN_WPUconfigures pull up81 + FUN_WPDconfigures pull down71 + MCU_DRVconfigures drive strength during sleep mode52 + MCU_IEconfigures input enable during sleep mode41 + MCU_WPUconfigures pull up during sleep mode31 + MCU_WPDconfigures pull down during sleep mode21 + SLP_SELconfigures sleep mode selection11 + MCU_OEconfigures output enable during sleep mode01 + configures IO_MUX for U0RXD321322816 + U0TXDMCU_SELconfigures IO_MUX function122 + FUN_DRVconfigures drive strength102 + FUN_IEconfigures input enable91 + FUN_WPUconfigures pull up81 + FUN_WPDconfigures pull down71 + MCU_DRVconfigures drive strength during sleep mode52 + MCU_IEconfigures input enable during sleep mode41 + MCU_WPUconfigures pull up during sleep mode31 + MCU_WPDconfigures pull down during sleep mode21 + SLP_SELconfigures sleep mode selection11 + MCU_OEconfigures output enable during sleep mode01 + configures IO_MUX for U0TXD321362560 + GPIO23MCU_SELconfigures IO_MUX function122 + FUN_DRVconfigures drive strength102 + FUN_IEconfigures input enable91 + FUN_WPUconfigures pull up81 + FUN_WPDconfigures pull down71 + MCU_DRVconfigures drive strength during sleep mode52 + MCU_IEconfigures input enable during sleep mode41 + MCU_WPUconfigures pull up during sleep mode31 + MCU_WPDconfigures pull down during sleep mode21 + SLP_SELconfigures sleep mode selection11 + MCU_OEconfigures output enable during sleep mode01 + configures IO_MUX for GPIO23321402560 + GPIO24MCU_SELconfigures IO_MUX function122 + FUN_DRVconfigures drive strength102 + FUN_IEconfigures input enable91 + FUN_WPUconfigures pull up81 + FUN_WPDconfigures pull down71 + MCU_DRVconfigures drive strength during sleep mode52 + MCU_IEconfigures input enable during sleep mode41 + MCU_WPUconfigures pull up during sleep mode31 + MCU_WPDconfigures pull down during sleep mode21 + SLP_SELconfigures sleep mode selection11 + MCU_OEconfigures output enable during sleep mode01 + configures IO_MUX for GPIO24321442048 + + + + CAN + 0x3ff6b000 + + 0 + 0x00000000 + registers + + + CAN_INTRinterrupt of can, level45 + + + I2S + 0x3ff4f000 + + 0 + 0x000005a0 + registers + + + + CONF + 0x8 + I2S_CONF + 32 + 0x00000000 + + + SIG_LOOPBACK + 18 + 1 + + + RX_MSB_RIGHT + 17 + 1 + + + TX_MSB_RIGHT + 16 + 1 + + + RX_MONO + 15 + 1 + + + TX_MONO + 14 + 1 + + + RX_SHORT_SYNC + 13 + 1 + + + TX_SHORT_SYNC + 12 + 1 + + + RX_MSB_SHIFT + 11 + 1 + + + TX_MSB_SHIFT + 10 + 1 + + + RX_RIGHT_FIRST + 9 + 1 + + + TX_RIGHT_FIRST + 8 + 1 + + + RX_SLAVE_MOD + 7 + 1 + + + TX_SLAVE_MOD + 6 + 1 + + + RX_START + 5 + 1 + + + TX_START + 4 + 1 + + + RX_FIFO_RESET + 3 + 1 + + + TX_FIFO_RESET + 2 + 1 + + + RX_RESET + 1 + 1 + + + TX_RESET + 0 + 1 + + + + + INT_RAW + 0xc + I2S_INT_RAW + 32 + 0x00000000 + + + OUT_TOTAL_EOF_INT_RAW + 16 + 1 + + + IN_DSCR_EMPTY_INT_RAW + 15 + 1 + + + OUT_DSCR_ERR_INT_RAW + 14 + 1 + + + IN_DSCR_ERR_INT_RAW + 13 + 1 + + + OUT_EOF_INT_RAW + 12 + 1 + + + OUT_DONE_INT_RAW + 11 + 1 + + + IN_ERR_EOF_INT_RAW + 10 + 1 + + + IN_SUC_EOF_INT_RAW + 9 + 1 + + + IN_DONE_INT_RAW + 8 + 1 + + + TX_HUNG_INT_RAW + 7 + 1 + + + RX_HUNG_INT_RAW + 6 + 1 + + + TX_REMPTY_INT_RAW + 5 + 1 + + + TX_WFULL_INT_RAW + 4 + 1 + + + RX_REMPTY_INT_RAW + 3 + 1 + + + RX_WFULL_INT_RAW + 2 + 1 + + + TX_PUT_DATA_INT_RAW + 1 + 1 + + + RX_TAKE_DATA_INT_RAW + 0 + 1 + + + + + INT_ST + 0x10 + I2S_INT_ST + 32 + 0x00000000 + + + OUT_TOTAL_EOF_INT_ST + 16 + 1 + + + IN_DSCR_EMPTY_INT_ST + 15 + 1 + + + OUT_DSCR_ERR_INT_ST + 14 + 1 + + + IN_DSCR_ERR_INT_ST + 13 + 1 + + + OUT_EOF_INT_ST + 12 + 1 + + + OUT_DONE_INT_ST + 11 + 1 + + + IN_ERR_EOF_INT_ST + 10 + 1 + + + IN_SUC_EOF_INT_ST + 9 + 1 + + + IN_DONE_INT_ST + 8 + 1 + + + TX_HUNG_INT_ST + 7 + 1 + + + RX_HUNG_INT_ST + 6 + 1 + + + TX_REMPTY_INT_ST + 5 + 1 + + + TX_WFULL_INT_ST + 4 + 1 + + + RX_REMPTY_INT_ST + 3 + 1 + + + RX_WFULL_INT_ST + 2 + 1 + + + TX_PUT_DATA_INT_ST + 1 + 1 + + + RX_TAKE_DATA_INT_ST + 0 + 1 + + + + + INT_ENA + 0x14 + I2S_INT_ENA + 32 + 0x00000000 + + + OUT_TOTAL_EOF_INT_ENA + 16 + 1 + + + IN_DSCR_EMPTY_INT_ENA + 15 + 1 + + + OUT_DSCR_ERR_INT_ENA + 14 + 1 + + + IN_DSCR_ERR_INT_ENA + 13 + 1 + + + OUT_EOF_INT_ENA + 12 + 1 + + + OUT_DONE_INT_ENA + 11 + 1 + + + IN_ERR_EOF_INT_ENA + 10 + 1 + + + IN_SUC_EOF_INT_ENA + 9 + 1 + + + IN_DONE_INT_ENA + 8 + 1 + + + TX_HUNG_INT_ENA + 7 + 1 + + + RX_HUNG_INT_ENA + 6 + 1 + + + TX_REMPTY_INT_ENA + 5 + 1 + + + TX_WFULL_INT_ENA + 4 + 1 + + + RX_REMPTY_INT_ENA + 3 + 1 + + + RX_WFULL_INT_ENA + 2 + 1 + + + TX_PUT_DATA_INT_ENA + 1 + 1 + + + RX_TAKE_DATA_INT_ENA + 0 + 1 + + + + + INT_CLR + 0x18 + I2S_INT_CLR + 32 + 0x00000000 + + + OUT_TOTAL_EOF_INT_CLR + 16 + 1 + + + IN_DSCR_EMPTY_INT_CLR + 15 + 1 + + + OUT_DSCR_ERR_INT_CLR + 14 + 1 + + + IN_DSCR_ERR_INT_CLR + 13 + 1 + + + OUT_EOF_INT_CLR + 12 + 1 + + + OUT_DONE_INT_CLR + 11 + 1 + + + IN_ERR_EOF_INT_CLR + 10 + 1 + + + IN_SUC_EOF_INT_CLR + 9 + 1 + + + IN_DONE_INT_CLR + 8 + 1 + + + TX_HUNG_INT_CLR + 7 + 1 + + + RX_HUNG_INT_CLR + 6 + 1 + + + TX_REMPTY_INT_CLR + 5 + 1 + + + TX_WFULL_INT_CLR + 4 + 1 + + + RX_REMPTY_INT_CLR + 3 + 1 + + + RX_WFULL_INT_CLR + 2 + 1 + + + PUT_DATA_INT_CLR + 1 + 1 + + + TAKE_DATA_INT_CLR + 0 + 1 + + + + + TIMING + 0x1c + I2S_TIMING + 32 + 0x00000000 + + + TX_BCK_IN_INV + 24 + 1 + + + DATA_ENABLE_DELAY + 22 + 2 + + + RX_DSYNC_SW + 21 + 1 + + + TX_DSYNC_SW + 20 + 1 + + + RX_BCK_OUT_DELAY + 18 + 2 + + + RX_WS_OUT_DELAY + 16 + 2 + + + TX_SD_OUT_DELAY + 14 + 2 + + + TX_WS_OUT_DELAY + 12 + 2 + + + TX_BCK_OUT_DELAY + 10 + 2 + + + RX_SD_IN_DELAY + 8 + 2 + + + RX_WS_IN_DELAY + 6 + 2 + + + RX_BCK_IN_DELAY + 4 + 2 + + + TX_WS_IN_DELAY + 2 + 2 + + + TX_BCK_IN_DELAY + 0 + 2 + + + + + FIFO_CONF + 0x20 + I2S_FIFO_CONF + 32 + 0x00000000 + + + RX_FIFO_MOD_FORCE_EN + 20 + 1 + + + TX_FIFO_MOD_FORCE_EN + 19 + 1 + + + RX_FIFO_MOD + 16 + 3 + + + TX_FIFO_MOD + 13 + 3 + + + DSCR_EN + 12 + 1 + + + TX_DATA_NUM + 6 + 6 + + + RX_DATA_NUM + 0 + 6 + + + + + RXEOF_NUM + 0x24 + I2S_RXEOF_NUM + 32 + 0x00000000 + + + RX_EOF_NUM + 0 + 32 + + + + + CONF_SIGLE_DATA + 0x28 + I2S_CONF_SIGLE_DATA + 32 + 0x00000000 + + + SIGLE_DATA + 0 + 32 + + + + + CONF_CHAN + 0x2c + I2S_CONF_CHAN + 32 + 0x00000000 + + + RX_CHAN_MOD + 3 + 2 + + + TX_CHAN_MOD + 0 + 3 + + + + + OUT_LINK + 0x30 + I2S_OUT_LINK + 32 + 0x00000000 + + + OUTLINK_PARK + 31 + 1 + + + OUTLINK_RESTART + 30 + 1 + + + OUTLINK_START + 29 + 1 + + + OUTLINK_STOP + 28 + 1 + + + OUTLINK_ADDR + 0 + 20 + + + + + IN_LINK + 0x34 + I2S_IN_LINK + 32 + 0x00000000 + + + INLINK_PARK + 31 + 1 + + + INLINK_RESTART + 30 + 1 + + + INLINK_START + 29 + 1 + + + INLINK_STOP + 28 + 1 + + + INLINK_ADDR + 0 + 20 + + + + + OUT_EOF_DES_ADDR + 0x38 + I2S_OUT_EOF_DES_ADDR + 32 + 0x00000000 + + + OUT_EOF_DES_ADDR + 0 + 32 + + + + + IN_EOF_DES_ADDR + 0x3c + I2S_IN_EOF_DES_ADDR + 32 + 0x00000000 + + + IN_SUC_EOF_DES_ADDR + 0 + 32 + + + + + OUT_EOF_BFR_DES_ADDR + 0x40 + I2S_OUT_EOF_BFR_DES_ADDR + 32 + 0x00000000 + + + OUT_EOF_BFR_DES_ADDR + 0 + 32 + + + + + AHB_TEST + 0x44 + I2S_AHB_TEST + 32 + 0x00000000 + + + AHB_TESTADDR + 4 + 2 + + + AHB_TESTMODE + 0 + 3 + + + + + INLINK_DSCR + 0x48 + I2S_INLINK_DSCR + 32 + 0x00000000 + + + INLINK_DSCR + 0 + 32 + + + + + INLINK_DSCR_BF0 + 0x4c + I2S_INLINK_DSCR_BF0 + 32 + 0x00000000 + + + INLINK_DSCR_BF0 + 0 + 32 + + + + + INLINK_DSCR_BF1 + 0x50 + I2S_INLINK_DSCR_BF1 + 32 + 0x00000000 + + + INLINK_DSCR_BF1 + 0 + 32 + + + + + OUTLINK_DSCR + 0x54 + I2S_OUTLINK_DSCR + 32 + 0x00000000 + + + OUTLINK_DSCR + 0 + 32 + + + + + OUTLINK_DSCR_BF0 + 0x58 + I2S_OUTLINK_DSCR_BF0 + 32 + 0x00000000 + + + OUTLINK_DSCR_BF0 + 0 + 32 + + + + + OUTLINK_DSCR_BF1 + 0x5c + I2S_OUTLINK_DSCR_BF1 + 32 + 0x00000000 + + + OUTLINK_DSCR_BF1 + 0 + 32 + + + + + LC_CONF + 0x60 + I2S_LC_CONF + 32 + 0x00000000 + + + MEM_TRANS_EN + 13 + 1 + + + CHECK_OWNER + 12 + 1 + + + OUT_DATA_BURST_EN + 11 + 1 + + + INDSCR_BURST_EN + 10 + 1 + + + OUTDSCR_BURST_EN + 9 + 1 + + + OUT_EOF_MODE + 8 + 1 + + + OUT_NO_RESTART_CLR + 7 + 1 + + + OUT_AUTO_WRBACK + 6 + 1 + + + IN_LOOP_TEST + 5 + 1 + + + OUT_LOOP_TEST + 4 + 1 + + + AHBM_RST + 3 + 1 + + + AHBM_FIFO_RST + 2 + 1 + + + OUT_RST + 1 + 1 + + + IN_RST + 0 + 1 + + + + + OUTFIFO_PUSH + 0x64 + I2S_OUTFIFO_PUSH + 32 + 0x00000000 + + + OUTFIFO_PUSH + 16 + 1 + + + OUTFIFO_WDATA + 0 + 9 + + + + + INFIFO_POP + 0x68 + I2S_INFIFO_POP + 32 + 0x00000000 + + + INFIFO_POP + 16 + 1 + + + INFIFO_RDATA + 0 + 12 + + + + + LC_STATE0 + 0x6c + I2S_LC_STATE0 + 32 + 0x00000000 + + + LC_STATE0 + 0 + 32 + + + + + LC_STATE1 + 0x70 + I2S_LC_STATE1 + 32 + 0x00000000 + + + LC_STATE1 + 0 + 32 + + + + + LC_HUNG_CONF + 0x74 + I2S_LC_HUNG_CONF + 32 + 0x00000000 + + + LC_FIFO_TIMEOUT_ENA + 11 + 1 + + + LC_FIFO_TIMEOUT_SHIFT + 8 + 3 + + + LC_FIFO_TIMEOUT + 0 + 8 + + + + + CVSD_CONF0 + 0x80 + I2S_CVSD_CONF0 + 32 + 0x00000000 + + + CVSD_Y_MIN + 16 + 16 + + + CVSD_Y_MAX + 0 + 16 + + + + + CVSD_CONF1 + 0x84 + I2S_CVSD_CONF1 + 32 + 0x00000000 + + + CVSD_SIGMA_MIN + 16 + 16 + + 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ESCO_CVSD_DEC_PACK_ERR + 2 + 1 + + + ESCO_CHAN_MOD + 1 + 1 + + + ESCO_EN + 0 + 1 + + + + + SCO_CONF0 + 0x9c + I2S_SCO_CONF0 + 32 + 0x00000000 + + + CVSD_ENC_RESET + 3 + 1 + + + CVSD_ENC_START + 2 + 1 + + + SCO_NO_I2S_EN + 1 + 1 + + + SCO_WITH_I2S_EN + 0 + 1 + + + + + CONF1 + 0xa0 + I2S_CONF1 + 32 + 0x00000000 + + + TX_ZEROS_RM_EN + 9 + 1 + + + TX_STOP_EN + 8 + 1 + + + RX_PCM_BYPASS + 7 + 1 + + + RX_PCM_CONF + 4 + 3 + + + TX_PCM_BYPASS + 3 + 1 + + + TX_PCM_CONF + 0 + 3 + + + + + PD_CONF + 0xa4 + I2S_PD_CONF + 32 + 0x00000000 + + + PLC_MEM_FORCE_PU + 3 + 1 + + + PLC_MEM_FORCE_PD + 2 + 1 + + + FIFO_FORCE_PU + 1 + 1 + + + FIFO_FORCE_PD + 0 + 1 + + + + + CONF2 + 0xa8 + I2S_CONF2 + 32 + 0x00000000 + + + INTER_VALID_EN + 7 + 1 + + + EXT_ADC_START_EN + 6 + 1 + + + LCD_EN + 5 + 1 + + + DATA_ENABLE + 4 + 1 + + + DATA_ENABLE_TEST_EN + 3 + 1 + + + LCD_TX_SDX2_EN + 2 + 1 + + + LCD_TX_WRX2_EN + 1 + 1 + + + CAMERA_EN + 0 + 1 + + + + + CLKM_CONF + 0xac + I2S_CLKM_CONF + 32 + 0x00000000 + + + CLKA_ENA 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SARADC_SAR2_PATT_LEN + 19 + 4 + + + SARADC_SAR1_PATT_LEN + 15 + 4 + + + SARADC_SAR_CLK_DIV + 7 + 8 + + + SARADC_SAR_CLK_GATED + 6 + 1 + + + SARADC_SAR_SEL + 5 + 1 + + + SARADC_WORK_MODE + 3 + 2 + + + SARADC_SAR2_MUX + 2 + 1 + + + SARADC_START + 1 + 1 + + + SARADC_START_FORCE + 0 + 1 + + + + + APB_SARADC_CTRL2 + 0x14 + APB_CTRL_APB_SARADC_CTRL2 + 32 + 0x00000000 + + + SARADC_SAR2_INV + 10 + 1 + + + SARADC_SAR1_INV + 9 + 1 + + + SARADC_MAX_MEAS_NUM + 1 + 8 + + + SARADC_MEAS_NUM_LIMIT + 0 + 1 + + + + + APB_SARADC_FSM + 0x18 + APB_CTRL_APB_SARADC_FSM + 32 + 0x00000000 + + + SARADC_SAMPLE_CYCLE + 24 + 8 + + + SARADC_START_WAIT + 16 + 8 + + + SARADC_STANDBY_WAIT + 8 + 8 + + + SARADC_RSTB_WAIT + 0 + 8 + + + + + APB_SARADC_SAR1_PATT_TAB1 + 0x1c + APB_CTRL_APB_SARADC_SAR1_PATT_TAB1 + 32 + 0x00000000 + + + SARADC_SAR1_PATT_TAB1 + 0 + 32 + + + + + APB_SARADC_SAR1_PATT_TAB2 + 0x20 + APB_CTRL_APB_SARADC_SAR1_PATT_TAB2 + 32 + 0x00000000 + + + SARADC_SAR1_PATT_TAB2 + 0 + 32 + + + + + APB_SARADC_SAR1_PATT_TAB3 + 0x24 + APB_CTRL_APB_SARADC_SAR1_PATT_TAB3 + 32 + 0x00000000 + + + SARADC_SAR1_PATT_TAB3 + 0 + 32 + + + + + APB_SARADC_SAR1_PATT_TAB4 + 0x28 + APB_CTRL_APB_SARADC_SAR1_PATT_TAB4 + 32 + 0x00000000 + + + SARADC_SAR1_PATT_TAB4 + 0 + 32 + + + + + APB_SARADC_SAR2_PATT_TAB1 + 0x2c + APB_CTRL_APB_SARADC_SAR2_PATT_TAB1 + 32 + 0x00000000 + + + SARADC_SAR2_PATT_TAB1 + 0 + 32 + + + + + APB_SARADC_SAR2_PATT_TAB2 + 0x30 + APB_CTRL_APB_SARADC_SAR2_PATT_TAB2 + 32 + 0x00000000 + + + SARADC_SAR2_PATT_TAB2 + 0 + 32 + + + + + APB_SARADC_SAR2_PATT_TAB3 + 0x34 + APB_CTRL_APB_SARADC_SAR2_PATT_TAB3 + 32 + 0x00000000 + + + SARADC_SAR2_PATT_TAB3 + 0 + 32 + + + + + APB_SARADC_SAR2_PATT_TAB4 + 0x38 + APB_CTRL_APB_SARADC_SAR2_PATT_TAB4 + 32 + 0x00000000 + + + SARADC_SAR2_PATT_TAB4 + 0 + 32 + + + + + APLL_TICK_CONF + 0x3c + APB_CTRL_APLL_TICK_CONF + 32 + 0x00000000 + + + APLL_TICK_NUM + 0 + 8 + + + + + DATE + 0x7c + APB_CTRL_DATE + 32 + 0x00000000 + + + DATE + 0 + 32 + + + + + + + SYSCON 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SARADC_START + 1 + 1 + + + SARADC_START_FORCE + 0 + 1 + + + + + SARADC_CTRL2 + 0x14 + SYSCON_SARADC_CTRL2 + 32 + 0x00000000 + + + SARADC_SAR2_INV + 10 + 1 + + + SARADC_SAR1_INV + 9 + 1 + + + SARADC_MAX_MEAS_NUM + 1 + 8 + + + SARADC_MEAS_NUM_LIMIT + 0 + 1 + + + + + SARADC_FSM + 0x18 + SYSCON_SARADC_FSM + 32 + 0x00000000 + + + SARADC_SAMPLE_CYCLE + 24 + 8 + + + SARADC_START_WAIT + 16 + 8 + + + SARADC_STANDBY_WAIT + 8 + 8 + + + SARADC_RSTB_WAIT + 0 + 8 + + + + + SARADC_SAR1_PATT_TAB1 + 0x1c + SYSCON_SARADC_SAR1_PATT_TAB1 + 32 + 0x00000000 + + + SARADC_SAR1_PATT_TAB1 + 0 + 32 + + + + + SARADC_SAR1_PATT_TAB2 + 0x20 + SYSCON_SARADC_SAR1_PATT_TAB2 + 32 + 0x00000000 + + + SARADC_SAR1_PATT_TAB2 + 0 + 32 + + + + + SARADC_SAR1_PATT_TAB3 + 0x24 + SYSCON_SARADC_SAR1_PATT_TAB3 + 32 + 0x00000000 + + + SARADC_SAR1_PATT_TAB3 + 0 + 32 + + + + + SARADC_SAR1_PATT_TAB4 + 0x28 + SYSCON_SARADC_SAR1_PATT_TAB4 + 32 + 0x00000000 + + + SARADC_SAR1_PATT_TAB4 + 0 + 32 + + + + + SARADC_SAR2_PATT_TAB1 + 0x2c + SYSCON_SARADC_SAR2_PATT_TAB1 + 32 + 0x00000000 + + + SARADC_SAR2_PATT_TAB1 + 0 + 32 + + + + + SARADC_SAR2_PATT_TAB2 + 0x30 + SYSCON_SARADC_SAR2_PATT_TAB2 + 32 + 0x00000000 + + + SARADC_SAR2_PATT_TAB2 + 0 + 32 + + + + + SARADC_SAR2_PATT_TAB3 + 0x34 + SYSCON_SARADC_SAR2_PATT_TAB3 + 32 + 0x00000000 + + + SARADC_SAR2_PATT_TAB3 + 0 + 32 + + + + + SARADC_SAR2_PATT_TAB4 + 0x38 + SYSCON_SARADC_SAR2_PATT_TAB4 + 32 + 0x00000000 + + + SARADC_SAR2_PATT_TAB4 + 0 + 32 + + + + + APLL_TICK_CONF + 0x3c + SYSCON_APLL_TICK_CONF + 32 + 0x00000000 + + + APLL_TICK_NUM + 0 + 8 + + + + + DATE + 0x7c + SYSCON_DATE + 32 + 0x00000000 + + + DATE + 0 + 32 + + + + + + + FE2 + 0x3ff45000 + + 0 + 0x00000000 + registers + + + + + RTC_I2C + 0x3ff48c00 + + 0 + 0x00000160 + registers + + + + SCL_LOW_PERIOD + 0x0 + RTC_I2C_SCL_LOW_PERIOD + 32 + 0x00000000 + + + SCL_LOW_PERIOD + 0 + 19 + + + + + CTRL + 0x4 + RTC_I2C_CTRL + 32 + 0x00000000 + + + RX_LSB_FIRST + 7 + 1 + + + TX_LSB_FIRST + 6 + 1 + + + TRANS_START + 5 + 1 + + + MS_MODE + 4 + 1 + + + SCL_FORCE_OUT + 1 + 1 + + + SDA_FORCE_OUT + 0 + 1 + + + + + DEBUG_STATUS + 0x8 + RTC_I2C_DEBUG_STATUS + 32 + 0x00000000 + + + SCL_STATE + 28 + 3 + + + MAIN_STATE + 25 + 3 + + + BYTE_TRANS + 6 + 1 + + + SLAVE_ADDR_MATCH + 5 + 1 + + + BUS_BUSY + 4 + 1 + + + ARB_LOST + 3 + 1 + + + TIMED_OUT + 2 + 1 + + + SLAVE_RW + 1 + 1 + + + ACK_VAL + 0 + 1 + + + + + TIMEOUT + 0xc + RTC_I2C_TIMEOUT + 32 + 0x00000000 + + + TIMEOUT + 0 + 20 + + + + + SLAVE_ADDR + 0x10 + RTC_I2C_SLAVE_ADDR + 32 + 0x00000000 + + + SLAVE_ADDR_10BIT + 31 + 1 + + + SLAVE_ADDR + 0 + 15 + + + + + INT_RAW + 0x20 + RTC_I2C_INT_RAW + 32 + 0x00000000 + + + TIME_OUT_INT_RAW + 7 + 1 + + + TRANS_COMPLETE_INT_RAW + 6 + 1 + + + MASTER_TRANS_COMPLETE_INT_RAW + 5 + 1 + + + ARBITRATION_LOST_INT_RAW + 4 + 1 + + + SLAVE_TRANS_COMPLETE_INT_RAW + 3 + 1 + + + + + INT_CLR + 0x24 + RTC_I2C_INT_CLR + 32 + 0x00000000 + + + TIME_OUT_INT_CLR + 8 + 1 + + + TRANS_COMPLETE_INT_CLR + 7 + 1 + + + MASTER_TRANS_COMPLETE_INT_CLR + 6 + 1 + + + ARBITRATION_LOST_INT_CLR + 5 + 1 + + + SLAVE_TRANS_COMPLETE_INT_CLR + 4 + 1 + + + + + SDA_DUTY + 0x30 + RTC_I2C_SDA_DUTY + 32 + 0x00000000 + + + SDA_DUTY + 0 + 20 + + + + + SCL_HIGH_PERIOD + 0x38 + RTC_I2C_SCL_HIGH_PERIOD + 32 + 0x00000000 + + + SCL_HIGH_PERIOD + 0 + 20 + + + + + SCL_START_PERIOD + 0x40 + RTC_I2C_SCL_START_PERIOD + 32 + 0x00000000 + + + SCL_START_PERIOD + 0 + 20 + + + + + SCL_STOP_PERIOD + 0x44 + RTC_I2C_SCL_STOP_PERIOD + 32 + 0x00000000 + + + SCL_STOP_PERIOD + 0 + 20 + + + + + + + BT + 0x3ff51000 + + 0 + 0x00000000 + registers + + + + + UART + 0x3ff40000 + + + INT_RAW + 0x4 + UART_INT_RAW + 32 + 0x00000000 + + + AT_CMD_CHAR_DET_INT_RAW + 18 + 1 + + + RS485_CLASH_INT_RAW + 17 + 1 + + + RS485_FRM_ERR_INT_RAW + 16 + 1 + + + RS485_PARITY_ERR_INT_RAW + 15 + 1 + + + TX_DONE_INT_RAW + 14 + 1 + + + TX_BRK_IDLE_DONE_INT_RAW + 13 + 1 + + + TX_BRK_DONE_INT_RAW + 12 + 1 + + + GLITCH_DET_INT_RAW + 11 + 1 + + + SW_XOFF_INT_RAW + 10 + 1 + + + SW_XON_INT_RAW + 9 + 1 + + + RXFIFO_TOUT_INT_RAW + 8 + 1 + + + BRK_DET_INT_RAW + 7 + 1 + + + CTS_CHG_INT_RAW + 6 + 1 + + + DSR_CHG_INT_RAW + 5 + 1 + + + RXFIFO_OVF_INT_RAW + 4 + 1 + + + FRM_ERR_INT_RAW + 3 + 1 + + + PARITY_ERR_INT_RAW + 2 + 1 + + + TXFIFO_EMPTY_INT_RAW + 1 + 1 + + + RXFIFO_FULL_INT_RAW + 0 + 1 + + + + + INT_ST + 0x8 + UART_INT_ST + 32 + 0x00000000 + + + AT_CMD_CHAR_DET_INT_ST + 18 + 1 + + + RS485_CLASH_INT_ST + 17 + 1 + + + RS485_FRM_ERR_INT_ST + 16 + 1 + + + RS485_PARITY_ERR_INT_ST + 15 + 1 + + + TX_DONE_INT_ST + 14 + 1 + + + TX_BRK_IDLE_DONE_INT_ST + 13 + 1 + + + TX_BRK_DONE_INT_ST + 12 + 1 + + + GLITCH_DET_INT_ST + 11 + 1 + + + SW_XOFF_INT_ST + 10 + 1 + + + SW_XON_INT_ST + 9 + 1 + + + RXFIFO_TOUT_INT_ST + 8 + 1 + + + BRK_DET_INT_ST + 7 + 1 + + + CTS_CHG_INT_ST + 6 + 1 + + + DSR_CHG_INT_ST + 5 + 1 + + + RXFIFO_OVF_INT_ST + 4 + 1 + + + FRM_ERR_INT_ST + 3 + 1 + + + PARITY_ERR_INT_ST + 2 + 1 + + + TXFIFO_EMPTY_INT_ST + 1 + 1 + + + RXFIFO_FULL_INT_ST + 0 + 1 + + + + + INT_ENA + 0xc + UART_INT_ENA + 32 + 0x00000000 + + + AT_CMD_CHAR_DET_INT_ENA + 18 + 1 + + + RS485_CLASH_INT_ENA + 17 + 1 + + + RS485_FRM_ERR_INT_ENA + 16 + 1 + + + RS485_PARITY_ERR_INT_ENA + 15 + 1 + + + TX_DONE_INT_ENA + 14 + 1 + + + TX_BRK_IDLE_DONE_INT_ENA + 13 + 1 + + + TX_BRK_DONE_INT_ENA + 12 + 1 + + + GLITCH_DET_INT_ENA + 11 + 1 + + + SW_XOFF_INT_ENA + 10 + 1 + + + SW_XON_INT_ENA + 9 + 1 + + + RXFIFO_TOUT_INT_ENA + 8 + 1 + + + BRK_DET_INT_ENA + 7 + 1 + + + CTS_CHG_INT_ENA + 6 + 1 + + + DSR_CHG_INT_ENA + 5 + 1 + + + RXFIFO_OVF_INT_ENA + 4 + 1 + + + FRM_ERR_INT_ENA + 3 + 1 + + + PARITY_ERR_INT_ENA + 2 + 1 + + + TXFIFO_EMPTY_INT_ENA + 1 + 1 + + + RXFIFO_FULL_INT_ENA + 0 + 1 + + + + + INT_CLR + 0x10 + UART_INT_CLR + 32 + 0x00000000 + + + AT_CMD_CHAR_DET_INT_CLR + 18 + 1 + + + RS485_CLASH_INT_CLR + 17 + 1 + + + RS485_FRM_ERR_INT_CLR + 16 + 1 + + + RS485_PARITY_ERR_INT_CLR + 15 + 1 + + + TX_DONE_INT_CLR + 14 + 1 + + + TX_BRK_IDLE_DONE_INT_CLR + 13 + 1 + + + TX_BRK_DONE_INT_CLR + 12 + 1 + + + GLITCH_DET_INT_CLR + 11 + 1 + + + SW_XOFF_INT_CLR + 10 + 1 + + + SW_XON_INT_CLR + 9 + 1 + + + RXFIFO_TOUT_INT_CLR + 8 + 1 + + + BRK_DET_INT_CLR + 7 + 1 + + + CTS_CHG_INT_CLR + 6 + 1 + + + DSR_CHG_INT_CLR + 5 + 1 + + + RXFIFO_OVF_INT_CLR + 4 + 1 + + + FRM_ERR_INT_CLR + 3 + 1 + + + PARITY_ERR_INT_CLR + 2 + 1 + + + TXFIFO_EMPTY_INT_CLR + 1 + 1 + + + RXFIFO_FULL_INT_CLR + 0 + 1 + + + + + CLKDIV + 0x14 + UART_CLKDIV + 32 + 0x00000000 + + + CLKDIV_FRAG + 20 + 4 + + + CLKDIV + 0 + 20 + + + + + AUTOBAUD + 0x18 + UART_AUTOBAUD + 32 + 0x00000000 + + + GLITCH_FILT + 8 + 8 + + + AUTOBAUD_EN + 0 + 1 + + + + + STATUS + 0x1c + UART_STATUS + 32 + 0x00000000 + + + TXD + 31 + 1 + + + RTSN + 30 + 1 + + + DTRN + 29 + 1 + + + ST_UTX_OUT + 24 + 4 + UART_ST_UTX_OUTread-writeTX_IDLETX_IDLE0TX_STRTTX_STRT1TX_DAT0TX_DAT02TX_DAT1TX_DAT13TX_DAT2TX_DAT24TX_DAT3TX_DAT35TX_DAT4TX_DAT46TX_DAT5TX_DAT57TX_DAT6TX_DAT68TX_DAT7TX_DAT79TX_PRTYTX_PRTY10TX_STP1TX_STP111TX_STP2TX_STP212TX_DL1TX_DL114 + + + TXFIFO_CNT + 16 + 8 + + + RXD + 15 + 1 + + + CTSN + 14 + 1 + + + DSRN + 13 + 1 + + + ST_URX_OUT + 8 + 4 + UART_ST_URX_OUTread-writeRX_IDLERX_IDLE0RX_STRTRX_STRT1RX_DAT0RX_DAT02RX_DAT1RX_DAT13RX_DAT2RX_DAT24RX_DAT3RX_DAT35RX_DAT4RX_DAT46RX_DAT5RX_DAT57RX_DAT6RX_DAT68RX_DAT7RX_DAT79RX_PRTYRX_PRTY10RX_STP1RX_STP111RX_STP2RX_STP212RX_DL1RX_DL113 + + + RXFIFO_CNT + 0 + 8 + + + + + CONF0 + 0x20 + UART_CONF0 + 32 + 0x00000000 + + + TICK_REF_ALWAYS_ON + 27 + 1 + + + ERR_WR_MASK + 26 + 1 + + + CLK_EN + 25 + 1 + + + DTR_INV + 24 + 1 + + + RTS_INV + 23 + 1 + + + TXD_INV + 22 + 1 + + + DSR_INV + 21 + 1 + + + CTS_INV + 20 + 1 + + + RXD_INV + 19 + 1 + + + TXFIFO_RST + 18 + 1 + + + RXFIFO_RST + 17 + 1 + + + IRDA_EN + 16 + 1 + + + TX_FLOW_EN + 15 + 1 + + + LOOPBACK + 14 + 1 + + + IRDA_RX_INV + 13 + 1 + + + IRDA_TX_INV + 12 + 1 + + + IRDA_WCTL + 11 + 1 + + + IRDA_TX_EN + 10 + 1 + + + IRDA_DPLX + 9 + 1 + + + TXD_BRK + 8 + 1 + + + SW_DTR + 7 + 1 + + + SW_RTS + 6 + 1 + + + STOP_BIT_NUM + 4 + 2 + UART_STOP_BIT_NUMread-writeSTOP_BITS_11 stop bits1STOP_BITS_1p51.5 stop bits2STOP_BITS_22 stop bits3 + + + BIT_NUM + 2 + 2 + UART_BIT_NUMread-writeDATA_BITS_55 data bits0DATA_BITS_66 data bits1DATA_BITS_77 data bits2DATA_BITS_88 data bits3 + + + PARITY_EN + 1 + 1 + + + PARITY + 0 + 1 + + + + + CONF1 + 0x24 + UART_CONF1 + 32 + 0x00000000 + + + RX_TOUT_EN + 31 + 1 + + + RX_TOUT_THRHD + 24 + 7 + + + RX_FLOW_EN + 23 + 1 + + + RX_FLOW_THRHD + 16 + 7 + + + TXFIFO_EMPTY_THRHD + 8 + 7 + + + RXFIFO_FULL_THRHD + 0 + 7 + + + + + LOWPULSE + 0x28 + UART_LOWPULSE + 32 + 0x00000000 + + + LOWPULSE_MIN_CNT + 0 + 20 + + + + + HIGHPULSE + 0x2c + UART_HIGHPULSE + 32 + 0x00000000 + + + HIGHPULSE_MIN_CNT + 0 + 20 + + + + + RXD_CNT + 0x30 + UART_RXD_CNT + 32 + 0x00000000 + + + RXD_EDGE_CNT + 0 + 10 + + + + + FLOW_CONF + 0x34 + UART_FLOW_CONF + 32 + 0x00000000 + + + SEND_XOFF + 5 + 1 + + + SEND_XON + 4 + 1 + + + FORCE_XOFF + 3 + 1 + + + FORCE_XON + 2 + 1 + + + XONOFF_DEL + 1 + 1 + + + SW_FLOW_CON_EN + 0 + 1 + + + + + SLEEP_CONF + 0x38 + UART_SLEEP_CONF + 32 + 0x00000000 + + + ACTIVE_THRESHOLD + 0 + 10 + + + + + SWFC_CONF + 0x3c + UART_SWFC_CONF + 32 + 0x00000000 + + + XOFF_CHAR + 24 + 8 + + + XON_CHAR + 16 + 8 + + + XOFF_THRESHOLD + 8 + 8 + + + XON_THRESHOLD + 0 + 8 + + + + + IDLE_CONF + 0x40 + UART_IDLE_CONF + 32 + 0x00000000 + + + TX_BRK_NUM + 20 + 8 + + + TX_IDLE_NUM + 10 + 10 + + + RX_IDLE_THRHD + 0 + 10 + + + + + RS485_CONF + 0x44 + UART_RS485_CONF + 32 + 0x00000000 + + + RS485_TX_DLY_NUM + 6 + 4 + + + RS485_RX_DLY_NUM + 5 + 1 + + + RS485RXBY_TX_EN + 4 + 1 + + + RS485TX_RX_EN + 3 + 1 + + + DL1_EN + 2 + 1 + + + DL0_EN + 1 + 1 + + + RS485_EN + 0 + 1 + + + + + AT_CMD_PRECNT + 0x48 + UART_AT_CMD_PRECNT + 32 + 0x00000000 + + + PRE_IDLE_NUM + 0 + 24 + + + + + AT_CMD_POSTCNT + 0x4c + UART_AT_CMD_POSTCNT + 32 + 0x00000000 + + + POST_IDLE_NUM + 0 + 24 + + + + + AT_CMD_GAPTOUT + 0x50 + UART_AT_CMD_GAPTOUT + 32 + 0x00000000 + + + RX_GAP_TOUT + 0 + 24 + + + + + AT_CMD_CHAR + 0x54 + UART_AT_CMD_CHAR + 32 + 0x00000000 + + + CHAR_NUM + 8 + 8 + + + AT_CMD_CHAR + 0 + 8 + + + + + MEM_CONF + 0x58 + UART_MEM_CONF + 32 + 0x00000000 + + + TX_MEM_EMPTY_THRHD + 28 + 3 + + + RX_MEM_FULL_THRHD + 25 + 3 + + + XOFF_THRESHOLD_H2 + 23 + 2 + + + XON_THRESHOLD_H2 + 21 + 2 + + + RX_TOUT_THRHD_H3 + 18 + 3 + + + RX_FLOW_THRHD_H3 + 15 + 3 + + + TX_SIZE + 7 + 4 + + + RX_SIZE + 3 + 4 + + + MEM_PD + 0 + 1 + + + + + MEM_TX_STATUS + 0x5c + UART_MEM_TX_STATUS + 32 + 0x00000000 + + + MEM_TX_STATUS + 0 + 24 + + + + + MEM_RX_STATUS + 0x60 + UART_MEM_RX_STATUS + 32 + 0x00000000 + + + MEM_RX_STATUS + 0 + 24 + + + MEM_RX_RD_ADDR + 2 + 11 + + + MEM_RX_WR_ADDR + 13 + 11 + + + + + MEM_CNT_STATUS + 0x64 + UART_MEM_CNT_STATUS + 32 + 0x00000000 + + + TX_MEM_CNT + 3 + 3 + + + RX_MEM_CNT + 0 + 3 + + + + + POSPULSE + 0x68 + UART_POSPULSE + 32 + 0x00000000 + + + POSEDGE_MIN_CNT + 0 + 20 + + + + + NEGPULSE + 0x6c + UART_NEGPULSE + 32 + 0x00000000 + + + NEGEDGE_MIN_CNT + 0 + 20 + + + + + DATE + 0x78 + UART_DATE + 32 + 0x00000000 + + + DATE + 0 + 32 + + + + + ID + 0x7c + UART_ID + 32 + 0x00000000 + + + ID + 0 + 32 + + + + TX_FIFODATATX FIFO Data08 + UART_TX_FIFO5376573448write-only + RX_FIFODATATX FIFO Data08 + UART_RX_FIFO08read-only + + 01024UART registers5376573444TX FIFOUART0_INTRinterrupt of UART0, level34 + UART1_INTRinterrupt of UART1, level35 + UART2_INTRinterrupt of UART2, level36 + SPI0_INTRinterrupt of SPI0, level, SPI0 is for Cache Access, do not use this28 + SPI1_INTRinterrupt of SPI1, level, SPI1 is for flash read/write, do not use this29 + SPI2_INTRinterrupt of SPI2, level30 + SPI3_INTRinterrupt of SPI3, level31 + + + LEDC + 0x3ff59000 + + 0 + 0x00000cc0 + registers + + + + HSCH0_CONF0 + 0x0 + LEDC_HSCH0_CONF0 + 32 + 0x00000000 + + + CLK_EN + 31 + 1 + + + IDLE_LV_HSCH0 + 3 + 1 + + + SIG_OUT_EN_HSCH0 + 2 + 1 + + + TIMER_SEL_HSCH0 + 0 + 2 + + + + + HSCH0_HPOINT + 0x4 + LEDC_HSCH0_HPOINT + 32 + 0x00000000 + + + HPOINT_HSCH0 + 0 + 20 + + + + + HSCH0_DUTY + 0x8 + LEDC_HSCH0_DUTY + 32 + 0x00000000 + + + DUTY_HSCH0 + 0 + 25 + + + + + HSCH0_CONF1 + 0xc + LEDC_HSCH0_CONF1 + 32 + 0x00000000 + + + DUTY_START_HSCH0 + 31 + 1 + + + DUTY_INC_HSCH0 + 30 + 1 + + + DUTY_NUM_HSCH0 + 20 + 10 + + + DUTY_CYCLE_HSCH0 + 10 + 10 + + + DUTY_SCALE_HSCH0 + 0 + 10 + + + + + HSCH0_DUTY_R + 0x10 + LEDC_HSCH0_DUTY_R + 32 + 0x00000000 + + + DUTY_HSCH0 + 0 + 25 + + + + + HSCH1_CONF0 + 0x14 + LEDC_HSCH1_CONF0 + 32 + 0x00000000 + + + IDLE_LV_HSCH1 + 3 + 1 + + + SIG_OUT_EN_HSCH1 + 2 + 1 + + + TIMER_SEL_HSCH1 + 0 + 2 + + + + + HSCH1_HPOINT + 0x18 + LEDC_HSCH1_HPOINT + 32 + 0x00000000 + + + HPOINT_HSCH1 + 0 + 20 + + + + + HSCH1_DUTY + 0x1c + LEDC_HSCH1_DUTY + 32 + 0x00000000 + + + DUTY_HSCH1 + 0 + 25 + + + + + HSCH1_CONF1 + 0x20 + LEDC_HSCH1_CONF1 + 32 + 0x00000000 + + + DUTY_START_HSCH1 + 31 + 1 + + + DUTY_INC_HSCH1 + 30 + 1 + + + DUTY_NUM_HSCH1 + 20 + 10 + + + DUTY_CYCLE_HSCH1 + 10 + 10 + + + DUTY_SCALE_HSCH1 + 0 + 10 + + + + + HSCH1_DUTY_R + 0x24 + LEDC_HSCH1_DUTY_R + 32 + 0x00000000 + + + DUTY_HSCH1 + 0 + 25 + + + + + HSCH2_CONF0 + 0x28 + LEDC_HSCH2_CONF0 + 32 + 0x00000000 + + + IDLE_LV_HSCH2 + 3 + 1 + + + SIG_OUT_EN_HSCH2 + 2 + 1 + + + TIMER_SEL_HSCH2 + 0 + 2 + + + + + HSCH2_HPOINT + 0x2c + LEDC_HSCH2_HPOINT + 32 + 0x00000000 + + + HPOINT_HSCH2 + 0 + 20 + + + + + HSCH2_DUTY + 0x30 + LEDC_HSCH2_DUTY + 32 + 0x00000000 + + + DUTY_HSCH2 + 0 + 25 + + + + + HSCH2_CONF1 + 0x34 + LEDC_HSCH2_CONF1 + 32 + 0x00000000 + + + DUTY_START_HSCH2 + 31 + 1 + + + DUTY_INC_HSCH2 + 30 + 1 + + + DUTY_NUM_HSCH2 + 20 + 10 + + + DUTY_CYCLE_HSCH2 + 10 + 10 + + + DUTY_SCALE_HSCH2 + 0 + 10 + + + + + HSCH2_DUTY_R + 0x38 + LEDC_HSCH2_DUTY_R + 32 + 0x00000000 + + + DUTY_HSCH2 + 0 + 25 + + + + + HSCH3_CONF0 + 0x3c + LEDC_HSCH3_CONF0 + 32 + 0x00000000 + + + IDLE_LV_HSCH3 + 3 + 1 + + + SIG_OUT_EN_HSCH3 + 2 + 1 + + + TIMER_SEL_HSCH3 + 0 + 2 + + + + + HSCH3_HPOINT + 0x40 + LEDC_HSCH3_HPOINT + 32 + 0x00000000 + + + HPOINT_HSCH3 + 0 + 20 + + + + + HSCH3_DUTY + 0x44 + LEDC_HSCH3_DUTY + 32 + 0x00000000 + + + DUTY_HSCH3 + 0 + 25 + + + + + HSCH3_CONF1 + 0x48 + LEDC_HSCH3_CONF1 + 32 + 0x00000000 + + + DUTY_START_HSCH3 + 31 + 1 + + + DUTY_INC_HSCH3 + 30 + 1 + + + DUTY_NUM_HSCH3 + 20 + 10 + + + DUTY_CYCLE_HSCH3 + 10 + 10 + + + DUTY_SCALE_HSCH3 + 0 + 10 + + + + + HSCH3_DUTY_R + 0x4c + LEDC_HSCH3_DUTY_R + 32 + 0x00000000 + + + DUTY_HSCH3 + 0 + 25 + + + + + HSCH4_CONF0 + 0x50 + LEDC_HSCH4_CONF0 + 32 + 0x00000000 + + + IDLE_LV_HSCH4 + 3 + 1 + + + SIG_OUT_EN_HSCH4 + 2 + 1 + + + TIMER_SEL_HSCH4 + 0 + 2 + + + + + HSCH4_HPOINT + 0x54 + LEDC_HSCH4_HPOINT + 32 + 0x00000000 + + + HPOINT_HSCH4 + 0 + 20 + + + + + HSCH4_DUTY + 0x58 + LEDC_HSCH4_DUTY + 32 + 0x00000000 + + + DUTY_HSCH4 + 0 + 25 + + + + + HSCH4_CONF1 + 0x5c + LEDC_HSCH4_CONF1 + 32 + 0x00000000 + + + DUTY_START_HSCH4 + 31 + 1 + + + DUTY_INC_HSCH4 + 30 + 1 + + + DUTY_NUM_HSCH4 + 20 + 10 + + + DUTY_CYCLE_HSCH4 + 10 + 10 + + + DUTY_SCALE_HSCH4 + 0 + 10 + + + + + HSCH4_DUTY_R + 0x60 + LEDC_HSCH4_DUTY_R + 32 + 0x00000000 + + + DUTY_HSCH4 + 0 + 25 + + + + + HSCH5_CONF0 + 0x64 + LEDC_HSCH5_CONF0 + 32 + 0x00000000 + + + IDLE_LV_HSCH5 + 3 + 1 + + + SIG_OUT_EN_HSCH5 + 2 + 1 + + + TIMER_SEL_HSCH5 + 0 + 2 + + + + + HSCH5_HPOINT + 0x68 + LEDC_HSCH5_HPOINT + 32 + 0x00000000 + + + HPOINT_HSCH5 + 0 + 20 + + + + + HSCH5_DUTY + 0x6c + LEDC_HSCH5_DUTY + 32 + 0x00000000 + + + DUTY_HSCH5 + 0 + 25 + + + + + HSCH5_CONF1 + 0x70 + LEDC_HSCH5_CONF1 + 32 + 0x00000000 + + + DUTY_START_HSCH5 + 31 + 1 + + + DUTY_INC_HSCH5 + 30 + 1 + + + DUTY_NUM_HSCH5 + 20 + 10 + + + DUTY_CYCLE_HSCH5 + 10 + 10 + + + DUTY_SCALE_HSCH5 + 0 + 10 + + + + + HSCH5_DUTY_R + 0x74 + LEDC_HSCH5_DUTY_R + 32 + 0x00000000 + + + DUTY_HSCH5 + 0 + 25 + + + + + HSCH6_CONF0 + 0x78 + LEDC_HSCH6_CONF0 + 32 + 0x00000000 + + + IDLE_LV_HSCH6 + 3 + 1 + + + SIG_OUT_EN_HSCH6 + 2 + 1 + + + TIMER_SEL_HSCH6 + 0 + 2 + + + + + HSCH6_HPOINT + 0x7c + LEDC_HSCH6_HPOINT + 32 + 0x00000000 + + + HPOINT_HSCH6 + 0 + 20 + + + + + HSCH6_DUTY + 0x80 + LEDC_HSCH6_DUTY + 32 + 0x00000000 + + + DUTY_HSCH6 + 0 + 25 + + + + + HSCH6_CONF1 + 0x84 + LEDC_HSCH6_CONF1 + 32 + 0x00000000 + + + DUTY_START_HSCH6 + 31 + 1 + + + DUTY_INC_HSCH6 + 30 + 1 + + + DUTY_NUM_HSCH6 + 20 + 10 + + + DUTY_CYCLE_HSCH6 + 10 + 10 + + + DUTY_SCALE_HSCH6 + 0 + 10 + + + + + HSCH6_DUTY_R + 0x88 + LEDC_HSCH6_DUTY_R + 32 + 0x00000000 + + + DUTY_HSCH6 + 0 + 25 + + + + + HSCH7_CONF0 + 0x8c + LEDC_HSCH7_CONF0 + 32 + 0x00000000 + + + IDLE_LV_HSCH7 + 3 + 1 + + + SIG_OUT_EN_HSCH7 + 2 + 1 + + + TIMER_SEL_HSCH7 + 0 + 2 + + + + + HSCH7_HPOINT + 0x90 + LEDC_HSCH7_HPOINT + 32 + 0x00000000 + + + HPOINT_HSCH7 + 0 + 20 + + + + + HSCH7_DUTY + 0x94 + LEDC_HSCH7_DUTY + 32 + 0x00000000 + + + DUTY_HSCH7 + 0 + 25 + + + + + HSCH7_CONF1 + 0x98 + LEDC_HSCH7_CONF1 + 32 + 0x00000000 + + + DUTY_START_HSCH7 + 31 + 1 + + + DUTY_INC_HSCH7 + 30 + 1 + + + DUTY_NUM_HSCH7 + 20 + 10 + + + DUTY_CYCLE_HSCH7 + 10 + 10 + + + DUTY_SCALE_HSCH7 + 0 + 10 + + + + + HSCH7_DUTY_R + 0x9c + LEDC_HSCH7_DUTY_R + 32 + 0x00000000 + + + DUTY_HSCH7 + 0 + 25 + + + + + LSCH0_CONF0 + 0xa0 + LEDC_LSCH0_CONF0 + 32 + 0x00000000 + + + PARA_UP_LSCH0 + 4 + 1 + + + IDLE_LV_LSCH0 + 3 + 1 + + + SIG_OUT_EN_LSCH0 + 2 + 1 + + + TIMER_SEL_LSCH0 + 0 + 2 + + + + + LSCH0_HPOINT + 0xa4 + LEDC_LSCH0_HPOINT + 32 + 0x00000000 + + + HPOINT_LSCH0 + 0 + 20 + + + + + LSCH0_DUTY + 0xa8 + LEDC_LSCH0_DUTY + 32 + 0x00000000 + + + DUTY_LSCH0 + 0 + 25 + + + + + LSCH0_CONF1 + 0xac + LEDC_LSCH0_CONF1 + 32 + 0x00000000 + + + DUTY_START_LSCH0 + 31 + 1 + + + DUTY_INC_LSCH0 + 30 + 1 + + + DUTY_NUM_LSCH0 + 20 + 10 + + + DUTY_CYCLE_LSCH0 + 10 + 10 + + + DUTY_SCALE_LSCH0 + 0 + 10 + + + + + LSCH0_DUTY_R + 0xb0 + LEDC_LSCH0_DUTY_R + 32 + 0x00000000 + + + DUTY_LSCH0 + 0 + 25 + + + + + LSCH1_CONF0 + 0xb4 + LEDC_LSCH1_CONF0 + 32 + 0x00000000 + + + PARA_UP_LSCH1 + 4 + 1 + + + IDLE_LV_LSCH1 + 3 + 1 + + + SIG_OUT_EN_LSCH1 + 2 + 1 + + + TIMER_SEL_LSCH1 + 0 + 2 + + + + + LSCH1_HPOINT + 0xb8 + LEDC_LSCH1_HPOINT + 32 + 0x00000000 + + + HPOINT_LSCH1 + 0 + 20 + + + + + LSCH1_DUTY + 0xbc + LEDC_LSCH1_DUTY + 32 + 0x00000000 + + + DUTY_LSCH1 + 0 + 25 + + + + + LSCH1_CONF1 + 0xc0 + LEDC_LSCH1_CONF1 + 32 + 0x00000000 + + + DUTY_START_LSCH1 + 31 + 1 + + + DUTY_INC_LSCH1 + 30 + 1 + + + DUTY_NUM_LSCH1 + 20 + 10 + + + DUTY_CYCLE_LSCH1 + 10 + 10 + + + DUTY_SCALE_LSCH1 + 0 + 10 + + + + + LSCH1_DUTY_R + 0xc4 + LEDC_LSCH1_DUTY_R + 32 + 0x00000000 + + + DUTY_LSCH1 + 0 + 25 + + + + + LSCH2_CONF0 + 0xc8 + LEDC_LSCH2_CONF0 + 32 + 0x00000000 + + + PARA_UP_LSCH2 + 4 + 1 + + + IDLE_LV_LSCH2 + 3 + 1 + + + SIG_OUT_EN_LSCH2 + 2 + 1 + + + TIMER_SEL_LSCH2 + 0 + 2 + + + + + LSCH2_HPOINT + 0xcc + LEDC_LSCH2_HPOINT + 32 + 0x00000000 + + + HPOINT_LSCH2 + 0 + 20 + + + + + LSCH2_DUTY + 0xd0 + LEDC_LSCH2_DUTY + 32 + 0x00000000 + + + DUTY_LSCH2 + 0 + 25 + + + + + LSCH2_CONF1 + 0xd4 + LEDC_LSCH2_CONF1 + 32 + 0x00000000 + + + DUTY_START_LSCH2 + 31 + 1 + + + DUTY_INC_LSCH2 + 30 + 1 + + + DUTY_NUM_LSCH2 + 20 + 10 + + + DUTY_CYCLE_LSCH2 + 10 + 10 + + + DUTY_SCALE_LSCH2 + 0 + 10 + + + + + LSCH2_DUTY_R + 0xd8 + LEDC_LSCH2_DUTY_R + 32 + 0x00000000 + + + DUTY_LSCH2 + 0 + 25 + + + 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0x00000000 + + + FH0_OST_ON + 1 + 1 + + + FH0_CBC_ON + 0 + 1 + + + + + GEN1_STMP_CFG + 0x74 + MCPWM_GEN1_STMP_CFG + 32 + 0x00000000 + + + GEN1_B_SHDW_FULL + 9 + 1 + + + GEN1_A_SHDW_FULL + 8 + 1 + + + GEN1_B_UPMETHOD + 4 + 4 + + + GEN1_A_UPMETHOD + 0 + 4 + + + + + GEN1_TSTMP_A + 0x78 + MCPWM_GEN1_TSTMP_A + 32 + 0x00000000 + + + GEN1_A + 0 + 16 + + + + + GEN1_TSTMP_B + 0x7c + MCPWM_GEN1_TSTMP_B + 32 + 0x00000000 + + + GEN1_B + 0 + 16 + + + + + GEN1_CFG0 + 0x80 + MCPWM_GEN1_CFG0 + 32 + 0x00000000 + + + GEN1_T1_SEL + 7 + 3 + + + GEN1_T0_SEL + 4 + 3 + + + GEN1_CFG_UPMETHOD + 0 + 4 + + + + + GEN1_FORCE + 0x84 + MCPWM_GEN1_FORCE + 32 + 0x00000000 + + + GEN1_B_NCIFORCE_MODE + 14 + 2 + + + GEN1_B_NCIFORCE + 13 + 1 + + + GEN1_A_NCIFORCE_MODE + 11 + 2 + + + GEN1_A_NCIFORCE + 10 + 1 + + + GEN1_B_CNTUFORCE_MODE + 8 + 2 + + + GEN1_A_CNTUFORCE_MODE + 6 + 2 + + + GEN1_CNTUFORCE_UPMETHOD + 0 + 6 + + + + + GEN1_A + 0x88 + MCPWM_GEN1_A + 32 + 0x00000000 + + + GEN1_A_DT1 + 22 + 2 + + + GEN1_A_DT0 + 20 + 2 + + + GEN1_A_DTEB + 18 + 2 + + + GEN1_A_DTEA + 16 + 2 + + + GEN1_A_DTEP + 14 + 2 + + + GEN1_A_DTEZ + 12 + 2 + + + GEN1_A_UT1 + 10 + 2 + + + GEN1_A_UT0 + 8 + 2 + + + GEN1_A_UTEB + 6 + 2 + + + GEN1_A_UTEA + 4 + 2 + + + GEN1_A_UTEP + 2 + 2 + + + GEN1_A_UTEZ + 0 + 2 + + + + + GEN1_B + 0x8c + MCPWM_GEN1_B + 32 + 0x00000000 + + + GEN1_B_DT1 + 22 + 2 + + + GEN1_B_DT0 + 20 + 2 + + + GEN1_B_DTEB + 18 + 2 + + + GEN1_B_DTEA + 16 + 2 + + + GEN1_B_DTEP + 14 + 2 + + + GEN1_B_DTEZ + 12 + 2 + + + GEN1_B_UT1 + 10 + 2 + + + GEN1_B_UT0 + 8 + 2 + + + GEN1_B_UTEB + 6 + 2 + + + GEN1_B_UTEA + 4 + 2 + + + GEN1_B_UTEP + 2 + 2 + + + GEN1_B_UTEZ + 0 + 2 + + + + + DT1_CFG + 0x90 + MCPWM_DT1_CFG + 32 + 0x00000000 + + + DT1_CLK_SEL + 17 + 1 + + + DT1_B_OUTBYPASS + 16 + 1 + + + DT1_A_OUTBYPASS + 15 + 1 + + + DT1_FED_OUTINVERT + 14 + 1 + + + DT1_RED_OUTINVERT + 13 + 1 + + + DT1_FED_INSEL + 12 + 1 + + + DT1_RED_INSEL + 11 + 1 + + + DT1_B_OUTSWAP + 10 + 1 + + + DT1_A_OUTSWAP + 9 + 1 + + + DT1_DEB_MODE + 8 + 1 + + + DT1_RED_UPMETHOD + 4 + 4 + + + DT1_FED_UPMETHOD + 0 + 4 + + + + + DT1_FED_CFG + 0x94 + MCPWM_DT1_FED_CFG + 32 + 0x00000000 + + + DT1_FED + 0 + 16 + + + + + DT1_RED_CFG + 0x98 + MCPWM_DT1_RED_CFG + 32 + 0x00000000 + + + DT1_RED + 0 + 16 + + + + + CARRIER1_CFG + 0x9c + MCPWM_CARRIER1_CFG + 32 + 0x00000000 + + + CARRIER1_IN_INVERT + 13 + 1 + + + CARRIER1_OUT_INVERT + 12 + 1 + + + CARRIER1_OSHWTH + 8 + 4 + + + CARRIER1_DUTY + 5 + 3 + + + CARRIER1_PRESCALE + 1 + 4 + + + CARRIER1_EN + 0 + 1 + + + + + FH1_CFG0 + 0xa0 + MCPWM_FH1_CFG0 + 32 + 0x00000000 + + + FH1_B_OST_U + 22 + 2 + + + FH1_B_OST_D + 20 + 2 + + + FH1_B_CBC_U + 18 + 2 + + + FH1_B_CBC_D + 16 + 2 + + + FH1_A_OST_U + 14 + 2 + + + FH1_A_OST_D + 12 + 2 + + + FH1_A_CBC_U + 10 + 2 + + + FH1_A_CBC_D + 8 + 2 + + + FH1_F0_OST + 7 + 1 + + + FH1_F1_OST + 6 + 1 + + + FH1_F2_OST + 5 + 1 + + + FH1_SW_OST + 4 + 1 + + + FH1_F0_CBC + 3 + 1 + + + FH1_F1_CBC + 2 + 1 + + + FH1_F2_CBC + 1 + 1 + + + FH1_SW_CBC + 0 + 1 + + + + + FH1_CFG1 + 0xa4 + MCPWM_FH1_CFG1 + 32 + 0x00000000 + + + FH1_FORCE_OST + 4 + 1 + + + FH1_FORCE_CBC + 3 + 1 + + + FH1_CBCPULSE + 1 + 2 + + + FH1_CLR_OST + 0 + 1 + + + + + FH1_STATUS + 0xa8 + MCPWM_FH1_STATUS + 32 + 0x00000000 + + + FH1_OST_ON + 1 + 1 + + + FH1_CBC_ON + 0 + 1 + + + + + GEN2_STMP_CFG + 0xac + MCPWM_GEN2_STMP_CFG + 32 + 0x00000000 + + + GEN2_B_SHDW_FULL + 9 + 1 + + + GEN2_A_SHDW_FULL + 8 + 1 + + + GEN2_B_UPMETHOD + 4 + 4 + + + GEN2_A_UPMETHOD + 0 + 4 + + + + + GEN2_TSTMP_A + 0xb0 + MCPWM_GEN2_TSTMP_A + 32 + 0x00000000 + + + GEN2_A + 0 + 16 + + + + + GEN2_TSTMP_B + 0xb4 + MCPWM_GEN2_TSTMP_B + 32 + 0x00000000 + + + GEN2_B + 0 + 16 + + + + + GEN2_CFG0 + 0xb8 + MCPWM_GEN2_CFG0 + 32 + 0x00000000 + + + GEN2_T1_SEL + 7 + 3 + + + GEN2_T0_SEL + 4 + 3 + + + GEN2_CFG_UPMETHOD + 0 + 4 + + + + + GEN2_FORCE + 0xbc + MCPWM_GEN2_FORCE + 32 + 0x00000000 + + + GEN2_B_NCIFORCE_MODE + 14 + 2 + + + GEN2_B_NCIFORCE + 13 + 1 + + + GEN2_A_NCIFORCE_MODE + 11 + 2 + + + GEN2_A_NCIFORCE + 10 + 1 + + + GEN2_B_CNTUFORCE_MODE + 8 + 2 + + + GEN2_A_CNTUFORCE_MODE + 6 + 2 + + + GEN2_CNTUFORCE_UPMETHOD + 0 + 6 + + + + + GEN2_A + 0xc0 + MCPWM_GEN2_A + 32 + 0x00000000 + + + GEN2_A_DT1 + 22 + 2 + + + GEN2_A_DT0 + 20 + 2 + + + GEN2_A_DTEB + 18 + 2 + + + GEN2_A_DTEA + 16 + 2 + + + GEN2_A_DTEP + 14 + 2 + + + GEN2_A_DTEZ + 12 + 2 + + + GEN2_A_UT1 + 10 + 2 + + + GEN2_A_UT0 + 8 + 2 + + + GEN2_A_UTEB + 6 + 2 + + + GEN2_A_UTEA + 4 + 2 + + + GEN2_A_UTEP + 2 + 2 + + + GEN2_A_UTEZ + 0 + 2 + + + + + GEN2_B + 0xc4 + MCPWM_GEN2_B + 32 + 0x00000000 + + + GEN2_B_DT1 + 22 + 2 + + + GEN2_B_DT0 + 20 + 2 + + + GEN2_B_DTEB + 18 + 2 + + + GEN2_B_DTEA + 16 + 2 + + + GEN2_B_DTEP + 14 + 2 + + + GEN2_B_DTEZ + 12 + 2 + + + GEN2_B_UT1 + 10 + 2 + + + GEN2_B_UT0 + 8 + 2 + + + GEN2_B_UTEB + 6 + 2 + + + GEN2_B_UTEA + 4 + 2 + + + GEN2_B_UTEP + 2 + 2 + + + GEN2_B_UTEZ + 0 + 2 + + + + + DT2_CFG + 0xc8 + MCPWM_DT2_CFG + 32 + 0x00000000 + + + DT2_CLK_SEL + 17 + 1 + + + DT2_B_OUTBYPASS + 16 + 1 + + + DT2_A_OUTBYPASS + 15 + 1 + + + DT2_FED_OUTINVERT + 14 + 1 + + + DT2_RED_OUTINVERT + 13 + 1 + + + DT2_FED_INSEL + 12 + 1 + + + DT2_RED_INSEL + 11 + 1 + + + DT2_B_OUTSWAP + 10 + 1 + + + DT2_A_OUTSWAP + 9 + 1 + + + DT2_DEB_MODE + 8 + 1 + + + DT2_RED_UPMETHOD + 4 + 4 + + + DT2_FED_UPMETHOD + 0 + 4 + + + + + DT2_FED_CFG + 0xcc + MCPWM_DT2_FED_CFG + 32 + 0x00000000 + + + DT2_FED + 0 + 16 + + + + + DT2_RED_CFG + 0xd0 + MCPWM_DT2_RED_CFG + 32 + 0x00000000 + + + DT2_RED + 0 + 16 + + + + + CARRIER2_CFG + 0xd4 + MCPWM_CARRIER2_CFG + 32 + 0x00000000 + + + CARRIER2_IN_INVERT + 13 + 1 + + + CARRIER2_OUT_INVERT + 12 + 1 + + + CARRIER2_OSHWTH + 8 + 4 + + + CARRIER2_DUTY + 5 + 3 + + + CARRIER2_PRESCALE + 1 + 4 + + + CARRIER2_EN + 0 + 1 + + + + + FH2_CFG0 + 0xd8 + MCPWM_FH2_CFG0 + 32 + 0x00000000 + + + FH2_B_OST_U + 22 + 2 + + + FH2_B_OST_D + 20 + 2 + + + FH2_B_CBC_U + 18 + 2 + + + FH2_B_CBC_D + 16 + 2 + + + FH2_A_OST_U + 14 + 2 + + + FH2_A_OST_D + 12 + 2 + + + FH2_A_CBC_U + 10 + 2 + + + FH2_A_CBC_D + 8 + 2 + + + FH2_F0_OST + 7 + 1 + + + FH2_F1_OST + 6 + 1 + + + FH2_F2_OST + 5 + 1 + + + FH2_SW_OST + 4 + 1 + + + FH2_F0_CBC + 3 + 1 + + + FH2_F1_CBC + 2 + 1 + + + FH2_F2_CBC + 1 + 1 + + + FH2_SW_CBC + 0 + 1 + + + + + FH2_CFG1 + 0xdc + MCPWM_FH2_CFG1 + 32 + 0x00000000 + + + FH2_FORCE_OST + 4 + 1 + + + FH2_FORCE_CBC + 3 + 1 + + + FH2_CBCPULSE + 1 + 2 + + + FH2_CLR_OST + 0 + 1 + + + + + FH2_STATUS + 0xe0 + MCPWM_FH2_STATUS + 32 + 0x00000000 + + + FH2_OST_ON + 1 + 1 + + + FH2_CBC_ON + 0 + 1 + + + + + FAULT_DETECT + 0xe4 + MCPWM_FAULT_DETECT + 32 + 0x00000000 + + + EVENT_F2 + 8 + 1 + + + EVENT_F1 + 7 + 1 + + + EVENT_F0 + 6 + 1 + + + F2_POLE + 5 + 1 + + + F1_POLE + 4 + 1 + + + F0_POLE + 3 + 1 + + + F2_EN + 2 + 1 + + + F1_EN + 1 + 1 + + + F0_EN + 0 + 1 + + + + + CAP_TIMER_CFG + 0xe8 + MCPWM_CAP_TIMER_CFG + 32 + 0x00000000 + + + CAP_SYNC_SW + 5 + 1 + + + CAP_SYNCI_SEL + 2 + 3 + + + CAP_SYNCI_EN + 1 + 1 + + + CAP_TIMER_EN + 0 + 1 + + + + + CAP_TIMER_PHASE + 0xec + MCPWM_CAP_TIMER_PHASE + 32 + 0x00000000 + + + CAP_PHASE + 0 + 32 + + + + + CAP_CH0_CFG + 0xf0 + MCPWM_CAP_CH0_CFG + 32 + 0x00000000 + + + CAP0_SW + 12 + 1 + + + CAP0_IN_INVERT + 11 + 1 + + + CAP0_PRESCALE + 3 + 8 + + + CAP0_MODE + 1 + 2 + + + CAP0_EN + 0 + 1 + + + + + CAP_CH1_CFG + 0xf4 + MCPWM_CAP_CH1_CFG + 32 + 0x00000000 + + + CAP1_SW + 12 + 1 + + + CAP1_IN_INVERT + 11 + 1 + + + CAP1_PRESCALE + 3 + 8 + + + CAP1_MODE + 1 + 2 + + + CAP1_EN + 0 + 1 + + + + + CAP_CH2_CFG + 0xf8 + MCPWM_CAP_CH2_CFG + 32 + 0x00000000 + + + CAP2_SW + 12 + 1 + + + CAP2_IN_INVERT + 11 + 1 + + + CAP2_PRESCALE + 3 + 8 + + + CAP2_MODE + 1 + 2 + + + CAP2_EN + 0 + 1 + + + + + CAP_CH0 + 0xfc + MCPWM_CAP_CH0 + 32 + 0x00000000 + + + CAP0_VALUE + 0 + 32 + + + + + CAP_CH1 + 0x100 + MCPWM_CAP_CH1 + 32 + 0x00000000 + + + CAP1_VALUE + 0 + 32 + + + + + CAP_CH2 + 0x104 + MCPWM_CAP_CH2 + 32 + 0x00000000 + + + CAP2_VALUE + 0 + 32 + + + + + CAP_STATUS + 0x108 + MCPWM_CAP_STATUS + 32 + 0x00000000 + + + CAP2_EDGE + 2 + 1 + + + CAP1_EDGE + 1 + 1 + + + CAP0_EDGE + 0 + 1 + + + + + UPDATE_CFG + 0x10c + MCPWM_UPDATE_CFG + 32 + 0x00000000 + + + OP2_FORCE_UP + 7 + 1 + + + OP2_UP_EN + 6 + 1 + + + OP1_FORCE_UP + 5 + 1 + + + OP1_UP_EN + 4 + 1 + + + OP0_FORCE_UP + 3 + 1 + + + OP0_UP_EN + 2 + 1 + + + GLOBAL_FORCE_UP + 1 + 1 + + + GLOBAL_UP_EN + 0 + 1 + + + + + MCMCPWM_INT_ENA_MCPWM + 0x110 + MCMCPWM_INT_ENA_MCPWM + 32 + 0x00000000 + + + CAP2_INT_ENA + 29 + 1 + + + CAP1_INT_ENA + 28 + 1 + + + CAP0_INT_ENA + 27 + 1 + + + FH2_OST_INT_ENA + 26 + 1 + + + FH1_OST_INT_ENA + 25 + 1 + + + FH0_OST_INT_ENA + 24 + 1 + + + FH2_CBC_INT_ENA + 23 + 1 + + + FH1_CBC_INT_ENA + 22 + 1 + + + FH0_CBC_INT_ENA + 21 + 1 + + + OP2_TEB_INT_ENA + 20 + 1 + + + OP1_TEB_INT_ENA + 19 + 1 + + + OP0_TEB_INT_ENA + 18 + 1 + + + OP2_TEA_INT_ENA + 17 + 1 + + + OP1_TEA_INT_ENA + 16 + 1 + + + OP0_TEA_INT_ENA + 15 + 1 + + + FAULT2_CLR_INT_ENA + 14 + 1 + + + FAULT1_CLR_INT_ENA + 13 + 1 + + + FAULT0_CLR_INT_ENA + 12 + 1 + + + FAULT2_INT_ENA + 11 + 1 + + + FAULT1_INT_ENA + 10 + 1 + + + FAULT0_INT_ENA + 9 + 1 + + + TIMER2_TEP_INT_ENA + 8 + 1 + + + TIMER1_TEP_INT_ENA + 7 + 1 + + + TIMER0_TEP_INT_ENA + 6 + 1 + + + TIMER2_TEZ_INT_ENA + 5 + 1 + + + TIMER1_TEZ_INT_ENA + 4 + 1 + + + TIMER0_TEZ_INT_ENA + 3 + 1 + + + TIMER2_STOP_INT_ENA + 2 + 1 + + + TIMER1_STOP_INT_ENA + 1 + 1 + + + TIMER0_STOP_INT_ENA + 0 + 1 + + + + + MCMCPWM_INT_RAW_MCPWM + 0x114 + MCMCPWM_INT_RAW_MCPWM + 32 + 0x00000000 + + + CAP2_INT_RAW + 29 + 1 + + + CAP1_INT_RAW + 28 + 1 + + + CAP0_INT_RAW + 27 + 1 + + + FH2_OST_INT_RAW + 26 + 1 + + + FH1_OST_INT_RAW + 25 + 1 + + + FH0_OST_INT_RAW + 24 + 1 + + + FH2_CBC_INT_RAW + 23 + 1 + + + FH1_CBC_INT_RAW + 22 + 1 + + + FH0_CBC_INT_RAW + 21 + 1 + + + OP2_TEB_INT_RAW + 20 + 1 + + + OP1_TEB_INT_RAW + 19 + 1 + + + OP0_TEB_INT_RAW + 18 + 1 + + + OP2_TEA_INT_RAW + 17 + 1 + + + OP1_TEA_INT_RAW + 16 + 1 + + + OP0_TEA_INT_RAW + 15 + 1 + + + FAULT2_CLR_INT_RAW + 14 + 1 + + + FAULT1_CLR_INT_RAW + 13 + 1 + + + FAULT0_CLR_INT_RAW + 12 + 1 + + + FAULT2_INT_RAW + 11 + 1 + + + FAULT1_INT_RAW + 10 + 1 + + + FAULT0_INT_RAW + 9 + 1 + + + TIMER2_TEP_INT_RAW + 8 + 1 + + + TIMER1_TEP_INT_RAW + 7 + 1 + + + TIMER0_TEP_INT_RAW + 6 + 1 + + + TIMER2_TEZ_INT_RAW + 5 + 1 + + + TIMER1_TEZ_INT_RAW + 4 + 1 + + + TIMER0_TEZ_INT_RAW + 3 + 1 + + + TIMER2_STOP_INT_RAW + 2 + 1 + + + TIMER1_STOP_INT_RAW + 1 + 1 + + + TIMER0_STOP_INT_RAW + 0 + 1 + + + + + MCMCPWM_INT_ST_MCPWM + 0x118 + MCMCPWM_INT_ST_MCPWM + 32 + 0x00000000 + + + CAP2_INT_ST + 29 + 1 + + + CAP1_INT_ST + 28 + 1 + + + CAP0_INT_ST + 27 + 1 + + + FH2_OST_INT_ST + 26 + 1 + + + FH1_OST_INT_ST + 25 + 1 + + + FH0_OST_INT_ST + 24 + 1 + + + FH2_CBC_INT_ST + 23 + 1 + + + FH1_CBC_INT_ST + 22 + 1 + + + FH0_CBC_INT_ST + 21 + 1 + + + OP2_TEB_INT_ST + 20 + 1 + + + OP1_TEB_INT_ST + 19 + 1 + + + OP0_TEB_INT_ST + 18 + 1 + + + OP2_TEA_INT_ST + 17 + 1 + + + OP1_TEA_INT_ST + 16 + 1 + + + OP0_TEA_INT_ST + 15 + 1 + + + FAULT2_CLR_INT_ST + 14 + 1 + + + FAULT1_CLR_INT_ST + 13 + 1 + + + FAULT0_CLR_INT_ST + 12 + 1 + + + FAULT2_INT_ST + 11 + 1 + + + FAULT1_INT_ST + 10 + 1 + + + FAULT0_INT_ST + 9 + 1 + + + TIMER2_TEP_INT_ST + 8 + 1 + + + TIMER1_TEP_INT_ST + 7 + 1 + + + TIMER0_TEP_INT_ST + 6 + 1 + + + TIMER2_TEZ_INT_ST + 5 + 1 + + + TIMER1_TEZ_INT_ST + 4 + 1 + + + TIMER0_TEZ_INT_ST + 3 + 1 + + + TIMER2_STOP_INT_ST + 2 + 1 + + + TIMER1_STOP_INT_ST + 1 + 1 + + + TIMER0_STOP_INT_ST + 0 + 1 + + + + + MCMCPWM_INT_CLR_MCPWM + 0x11c + MCMCPWM_INT_CLR_MCPWM + 32 + 0x00000000 + + + CAP2_INT_CLR + 29 + 1 + + + CAP1_INT_CLR + 28 + 1 + + + CAP0_INT_CLR + 27 + 1 + + + FH2_OST_INT_CLR + 26 + 1 + + + FH1_OST_INT_CLR + 25 + 1 + + + FH0_OST_INT_CLR + 24 + 1 + + + FH2_CBC_INT_CLR + 23 + 1 + + + FH1_CBC_INT_CLR + 22 + 1 + + + FH0_CBC_INT_CLR + 21 + 1 + + + OP2_TEB_INT_CLR + 20 + 1 + + + OP1_TEB_INT_CLR + 19 + 1 + + + OP0_TEB_INT_CLR + 18 + 1 + + + OP2_TEA_INT_CLR + 17 + 1 + + + OP1_TEA_INT_CLR + 16 + 1 + + + OP0_TEA_INT_CLR + 15 + 1 + + + FAULT2_CLR_INT_CLR + 14 + 1 + + + FAULT1_CLR_INT_CLR + 13 + 1 + + + FAULT0_CLR_INT_CLR + 12 + 1 + + + FAULT2_INT_CLR + 11 + 1 + + + FAULT1_INT_CLR + 10 + 1 + + + FAULT0_INT_CLR + 9 + 1 + + + TIMER2_TEP_INT_CLR + 8 + 1 + + + TIMER1_TEP_INT_CLR + 7 + 1 + + + TIMER0_TEP_INT_CLR + 6 + 1 + + + TIMER2_TEZ_INT_CLR + 5 + 1 + + + TIMER1_TEZ_INT_CLR + 4 + 1 + + + TIMER0_TEZ_INT_CLR + 3 + 1 + + + TIMER2_STOP_INT_CLR + 2 + 1 + + + TIMER1_STOP_INT_CLR + 1 + 1 + + + TIMER0_STOP_INT_CLR + 0 + 1 + + + + + CLK + 0x120 + MCPWM_CLK + 32 + 0x00000000 + + + CLK_EN + 0 + 1 + + + + + VERSION + 0x124 + MCPWM_VERSION + 32 + 0x00000000 + + + DATE + 0 + 28 + + + + + + + UART1 + 0x3ff50000 + + + SPI1 + 0x3ff42000 + + + I2S1 + 0x3ff6d000 + + 0 + 0x00000000 + registers + + + + UART00x3ff40000 + + XTENSA_INTERNAL0INTERNAL_TIMER0_INTRInternal Timer 0 interrupt69 + INTERNAL_SOFTWARE_LEVEL_1_INTRSoftware Level 1 interrupt70 + INTERNAL_PROFILING_INTRProfiling interrupt71 + INTERNAL_TIMER1_INTRInternal Timer 1 interrupt72 + INTERNAL_TIMER2_INTRInternal Timer 1 interrupt73 + INTERNAL_SOFTWARE_LEVEL_3_INTRSoftware Level 3 interrupt74 + + XTENSA0FROM_CPU_INTR0interrupt0 generated from a CPU, level24 + FROM_CPU_INTR1interrupt1 generated from a CPU, level25 + FROM_CPU_INTR2interrupt2 generated from a CPU, level26 + FROM_CPU_INTR3interrupt3 generated from a CPU, level27 + TIMER1_INTRwill be cancelled56 + TIMER2_INTRwill be cancelled57 + MMU_IA_INTRinterrupt of MMU Invalid Access, LEVEL66 + MPU_IA_INTRinterrupt of MPU Invalid Access, LEVEL67 + CACHE_IA_INTRinterrupt of Cache Invalid Access, LEVEL68 + + WIFI_MAC0WIFI_MAC_INTRinterrupt of WiFi MAC, level0 + WIFI_MAC_NMIinterrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI1 + + WIFI_BB0WIFI_BB_INTRinterrupt of WiFi BB, level, we can do some calibration2 + + BT_MAC0BT_MAC_INTRwill be cancelled3 + + BT_BB0BT_BB_INTRinterrupt of BT BB, level4 + BT_BB_NMIinterrupt of BT BB, NMI, use if BB have bug to fix in NMI5 + + RW_BT0RWBT_INTRinterrupt of RWBT, level6 + RWBT_NMIinterrupt of RWBT, NMI, use if RWBT have bug to fix in NMI8 + + RW_BLE0RWBLE_INTRinterrupt of RWBLE, level7 + RWBLE_NMIinterrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI9 + + ETH_MAC0 + SDIO0SDIO_HOST_INTRinterrupt of SD/SDIO/MMC HOST, level37 + + ETH0ETH_MAC_INTRinterrupt of ethernet mac, level38 + + WDT0WDT_INTRwill be cancelled55 + + + \ No newline at end of file diff --git a/svd/patches/_indexed_interrupts_flat.yaml b/svd/patches/_indexed_interrupts_flat.yaml new file mode 100644 index 00000000..0c2a35b3 --- /dev/null +++ b/svd/patches/_indexed_interrupts_flat.yaml @@ -0,0 +1,152 @@ + + +TIMG: + _add: + _interrupts: + TG0_T0_LEVEL_INTR: + description: "interrupt of TIMER_GROUP0, TIMER0, level, we would like use EDGE for timer if permission" + value: 14 + + TG0_T1_LEVEL_INTR: + description: "interrupt of TIMER_GROUP0, TIMER1, level, we would like use EDGE for timer if permission" + value: 15 + + TG0_WDT_LEVEL_INTR: + description: "interrupt of TIMER_GROUP0, WATCHDOG, level" + value: 16 + + TG0_LACT_LEVEL_INTR: + description: "interrupt of TIMER_GROUP0, LACT, level" + value: 17 + + TG1_T0_LEVEL_INTR: + description: "interrupt of TIMER_GROUP1, TIMER0, level, we would like use EDGE for timer if permission" + value: 18 + + TG1_T1_LEVEL_INTR: + description: "interrupt of TIMER_GROUP1, TIMER1, level, we would like use EDGE for timer if permission" + value: 19 + + TG1_WDT_LEVEL_INTR: + description: "interrupt of TIMER_GROUP1, WATCHDOG, level" + value: 20 + + TG1_LACT_LEVEL_INTR: + description: "interrupt of TIMER_GROUP1, LACT, level" + value: 21 + + TG0_T0_EDGE_INTR: + description: "interrupt of TIMER_GROUP0, TIMER0, EDGE" + value: 58 + + TG0_T1_EDGE_INTR: + description: "interrupt of TIMER_GROUP0, TIMER1, EDGE" + value: 59 + + TG0_WDT_EDGE_INTR: + description: "interrupt of TIMER_GROUP0, WATCH DOG, EDGE" + value: 60 + + TG0_LACT_EDGE_INTR: + description: "interrupt of TIMER_GROUP0, LACT, EDGE" + value: 61 + + TG1_T0_EDGE_INTR: + description: "interrupt of TIMER_GROUP1, TIMER0, EDGE" + value: 62 + + TG1_T1_EDGE_INTR: + description: "interrupt of TIMER_GROUP1, TIMER1, EDGE" + value: 63 + + TG1_WDT_EDGE_INTR: + description: "interrupt of TIMER_GROUP1, WATCHDOG, EDGE" + value: 64 + + TG1_LACT_EDGE_INTR: + description: "interrupt of TIMER_GROUP0, LACT, EDGE" + value: 65 + +SPI: + _add: + _interrupts: + SPI1_DMA_INTR: + description: "interrupt of SPI1 DMA, SPI1 is for flash read/write, do not use this" + value: 52 + + SPI2_DMA_INTR: + description: "interrupt of SPI2 DMA, level" + value: 53 + + SPI3_DMA_INTR: + description: "interrupt of SPI3 DMA, level" + value: 54 + +I2C: + _add: + _interrupts: + I2C_EXT0_INTR: + description: "interrupt of I2C controller0, level" + value: 49 + + I2C_EXT1_INTR: + description: "interrupt of I2C controller1, level" + value: 50 + + PWM0_INTR: + description: "interrupt of PWM0, level, Reserved" + value: 39 + + PWM1_INTR: + description: "interrupt of PWM1, level, Reserved" + value: 40 + + PWM2_INTR: + description: "interrupt of PWM2, level" + value: 41 + + PWM3_INTR: + description: "interrupt of PWM3, level" + value: 42 + +UART: + _add: + _interrupts: + UART0_INTR: + description: "interrupt of UART0, level" + value: 34 + + UART1_INTR: + description: "interrupt of UART1, level" + value: 35 + + UART2_INTR: + description: "interrupt of UART2, level" + value: 36 + + SPI0_INTR: + description: "interrupt of SPI0, level, SPI0 is for Cache Access, do not use this" + value: 28 + + SPI1_INTR: + description: "interrupt of SPI1, level, SPI1 is for flash read/write, do not use this" + value: 29 + + SPI2_INTR: + description: "interrupt of SPI2, level" + value: 30 + + SPI3_INTR: + description: "interrupt of SPI3, level" + value: 31 + +UHCI: + _add: + _interrupts: + UHCI0_INTR: + description: "interrupt of UHCI0, level" + value: 12 + + UHCI1_INTR: + description: "interrupt of UHCI1, level" + value: 13 diff --git a/svd/patches/_interrupts.yaml b/svd/patches/_interrupts.yaml index b5357c7d..4e5c1db0 100644 --- a/svd/patches/_interrupts.yaml +++ b/svd/patches/_interrupts.yaml @@ -3,6 +3,11 @@ # Technical Reference manual, page 33. _add: + + # Xtensa Internal: these are not routed via teh interrupt matrix + XTENSA_INTERNAL: + baseAddress: 0 + # Processor specific interrupts and exceptions XTENSA: baseAddress: 0 @@ -92,16 +97,6 @@ RW_BT: description: "interrupt of RWBT, level" value: 6 -RW_BLE: - _add: - _interrupts: - RWBLE_INTR: - description: "interrupt of RWBLE, level" - value: 7 - -RW_BT: - _add: - _interrupts: RWBT_NMI: description: "interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI" value: 8 @@ -109,6 +104,10 @@ RW_BT: RW_BLE: _add: _interrupts: + RWBLE_INTR: + description: "interrupt of RWBLE, level" + value: 7 + RWBLE_NMI: description: "interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI" value: 9 @@ -153,7 +152,26 @@ XTENSA: FROM_CPU_INTR3: description: "interrupt3 generated from a CPU, level" value: 27 + + TIMER1_INTR: + description: "will be cancelled" + value: 56 + + TIMER2_INTR: + description: "will be cancelled" + value: 57 + MMU_IA_INTR: + description: "interrupt of MMU Invalid Access, LEVEL" + value: 66 + + MPU_IA_INTR: + description: "interrupt of MPU Invalid Access, LEVEL" + value: 67 + + CACHE_IA_INTR: + description: "interrupt of Cache Invalid Access, LEVEL" + value: 68 I2S: _add: _interrupts: @@ -235,28 +253,28 @@ WDT: description: "will be cancelled" value: 55 -XTENSA: - _add: - _interrupts: - TIMER1_INTR: - description: "will be cancelled" - value: 56 - - TIMER2_INTR: - description: "will be cancelled" - value: 57 -XTENSA: +# Xtensa Internal interrupts are not routed via the interrupt matrix and +# therefore have fixed priorities +# The numbers are chosen sequentially to be able to use same handler mechanism +XTENSA_INTERNAL: _add: - _interrupts: - MMU_IA_INTR: - description: "interrupt of MMU Invalid Access, LEVEL" - value: 66 - - MPU_IA_INTR: - description: "interrupt of MPU Invalid Access, LEVEL" - value: 67 - - CACHE_IA_INTR: - description: "interrupt of Cache Invalid Access, LEVEL" - value: 68 \ No newline at end of file + _interrupts: + INTERNAL_TIMER0_INTR: + description: "Internal Timer 0 interrupt" + value: 69 + INTERNAL_SOFTWARE_LEVEL_1_INTR: + description: "Software Level 1 interrupt" + value: 70 + INTERNAL_PROFILING_INTR: + description: "Profiling interrupt" + value: 71 + INTERNAL_TIMER1_INTR: + description: "Internal Timer 1 interrupt" + value: 72 + INTERNAL_TIMER2_INTR: + description: "Internal Timer 1 interrupt" + value: 73 + INTERNAL_SOFTWARE_LEVEL_3_INTR: + description: "Software Level 3 interrupt" + value: 74 diff --git a/svd/patches/_timg.yaml b/svd/patches/_timg.yaml index 664c2c73..026f97f3 100644 --- a/svd/patches/_timg.yaml +++ b/svd/patches/_timg.yaml @@ -4,3 +4,18 @@ TIMG: RTC_MUX: [0, "Select RTC slow clock"] CK8M_D256: [1, "Internal 8 MHz RC oscillator, divided by 256"] XTAL32K: [2, "Select XTAL_32K"] + WDTCONFIG0: + "WDT_STG*": + Disable: [0, "Disabled"] + Interrupt: [1, "Trigger an interrupt"] + ResetCPU: [2, "Reset CPU core"] + ResetSystem: [3, "Reset System"] + "*_RESET_LENGTH": + T100ns: [0, "100ns"] + T200ns: [1, "200ns"] + T300ns: [2, "300ns"] + T400ns: [3, "400ns"] + T500ns: [4, "500ns"] + T800ns: [5, "800ns"] + T1600ns: [6, "1600ns"] + T3200ns: [7, "3200ns"] diff --git a/svd/patches/esp32.yaml b/svd/patches/esp32.yaml index d7bbf81e..6c4bc018 100644 --- a/svd/patches/esp32.yaml +++ b/svd/patches/esp32.yaml @@ -11,6 +11,7 @@ _include: - "_interrupts.yaml" - "_timg.yaml" # - "_indexed_interrupts.yaml" # currently broken with svdtools, see: https://github.com/esp-rs/esp32/issues/17 + - "_indexed_interrupts_flat.yaml" # currently broken with svdtools, see: https://github.com/esp-rs/esp32/issues/17 _modify: PWM: