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Verilog: one bit signed/unsigned types #715

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Merged
merged 1 commit into from
Sep 23, 2024
Merged

Verilog: one bit signed/unsigned types #715

merged 1 commit into from
Sep 23, 2024

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kroening
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This adds support for specifying 1-bit signed/unsigned types to SystemVerilog frontend.

@kroening
Verilog: one bit signed/unsigned types
8d5a768 
This adds support for specifying 1-bit signed/unsigned types to
SystemVerilog frontend.
@kroening kroening marked this pull request as ready for review September 22, 2024 17:39
@tautschnig tautschnig merged commit 7c536e8 into main Sep 23, 2024
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@tautschnig tautschnig deleted the signed1-fix branch September 23, 2024 12:15
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@tautschnig tautschnig tautschnig approved these changes

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@kroening @tautschnig