From c6cb066df970bf4ea742c47b9c98f98aeff373e5 Mon Sep 17 00:00:00 2001
From: Daniel Kroening <dkr@amazon.com>
Date: Sun, 22 Sep 2024 09:53:21 -0700
Subject: [PATCH] Verilog: ports5 test passes

---
 regression/verilog/modules/ports5.desc | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/regression/verilog/modules/ports5.desc b/regression/verilog/modules/ports5.desc
index c5011a1e1..18a4fa264 100644
--- a/regression/verilog/modules/ports5.desc
+++ b/regression/verilog/modules/ports5.desc
@@ -1,4 +1,4 @@
-KNOWNBUG
+CORE
 ports5.sv
 --bound 0
 ^EXIT=0$
@@ -6,4 +6,3 @@ ports5.sv
 --
 ^warning: ignoring
 --
-The grammar currently doesn't allow datatypes as port types.