diff --git a/regression/verilog/modules/ports5.desc b/regression/verilog/modules/ports5.desc
index c5011a1e1..18a4fa264 100644
--- a/regression/verilog/modules/ports5.desc
+++ b/regression/verilog/modules/ports5.desc
@@ -1,4 +1,4 @@
-KNOWNBUG
+CORE
 ports5.sv
 --bound 0
 ^EXIT=0$
@@ -6,4 +6,3 @@ ports5.sv
 --
 ^warning: ignoring
 --
-The grammar currently doesn't allow datatypes as port types.