diff --git a/regression/verilog/synthesis/part_select2.desc b/regression/verilog/synthesis/part_select2.desc
new file mode 100644
index 000000000..34200b16b
--- /dev/null
+++ b/regression/verilog/synthesis/part_select2.desc
@@ -0,0 +1,9 @@
+KNOWNBUG
+part_select2.sv
+
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+The non constant index for the part select assignment is not supported.
diff --git a/regression/verilog/synthesis/part_select2.sv b/regression/verilog/synthesis/part_select2.sv
new file mode 100644
index 000000000..84793958d
--- /dev/null
+++ b/regression/verilog/synthesis/part_select2.sv
@@ -0,0 +1,14 @@
+module main(input clk, input [3:0] index);
+
+  reg [31:0] t;
+
+  always_ff @(posedge clk) begin
+    // The LHS of the part select does not have to be constant.
+    t[index*2 +: 2] = 'b01; 
+
+    // should pass
+    assert(t[index*2] == 1);
+    assert(t[index*2+1] == 0);
+  end
+
+endmodule