From 90801d378f69265e3304f28942691d3c9b258be7 Mon Sep 17 00:00:00 2001
From: Daniel Kroening <dkr@amazon.com>
Date: Sun, 20 Apr 2025 17:35:56 -0700
Subject: [PATCH] KNOWNBUG test for four-valued << and >>

---
 regression/verilog/expressions/shl3.desc |  9 +++++++++
 regression/verilog/expressions/shl3.sv   | 13 +++++++++++++
 regression/verilog/expressions/shr3.desc |  9 +++++++++
 regression/verilog/expressions/shr3.sv   | 13 +++++++++++++
 4 files changed, 44 insertions(+)
 create mode 100644 regression/verilog/expressions/shl3.desc
 create mode 100644 regression/verilog/expressions/shl3.sv
 create mode 100644 regression/verilog/expressions/shr3.desc
 create mode 100644 regression/verilog/expressions/shr3.sv

diff --git a/regression/verilog/expressions/shl3.desc b/regression/verilog/expressions/shl3.desc
new file mode 100644
index 000000000..3cd8bd35f
--- /dev/null
+++ b/regression/verilog/expressions/shl3.desc
@@ -0,0 +1,9 @@
+KNOWNBUG
+shl3.sv
+--bound 0
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+aval/bval encoding is missing.
diff --git a/regression/verilog/expressions/shl3.sv b/regression/verilog/expressions/shl3.sv
new file mode 100644
index 000000000..bd14b4397
--- /dev/null
+++ b/regression/verilog/expressions/shl3.sv
@@ -0,0 +1,13 @@
+module main;
+
+  assert final (3'b101 << 1 === 3'b010);
+  assert final ('b101 << 1 === 'b1010);
+  assert final ('b10x << 1 === 'b10x0);
+  assert final (3'b101 << 'bx === 3'bxxx);
+
+  assert final (3'b101 <<< 1 === 3'b010);
+  assert final ('b101 <<< 1 === 'b1010);
+  assert final ('b10x <<< 1 === 'b10x0);
+  assert final (3'b101 <<< 'bx === 3'bxxx);
+
+endmodule
diff --git a/regression/verilog/expressions/shr3.desc b/regression/verilog/expressions/shr3.desc
new file mode 100644
index 000000000..563495572
--- /dev/null
+++ b/regression/verilog/expressions/shr3.desc
@@ -0,0 +1,9 @@
+KNOWNBUG
+shr3.sv
+--bound 0
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+aval/bval encoding is missing.
diff --git a/regression/verilog/expressions/shr3.sv b/regression/verilog/expressions/shr3.sv
new file mode 100644
index 000000000..6f8eae5c4
--- /dev/null
+++ b/regression/verilog/expressions/shr3.sv
@@ -0,0 +1,13 @@
+module main;
+
+  assert final (3'b101 >> 1 === 3'b010);
+  assert final ('b101 >> 1 === 'b10);
+  assert final ('b1x0 >> 1 === 'b1x);
+  assert final (3'b101 >> 'bx === 3'bxxx);
+
+  assert final (3'b101 >>> 1 === 3'b010);
+  assert final ('b101 >>> 1 === 'b10);
+  assert final ('b1x0 >>> 1 === 'b1x);
+  assert final (3'b101 >>> 'bx === 3'bxxx);
+
+endmodule