Verilog: KNOWNBUG test for file in subdirectory with local include

This adds a KNOWNBUG test for the case where a Verilog file is in a
subdirectory and a local include is in the same subdirectory.

Author: kroening

regression/verilog/preprocessor/in_subdir.desc

@@ -0,0 +1,7 @@
+KNOWNBUG
+subdir/in_subdir.v
+--preprocess
+^EXIT=0$
+^SIGNAL=0$
+--
+include file in subdirectory not found

regression/verilog/preprocessor/subdir/in_subdir.v

@@ -0,0 +1 @@
+`include "include_file.vh"