Merge pull request #713 from diffblue/ports5-fixed

tautschnig · web-flow · commit b918fe082f3f · 2024-09-23T14:27:17.000+02:00
Verilog: ports5 test passes
diff --git a/regression/verilog/modules/ports5.desc b/regression/verilog/modules/ports5.desc
@@ -1,9 +1,8 @@
-KNOWNBUG
+CORE
 ports5.sv
 --bound 0
 ^EXIT=0$
 ^SIGNAL=0$
 --
 ^warning: ignoring
 --
-The grammar currently doesn't allow datatypes as port types.
