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2 parents 7cfbb43 + eae358e commit 810be55Copy full SHA for 810be55
regression/verilog/synthesis/part_select2.desc
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+KNOWNBUG
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+part_select2.sv
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+
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+^EXIT=0$
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+^SIGNAL=0$
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+--
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+^warning: ignoring
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+The non constant index for the part select assignment is not supported.
regression/verilog/synthesis/part_select2.sv
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+module main(input clk, input [3:0] index);
+ reg [31:0] t;
+ always_ff @(posedge clk) begin
+ // The LHS of the part select does not have to be constant.
+ t[index*2 +: 2] = 'b01;
+ // should pass
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+ assert(t[index*2] == 1);
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+ assert(t[index*2+1] == 0);
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+ end
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+endmodule
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