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regression/verilog/expressions/shr3.desc
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+KNOWNBUG
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+shr3.sv
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+--bound 0
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+^EXIT=0$
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+^SIGNAL=0$
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+--
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+^warning: ignoring
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+aval/bval encoding is missing.
regression/verilog/expressions/shr3.sv
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+module main;
+
+ assert final (3'b101 << 1 === 3'b010);
+ assert final ('b101 << 1 === 'b1010);
+ assert final ('b10x << 1 === 'b10x0);
+ assert final (3'b101 << 'bx === 32'hxxxx_xxxx);
+endmodule
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