AMDGPU: Switch a test to generated checks which only tested labels (llvm#131257)

Also remove an undef use

Author: arsenm

llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll

@@ -1,16 +1,58 @@
-; RUN: llc -mtriple=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn -mcpu=verde < %s | FileCheck -check-prefix=GFX6 %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GFX8 %s
 
-; CHECK-LABEL: {{^}}main:
-;
 ; Test for compilation only. This generated an invalid machine instruction
 ; by trying to commute the operands of a V_CMP_EQ_i32_e32 instruction, both
 ; of which were in SGPRs.
 define amdgpu_vs float @main(i32 %v) {
+; GFX6-LABEL: main:
+; GFX6:       ; %bb.0: ; %main_body
+; GFX6-NEXT:    s_cbranch_scc1 .LBB0_2
+; GFX6-NEXT:  ; %bb.1: ; %IF57
+; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
+; GFX6-NEXT:  .LBB0_2: ; %ENDIF56
+; GFX6-NEXT:    s_buffer_load_dword s0, s[0:3], 0xf0
+; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:    s_cmp_eq_u32 s0, 0
+; GFX6-NEXT:    s_cbranch_scc1 .LBB0_4
+; GFX6-NEXT:  ; %bb.3: ; %IF60
+; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
+; GFX6-NEXT:  .LBB0_4: ; %ENDIF59
+; GFX6-NEXT:    s_buffer_load_dword s0, s[0:3], 0xf4
+; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:    s_cmp_eq_u32 s0, 0
+; GFX6-NEXT:    s_cbranch_scc0 .LBB0_6
+; GFX6-NEXT:  ; %bb.5: ; %ENDIF62
+; GFX6-NEXT:    s_branch .LBB0_7
+; GFX6-NEXT:  .LBB0_6: ; %IF63
+; GFX6-NEXT:  .LBB0_7:
+;
+; GFX8-LABEL: main:
+; GFX8:       ; %bb.0: ; %main_body
+; GFX8-NEXT:    s_cbranch_scc1 .LBB0_2
+; GFX8-NEXT:  ; %bb.1: ; %IF57
+; GFX8-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
+; GFX8-NEXT:  .LBB0_2: ; %ENDIF56
+; GFX8-NEXT:    s_buffer_load_dword s0, s[0:3], 0x3c0
+; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:    s_cmp_eq_u32 s0, 0
+; GFX8-NEXT:    s_cbranch_scc1 .LBB0_4
+; GFX8-NEXT:  ; %bb.3: ; %IF60
+; GFX8-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
+; GFX8-NEXT:  .LBB0_4: ; %ENDIF59
+; GFX8-NEXT:    s_buffer_load_dword s0, s[0:3], 0x3d0
+; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:    s_cmp_eq_u32 s0, 0
+; GFX8-NEXT:    s_cbranch_scc0 .LBB0_6
+; GFX8-NEXT:  ; %bb.5: ; %ENDIF62
+; GFX8-NEXT:    s_branch .LBB0_7
+; GFX8-NEXT:  .LBB0_6: ; %IF63
+; GFX8-NEXT:  .LBB0_7:
 main_body:
   %d1 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> poison, i32 960, i32 0)
   %d2 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> poison, i32 976, i32 0)
-  br i1 undef, label %ENDIF56, label %IF57
+  br i1 poison, label %ENDIF56, label %IF57
 
 IF57:                                             ; preds = %ENDIF
   %v.1 = mul i32 %v, 2
@@ -40,7 +82,6 @@ ENDIF62:                                          ; preds = %ENDIF59
   ret float %r
 }
 
-; Function Attrs: nounwind readnone
 declare float @llvm.amdgcn.s.buffer.load.f32(<4 x i32>, i32, i32) #0
 
 attributes #0 = { nounwind readnone }