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shepmaster opened this issue Apr 28, 2017 · 2 comments
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Assertion failed: (MI && "No instruction defining live value"), function computeDeadValues #35

shepmaster opened this issue Apr 28, 2017 · 2 comments
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A-libcore Affects compiling the core library A-llvm Affects the LLVM AVR backend

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shepmaster commented Apr 28, 2017 •
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A reproduction:

; ModuleID = 'bugpoint-reduced-simplified.bc'
source_filename = "bugpoint-output-7b72b44.bc"
target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-n8"
target triple = "avr"

%BN1.0.5.14.17.18.19.21.26.29.31.34.40.42.57.71.80.84.89.91.95.105 = type { i16, [2 x i8], [40 x i32], [0 x i8] }

@DragonCodeAlpha = external constant [14 x i32], align 4

; Function Attrs: uwtable
define nonnull dereferenceable(164) %BN1.0.5.14.17.18.19.21.26.29.31.34.40.42.57.71.80.84.89.91.95.105* @DragonAlpha(%BN1.0.5.14.17.18.19.21.26.29.31.34.40.42.57.71.80.84.89.91.95.105* returned dereferenceable(164), i16) unnamed_addr #0 personality i32 (...)* @rust_eh_personality {
start:
  %ret.i = alloca [40 x i32], align 4
  br i1 undef, label %bb5, label %bb1

bb1:                                              ; preds = %start
  unreachable

bb5:                                              ; preds = %start
  %2 = icmp eq i16 undef, 0
  br i1 %2, label %bb10, label %bb8

bb8:                                              ; preds = %bb5
  unreachable

bb10:                                             ; preds = %bb5
  %3 = bitcast [40 x i32]* %ret.i to i8*
  %4 = load i16, i16* undef, align 2
  %5 = getelementptr inbounds %BN1.0.5.14.17.18.19.21.26.29.31.34.40.42.57.71.80.84.89.91.95.105, %BN1.0.5.14.17.18.19.21.26.29.31.34.40.42.57.71.80.84.89.91.95.105* %0, i16 0, i32 2, i16 0
  br i1 undef, label %bb2.i38, label %bb3.i39

bb2.i38:                                          ; preds = %bb10
  %6 = getelementptr inbounds %BN1.0.5.14.17.18.19.21.26.29.31.34.40.42.57.71.80.84.89.91.95.105, %BN1.0.5.14.17.18.19.21.26.29.31.34.40.42.57.71.80.84.89.91.95.105* %0, i16 0, i32 2, i16 %4
  br label %bb4.outer.i122

bb4.outer.i122:                                   ; preds = %bb24.i141, %bb2.i38
  %iter.sroa.7.0.ph.i120 = phi i16 [ %8, %bb24.i141 ], [ 0, %bb2.i38 ]
  %retsz.0.ph.i121 = phi i16 [ %.retsz.0.i140, %bb24.i141 ], [ 0, %bb2.i38 ]
  br label %bb4.i125

bb4.i125:                                         ; preds = %EnumerateAlpha, %bb4.outer.i122
  %iter.sroa.7.0.i124 = phi i16 [ %8, %EnumerateAlpha ], [ %iter.sroa.7.0.ph.i120, %bb4.outer.i122 ]
  %7 = icmp eq i32* undef, %6
  br i1 %7, label %_ZN4core3num6bignum8Big32x4010mul_digits17hb016ab455b44b71bE.exit44, label %EnumerateAlpha

EnumerateAlpha:                                   ; preds = %bb4.i125
  %8 = add i16 %iter.sroa.7.0.i124, 1
  %9 = icmp eq i32 undef, 0
  br i1 %9, label %bb4.i125, label %EnumerateBeta

EnumerateBeta:                                    ; preds = %EnumerateAlpha
  %10 = zext i32 undef to i64
  br label %EnumerateGamma

EnumerateGamma:                                   ; preds = %EnumerateBeta
  %11 = icmp ult i16 undef, 40
  br i1 %11, label %SliceMutAlpha, label %panic.i.i14.i134, !prof !0

bb16.i133:                                        ; preds = %SliceMutAlpha
  br i1 undef, label %bb24.i141, label %bb21.i136

panic.i.i14.i134:                                 ; preds = %EnumerateGamma
  unreachable

SliceMutAlpha:                                    ; preds = %EnumerateGamma
  %12 = load i32, i32* undef, align 4, !alias.scope !1, !noalias !4
  %13 = zext i32 %12 to i64
  %14 = mul nuw i64 %13, %10
  %15 = add i64 0, %14
  %16 = lshr i64 %15, 32
  %17 = trunc i64 %15 to i32
  store i32 %17, i32* undef, align 4, !noalias !6
  br label %bb16.i133

bb21.i136:                                        ; preds = %bb16.i133
  br i1 undef, label %SliceMutBeta, label %panic.i.i.i137, !prof !0

panic.i.i.i137:                                   ; preds = %bb21.i136
  unreachable

SliceMutBeta:                                     ; preds = %bb21.i136
  br label %bb24.i141

bb24.i141:                                        ; preds = %SliceMutBeta, %bb16.i133
  %18 = add i16 0, %iter.sroa.7.0.i124
  %19 = icmp ult i16 %retsz.0.ph.i121, %18
  %.retsz.0.i140 = select i1 %19, i16 %18, i16 %retsz.0.ph.i121
  br label %bb4.outer.i122

bb3.i39:                                          ; preds = %bb10
  %20 = call fastcc i16 @BignumInnerAlpha([40 x i32]* nonnull dereferenceable(160) %ret.i, i32* noalias nonnull readonly getelementptr inbounds ([14 x i32], [14 x i32]* @DragonCodeAlpha, i16 0, i16 0), i16 14, i32* noalias nonnull readonly %5, i16 %4)
  br label %_ZN4core3num6bignum8Big32x4010mul_digits17hb016ab455b44b71bE.exit44

_ZN4core3num6bignum8Big32x4010mul_digits17hb016ab455b44b71bE.exit44: ; preds = %bb3.i39, %bb4.i125
  %retsz.0.i40 = phi i16 [ %20, %bb3.i39 ], [ %retsz.0.ph.i121, %bb4.i125 ]
  %21 = getelementptr inbounds %BN1.0.5.14.17.18.19.21.26.29.31.34.40.42.57.71.80.84.89.91.95.105, %BN1.0.5.14.17.18.19.21.26.29.31.34.40.42.57.71.80.84.89.91.95.105* %0, i16 0, i32 2
  %22 = bitcast [40 x i32]* %21 to i8*
  call void @llvm.memcpy.p0i8.p0i8.i16(i8* %22, i8* nonnull %3, i16 160, i32 4, i1 false), !noalias !7
  store i16 %retsz.0.i40, i16* undef, align 2, !noalias !7
  %23 = and i16 %1, 256
  %24 = icmp eq i16 %23, 0
  br i1 %24, label %bb30, label %bb27

bb27:                                             ; preds = %_ZN4core3num6bignum8Big32x4010mul_digits17hb016ab455b44b71bE.exit44
  unreachable

bb30:                                             ; preds = %_ZN4core3num6bignum8Big32x4010mul_digits17hb016ab455b44b71bE.exit44
  ret %BN1.0.5.14.17.18.19.21.26.29.31.34.40.42.57.71.80.84.89.91.95.105* %0
}

; Function Attrs: uwtable
declare fastcc i16 @BignumInnerAlpha([40 x i32]* nocapture dereferenceable(160), i32* noalias nonnull readonly, i16, i32* noalias nonnull readonly, i16) unnamed_addr #0

; Function Attrs: argmemonly nounwind
declare void @llvm.memcpy.p0i8.p0i8.i16(i8* nocapture writeonly, i8* nocapture readonly, i16, i32, i1) #1

declare i32 @rust_eh_personality(...) unnamed_addr

attributes #0 = { uwtable }
attributes #1 = { argmemonly nounwind }

!0 = !{!"branch_weights", i32 2000, i32 1}
!1 = !{!2}
!2 = distinct !{!2, !3, !"BignumInnerAlpha: argument 1"}
!3 = distinct !{!3, !"BignumInnerAlpha"}
!4 = !{!5}
!5 = distinct !{!5, !3, !"BignumInnerAlpha: argument 0"}
!6 = !{!5, !2}
!7 = !{!8}
!8 = distinct !{!8, !9, !"_ZN4core3num6bignum8Big32x4010mul_digits17hb016ab455b44b71bE: argument 0"}
!9 = distinct !{!9, !"_ZN4core3num6bignum8Big32x4010mul_digits17hb016ab455b44b71bE"}
@shepmaster shepmaster added A-libcore Affects compiling the core library A-llvm Affects the LLVM AVR backend labels Apr 28, 2017
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@dylanmckay ready for you to work your magic ;-)

@shepmaster
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Oops, this is #26, just with better information

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