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This repository was archived by the owner on Sep 2, 2018. It is now read-only.
A hierarchy needs to be identified. We cannot have a predicate for every register and every function, and manually add each one by enumerating the datasheet for every MCU.
Patterns need to be identified
Do all MCUs with SRAM have push/pop/etc?
Does the presence of MUL imply MULS and MULSU?
Does MUL[s][u] imply FMUL[s][u]?`
Does AVR-GCC's license allow us to use their subtarget feature code as a resource/reference?
Rewrite subtarget feature code so that it works correctly.
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