@@ -1479,7 +1479,6 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF,
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bool CS1Spilled = false ;
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bool LRSpilled = false ;
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unsigned NumGPRSpills = 0 ;
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- unsigned NumFPRSpills = 0 ;
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SmallVector<unsigned , 4 > UnspilledCS1GPRs;
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SmallVector<unsigned , 4 > UnspilledCS2GPRs;
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const ARMBaseRegisterInfo *RegInfo = static_cast <const ARMBaseRegisterInfo *>(
@@ -1534,17 +1533,8 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF,
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CanEliminateFrame = false ;
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}
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- if (!ARM::GPRRegClass.contains (Reg)) {
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- if (Spilled) {
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- if (ARM::SPRRegClass.contains (Reg))
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- NumFPRSpills++;
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- else if (ARM::DPRRegClass.contains (Reg))
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- NumFPRSpills += 2 ;
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- else if (ARM::QPRRegClass.contains (Reg))
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- NumFPRSpills += 4 ;
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- }
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+ if (!ARM::GPRRegClass.contains (Reg))
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continue ;
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- }
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if (Spilled) {
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NumGPRSpills++;
@@ -1617,14 +1607,11 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF,
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// FIXME: We could add logic to be more precise about negative offsets
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// and which instructions will need a scratch register for them. Is it
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// worth the effort and added fragility?
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- auto ArgStackSize = MF.getInfo <ARMFunctionInfo>()->getArgumentStackSize ();
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- bool BigStack =
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- (RS && (MFI->estimateStackSize (MF) + 4 * (NumGPRSpills + NumFPRSpills) +
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- (!hasFP (MF) ? ArgStackSize : 0 ) + 16 /* possible paddings */ +
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- ((hasFP (MF) && AFI->hasStackFrame ()) ? 4 : 0 ) >=
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- estimateRSStackSizeLimit (MF, this ))) ||
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- MFI->hasVarSizedObjects () ||
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- (MFI->adjustsStack () && !canSimplifyCallFramePseudos (MF));
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+ bool BigStack = (RS && (MFI->estimateStackSize (MF) +
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+ ((hasFP (MF) && AFI->hasStackFrame ()) ? 4 : 0 ) >=
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+ estimateRSStackSizeLimit (MF, this ))) ||
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+ MFI->hasVarSizedObjects () ||
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+ (MFI->adjustsStack () && !canSimplifyCallFramePseudos (MF));
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bool ExtraCSSpill = false ;
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if (BigStack || !CanEliminateFrame || RegInfo->cannotEliminateFrame (MF)) {
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