@@ -3,11 +3,34 @@ extern "C" {
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#include " ram_internal.h"
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}
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+ static void MPU_Config () {
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+ MPU_Region_InitTypeDef MPU_InitStruct;
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+
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+ /* Disable the MPU */
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+ HAL_MPU_Disable ();
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+
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+ // Initialize SDRAM Start as shareable
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+ MPU_InitStruct.Enable = MPU_REGION_ENABLE;
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+ MPU_InitStruct.BaseAddress = SDRAM_START_ADDRESS;
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+ MPU_InitStruct.Size = ARM_MPU_REGION_SIZE_8MB;
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+ // MPU_InitStruct.SubRegionDisable = 0x00;
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+ MPU_InitStruct.Number = MPU_REGION_NUMBER5;
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+ MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
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+ MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
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+ MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
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+ MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
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+ MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
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+ MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
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+
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+ HAL_MPU_ConfigRegion (&MPU_InitStruct);
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+
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+ /* Enable the MPU */
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+ HAL_MPU_Enable (MPU_PRIVILEGED_DEFAULT);
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+ }
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+
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int SDRAMClass::begin (uint32_t start_address) {
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- printf (" FMC_SDRAM_DEVICE->SDCMR: %x\n " , FMC_SDRAM_DEVICE->SDCMR );
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if (FMC_SDRAM_DEVICE->SDCMR == 0x00000000U ) {
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- printf (" initializing external ram\n " );
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bool ret = sdram_init ();
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if (ret == false ) {
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return 0 ;
@@ -18,51 +41,16 @@ int SDRAMClass::begin(uint32_t start_address) {
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then enable access/caching for the size used
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*/
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- if (SDRAM_START_ADDRESS != 0xC0000000 ) {
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- printf (" remap ram to 0x60000000\n " );
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+ if (SDRAM_START_ADDRESS == 0x60000000 ) {
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HAL_SetFMCMemorySwappingConfig (FMC_SWAPBMAP_SDRAM_SRAM);
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}
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- #if 0
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-
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- printf("setup mpu\n");
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- #define MPU_SDRAM_EXEC_REGION_NUMBER MPU_REGION_SDRAM1
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- #define MPU_SDRAM_REGION_TEX (0x4 << MPU_RASR_TEX_Pos) /* Cached memory */
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- #define MPU_SDRAM_EXEC_REGION_SIZE (22 << MPU_RASR_SIZE_Pos) /* 2^(22+1) = 8Mo */
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- #define MPU_SDRAM_ACCESS_PERMSSION (0x03UL << MPU_RASR_AP_Pos)
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- #define MPU_SDRAM_REGION_CACHABLE (0x01UL << MPU_RASR_C_Pos)
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- #define MPU_SDRAM_REGION_BUFFERABLE (0x01UL << MPU_RASR_B_Pos)
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-
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- MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
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- /* Configure SDARM region as first region */
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- MPU->RNR = MPU_SDRAM_EXEC_REGION_NUMBER;
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- /* Set MPU SDARM base address (0xD0000000) */
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- MPU->RBAR = SDRAM_START_ADDRESS;
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- /*
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- - Execute region: RASR[size] = 22 -> 2^(22+1) -> size 8MB
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- - Access permission: Full access: RASR[AP] = 0b011
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- - Cached memory: RASR[TEX] = 0b0100
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- - Disable the Execute Never option: to allow the code execution on SDRAM: RASR[XN] = 0
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- - Enable the region MPU: RASR[EN] = 1
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- */
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- MPU->RASR = (MPU_SDRAM_EXEC_REGION_SIZE | MPU_SDRAM_ACCESS_PERMSSION | MPU_SDRAM_REGION_TEX | \
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- MPU_RASR_ENABLE_Msk | MPU_SDRAM_REGION_BUFFERABLE) & ~MPU_RASR_XN_Msk ;
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-
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- /* Enable MPU and leave the predefined regions to default configuration */
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- MPU->CTRL |= MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_ENABLE_Msk;
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- #endif
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-
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- #if 0
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- mpu_config_start();
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- mpu_config_region(MPU_REGION_SDRAM1, SDRAM_START_ADDRESS, MPU_CONFIG_DISABLE(0x00, MPU_REGION_SIZE_512MB));
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- mpu_config_region(MPU_REGION_SDRAM2, SDRAM_START_ADDRESS, MPU_CONFIG_SDRAM(SDRAM_MPU_REGION_SIZE));
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- mpu_config_end();
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- #endif
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-
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+ #ifdef CORE_CM4
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+ MPU_Config ();
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+ #endif
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}
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if (start_address) {
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- printf (" malloc_addblock: allocate %d bytes\n " , SDRAM_END_ADDRESS - start_address);
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malloc_addblock ((void *)start_address, SDRAM_END_ADDRESS - start_address);
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}
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@@ -77,7 +65,7 @@ void SDRAMClass::free(void* ptr) {
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ea_free (ptr);
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}
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- bool __attribute__ ((optimize(" O0" ))) SDRAMClass::test(bool fast) {
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+ bool __attribute__ ((optimize(" O0" ))) SDRAMClass::test(bool fast, Stream& _serial ) {
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uint8_t const pattern = 0xaa ;
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uint8_t const antipattern = 0x55 ;
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uint8_t *const mem_base = (uint8_t *)SDRAM_START_ADDRESS;
@@ -86,7 +74,7 @@ bool __attribute__((optimize("O0"))) SDRAMClass::test(bool fast) {
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for (uint8_t i = 1 ; i; i <<= 1 ) {
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*mem_base = i;
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if (*mem_base != i) {
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- printf (" data bus lines test failed! data (%d) \n " , i );
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+ _serial. println (" data bus lines test failed! data (" + String (i) + " ) " );
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__asm__ volatile (" BKPT" );
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}
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}
@@ -96,7 +84,7 @@ bool __attribute__((optimize("O0"))) SDRAMClass::test(bool fast) {
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for (uint32_t i = 1 ; i < HW_SDRAM_SIZE; i <<= 1 ) {
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mem_base[i] = pattern;
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if (mem_base[i] != pattern) {
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- printf (" address bus lines test failed! address (%p) \n " , &mem_base[i]);
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+ _serial. println (" address bus lines test failed! address (" + String (( uint32_t ) &mem_base[i], HEX) + " ) " );
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__asm__ volatile (" BKPT" );
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}
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}
@@ -105,7 +93,7 @@ bool __attribute__((optimize("O0"))) SDRAMClass::test(bool fast) {
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mem_base[0 ] = antipattern;
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for (uint32_t i = 1 ; i < HW_SDRAM_SIZE; i <<= 1 ) {
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if (mem_base[i] != pattern) {
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- printf (" address bus overlap %p \n " , &mem_base[i]);
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+ _serial. println (" address bus overlap! address ( " + String (( uint32_t ) &mem_base[i], HEX) + " ) " );
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__asm__ volatile (" BKPT" );
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}
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}
@@ -115,7 +103,7 @@ bool __attribute__((optimize("O0"))) SDRAMClass::test(bool fast) {
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for (uint32_t i = 0 ; i < HW_SDRAM_SIZE; ++i) {
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mem_base[i] = pattern;
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if (mem_base[i] != pattern) {
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- printf (" address bus test failed! address (%p) \n " , &mem_base[i]);
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+ _serial. println (" address bus test failed! address (" + String (( uint32_t ) &mem_base[i], HEX) + " ) " );
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__asm__ volatile (" BKPT" );
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}
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}
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