diff --git a/docs/library/axi_ad35xxr/index.rst b/docs/library/axi_ad35xxr/index.rst index df87921c9e8..8169243ec1a 100644 --- a/docs/library/axi_ad35xxr/index.rst +++ b/docs/library/axi_ad35xxr/index.rst @@ -150,18 +150,44 @@ the 16 LSBs -- The 4 LSBs of this word are 0's for the 12-bit accuracy. Register Map -------------------------------------------------------------------------------- +The register map of the core contains instances of several generic register maps +like DAC common, DAC channel. +The following table presents the base addresses of each instance, after it you +can find the detailed description of each generic register map. + For the AXI_AD3XXR control used registers from DAC Common are: .. hdl-regmap:: :name: AXI_AD35XXR_DAC_COMMON - For the AXI_AD35XXR control used registers from DAC Channel are: .. hdl-regmap:: :name: AXI_AD35XXR_DAC_CHANNEL -For reference, all the register map templates are: +The absolute address of a register should be calculated by adding the instance +base address to the registers relative address. For a more detailed explanation, +see :ref:`DAC register access `. + +.. list-table:: Register Map base addresses for axi_ad35xxr + :header-rows: 1 + + * - HDL reg + - Software reg + - Name + - Description + * - 0x0000 + - 0x0000 + - BASE + - See the `Base <#hdl-regmap-COMMON>`__ table for more details. + * - 0x0000 + - 0x0000 + - TX COMMON + - See the `DAC Common <#hdl-regmap-DAC_COMMON>`__ table for more details. + * - 0x0000 + - 0x0000 + - TX CHANNELS + - See the `DAC Channel <#hdl-regmap-DAC_CHANNEL>`__ table for more details. .. hdl-regmap:: :name: COMMON diff --git a/docs/library/axi_ad408x/index.rst b/docs/library/axi_ad408x/index.rst index 12d42e62b48..aa22ea24449 100644 --- a/docs/library/axi_ad408x/index.rst +++ b/docs/library/axi_ad408x/index.rst @@ -122,13 +122,14 @@ The following table presents the base addresses of each instance, after it you can find the detailed description of each generic register map. The absolute address of a register should be calculated by adding the instance -base address to the registers relative address. +base address to the registers relative address. For a more detailed explanation, +see :ref:`ADC register access `. .. list-table:: Register Map base addresses for axi_ad408x :header-rows: 1 - * - DWORD - - BYTE + * - HDL reg + - Software reg - Name - Description * - 0x0000 diff --git a/docs/library/axi_ad485x/index.rst b/docs/library/axi_ad485x/index.rst index 81885dd5b90..a0996ad01f0 100644 --- a/docs/library/axi_ad485x/index.rst +++ b/docs/library/axi_ad485x/index.rst @@ -302,14 +302,16 @@ The register map of the core contains instances of several generic register maps like ADC common, ADC channel, :git-hdl:`up_delay_ctrl `. The following table presents the base addresses of each instance, after it you can find the detailed description of each generic register map. + The absolute address of a register should be calculated by adding the instance -base address to the registers relative address. +base address to the registers relative address. For a more detailed explanation, +see :ref:`ADC register access `. .. list-table:: Register Map base addresses for axi_ad485x :header-rows: 1 - * - DWORD - - BYTE + * - HDL reg + - Software reg - Name - Description * - 0x0000 diff --git a/docs/library/axi_ad7405/index.rst b/docs/library/axi_ad7405/index.rst index 955cfbe2ca0..2ddba25b317 100644 --- a/docs/library/axi_ad7405/index.rst +++ b/docs/library/axi_ad7405/index.rst @@ -57,9 +57,33 @@ Register Map -------------------------------------------------------------------------------- The register map of the core contains instances of several generic register maps -like ADC common, ADC channel or PWM Generator. The following table presents the -base addresses of each instance, after that can be found the detailed -description of each generic register map. +like ADC common, ADC channel. +The following table presents the base addresses of each instance, after it you +can find the detailed description of each generic register map. + +The absolute address of a register should be calculated by adding the instance +base address to the registers relative address. For a more detailed explanation, +see :ref:`ADC register access `. + +.. list-table:: Register Map base addresses for axi_ad7405 + :header-rows: 1 + + * - HDL reg + - Software reg + - Name + - Description + * - 0x0000 + - 0x0000 + - BASE + - See the `Base <#hdl-regmap-COMMON>`__ table for more details. + * - 0x0000 + - 0x0000 + - RX COMMON + - See the `ADC Common <#hdl-regmap-ADC_COMMON>`__ table for more details. + * - 0x0000 + - 0x0000 + - RX CHANNELS + - See the `ADC Channel <#hdl-regmap-ADC_CHANNEL>`__ table for more details. .. hdl-regmap:: :name: COMMON diff --git a/docs/library/axi_ad7606x/index.rst b/docs/library/axi_ad7606x/index.rst index 4f72b60b534..c7569aa6520 100644 --- a/docs/library/axi_ad7606x/index.rst +++ b/docs/library/axi_ad7606x/index.rst @@ -89,9 +89,33 @@ Register Map -------------------------------------------------------------------------------- The register map of the core contains instances of several generic register maps -like ADC common, ADC channel or PWM Generator. The following table presents the -base addresses of each instance, after that can be found the detailed -description of each generic register map. +like ADC common, ADC channel. +The following table presents the base addresses of each instance, after it you +can find the detailed description of each generic register map. + +The absolute address of a register should be calculated by adding the instance +base address to the registers relative address. For a more detailed explanation, +see :ref:`ADC register access `. + +.. list-table:: Register Map base addresses for axi_ad7606x + :header-rows: 1 + + * - HDL reg + - Software reg + - Name + - Description + * - 0x0000 + - 0x0000 + - BASE + - See the `Base <#hdl-regmap-COMMON>`__ table for more details. + * - 0x0000 + - 0x0000 + - RX COMMON + - See the `ADC Common <#hdl-regmap-ADC_COMMON>`__ table for more details. + * - 0x0000 + - 0x0000 + - RX CHANNELS + - See the `ADC Channel <#hdl-regmap-ADC_CHANNEL>`__ table for more details. .. hdl-regmap:: :name: COMMON diff --git a/docs/library/axi_ad7616/index.rst b/docs/library/axi_ad7616/index.rst index 697acf5fe7e..00e5abda631 100644 --- a/docs/library/axi_ad7616/index.rst +++ b/docs/library/axi_ad7616/index.rst @@ -83,9 +83,33 @@ Register Map -------------------------------------------------------------------------------- The register map of the core contains instances of several generic register maps -like ADC common, ADC channel or PWM Generator. The following table presents the -base addresses of each instance, after that can be found the detailed -description of each generic register map. +like ADC common, ADC channel. +The following table presents the base addresses of each instance, after it you +can find the detailed description of each generic register map. + +The absolute address of a register should be calculated by adding the instance +base address to the registers relative address. For a more detailed explanation, +see :ref:`ADC register access `. + +.. list-table:: Register Map base addresses for axi_ad7616 + :header-rows: 1 + + * - HDL reg + - Software reg + - Name + - Description + * - 0x0000 + - 0x0000 + - BASE + - See the `Base <#hdl-regmap-COMMON>`__ table for more details. + * - 0x0000 + - 0x0000 + - RX COMMON + - See the `ADC Common <#hdl-regmap-ADC_COMMON>`__ table for more details. + * - 0x0000 + - 0x0000 + - RX CHANNELS + - See the `ADC Channel <#hdl-regmap-ADC_CHANNEL>`__ table for more details. .. hdl-regmap:: :name: COMMON diff --git a/docs/library/axi_ad7768/index.rst b/docs/library/axi_ad7768/index.rst index 98714676ec8..4c394eb0bc6 100644 --- a/docs/library/axi_ad7768/index.rst +++ b/docs/library/axi_ad7768/index.rst @@ -119,6 +119,35 @@ basic monitoring and control of the ADC's channel. Register Map -------------------------------------------------------------------------------- +The register map of the core contains instances of several generic register maps +like ADC common, ADC channel. +The following table presents the base addresses of each instance, after it you +can find the detailed description of each generic register map. + +The absolute address of a register should be calculated by adding the instance +base address to the registers relative address. For a more detailed explanation, +see :ref:`ADC register access `. + +.. list-table:: Register Map base addresses for axi_ad7768 + :header-rows: 1 + + * - HDL reg + - Software reg + - Name + - Description + * - 0x0000 + - 0x0000 + - BASE + - See the `Base <#hdl-regmap-COMMON>`__ table for more details. + * - 0x0000 + - 0x0000 + - RX COMMON + - See the `ADC Common <#hdl-regmap-ADC_COMMON>`__ table for more details. + * - 0x0000 + - 0x0000 + - RX CHANNELS + - See the `ADC Channel <#hdl-regmap-ADC_CHANNEL>`__ table for more details. + .. hdl-regmap:: :name: COMMON :no-type-info: @@ -131,6 +160,7 @@ Register Map :name: ADC_CHANNEL :no-type-info: + Design Guidelines -------------------------------------------------------------------------------- diff --git a/docs/library/axi_ad777x/index.rst b/docs/library/axi_ad777x/index.rst index fb6a2e5dbe8..3f63c788819 100644 --- a/docs/library/axi_ad777x/index.rst +++ b/docs/library/axi_ad777x/index.rst @@ -114,6 +114,35 @@ basic monitoring and control of the ADC's channel. Register Map -------------------------------------------------------------------------------- +The register map of the core contains instances of several generic register maps +like ADC common, ADC channel. +The following table presents the base addresses of each instance, after it you +can find the detailed description of each generic register map. + +The absolute address of a register should be calculated by adding the instance +base address to the registers relative address. For a more detailed explanation, +see :ref:`ADC register access `. + +.. list-table:: Register Map base addresses for axi_ad777x + :header-rows: 1 + + * - HDL reg + - Software reg + - Name + - Description + * - 0x0000 + - 0x0000 + - BASE + - See the `Base <#hdl-regmap-COMMON>`__ table for more details. + * - 0x0000 + - 0x0000 + - RX COMMON + - See the `ADC Common <#hdl-regmap-ADC_COMMON>`__ table for more details. + * - 0x0000 + - 0x0000 + - RX CHANNELS + - See the `ADC Channel <#hdl-regmap-ADC_CHANNEL>`__ table for more details. + .. hdl-regmap:: :name: COMMON :no-type-info: diff --git a/docs/library/axi_ad9144/index.rst b/docs/library/axi_ad9144/index.rst deleted file mode 100644 index 0f6b146dfb3..00000000000 --- a/docs/library/axi_ad9144/index.rst +++ /dev/null @@ -1,182 +0,0 @@ -.. _axi_ad9144: - -AXI AD9144 (OBSOLETE) -================================================================================ - -.. warning:: - - The support for :git-hdl:`AXI AD9144 ` - has been discontinued, the latest tested release being ``hdl_2019_r2``. - This page is for legacy purposes only. - -The :git-hdl:`AXI AD9144 ` IP core can be used -to interface the :adi:`AD9144` DAC. An AXI Memory Map interface is used for -configuration. Data is sent in a format that can be transmitted by AMD Xilinx's -JESD IP. - -More about the generic framework interfacing DACs, can be read in :ref:`axi_adc`. - -Features --------------------------------------------------------------------------------- - -* AXI based configuration -* Hardware PRBS generation -* Hardware DDS generation -* Xilinx Vivado compatible -* Altera Quartus compatible - -Files --------------------------------------------------------------------------------- - -.. list-table:: - :header-rows: 1 - - * - Name - - Description - * - :git-hdl:`hdl_2019_r2:library/axi_ad9144/axi_ad9144.v` - - Verilog source for the AXI AD9144. - * - :git-hdl:`hdl_2019_r2:library/axi_ad9144/axi_ad9144_ip.tcl` - - TCL script to generate the Vivado IP-integrator project. - * - :git-hdl:`hdl_2019_r2:library/axi_ad9144/axi_ad9144_hw.tcl` - - TCL script to generate the Quartus IP-integrator project. - * - :git-hdl:`hdl_2019_r2:library/axi_ad9144/axi_ad9144_constr.xdc` - - Constraint file of the IP. - -Block Diagram --------------------------------------------------------------------------------- - -.. image:: block_diagram.svg - :alt: AXI AD9144 block diagram - :align: center - -Configuration Parameters --------------------------------------------------------------------------------- - -.. list-table:: - :header-rows: 1 - - * - ID - - Core ID should be unique for each IP in the system - * - QUAD_OR_DUAL_N - - Selects if 4 lanes (1) or 2 lanes (0) are connected - * - DAC_DATAPATH_DISABLE - - The delay group name which is set for the delay controller - -Interface --------------------------------------------------------------------------------- - -.. list-table:: - :header-rows: 1 - - * - jesd_interface - - Data to be connected to the JESD core - * - s_axi - - Standard AXI Slave Memory Map interface - * - dma_interface - - FIFO interface for connecting to the DMA - * - dac_clk - - Loopback of the tx_clk. Most of the modules of the core run on this clock - * - dac_enable - - Set when the channel is enabled, activated by software - * - dac_valid - - Set when valid data is available on the bus - * - adc_enable - - Set when the channel is enabled, activated by software - * - dac_ddata - - Data for channel samples - * - dac_dovf - - Data overflow input - * - dac_dunf - - Data underflow input - -Detailed Architecture --------------------------------------------------------------------------------- - -.. image:: detailed_architecture.svg - :alt: AXI AD9144 detailed architecture - :align: center - -Detailed Description --------------------------------------------------------------------------------- - -The top module, axi_ad9144, instantiates: - -* the JESD204B interface module -* the DAC core module -* the AXI handling interface - -The JESD204B interface module handles the serialization and deserialization of -data to and from the DAC, ensuring proper data alignment and timing for -high-speed communication. - -The DAC core module includes: - -* Data path for digital-to-analog conversion PRBS (Pseudo-Random Binary - Sequence) generation for testing -* DDS (Direct Digital Synthesis) for generating sine waves and other waveforms -* Fixed pattern generators for consistent test signals - -The AXI handling interface manages the communication between the DAC and the -system's AXI bus, facilitating efficient data transfer and control. - -Register Map --------------------------------------------------------------------------------- - -.. hdl-regmap:: - :name: COMMON - :no-type-info: - -.. hdl-regmap:: - :name: DAC_COMMON - :no-type-info: - -.. hdl-regmap:: - :name: DAC_CHANNEL - :no-type-info: - -.. hdl-regmap:: - :name: JESD_TPL - :no-type-info: - -Design Guidelines --------------------------------------------------------------------------------- - -The IP was developed part of the -:dokuwiki+deprecated:`[Wiki] AD9144 Evaluation Boards `. - -The control of the :git-hdl:`AXI AD9144 ` chip -is done through a SPI interface, using ACE software. The ACE -(Analysis - Control- Evaluate) software provides a graphical user interface for -configuring and controlling the :adi:`AD9144`, allowing for easy setup and -evaluation of the DAC's performance. - -.. warning:: - We **do not** offer support for ACE anymore. Limited support is available. - -Software Support --------------------------------------------------------------------------------- - -* Linux device driver at :git-linux:`2019_R2:drivers/iio/frequency/ad9144.c` -* Linux device tree at: - - * :git-linux:`2019_R2:arch/arm64/boot/dts/xilinx/adi-ad9144-fmc-ebz.dtsi` - * :git-linux:`2019_R2:arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9144-fmc-ebz.dts` - -* No-OS device driver at: - - * :git-no-os:`2019_r2:drivers/dac/ad9144/ad9144.c` - * :git-no-os:`2019_r2:drivers/dac/ad9144/iio_ad9144.c` - -* No-OS project at :git-no-os:`2019_r2:drivers/dac/ad9144` - -References --------------------------------------------------------------------------------- - -* HDL IP core at :git-hdl:`hdl_2019_r2:library/axi_ad9144` -* :adi:`AD9144` -* :dokuwiki+deprecated:`[Wiki] Evaluating the AD9144 DIGITAL-TO-ANALOG converter ` -* :dokuwiki+deprecated:`[Wiki] AD9144-ADRF6720-EBZ Evaluation Board Quick Start Guide ` -* :dokuwiki+deprecated:`[Wiki] AD9144-EBZ Evaluation Board Quick Start Guide ` -* :dokuwiki+deprecated:`[Wiki] AD9144-FMC-EBZ Evaluation Board Quick Start Guide ` -* :dokuwiki+deprecated:`[Wiki] AD9144-EBZ Evaluation Board Quick Start Guide Using ACE (Analysis | Control | Evaluate) Software ` -* :xilinx:`7 Series libraries ` diff --git a/docs/library/axi_ad9265/index.rst b/docs/library/axi_ad9265/index.rst index 5c81de21642..63c4ff8c69f 100644 --- a/docs/library/axi_ad9265/index.rst +++ b/docs/library/axi_ad9265/index.rst @@ -141,6 +141,35 @@ monitoring the PRBS sequence. Register Map -------------------------------------------------------------------------------- +The register map of the core contains instances of several generic register maps +like ADC common, ADC channel. +The following table presents the base addresses of each instance, after it you +can find the detailed description of each generic register map. + +The absolute address of a register should be calculated by adding the instance +base address to the registers relative address. For a more detailed explanation, +see :ref:`ADC register access `. + +.. list-table:: Register Map base addresses for axi_ad9265 + :header-rows: 1 + + * - HDL reg + - Software reg + - Name + - Description + * - 0x0000 + - 0x0000 + - BASE + - See the `Base <#hdl-regmap-COMMON>`__ table for more details. + * - 0x0000 + - 0x0000 + - RX COMMON + - See the `ADC Common <#hdl-regmap-ADC_COMMON>`__ table for more details. + * - 0x0000 + - 0x0000 + - RX CHANNELS + - See the `ADC Channel <#hdl-regmap-ADC_CHANNEL>`__ table for more details. + .. hdl-regmap:: :name: COMMON :no-type-info: diff --git a/docs/library/axi_ad9361/index.rst b/docs/library/axi_ad9361/index.rst index 7758a6edb76..e7cdc24929b 100644 --- a/docs/library/axi_ad9361/index.rst +++ b/docs/library/axi_ad9361/index.rst @@ -370,17 +370,21 @@ Register Map -------------------------------------------------------------------------------- The register map of the core contains instances of several generic register maps -like ADC common, ADC channel, DAC common, DAC channel etc. The following table -presents the base addresses of each instance, after that can be found the -detailed description of each generic register map. The absolute address of a -register should be calculated by adding the instance base address to the -registers relative address. +like ADC common, ADC channel, DAC common, DAC channel etc. +The following table presents the base addresses of each instance, after that can +be found the detailed description of each generic register map. + +The absolute address of a register should be calculated by adding the instance +base address to the registers relative address. For a more detailed explanation, +see :ref:`ADC register access ` and +:ref:`DAC register access `. + .. list-table:: Register Map base addresses for axi_ad9361 :header-rows: 1 - * - DWORD - - BYTE + * - HDL reg + - Software reg - Name - Description * - 0x0000 diff --git a/docs/library/axi_ad9371/block_diagram.svg b/docs/library/axi_ad9371/block_diagram.svg deleted file mode 100644 index 05b7e5959db..00000000000 --- a/docs/library/axi_ad9371/block_diagram.svg +++ /dev/null @@ -1,1389 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - image/svg+xml - - - - - - - - - AD9371 INTERFACE - - DAC_CLK - - DAC_DATA - - ADC_CLK - - ADC_SOF - - ADC_DATA - - - - - - ADC CHANNEL - - - - - - - - - - - - - - IQ Corr - DC Filter - - - - - - - - ADC CORE - - - - - - - - IQC - - - - PATTERN - - DDS - - - DMA - - - - - DAC CHANNEL - - - - - DAC CORE - - - - - - - - - - - - - - - - - - - - - DAC_FIFO_I0 - DAC_FIFO_Q0 - DAC_FIFO_I1 - DAC_FIFO_Q1 - ADC_FIFO_I0 - ADC_FIFO_Q0 - ADC_FIFO_I1 - ADC_FIFO_Q1 - - - Register Map - - - - S_AXI_MM - - - - - - - - - DAC core frame - - - - ADC OS CHANNEL - ADC OS CORE - - - - - - - - - - - - - - - - - - IQ Corr - - - DC Filter - - - - - - - - - - - ADC_OS_FIFO_I0 - ADC_OS_FIFO_Q0 - - ADC_OS_CLK - - ADC_OS_SOF - - ADC_OS_DATA - - diff --git a/docs/library/axi_ad9371/index.rst b/docs/library/axi_ad9371/index.rst deleted file mode 100644 index 5531f27c7b2..00000000000 --- a/docs/library/axi_ad9371/index.rst +++ /dev/null @@ -1,285 +0,0 @@ -.. _axi_ad9371: - -AXI AD9371 (OBSOLETE) -================================================================================ - -.. warning:: - - The support for :git-hdl:`AXI AD9371 ` - has been discontinued, the latest tested release being ``hdl_2019_r2``. - This page is for legacy purposes only. - -.. note:: - This page has a great historical background. The same functionalities are - implemented using the generic JESD204 TPL IPs. - -The :git-hdl:`AXI AD9371 ` IP core can be used -to interface the :adi:`AD9371` device. An AXI Memory Map interface is used for -configuration. Data is sent in a format that can be transmitted by Xilinx's -JESD IP. - -More about the generic framework interfacing ADCs and DACs, that contains the -``up_dac_channel``, ``up_adc_channel`` and ``up_dac_common modules``, -``up_adc_common modules`` can be read in :ref:`axi_dac` and :ref:`axi_adc`. - -Features --------------------------------------------------------------------------------- - -* AXI Lite control/status interface -* Hardware and software DC filtering -* IQ correction -* Internal DDS -* Receive and transmit loopback -* Supports both Altera and Xilinx devices - -Files --------------------------------------------------------------------------------- - -.. list-table:: - :header-rows: 1 - - * - Name - - Description - * - :git-hdl:`hdl_2019_r2:library/axi_ad9371/axi_ad9371.v` - - Verilog source for the AXI AD9371. - * - :git-hdl:`hdl_2019_r2:library/axi_ad9371/axi_ad9371_ip.tcl` - - TCL script to generate the Vivado IP-integrator project. - * - :git-hdl:`hdl_2019_r2:library/axi_ad9371/axi_ad9371_hw.tcl` - - TCL script to generate the Quartus IP-integrator project. - * - :git-hdl:`hdl_2019_r2:library/axi_ad9371/axi_ad9371_constr.xdc` - - Constraint file of the IP. - * - :git-hdl:`hdl_2019_r2:library/axi_ad9371/axi_ad9371_rx.v` - - Verilog source for the AXI AD9371 RX component. - * - :git-hdl:`hdl_2019_r2:library/axi_ad9371/axi_ad9371_rx_channel.v` - - Verilog source for the AXI AD9371 RX channel. - * - :git-hdl:`hdl_2019_r2:library/axi_ad9371/axi_ad9371_rx_os.v` - - Verilog source for the AXI AD9371 RX channel observation component. - * - :git-hdl:`hdl_2019_r2:library/axi_ad9371/axi_ad9371_tx.v` - - Verilog source for the AXI AD9371 TX component. - * - :git-hdl:`hdl_2019_r2:library/axi_ad9371/axi_ad9371_tx_channel.v` - - Verilog source for the AXI AD9371 TX channel. - * - :git-hdl:`library/common/up_adc_common.v` - - Verilog source for the ADC Common regmap. - * - :git-hdl:`library/common/up_adc_channel.v` - - Verilog source for the ADC Channel regmap. - * - :git-hdl:`library/common/up_dac_common.v` - - Verilog source for the DAC Common regmap. - * - :git-hdl:`library/common/up_dac_channel.v` - - Verilog source for the DAC Channel regmap. - -Block Diagram --------------------------------------------------------------------------------- - -.. image:: block_diagram.svg - :alt: AXI AD9371 block diagram - :align: center - -Configuration Parameters --------------------------------------------------------------------------------- - -.. list-table:: - :header-rows: 1 - - * - ID - - Core ID should be unique for each IP in the system. - * - DEVICE_TYPE - - Used to select between 7 Series (0), Virtex 6 (1) or Ultrascale (2) for - Xilinx devices. - * - ADC_DATAPATH_DISABLE - - Disable the receive data path modules. - * - DAC_DATAPATH_DISABLE - - Disable the transmit data path modules. - -Interface --------------------------------------------------------------------------------- - -The interface module of the core is connected to the JESD204B IP core and does -a simple realignment of the data stream. Below it's a list of I/O signals: - -.. list-table:: - :header-rows: 1 - - * - adc_clk - - Rx core clock from the GTs, in general clock rate is (Lane Rate)/40. - * - adc_rx_valid - - This signal is unused; is defined just to make tools happy. - * - adc_rx_sof - - Frame boundary indication signals. Indicate the byte position of the - first byte of a frame. - * - adc_rx_data - - Received data stream from the JESD204B IP. - * - adc_rx_ready - - This signal is tied to one; is defined just to make tools happy. - * - adc_os_clk - - Rx core clock from the GTs, in general clock rate is (Lane Rate)/40. - * - adc_rx_os_valid - - This signal is unused; is defined just to make tools happy. - * - adc_rx_os_sof - - Frame boundary indication signals. Indicate the byte position of the - first byte of a frame - * - adc_rx_os_data - - Received data stream from the JESD204B IP. - * - adc_rx_os_ready - - This signal is tied to one; is defined just to make tools happy. - * - dac_clk - - Tx core clock from the GTs, in general clock rate is (Lane Rate)/40. - * - dac_tx_valid - - This signal is tied to one; is defined just to make tools happy. - * - dac_tx_data - - Transmitted data stream to the JESD204B IP. - * - dac_tx_ready - - This signal is not used; is defined just to make tools happy. - * - dac_sync_in - - Synchronization signal of the transmit path for slave devices (ID>0) - * - dac_sync_out - - Synchronization signal of the transmit path for master device (ID==0) - * - adc_enable - - If set, the channel is enabled (one for each channel) - * - adc_valid - - Indicates valid data at the current channel (one for each channel) - * - adc_data - - Received data output (one for each channel) - * - adc_dovf - - Data overflow, must be connected to the DMA - * - adc_dunf - - Data underflow, must be connected to the DMA - * - adc_os_enable - - If set, the channel is enabled (one for each channel) - * - adc_os_valid - - Indicates valid data at the current channel (one for each channel) - * - adc_os_data - - Received data output (one for each channel) - * - adc_os_dovf - - Data overflow, must be connected to the DMA - * - adc_os_dunf - - Data underflow, must be connected to the DMA - * - dac_enable - - If set, the channel is enabled (one for each channel) - * - dac_valid - - Indicates valid data request at the current channel (one for each channel) - * - dac_data - - Transmitted data output (one for each channel) - * - dac_dovf - - Data overflow, must be connected to the DMA - * - dac_dunf - - Data underflow, must be connected to the DMA - * - s_axi - - Standard AXI Slave Memory Map interface - -Detailed Description --------------------------------------------------------------------------------- - -The axi_ad9371 cores architecture contains: - -* Interface module, which implements the application layer of the JESD20B - interface. This interface is connected to the JESD204B IP core. -* Receive module, which contains: - - * ADC channel processing modules, one for each channel - (receive path supports 4 channels) - - * data processing modules ( DC filter, IQ Correction and Data format - control) - * ADC Channel register map - - * ADC Common register map - -* Observation module, which has the same architecture as the Receive module, but - supports just 2 channels -* Transmit module, which contains: - - * DAC channel processing modules, one for each channel - - * Different data generators ( DDS, pattern) - * IQ Correction - * DAC Channel register map - - * Delay Control and DAC Common register map - -* AXI to uP interface wrapper modules (more details :dokuwiki:`here `) - -Register Map --------------------------------------------------------------------------------- - -.. hdl-regmap:: - :name: COMMON - :no-type-info: - -.. hdl-regmap:: - :name: ADC_COMMON - :no-type-info: - -.. hdl-regmap:: - :name: ADC_CHANNEL - :no-type-info: - -.. hdl-regmap:: - :name: DAC_COMMON - :no-type-info: - -.. hdl-regmap:: - :name: DAC_CHANNEL - :no-type-info: - -.. hdl-regmap:: - :name: JESD_TPL - :no-type-info: - -Design Guidelines --------------------------------------------------------------------------------- - -The IP was developed part of the :adi:`AD9371` chip, that can be found on -:adi:`EVAL-ADRV9371`. - -The control of the :git-hdl:`AXI AD9371 ` chip -is done through a SPI interface, using ACE software. The ACE -(Analysis - Control- Evaluate) software provides a graphical user interface for -configuring and controlling the :adi:`AD9371`, allowing for easy setup and -evaluation of the DAC's performance. - -.. warning:: - We **do not** offer support for ACE anymore. Limited support is available. - -Software Support --------------------------------------------------------------------------------- - -* Linux device driver at: - - * :git-linux:`2019_R2:drivers/iio/adc/ad9371.c` - * :git-linux:`2019_R2:drivers/iio/adc/ad9371_conv.c` - -* Linux device tree at: - - * :git-linux:`2019_R2:arch/arm/boot/dts/adi-adrv9371.dtsi` - * :git-linux:`2019_R2:arch/microblaze/boot/dts/adi-adrv9371.dtsi` - * :git-linux:`2019_R2:arch/arm64/boot/dts/xilinx/adi-adrv9371.dtsi` - * :git-linux:`2019_R2:arch/nios2/boot/dts/a10gx_adrv9371.dts` - * :git-linux:`2019_R2:arch/microblaze/boot/dts/kcu105_adrv9371x.dts` - * :git-linux:`2019_R2:arch/arm/boot/dts/zynq-zc706-adv7511-adrv9371.dts` - * :git-linux:`2019_R2:arch/arm/boot/dts/socfpga_arria10_socdk_adrv9371.dts` - * :git-linux:`2019_R2:arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-adrv9371.dts` - * :git-linux:`2019_R2:arch/arm/boot/dts/zynq-zc706-adv7511-adrv9371-jesd204-fsm.dts` - * :git-linux:`2019_R2:arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-adrv9371-jesd204-fsm.dts` - -* No-OS project at :git-no-os:`2019_r2:projects/ad9371` - -References --------------------------------------------------------------------------------- - -* HDL IP core at :git-hdl:`hdl_2019_r2:library/axi_ad9371` -* :adi:`AD9371` -* :adi:`EVAL-ADRV9371` -* :dokuwiki+deprecated:`[Wiki] Prerequisites for AD9371 based boards ` -* :dokuwiki+deprecated:`[Wiki] AXI_AD9371 (Obsolete) ` -* :dokuwiki+deprecated:`[Wiki] AD9371 & AD9375 Prototyping Platform User Guide ` -* :dokuwiki+deprecated:`[Wiki] AD9371 Plugin Description ` -* :dokuwiki+deprecated:`[Wiki] AD9371, AD9375 highly integrated, wideband RF transceiver Linux device driver ` -* :dokuwiki+deprecated:`[Wiki] AD9371/AD9375 Advanced Plugin ` -* :dokuwiki+deprecated:`[Wiki] AD9371 detailed Block Diagram ` -* :dokuwiki+deprecated:`[Wiki] AD9371/AD9375 Device Driver Customization ` -* :dokuwiki+deprecated:`[Wiki] IIO OSC AD9371 Capture Window ` -* :dokuwiki+deprecated:`[Wiki] AD9371/AD9375 No-OS Setup ` -* :dokuwiki+deprecated:`[Wiki] AD9371 Basic IQ Datafiles ` -* :xilinx:`Zynq-7000 SoC Overview ` -* :xilinx:`Zynq-7000 SoC Packaging and Pinout ` -* :xilinx:`7 Series libraries ` diff --git a/docs/library/axi_ad9467/index.rst b/docs/library/axi_ad9467/index.rst index e80cec77fb5..458d4f6ee46 100644 --- a/docs/library/axi_ad9467/index.rst +++ b/docs/library/axi_ad9467/index.rst @@ -134,6 +134,35 @@ monitoring and control of the ADC. Register Map -------------------------------------------------------------------------------- +The register map of the core contains instances of several generic register maps +like ADC common, ADC channel. +The following table presents the base addresses of each instance, after it you +can find the detailed description of each generic register map. + +The absolute address of a register should be calculated by adding the instance +base address to the registers relative address. For a more detailed explanation, +see :ref:`ADC register access `. + +.. list-table:: Register Map base addresses for axi_ad9467 + :header-rows: 1 + + * - HDL reg + - Software reg + - Name + - Description + * - 0x0000 + - 0x0000 + - BASE + - See the `Base <#hdl-regmap-COMMON>`__ table for more details. + * - 0x0000 + - 0x0000 + - RX COMMON + - See the `ADC Common <#hdl-regmap-ADC_COMMON>`__ table for more details. + * - 0x0000 + - 0x0000 + - RX CHANNELS + - See the `ADC Channel <#hdl-regmap-ADC_CHANNEL>`__ table for more details. + .. hdl-regmap:: :name: COMMON :no-type-info: diff --git a/docs/library/axi_ad9643/index.rst b/docs/library/axi_ad9643/index.rst index 1806e02da12..f6d8e1e9f9c 100644 --- a/docs/library/axi_ad9643/index.rst +++ b/docs/library/axi_ad9643/index.rst @@ -204,6 +204,35 @@ The example design uses a processor to program all the registers. If no processo Register Map -------------------------------------------------------------------------------- +The register map of the core contains instances of several generic register maps +like ADC common, ADC channel. +The following table presents the base addresses of each instance, after it you +can find the detailed description of each generic register map. + +The absolute address of a register should be calculated by adding the instance +base address to the registers relative address. For a more detailed explanation, +see :ref:`ADC register access `. + +.. list-table:: Register Map base addresses for axi_ad9643 + :header-rows: 1 + + * - HDL reg + - Software reg + - Name + - Description + * - 0x0000 + - 0x0000 + - BASE + - See the `Base <#hdl-regmap-COMMON>`__ table for more details. + * - 0x0000 + - 0x0000 + - RX COMMON + - See the `ADC Common <#hdl-regmap-ADC_COMMON>`__ table for more details. + * - 0x0000 + - 0x0000 + - RX CHANNELS + - See the `ADC Channel <#hdl-regmap-ADC_CHANNEL>`__ table for more details. + .. hdl-regmap:: :name: COMMON :no-type-info: diff --git a/docs/library/axi_ad9671/index.rst b/docs/library/axi_ad9671/index.rst index 266c1d6140e..24ed36256be 100644 --- a/docs/library/axi_ad9671/index.rst +++ b/docs/library/axi_ad9671/index.rst @@ -132,6 +132,35 @@ The channel module implements: Register Map -------------------------------------------------------------------------------- +The register map of the core contains instances of several generic register maps +like ADC common, ADC channel. +The following table presents the base addresses of each instance, after it you +can find the detailed description of each generic register map. + +The absolute address of a register should be calculated by adding the instance +base address to the registers relative address. For a more detailed explanation, +see :ref:`ADC register access `. + +.. list-table:: Register Map base addresses for axi_ad9643 + :header-rows: 1 + + * - HDL reg + - Software reg + - Name + - Description + * - 0x0000 + - 0x0000 + - BASE + - See the `Base <#hdl-regmap-COMMON>`__ table for more details. + * - 0x0000 + - 0x0000 + - RX COMMON + - See the `ADC Common <#hdl-regmap-ADC_COMMON>`__ table for more details. + * - 0x0000 + - 0x0000 + - RX CHANNELS + - See the `ADC Channel <#hdl-regmap-ADC_CHANNEL>`__ table for more details. + .. hdl-regmap:: :name: COMMON :no-type-info: diff --git a/docs/library/axi_ad9783/index.rst b/docs/library/axi_ad9783/index.rst index aac118e4b21..d569de286f0 100644 --- a/docs/library/axi_ad9783/index.rst +++ b/docs/library/axi_ad9783/index.rst @@ -254,17 +254,19 @@ Register Map -------------------------------------------------------------------------------- The register map of the core contains instances of several generic register maps -like ADC common, ADC channel, DAC common, DAC channel etc. The following table -presents the base addresses of each instance, after that can be found the -detailed description of each generic register map. The absolute address of a -register should be calculated by adding the instance base address to the -registers relative address. +like DAC common, DAC channel. +The following table presents the base addresses of each instance, after it you +can find the detailed description of each generic register map. + +The absolute address of a register should be calculated by adding the instance +base address to the registers relative address. For a more detailed explanation, +see :ref:`DAC register access `. .. list-table:: Register Map base addresses for axi_ad9783 :header-rows: 1 - * - DWORD - - BYTE + * - HDL reg + - Software reg - Name - Description * - 0x0000 diff --git a/docs/library/axi_ad9963/index.rst b/docs/library/axi_ad9963/index.rst index a69cbdf5bad..c265a5cd8dc 100644 --- a/docs/library/axi_ad9963/index.rst +++ b/docs/library/axi_ad9963/index.rst @@ -161,17 +161,20 @@ Register Map -------------------------------------------------------------------------------- The register map of the core contains instances of several generic register maps -like ADC common, ADC channel, DAC common, DAC channel etc. The following table -presents the base addresses of each instance, after that can be found the -detailed description of each generic register map. The absolute address of a -register should be calculated by adding the instance base address to the -registers relative address. +like ADC common, ADC channel, DAC common, DAC channel etc. +The following table presents the base addresses of each instance, after that can +be found the detailed description of each generic register map. + +The absolute address of a register should be calculated by adding the instance +base address to the registers relative address. For a more detailed explanation, +see :ref:`ADC register access ` and +:ref:`DAC register access `. .. list-table:: Register Map base addresses for axi_ad9361 :header-rows: 1 - * - DWORD - - BYTE + * - HDL reg + - Software reg - Name - Description * - 0x0000 diff --git a/docs/library/axi_ada4355/index.rst b/docs/library/axi_ada4355/index.rst index c2c530e1455..0c58e301a45 100644 --- a/docs/library/axi_ada4355/index.rst +++ b/docs/library/axi_ada4355/index.rst @@ -114,25 +114,26 @@ The following table presents the base addresses of each instance, after it you can find the detailed description of each generic register map. The absolute address of a register should be calculated by adding the instance -base address to the registers relative address. +base address to the registers relative address. For a more detailed explanation, +see :ref:`ADC register access `. .. list-table:: Register Map base addresses for axi_ada4355 :header-rows: 1 - * - DWORD - - BYTE + * - HDL reg + - Software reg - Name - Description * - 0x0000 - 0x0000 - BASE - See the `Base <#hdl-regmap-COMMON>`__ table for more details. - * - 0x0010 - - 0x0040 + * - 0x0000 + - 0x0000 - ADC COMMON - See the `ADC Common <#hdl-regmap-ADC_COMMON>`__ table for more details. - * - 0x0100 - - 0x0400 + * - 0x0000 + - 0x0000 - ADC CHANNELS - See the `ADC Channel <#hdl-regmap-ADC_CHANNEL>`__ table for more details. * - 0x0200 diff --git a/docs/library/axi_adaq8092/index.rst b/docs/library/axi_adaq8092/index.rst index 300de324476..c57ff82d117 100644 --- a/docs/library/axi_adaq8092/index.rst +++ b/docs/library/axi_adaq8092/index.rst @@ -165,6 +165,35 @@ line helps compensate trace differences between the data lines on the PCB. Register Map -------------------------------------------------------------------------------- +The register map of the core contains instances of several generic register maps +like ADC common, ADC channel. +The following table presents the base addresses of each instance, after it you +can find the detailed description of each generic register map. + +The absolute address of a register should be calculated by adding the instance +base address to the registers relative address. For a more detailed explanation, +see :ref:`ADC register access `. + +.. list-table:: Register Map base addresses for axi_adaq8092 + :header-rows: 1 + + * - HDL reg + - Software reg + - Name + - Description + * - 0x0000 + - 0x0000 + - BASE + - See the `Base <#hdl-regmap-COMMON>`__ table for more details. + * - 0x0000 + - 0x0000 + - RX COMMON + - See the `ADC Common <#hdl-regmap-ADC_COMMON>`__ table for more details. + * - 0x0000 + - 0x0000 + - RX CHANNELS + - See the `ADC Channel <#hdl-regmap-ADC_CHANNEL>`__ table for more details. + .. hdl-regmap:: :name: COMMON :no-type-info: diff --git a/docs/library/axi_adrv9001/index.rst b/docs/library/axi_adrv9001/index.rst index ee49db5d232..d5bcff2eee2 100644 --- a/docs/library/axi_adrv9001/index.rst +++ b/docs/library/axi_adrv9001/index.rst @@ -534,17 +534,20 @@ Register Map The register map of the core contains instances of several generic register maps like ADC common, ADC channel, DAC common, DAC channel etc. The following table presents the base addresses of each instance, after that can be found the -detailed description of each generic register map. The absolute address of a -register should be calculated by adding the instance base address to the -registers relative address. +detailed description of each generic register map. + +The absolute address of a register should be calculated by adding the instance +base address to the registers relative address. For a more detailed explanation, +see :ref:`ADC register access` and +:ref:`DAC register access `. Register Map base addresses for axi_adrv9001 -------------------------------------------------------------------------------- .. list-table:: - * - DWORD - - BYTE + * - HDL reg + - Software reg - Name - Description * - 0x0000 diff --git a/docs/library/axi_ltc235x/index.rst b/docs/library/axi_ltc235x/index.rst index 5e39e1277c9..37de82177e6 100644 --- a/docs/library/axi_ltc235x/index.rst +++ b/docs/library/axi_ltc235x/index.rst @@ -286,6 +286,35 @@ This includes the channel ID and the SoftSpan ID. Register Map ------------------------------------------------------------------------------- +The register map of the core contains instances of several generic register maps +like ADC common, ADC channel. +The following table presents the base addresses of each instance, after it you +can find the detailed description of each generic register map. + +The absolute address of a register should be calculated by adding the instance +base address to the registers relative address. For a more detailed explanation, +see :ref:`generic-adc-register-access`. + +.. list-table:: Register Map base addresses for axi_ltc235x + :header-rows: 1 + + * - HDL reg + - Software reg + - Name + - Description + * - 0x0000 + - 0x0000 + - BASE + - See the `Base <#hdl-regmap-COMMON>`__ table for more details. + * - 0x0000 + - 0x0000 + - RX COMMON + - See the `ADC Common <#hdl-regmap-ADC_COMMON>`__ table for more details. + * - 0x0000 + - 0x0000 + - RX CHANNELS + - See the `ADC Channel <#hdl-regmap-ADC_CHANNEL>`__ table for more details. + .. hdl-regmap:: :name: COMMON :no-type-info: diff --git a/docs/library/axi_ltc2387/index.rst b/docs/library/axi_ltc2387/index.rst index 35a9a525d48..391b8629eaa 100644 --- a/docs/library/axi_ltc2387/index.rst +++ b/docs/library/axi_ltc2387/index.rst @@ -117,6 +117,35 @@ additionally. Register Map -------------------------------------------------------------------------------- +The register map of the core contains instances of several generic register maps +like ADC common, ADC channel. +The following table presents the base addresses of each instance, after it you +can find the detailed description of each generic register map. + +The absolute address of a register should be calculated by adding the instance +base address to the registers relative address. For a more detailed explanation, +see :ref:`generic-adc-register-access`. + +.. list-table:: Register Map base addresses for axi_ltc2387 + :header-rows: 1 + + * - HDL reg + - Software reg + - Name + - Description + * - 0x0000 + - 0x0000 + - BASE + - See the `Base <#hdl-regmap-COMMON>`__ table for more details. + * - 0x0000 + - 0x0000 + - RX COMMON + - See the `ADC Common <#hdl-regmap-ADC_COMMON>`__ table for more details. + * - 0x0000 + - 0x0000 + - RX CHANNELS + - See the `ADC Channel <#hdl-regmap-ADC_CHANNEL>`__ table for more details. + .. hdl-regmap:: :name: COMMON :no-type-info: diff --git a/docs/library/index.rst b/docs/library/index.rst index 8e409aeeb01..b6f5f2d7aec 100644 --- a/docs/library/index.rst +++ b/docs/library/index.rst @@ -106,8 +106,6 @@ Obsolete IPs .. toctree:: :maxdepth: 1 - axi_ad9144/index - axi_ad9371/index axi_ad9643/index axi_ad9671/index diff --git a/docs/library/jesd204/ad_ip_jesd204_tpl_adc/index.rst b/docs/library/jesd204/ad_ip_jesd204_tpl_adc/index.rst index 31655a7694d..40aafb94b81 100644 --- a/docs/library/jesd204/ad_ip_jesd204_tpl_adc/index.rst +++ b/docs/library/jesd204/ad_ip_jesd204_tpl_adc/index.rst @@ -110,6 +110,35 @@ and interfaces are synchronous to the device_clk clock. Register Map -------------------------------------------------------------------------------- +The register map of the core contains instances of several generic register maps +like ADC common, ADC channel. +The following table presents the base addresses of each instance, after it you +can find the detailed description of each generic register map. + +The absolute address of a register should be calculated by adding the instance +base address to the registers relative address. For a more detailed explanation, +see :ref:`generic-adc-register-access`. + +.. list-table:: Register Map base addresses for ad_ip_jesd204_tpl_adc + :header-rows: 1 + + * - HDL reg + - Software reg + - Name + - Description + * - 0x0000 + - 0x0000 + - BASE + - See the `Base <#hdl-regmap-COMMON>`__ table for more details. + * - 0x0000 + - 0x0000 + - RX COMMON + - See the `ADC Common <#hdl-regmap-ADC_COMMON>`__ table for more details. + * - 0x0000 + - 0x0000 + - RX CHANNELS + - See the `ADC Channel <#hdl-regmap-ADC_CHANNEL>`__ table for more details. + .. hdl-regmap:: :name: COMMON :no-type-info: diff --git a/docs/library/jesd204/ad_ip_jesd204_tpl_dac/index.rst b/docs/library/jesd204/ad_ip_jesd204_tpl_dac/index.rst index f298e473389..b8dc3469892 100644 --- a/docs/library/jesd204/ad_ip_jesd204_tpl_dac/index.rst +++ b/docs/library/jesd204/ad_ip_jesd204_tpl_dac/index.rst @@ -106,6 +106,35 @@ Signal and Interface Pins Register Map -------------------------------------------------------------------------------- +The register map of the core contains instances of several generic register maps +like DAC common, DAC channel. +The following table presents the base addresses of each instance, after it you +can find the detailed description of each generic register map. + +The absolute address of a register should be calculated by adding the instance +base address to the registers relative address. For a more detailed explanation, +see :ref:`DAC register access `. + +.. list-table:: Register Map base addresses for ad_ip_jesd204_tpl_dac + :header-rows: 1 + + * - HDL reg + - Software reg + - Name + - Description + * - 0x0000 + - 0x0000 + - BASE + - See the `Base <#hdl-regmap-COMMON>`__ table for more details. + * - 0x0000 + - 0x0000 + - TX COMMON + - See the `DAC Common <#hdl-regmap-DAC_COMMON>`__ table for more details. + * - 0x0000 + - 0x0000 + - TX CHANNELS + - See the `DAC Channel <#hdl-regmap-DAC_CHANNEL>`__ table for more details. + .. hdl-regmap:: :name: COMMON :no-type-info: diff --git a/docs/user_guide/ip_cores/axi_adc/index.rst b/docs/user_guide/ip_cores/axi_adc/index.rst index e10c1bce713..ab815be28b1 100644 --- a/docs/user_guide/ip_cores/axi_adc/index.rst +++ b/docs/user_guide/ip_cores/axi_adc/index.rst @@ -33,7 +33,6 @@ Files * - :git-hdl:`library/common/up_adc_channel.v` - Verilog source for the ADC Channel regmap. - Architecture -------------------------------------------------------------------------------- @@ -219,6 +218,81 @@ see :ref:`axi_adc adc-channel` section. To find the instantiation of this module search for ``up_adc_channel`` inside the IP's directory. +.. _generic-adc-register-access: + +Register access +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The ADC IP supports **16 channels**, numbered from **0 to 15**. Usually, the +**base registers** start at offset ``0x0`` and the **common (global) registers** +start at address ``0x10``. Each **channel** has its own register block, starting +from address ``0x100`` (for channel 0). Each subsequent channel is spaced by +``0x10`` (HDL register address) or ``0x40`` (Software addressing). + +..note:: + + There are cases in which the offset is different from ``0x0``. Please refer to + the register map table of the specific IP for more details. + +Let's say the ADC IP base address is 0x44A0_0000. Here is how the channel offset +is computed: + +.. math:: + + \text{HDL}_{reg} = 0x100 + (n \times 0x10) \\ + +.. math:: + + \text{Software}_{addr} = IP_BaseAddr + (\text{HDL}_{reg} << 2) = 0x44A0\_0000 + 0x400 + (n \times 0x40) + +This means the first register's address ( **``CHAN_CNTRL_0``**) is: + +- For **channel 0**: + + - ``0x0100`` (HDL register)=> ``0x44A0_0400`` (Software addressing) + +- For **channel 3**: + + - ``0x0130`` (HDL register) => ``0x44A0_04C0`` (Software addressing) +- For **channel 15**: + + - ``0x01F0`` (HDL register) => ``0x44A0_07C0`` (Software addressing) + +If you want to access the **``CHAN_CNTRL_3``** register, its address is: + +- For **channel 0**: + + - ``0x0106`` (HDL register) => ``0x44A0_0418`` (Software addressing) + +- For **channel 5**: + + - ``0x0156`` (HDL register) => ``0x44A0_0558`` (Software addressing) + +In general, the address for the ``CHAN_CNTRL_3`` register of **channel *n*** can be calculated as: + +.. math:: + + \text{HDL}_{reg} = 0x100 + (n \times 0x10) + 0x06 \\ + +.. math:: + + \text{Software}_{addr} = IP_base_addr + 0x400 + (n \times 0x40) + 0x18 + +The software addresses for all channels can be found in the table below: + +========== ============== +Name Address range +========== ============== +Base 0x000 to 0x07C +Common 0x040 to 0x0C4 +Channel 0 0x400 to 0x424 +Channel 1 0x440 to 0x464 +Channel 2 0x480 to 0x4A4 +Channel 3 0x4C0 to 0x4E4 +*...* *...* +Channel 15 0x7C0 to 0x7E4 +========== ============== + Typical Register Map base addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/user_guide/ip_cores/axi_dac/index.rst b/docs/user_guide/ip_cores/axi_dac/index.rst index caf34f32e17..8e66c4ee6d9 100644 --- a/docs/user_guide/ip_cores/axi_dac/index.rst +++ b/docs/user_guide/ip_cores/axi_dac/index.rst @@ -211,6 +211,81 @@ see :ref:`axi_dac dac-channel` section. To find the instantiation of this module search for ``up_dac_channel`` inside the IP's directory. +.. _generic-dac-register-access: + +Register access +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The DAC IP supports **16 channels**, numbered from **0 to 15**. Usually, the +**base registers** start at offset ``0x0`` and the **common (global) registers** +start at address ``0x10``. Each **channel** has its own register block, starting +from address ``0x100`` (for channel 0). Each subsequent channel is spaced by +``0x10`` (HDL register address) or ``0x40`` (Software addressing). + +..note:: + + There are cases in which the offset is different from ``0x0``. Please refer to + the register map table of the specific IP for more details. + +Let's say the DAC IP base address is 0x44A0_0000. Here is how the channel offset +is computed: + +.. math:: + + \text{HDL}_{reg} = 0x100 + (n \times 0x10) \\ + +.. math:: + + \text{Software}_{addr} = IP_BaseAddr + (\text{HDL}_{reg} << 2) = 0x44A0\_0000 + 0x400 + (n \times 0x40) + +This means the first register's address ( **``CHAN_CNTRL_0``**) is: + +- For **channel 0**: + + - ``0x0100`` (HDL register)=> ``0x44A0_0400`` (Software addressing) + +- For **channel 3**: + + - ``0x0130`` (HDL register) => ``0x44A0_04C0`` (Software addressing) +- For **channel 15**: + + - ``0x01F0`` (HDL register) => ``0x44A0_07C0`` (Software addressing) + +If you want to access the **``CHAN_CNTRL_3``** register, its address is: + +- For **channel 0**: + + - ``0x0106`` (HDL register) => ``0x44A0_0418`` (Software addressing) + +- For **channel 5**: + + - ``0x0156`` (HDL register) => ``0x44A0_0558`` (Software addressing) + +In general, the address for the ``CHAN_CNTRL_3`` register of **channel *n*** can be calculated as: + +.. math:: + + \text{HDL}_{reg} = 0x100 + (n \times 0x10) + 0x06 \\ + +.. math:: + + \text{Software}_{addr} = IP_base_addr + 0x400 + (n \times 0x40) + 0x18 + +The software addresses for all channels can be found in the table below: + +========== ============== +Name Address range +========== ============== +Base 0x000 to 0x0BC +Common 0x040 to 0x0C4 +Channel 0 0x400 to 0x430 +Channel 1 0x440 to 0x470 +Channel 2 0x480 to 0x4B0 +Channel 3 0x4C0 to 0x4F0 +*...* *...* +Channel 15 0x7C0 to 0x7F0 +========== ============== + Typical Register Map base addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~