From bb167f04fa06ca7245c3f173d4ce108e36309c67 Mon Sep 17 00:00:00 2001 From: Lucian Copeland Date: Thu, 12 Mar 2020 14:54:43 -0400 Subject: [PATCH 01/17] WIP --- ports/stm/packages/stm32f4/LQFP100.h | 101 +++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) create mode 100644 ports/stm/packages/stm32f4/LQFP100.h diff --git a/ports/stm/packages/stm32f4/LQFP100.h b/ports/stm/packages/stm32f4/LQFP100.h new file mode 100644 index 0000000000000..3c0e244f99605 --- /dev/null +++ b/ports/stm/packages/stm32f4/LQFP100.h @@ -0,0 +1,101 @@ +STATIC const mp_rom_map_elem_t mcu_pin_globals_table[] = { +// Pins 1-25 + { MP_ROM_QSTR(MP_QSTR_PE02), MP_ROM_PTR(&pin_PE02) }, + { MP_ROM_QSTR(MP_QSTR_PE03), MP_ROM_PTR(&pin_PE03) }, + { MP_ROM_QSTR(MP_QSTR_PE04), MP_ROM_PTR(&pin_PE04) }, + { MP_ROM_QSTR(MP_QSTR_PE05), MP_ROM_PTR(&pin_PE05) }, + { MP_ROM_QSTR(MP_QSTR_PE06), MP_ROM_PTR(&pin_PE06) }, + /* VBAT -------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) }, + // PC14 OSC32_IN ----------------------------------*/ + // PC15 OSC32_OUT ---------------------------------*/ + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ + // PH0 OSC_IN -------------------------------------*/ + // PH1 OSC_OUT ------------------------------------*/ + // NRST -------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PC00), MP_ROM_PTR(&pin_PC00) }, + { MP_ROM_QSTR(MP_QSTR_PC01), MP_ROM_PTR(&pin_PC01) }, + { MP_ROM_QSTR(MP_QSTR_PC02), MP_ROM_PTR(&pin_PC02) }, + { MP_ROM_QSTR(MP_QSTR_PC03), MP_ROM_PTR(&pin_PC03) }, + // VSSA -------------------------------------------*/ + // VREF+ ------------------------------------------*/ + // VDDA -------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PA00), MP_ROM_PTR(&pin_PA00) }, + { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) }, + { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) }, + { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) }, + { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) }, + +// Pins 26-50 + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) }, + { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) }, + { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) }, + { MP_ROM_QSTR(MP_QSTR_PC04), MP_ROM_PTR(&pin_PC04) }, + { MP_ROM_QSTR(MP_QSTR_PC05), MP_ROM_PTR(&pin_PC05) }, + { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) }, + { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) }, + { MP_ROM_QSTR(MP_QSTR_PB02), MP_ROM_PTR(&pin_PB02) }, + { MP_ROM_QSTR(MP_QSTR_PE07), MP_ROM_PTR(&pin_PE07) }, + { MP_ROM_QSTR(MP_QSTR_PE08), MP_ROM_PTR(&pin_PE08) }, + { MP_ROM_QSTR(MP_QSTR_PE09), MP_ROM_PTR(&pin_PE09) }, + { MP_ROM_QSTR(MP_QSTR_PE10), MP_ROM_PTR(&pin_PE10) }, + { MP_ROM_QSTR(MP_QSTR_PE11), MP_ROM_PTR(&pin_PE11) }, + { MP_ROM_QSTR(MP_QSTR_PE12), MP_ROM_PTR(&pin_PE12) }, + { MP_ROM_QSTR(MP_QSTR_PE13), MP_ROM_PTR(&pin_PE13) }, + { MP_ROM_QSTR(MP_QSTR_PE14), MP_ROM_PTR(&pin_PE14) }, + { MP_ROM_QSTR(MP_QSTR_PE15), MP_ROM_PTR(&pin_PE15) }, + { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) }, +#if MCU_LINE == FOUNDATION || MCU_LINE == ADVANCED + { MP_ROM_QSTR(MP_QSTR_PB11), MP_ROM_PTR(&pin_PB11) }, +#endif + + + { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) }, + { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) }, + { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) }, + { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) }, + { MP_ROM_QSTR(MP_QSTR_PD08), MP_ROM_PTR(&pin_PD08) }, + { MP_ROM_QSTR(MP_QSTR_PD09), MP_ROM_PTR(&pin_PD09) }, + { MP_ROM_QSTR(MP_QSTR_PD10), MP_ROM_PTR(&pin_PD10) }, + { MP_ROM_QSTR(MP_QSTR_PD11), MP_ROM_PTR(&pin_PD11) }, + { MP_ROM_QSTR(MP_QSTR_PD12), MP_ROM_PTR(&pin_PD12) }, + { MP_ROM_QSTR(MP_QSTR_PD13), MP_ROM_PTR(&pin_PD13) }, + { MP_ROM_QSTR(MP_QSTR_PD14), MP_ROM_PTR(&pin_PD14) }, + { MP_ROM_QSTR(MP_QSTR_PD15), MP_ROM_PTR(&pin_PD15) }, + { MP_ROM_QSTR(MP_QSTR_PC06), MP_ROM_PTR(&pin_PC06) }, + { MP_ROM_QSTR(MP_QSTR_PC07), MP_ROM_PTR(&pin_PC07) }, + { MP_ROM_QSTR(MP_QSTR_PC08), MP_ROM_PTR(&pin_PC08) }, + { MP_ROM_QSTR(MP_QSTR_PC09), MP_ROM_PTR(&pin_PC09) }, + { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) }, + { MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) }, + { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) }, + { MP_ROM_QSTR(MP_QSTR_PA11), MP_ROM_PTR(&pin_PA11) }, + { MP_ROM_QSTR(MP_QSTR_PA12), MP_ROM_PTR(&pin_PA12) }, + { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) }, + { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) }, + { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) }, + { MP_ROM_QSTR(MP_QSTR_PC10), MP_ROM_PTR(&pin_PC10) }, + { MP_ROM_QSTR(MP_QSTR_PC11), MP_ROM_PTR(&pin_PC11) }, + { MP_ROM_QSTR(MP_QSTR_PC12), MP_ROM_PTR(&pin_PC12) }, + { MP_ROM_QSTR(MP_QSTR_PD00), MP_ROM_PTR(&pin_PD00) }, + { MP_ROM_QSTR(MP_QSTR_PD01), MP_ROM_PTR(&pin_PD01) }, + { MP_ROM_QSTR(MP_QSTR_PD02), MP_ROM_PTR(&pin_PD02) }, + { MP_ROM_QSTR(MP_QSTR_PD03), MP_ROM_PTR(&pin_PD03) }, + { MP_ROM_QSTR(MP_QSTR_PD04), MP_ROM_PTR(&pin_PD04) }, + { MP_ROM_QSTR(MP_QSTR_PD05), MP_ROM_PTR(&pin_PD05) }, + { MP_ROM_QSTR(MP_QSTR_PD06), MP_ROM_PTR(&pin_PD06) }, + { MP_ROM_QSTR(MP_QSTR_PD07), MP_ROM_PTR(&pin_PD07) }, + { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) }, + { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) }, + { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) }, + { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) }, + { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) }, + { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) }, + { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) }, + { MP_ROM_QSTR(MP_QSTR_PE00), MP_ROM_PTR(&pin_PE00) }, + { MP_ROM_QSTR(MP_QSTR_PE01), MP_ROM_PTR(&pin_PE01) }, +}; +MP_DEFINE_CONST_DICT(mcu_pin_globals, mcu_pin_globals_table); \ No newline at end of file From c4db8b87e2c57ca94b8f76e4b07ca02641df714e Mon Sep 17 00:00:00 2001 From: Lucian Copeland Date: Tue, 17 Mar 2020 18:26:13 -0400 Subject: [PATCH 02/17] Add F7 and H7 Support to the STM32 port Restructures the STM port of Circuitpython to be more generic about the STM32 chip lines to support the F7 and H7 series of chips. Adds the new Packages directory to organize different chip layouts between lines. Makes general changes to the Makefile to condense board-level flags to the minimum and support the new chip series. Adds the new chip line to the Peripherals directory, along with new python tools used to generate peripheral text automatically in the tools/ directory. --- ports/stm/Makefile | 154 ++-- ports/stm/README.md | 4 +- ports/stm/background.h | 6 +- ports/stm/boards/STM32H743ZITx_FLASH.ld | 193 +++++ ports/stm/boards/STM32H743_fs.ld | 164 ++++ .../stm/boards/espruino_pico/mpconfigboard.mk | 10 +- .../stm/boards/espruino_wifi/mpconfigboard.mk | 10 +- .../mpconfigboard.mk | 10 +- .../stm/boards/meowbit_v121/mpconfigboard.mk | 12 +- ports/stm/boards/pyb_nano_v2/mpconfigboard.mk | 10 +- ports/stm/boards/pyboard_v11/mpconfigboard.mk | 10 +- ports/stm/boards/startup_stm32h743xx.s | 748 ++++++++++++++++++ .../stm32f411ce_blackpill/mpconfigboard.mk | 10 +- .../stm32f411ve_discovery/mpconfigboard.mk | 10 +- .../stm32f412zg_discovery/mpconfigboard.mk | 10 +- .../boards/stm32f4_discovery/mpconfigboard.mk | 12 +- .../stm/boards/stm32h743zi_discovery/board.c | 38 + .../stm32h743zi_discovery/mpconfigboard.h | 35 + .../stm32h743zi_discovery/mpconfigboard.mk | 14 + ports/stm/boards/stm32h743zi_discovery/pins.c | 135 ++++ .../stm32h7xx_hal_conf.h | 493 ++++++++++++ ports/stm/common-hal/analogio/AnalogOut.h | 2 +- ports/stm/common-hal/busio/I2C.c | 17 +- ports/stm/common-hal/busio/I2C.h | 13 +- ports/stm/common-hal/busio/OneWire.h | 6 +- ports/stm/common-hal/busio/SPI.c | 27 +- ports/stm/common-hal/busio/SPI.h | 17 +- ports/stm/common-hal/busio/UART.c | 33 +- ports/stm/common-hal/busio/UART.h | 11 +- ports/stm/common-hal/digitalio/DigitalInOut.c | 6 +- ports/stm/common-hal/digitalio/DigitalInOut.h | 6 +- ports/stm/common-hal/microcontroller/Pin.c | 11 +- ports/stm/common-hal/microcontroller/Pin.h | 8 +- .../common-hal/microcontroller/Processor.c | 14 +- .../common-hal/microcontroller/Processor.h | 6 +- .../stm/common-hal/microcontroller/__init__.c | 136 ---- ports/stm/common-hal/os/__init__.c | 2 +- ports/stm/common-hal/pulseio/PWMOut.h | 2 +- ports/stm/common-hal/supervisor/Runtime.h | 6 +- ports/stm/mpconfigport.h | 9 +- ports/stm/mpconfigport.mk | 19 +- ports/stm/mphalport.c | 1 - ports/stm/mphalport.h | 6 +- ports/stm/packages/LQFP100_f4.c | 117 +++ .../{stm32f4/LQFP100.h => LQFP100_x7.c} | 22 +- ports/stm/packages/LQFP144.c | 159 ++++ ports/stm/packages/LQFP64.c | 81 ++ ports/stm/packages/UFQFPN48.c | 63 ++ ports/stm/peripherals/{stm32f4 => }/clocks.h | 4 +- ports/stm/peripherals/{stm32f4 => }/gpio.h | 5 +- ports/stm/peripherals/periph.h | 117 +++ ports/stm/peripherals/{stm32f4 => }/pins.h | 28 +- ports/stm/peripherals/stm32f4/periph.h | 180 ----- .../peripherals/stm32f4/stm32f401xe/clocks.c | 4 +- .../peripherals/stm32f4/stm32f401xe/gpio.c | 10 +- .../peripherals/stm32f4/stm32f401xe/periph.c | 132 ++-- .../peripherals/stm32f4/stm32f401xe/periph.h | 22 +- .../peripherals/stm32f4/stm32f401xe/pins.c | 2 +- .../peripherals/stm32f4/stm32f401xe/pins.h | 6 +- .../peripherals/stm32f4/stm32f405xx/clocks.c | 6 +- .../peripherals/stm32f4/stm32f405xx/gpio.c | 5 +- .../peripherals/stm32f4/stm32f405xx/periph.c | 134 ++-- .../peripherals/stm32f4/stm32f405xx/periph.h | 22 +- .../peripherals/stm32f4/stm32f405xx/pins.c | 2 +- .../peripherals/stm32f4/stm32f405xx/pins.h | 6 +- .../peripherals/stm32f4/stm32f407xx/clocks.c | 6 +- .../peripherals/stm32f4/stm32f407xx/gpio.c | 3 +- .../peripherals/stm32f4/stm32f407xx/periph.c | 134 ++-- .../peripherals/stm32f4/stm32f407xx/periph.h | 22 +- .../peripherals/stm32f4/stm32f407xx/pins.c | 2 +- .../peripherals/stm32f4/stm32f407xx/pins.h | 6 +- .../peripherals/stm32f4/stm32f411xe/clocks.c | 4 +- .../peripherals/stm32f4/stm32f411xe/gpio.c | 5 +- .../peripherals/stm32f4/stm32f411xe/periph.c | 176 ++--- .../peripherals/stm32f4/stm32f411xe/periph.h | 22 +- .../peripherals/stm32f4/stm32f411xe/pins.c | 2 +- .../peripherals/stm32f4/stm32f411xe/pins.h | 4 +- .../peripherals/stm32f4/stm32f412zx/clocks.c | 6 +- .../peripherals/stm32f4/stm32f412zx/gpio.c | 214 +---- .../peripherals/stm32f4/stm32f412zx/periph.c | 196 ++--- .../peripherals/stm32f4/stm32f412zx/periph.h | 22 +- .../peripherals/stm32f4/stm32f412zx/pins.c | 2 +- .../peripherals/stm32f4/stm32f412zx/pins.h | 7 +- .../peripherals/stm32h7/stm32h743xx/clocks.c | 162 ++++ .../peripherals/stm32h7/stm32h743xx/gpio.c | 48 ++ .../peripherals/stm32h7/stm32h743xx/periph.c | 260 ++++++ .../peripherals/stm32h7/stm32h743xx/periph.h | 55 ++ .../peripherals/stm32h7/stm32h743xx/pins.c | 210 +++++ .../peripherals/stm32h7/stm32h743xx/pins.h | 199 +++++ ports/stm/supervisor/port.c | 43 +- ports/stm/supervisor/usb.c | 17 +- ports/stm/system_stm32h7xx.c | 425 ++++++++++ ports/stm/tick.c | 2 - ports/stm/tick.h | 6 +- ports/stm/tools/parse_af_csv.py | 137 ++++ 95 files changed, 4672 insertions(+), 1298 deletions(-) create mode 100644 ports/stm/boards/STM32H743ZITx_FLASH.ld create mode 100644 ports/stm/boards/STM32H743_fs.ld create mode 100644 ports/stm/boards/startup_stm32h743xx.s create mode 100644 ports/stm/boards/stm32h743zi_discovery/board.c create mode 100644 ports/stm/boards/stm32h743zi_discovery/mpconfigboard.h create mode 100644 ports/stm/boards/stm32h743zi_discovery/mpconfigboard.mk create mode 100644 ports/stm/boards/stm32h743zi_discovery/pins.c create mode 100644 ports/stm/boards/stm32h743zi_discovery/stm32h7xx_hal_conf.h create mode 100644 ports/stm/packages/LQFP100_f4.c rename ports/stm/packages/{stm32f4/LQFP100.h => LQFP100_x7.c} (88%) create mode 100644 ports/stm/packages/LQFP144.c create mode 100644 ports/stm/packages/LQFP64.c create mode 100644 ports/stm/packages/UFQFPN48.c rename ports/stm/peripherals/{stm32f4 => }/clocks.h (91%) rename ports/stm/peripherals/{stm32f4 => }/gpio.h (87%) create mode 100644 ports/stm/peripherals/periph.h rename ports/stm/peripherals/{stm32f4 => }/pins.h (82%) delete mode 100644 ports/stm/peripherals/stm32f4/periph.h create mode 100644 ports/stm/peripherals/stm32h7/stm32h743xx/clocks.c create mode 100644 ports/stm/peripherals/stm32h7/stm32h743xx/gpio.c create mode 100644 ports/stm/peripherals/stm32h7/stm32h743xx/periph.c create mode 100644 ports/stm/peripherals/stm32h7/stm32h743xx/periph.h create mode 100644 ports/stm/peripherals/stm32h7/stm32h743xx/pins.c create mode 100644 ports/stm/peripherals/stm32h7/stm32h743xx/pins.h create mode 100644 ports/stm/system_stm32h7xx.c create mode 100644 ports/stm/tools/parse_af_csv.py diff --git a/ports/stm/Makefile b/ports/stm/Makefile index f8c05fd802b33..2eedcca1133b1 100755 --- a/ports/stm/Makefile +++ b/ports/stm/Makefile @@ -22,7 +22,6 @@ # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN # THE SOFTWARE. -# DEBUG = 1 # Select the board to build for. ifeq ($(BOARD),) @@ -58,21 +57,23 @@ include $(TOP)/py/circuitpy_defns.mk CROSS_COMPILE = arm-none-eabi- -####################################### -# CFLAGS -####################################### +MCU_SERIES_LOWER = $(shell echo $(MCU_SERIES) | tr '[:upper:]' '[:lower:]') +MCU_VARIANT_LOWER = $(shell echo $(MCU_VARIANT) | tr '[:upper:]' '[:lower:]') + +HAL_DIR=st_driver/STM32$(MCU_SERIES)xx_HAL_Driver INC += -I. INC += -I../.. INC += -I$(BUILD) INC += -I$(BUILD)/genhdr -INC += -I./st_driver/STM32F4xx_HAL_Driver/Inc -INC += -I./st_driver/STM32F4xx_HAL_Driver/Inc/Legacy -INC += -I./st_driver/CMSIS/Device/ST/STM32F4xx/Include +INC += -I./$(HAL_DIR)/Inc +INC += -I./$(HAL_DIR)/Inc/Legacy +INC += -I./st_driver/CMSIS/Device/ST/STM32$(MCU_SERIES)xx/Include INC += -I./st_driver/CMSIS/Include INC += -I./boards INC += -I./boards/$(BOARD) INC += -I./peripherals +INC += -I./packages INC += -I../../lib/mp-readline INC += -I../../lib/tinyusb/src INC += -I../../supervisor/shared/usb @@ -87,11 +88,11 @@ else CFLAGS += -Os -DNDEBUG CFLAGS += -ggdb # TODO: Test with -flto - ### CFLAGS += -flto + # CFLAGS += -flto endif - -C_DEFS = -DMCU_PACKAGE=$(MCU_PACKAGE) -DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER -D$(CMSIS_MCU) +# MCU Series is defined by the HAL package and doesn't need to be specified here +C_DEFS = -D$(MCU_PACKAGE) -DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER -D$(MCU_VARIANT) CFLAGS += $(INC) -Werror -Wall -std=gnu11 -nostdlib $(BASE_CFLAGS) $(C_DEFS) $(CFLAGS_MOD) $(COPT) @@ -102,17 +103,24 @@ CFLAGS += -Wno-undef # STM32 might do casts that increase alignment requirements. CFLAGS += -Wno-cast-align -CFLAGS += \ - -mthumb \ - -mabi=aapcs-linux \ - -mfloat-abi=hard \ - -mcpu=cortex-m4 \ - -mfpu=fpv4-sp-d16 +CFLAGS += -mthumb -mabi=aapcs-linux -# TODO: check this -CFLAGS += -D__START=main +# Arm core selection +MCU_FLAGS_F4 = -mtune=cortex-m4 -mcpu=cortex-m4 +MCU_FLAGS_F7 = -mtune=cortex-m7 -mcpu=cortex-m7 +MCU_FLAGS_H7 = -mtune=cortex-m7 -mcpu=cortex-m7 +CFLAGS += $(MCU_FLAGS_$(MCU_SERIES)) -#need both command and valid file to use uf2 bootloader +CFLAGS += -DSTM32_HAL_H='' + +# Floating point settings +ifeq ($(MCU_VARIANT),$(filter $(MCU_VARIANT),STM32F765xx STM32F767xx STM32F769xx STM32H743xx)) +CFLAGS += -mfpu=fpv5-d16 -mfloat-abi=hard +else +CFLAGS += -mfpu=fpv4-sp-d16 -mfloat-abi=hard +endif + +# Need both command and valid file to use uf2 bootloader ifndef LD_FILE ifneq ($(and $(UF2_BOOTLOADER),$(LD_BOOT)),) LD_FILE = $(LD_BOOT) @@ -131,7 +139,7 @@ endif LDFLAGS = $(CFLAGS) -fshort-enums -Wl,-nostdlib -Wl,-T,$(LD_FILE) -Wl,-Map=$@.map -Wl,-cref -Wl,-gc-sections -specs=nano.specs LIBS := -lgcc -lc -LDFLAGS += -mthumb -mcpu=cortex-m4 +LDFLAGS += -mthumb $(MCU_FLAGS_$(MCU_SERIES)) # Use toolchain libm if we're not using our own. ifndef INTERNAL_LIBM @@ -139,55 +147,52 @@ LIBS += -lm endif # TinyUSB defines -CFLAGS += -DCFG_TUSB_MCU=OPT_MCU_STM32F4 -DCFG_TUD_CDC_RX_BUFSIZE=1024 -DCFG_TUD_CDC_TX_BUFSIZE=1024 -DCFG_TUD_MSC_BUFSIZE=4096 -DCFG_TUD_MIDI_RX_BUFSIZE=128 -DCFG_TUD_MIDI_TX_BUFSIZE=128 - - -###################################### -# source -###################################### - -SRC_STM32 = \ - st_driver/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c \ - st_driver/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c \ - st_driver/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac.c \ - st_driver/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac_ex.c \ - st_driver/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c \ - st_driver/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c \ - st_driver/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c \ - st_driver/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rng.c \ - st_driver/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c \ - st_driver/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c \ - st_driver/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c \ - st_driver/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c \ - st_driver/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c \ - st_driver/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c \ - st_driver/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_usart.c \ - st_driver/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c \ - st_driver/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c \ - st_driver/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c \ - st_driver/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c \ - st_driver/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c \ - st_driver/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c \ - st_driver/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c \ - st_driver/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c \ - st_driver/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c \ - st_driver/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c \ - st_driver/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c \ - st_driver/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c \ - st_driver/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c \ - st_driver/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c \ - st_driver/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_gpio.c \ - st_driver/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.c \ - st_driver/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fsmc.c \ - st_driver/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_i2c.c \ - st_driver/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_dma.c \ - st_driver/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c \ - st_driver/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usart.c \ - st_driver/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rcc.c \ - st_driver/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_utils.c \ - st_driver/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_exti.c \ - system_stm32f4xx.c - +CFLAGS += -DCFG_TUSB_MCU=OPT_MCU_STM32$(MCU_SERIES) -DCFG_TUD_CDC_RX_BUFSIZE=1024 -DCFG_TUD_CDC_TX_BUFSIZE=1024 -DCFG_TUD_MSC_BUFSIZE=4096 -DCFG_TUD_MIDI_RX_BUFSIZE=128 -DCFG_TUD_MIDI_TX_BUFSIZE=128 + +SRC_STM32 = $(addprefix $(HAL_DIR)/Src/stm32$(MCU_SERIES_LOWER)xx_,\ + hal_adc.c \ + hal_adc_ex.c \ + hal_dac.c \ + hal_dac_ex.c \ + hal_i2c.c \ + hal_i2c_ex.c \ + hal_qspi.c \ + hal_rng.c \ + hal_rtc.c \ + hal_rtc_ex.c \ + hal_spi.c \ + hal_tim.c \ + hal_tim_ex.c \ + hal_uart.c \ + hal_usart.c \ + hal_rcc.c \ + hal_rcc_ex.c \ + hal_flash.c \ + hal_flash_ex.c \ + hal_gpio.c \ + hal_dma_ex.c \ + hal_dma.c \ + hal_pwr.c \ + hal_pwr_ex.c \ + hal_cortex.c \ + hal.c \ + hal_exti.c \ + hal_sd.c \ + ll_gpio.c \ + ll_adc.c \ + ll_i2c.c \ + ll_dma.c \ + ll_sdmmc.c \ + ll_usart.c \ + ll_rcc.c \ + ll_utils.c \ + ll_exti.c \ + ) +#removed: +# hal_flash_ramfunc.c \ +# ll_fsmc.c \ + +SRC_STM32 += system_stm32$(MCU_SERIES_LOWER)xx.c SRC_C += \ background.c \ @@ -196,10 +201,11 @@ SRC_C += \ tick.c \ boards/$(BOARD)/board.c \ boards/$(BOARD)/pins.c \ - peripherals/stm32f4/$(MCU_SUB_VARIANT)/pins.c \ - peripherals/stm32f4/$(MCU_SUB_VARIANT)/clocks.c \ - peripherals/stm32f4/$(MCU_SUB_VARIANT)/gpio.c \ - peripherals/stm32f4/$(MCU_SUB_VARIANT)/periph.c \ + peripherals/stm32$(MCU_SERIES_LOWER)/$(MCU_VARIANT_LOWER)/pins.c \ + peripherals/stm32$(MCU_SERIES_LOWER)/$(MCU_VARIANT_LOWER)/clocks.c \ + peripherals/stm32$(MCU_SERIES_LOWER)/$(MCU_VARIANT_LOWER)/gpio.c \ + peripherals/stm32$(MCU_SERIES_LOWER)/$(MCU_VARIANT_LOWER)/periph.c \ + packages/$(MCU_PACKAGE).c\ lib/libc/string0.c \ lib/mp-readline/readline.c \ lib/oofatfs/ff.c \ @@ -219,7 +225,7 @@ endif SRC_S = \ supervisor/cpu.s \ - boards/startup_$(MCU_SUB_VARIANT).s + boards/startup_$(MCU_VARIANT_LOWER).s SRC_COMMON_HAL_EXPANDED = $(addprefix shared-bindings/, $(SRC_COMMON_HAL)) \ $(addprefix shared-bindings/, $(SRC_BINDINGS_ENUMS)) \ diff --git a/ports/stm/README.md b/ports/stm/README.md index a860c01ce4593..f2e3e9b67b1fb 100644 --- a/ports/stm/README.md +++ b/ports/stm/README.md @@ -1,3 +1,3 @@ -# CircuitPython Port To The ST Microelectronics STM32F4 Series +# CircuitPython Port To The ST Microelectronics STM32 Series -This is a port of CircuitPython to the STM32F4 series of chips. +This is a port of CircuitPython to the STM32 series of chips. diff --git a/ports/stm/background.h b/ports/stm/background.h index 05a4f894a6c05..6225429f89cb4 100644 --- a/ports/stm/background.h +++ b/ports/stm/background.h @@ -24,12 +24,12 @@ * THE SOFTWARE. */ -#ifndef MICROPY_INCLUDED_STM32F4_BACKGROUND_H -#define MICROPY_INCLUDED_STM32F4_BACKGROUND_H +#ifndef MICROPY_INCLUDED_STM32_BACKGROUND_H +#define MICROPY_INCLUDED_STM32_BACKGROUND_H #include void background_tasks_reset(void); void run_background_tasks(void); -#endif // MICROPY_INCLUDED_STM32F4_BACKGROUND_H +#endif // MICROPY_INCLUDED_STM32_BACKGROUND_H diff --git a/ports/stm/boards/STM32H743ZITx_FLASH.ld b/ports/stm/boards/STM32H743ZITx_FLASH.ld new file mode 100644 index 0000000000000..38b1fe4eaae9b --- /dev/null +++ b/ports/stm/boards/STM32H743ZITx_FLASH.ld @@ -0,0 +1,193 @@ +/* +****************************************************************************** +** + +** File : LinkerScript.ld +** +** Author : Auto-generated by System Workbench for STM32 +** +** Abstract : Linker script for STM32H743ZITx series +** 2048Kbytes FLASH and 1056Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed “as is,” without any warranty +** of any kind. +** +***************************************************************************** +** @attention +** +**

© COPYRIGHT(c) 2019 STMicroelectronics

+** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** 1. Redistributions of source code must retain the above copyright notice, +** this list of conditions and the following disclaimer. +** 2. Redistributions in binary form must reproduce the above copyright notice, +** this list of conditions and the following disclaimer in the documentation +** and/or other materials provided with the distribution. +** 3. Neither the name of STMicroelectronics nor the names of its contributors +** may be used to endorse or promote products derived from this software +** without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20020000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +DTCMRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K +RAM_D1 (xrw) : ORIGIN = 0x24000000, LENGTH = 512K +RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K +RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K +ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 2048K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >DTCMRAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >DTCMRAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >DTCMRAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/ports/stm/boards/STM32H743_fs.ld b/ports/stm/boards/STM32H743_fs.ld new file mode 100644 index 0000000000000..395a074d3249c --- /dev/null +++ b/ports/stm/boards/STM32H743_fs.ld @@ -0,0 +1,164 @@ +/* +****************************************************************************** +** + +** File : LinkerScript.ld +** +** Author : Auto-generated by System Workbench for STM32 +** +** Abstract : Linker script for STM32H743ZITx series +** 2048Kbytes FLASH and 1056Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed “as is,” without any warranty +** of any kind. +** +***************************************************************************** +** @attention +** +**

© COPYRIGHT(c) 2019 STMicroelectronics

+** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** 1. Redistributions of source code must retain the above copyright notice, +** this list of conditions and the following disclaimer. +** 2. Redistributions in binary form must reproduce the above copyright notice, +** this list of conditions and the following disclaimer in the documentation +** and/or other materials provided with the distribution. +** 3. Neither the name of STMicroelectronics nor the names of its contributors +** may be used to endorse or promote products derived from this software +** without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20020000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 2048K + FLASH_ISR (rx) : ORIGIN = 0x08000000, LENGTH = 128K /* sector 0, 128K */ + FLASH_FS (r) : ORIGIN = 0x08020000, LENGTH = 128K /* sector 1, 128K */ + FLASH_TEXT (rx) : ORIGIN = 0x08040000, LENGTH = 1792K /* sectors 6*128 + 8*128 */ + DTCM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K /* Used for storage cache */ + RAM (xrw) : ORIGIN = 0x24000000, LENGTH = 512K /* AXI SRAM */ +} + +/* produce a link error if there is not this amount of RAM for these sections */ +_minimum_stack_size = 2K; +_minimum_heap_size = 16K; + +/* Define tho top end of the stack. The stack is full descending so begins just + above last byte of RAM. Note that EABI requires the stack to be 8-byte + aligned for a call. */ +_estack = ORIGIN(RAM) + LENGTH(RAM); + +/* RAM extents for the garbage collector */ +_ram_start = ORIGIN(RAM); +_ram_end = ORIGIN(RAM) + LENGTH(RAM); + +ENTRY(Reset_Handler) + +/* define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + + /* This first flash block is 16K annd the isr vectors only take up + about 400 bytes. Micropython pads this with files, but this didn't + work with the size of Circuitpython's ff object. */ + + . = ALIGN(4); + } >FLASH_ISR + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text*) /* .text* sections (code) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + /* *(.glue_7) */ /* glue arm to thumb code */ + /* *(.glue_7t) */ /* glue thumb to arm code */ + + . = ALIGN(4); + _etext = .; /* define a global symbol at end of code */ + } >FLASH_TEXT + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* This is the initialized data section + The program executes knowing that the data is in the RAM + but the loader puts the initial values in the FLASH (inidata). + It is one task of the startup to copy the initial values from FLASH to RAM. */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */ + } >RAM AT> FLASH_TEXT + + /* Uninitialized data section */ + .bss : + { + . = ALIGN(4); + _sbss = .; /* define a global symbol at bss start; used by startup code */ + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end; used by startup code and GC */ + } >RAM + + /* this is to define the start of the heap, and make sure we have a minimum size */ + .heap : + { + . = ALIGN(4); + . = . + _minimum_heap_size; + . = ALIGN(4); + } >RAM + + /* this just checks there is enough RAM for the stack */ + .stack : + { + . = ALIGN(4); + . = . + _minimum_stack_size; + . = ALIGN(4); + } >RAM + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/ports/stm/boards/espruino_pico/mpconfigboard.mk b/ports/stm/boards/espruino_pico/mpconfigboard.mk index 151ca1437a912..01264d512b9f8 100644 --- a/ports/stm/boards/espruino_pico/mpconfigboard.mk +++ b/ports/stm/boards/espruino_pico/mpconfigboard.mk @@ -5,12 +5,10 @@ USB_MANUFACTURER = "Espruino" USB_DEVICES = "CDC,MSC" INTERNAL_FLASH_FILESYSTEM = 1 -LONGINT_IMPL = NONE -MCU_SERIES = m4 -MCU_VARIANT = stm32f4 -MCU_SUB_VARIANT = stm32f401xe -MCU_PACKAGE = 48 -CMSIS_MCU = STM32F401xE +MCU_SERIES = F4 +MCU_VARIANT = STM32F401xE +MCU_PACKAGE = UFQFPN48 + LD_FILE = boards/STM32F401xd_fs.ld # use for internal flash diff --git a/ports/stm/boards/espruino_wifi/mpconfigboard.mk b/ports/stm/boards/espruino_wifi/mpconfigboard.mk index 8b28cf07c7f77..b4b394443989e 100644 --- a/ports/stm/boards/espruino_wifi/mpconfigboard.mk +++ b/ports/stm/boards/espruino_wifi/mpconfigboard.mk @@ -5,12 +5,10 @@ USB_MANUFACTURER = "Espruino" USB_DEVICES = "CDC,MSC" INTERNAL_FLASH_FILESYSTEM = 1 -LONGINT_IMPL = NONE -MCU_SERIES = m4 -MCU_VARIANT = stm32f4 -MCU_SUB_VARIANT = stm32f411xe -MCU_PACKAGE = 48 -CMSIS_MCU = STM32F411xE +MCU_SERIES = F4 +MCU_VARIANT = STM32F411xE +MCU_PACKAGE = UFQFPN48 + LD_FILE = boards/STM32F411VETx_FLASH.ld diff --git a/ports/stm/boards/feather_stm32f405_express/mpconfigboard.mk b/ports/stm/boards/feather_stm32f405_express/mpconfigboard.mk index 312ca6b480ef5..351adf1b8cd38 100644 --- a/ports/stm/boards/feather_stm32f405_express/mpconfigboard.mk +++ b/ports/stm/boards/feather_stm32f405_express/mpconfigboard.mk @@ -7,15 +7,11 @@ USB_DEVICES = "CDC,MSC" SPI_FLASH_FILESYSTEM = 1 EXTERNAL_FLASH_DEVICE_COUNT = 1 EXTERNAL_FLASH_DEVICES = GD25Q16C -LONGINT_IMPL = MPZ -MCU_SERIES = m4 -MCU_VARIANT = stm32f4 -MCU_SUB_VARIANT = stm32f405xx -MCU_PACKAGE = 64 -CMSIS_MCU = STM32F405xx +MCU_SERIES = F4 +MCU_VARIANT = STM32F405xx +MCU_PACKAGE = LQFP64 -# Default includes filesystem, but uses external flash LD_DEFAULT = boards/STM32F405_default.ld LD_BOOT = boards/STM32F405_boot.ld # UF2 boot option UF2_OFFSET = 0x8010000 diff --git a/ports/stm/boards/meowbit_v121/mpconfigboard.mk b/ports/stm/boards/meowbit_v121/mpconfigboard.mk index 16268ba11935d..0a725d75ba724 100644 --- a/ports/stm/boards/meowbit_v121/mpconfigboard.mk +++ b/ports/stm/boards/meowbit_v121/mpconfigboard.mk @@ -7,18 +7,14 @@ USB_DEVICES = "CDC,MSC" SPI_FLASH_FILESYSTEM = 1 EXTERNAL_FLASH_DEVICE_COUNT = 1 EXTERNAL_FLASH_DEVICES = W25Q16JV_IQ -LONGINT_IMPL = MPZ +# INTERNAL_FLASH_FILESYSTEM = 1 BOOTLOADER_OFFSET = 0x8010000 -# INTERNAL_FLASH_FILESYSTEM = 1 -# LONGINT_IMPL = NONE +MCU_SERIES = F4 +MCU_VARIANT = STM32F401xE +MCU_PACKAGE = LQFP64 -MCU_SERIES = m4 -MCU_VARIANT = stm32f4 -MCU_SUB_VARIANT = stm32f401xe -MCU_PACKAGE = 64 -CMSIS_MCU = STM32F401xE LD_FILE = boards/STM32F401xe_boot.ld # LD_FILE = boards/STM32F401xe_fs.ld # use for internal flash diff --git a/ports/stm/boards/pyb_nano_v2/mpconfigboard.mk b/ports/stm/boards/pyb_nano_v2/mpconfigboard.mk index a8472608b747d..e9f1d0369ef06 100644 --- a/ports/stm/boards/pyb_nano_v2/mpconfigboard.mk +++ b/ports/stm/boards/pyb_nano_v2/mpconfigboard.mk @@ -7,12 +7,10 @@ USB_DEVICES = "CDC,MSC" SPI_FLASH_FILESYSTEM = 1 EXTERNAL_FLASH_DEVICE_COUNT = 1 EXTERNAL_FLASH_DEVICES = W25Q64JV_IQ -LONGINT_IMPL = MPZ -MCU_SERIES = m4 -MCU_VARIANT = stm32f4 -MCU_SUB_VARIANT = stm32f411xe -MCU_PACKAGE = 48 -CMSIS_MCU = STM32F411xE +MCU_SERIES = F4 +MCU_VARIANT = STM32F411xE +MCU_PACKAGE = UFQFPN48 + LD_FILE = boards/STM32F411VETx_FLASH.ld diff --git a/ports/stm/boards/pyboard_v11/mpconfigboard.mk b/ports/stm/boards/pyboard_v11/mpconfigboard.mk index ef1b8f0ca156d..ab2ce86a983ad 100644 --- a/ports/stm/boards/pyboard_v11/mpconfigboard.mk +++ b/ports/stm/boards/pyboard_v11/mpconfigboard.mk @@ -5,12 +5,10 @@ USB_MANUFACTURER = "George Robotic" USB_DEVICES = "CDC,MSC" INTERNAL_FLASH_FILESYSTEM = 1 -LONGINT_IMPL = NONE -MCU_SERIES = m4 -MCU_VARIANT = stm32f4 -MCU_SUB_VARIANT = stm32f405xx -MCU_PACKAGE = 64 -CMSIS_MCU = STM32F405xx +MCU_SERIES = F4 +MCU_VARIANT = STM32F405xx +MCU_PACKAGE = LQFP64 + LD_FILE = boards/STM32F405_fs.ld diff --git a/ports/stm/boards/startup_stm32h743xx.s b/ports/stm/boards/startup_stm32h743xx.s new file mode 100644 index 0000000000000..357f7a7bab039 --- /dev/null +++ b/ports/stm/boards/startup_stm32h743xx.s @@ -0,0 +1,748 @@ +/** + ****************************************************************************** + * @file startup_stm32h743xx.s + * @author MCD Application Team + * @brief STM32H743xx Devices vector table for GCC based toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m7 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ +/* bl __libc_init_array */ +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */ + .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */ + .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */ + .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */ + .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */ + .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word 0 /* Reserved */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FMC_IRQHandler /* FMC */ + .word SDMMC1_IRQHandler /* SDMMC1 */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word 0 /* Reserved */ + .word RNG_IRQHandler /* Rng */ + .word FPU_IRQHandler /* FPU */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word SPI6_IRQHandler /* SPI6 */ + .word SAI1_IRQHandler /* SAI1 */ + .word LTDC_IRQHandler /* LTDC */ + .word LTDC_ER_IRQHandler /* LTDC error */ + .word DMA2D_IRQHandler /* DMA2D */ + .word SAI2_IRQHandler /* SAI2 */ + .word QUADSPI_IRQHandler /* QUADSPI */ + .word LPTIM1_IRQHandler /* LPTIM1 */ + .word CEC_IRQHandler /* HDMI_CEC */ + .word I2C4_EV_IRQHandler /* I2C4 Event */ + .word I2C4_ER_IRQHandler /* I2C4 Error */ + .word SPDIF_RX_IRQHandler /* SPDIF_RX */ + .word OTG_FS_EP1_OUT_IRQHandler /* USB OTG FS End Point 1 Out */ + .word OTG_FS_EP1_IN_IRQHandler /* USB OTG FS End Point 1 In */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */ + .word HRTIM1_Master_IRQHandler /* HRTIM Master Timer global Interrupt */ + .word HRTIM1_TIMA_IRQHandler /* HRTIM Timer A global Interrupt */ + .word HRTIM1_TIMB_IRQHandler /* HRTIM Timer B global Interrupt */ + .word HRTIM1_TIMC_IRQHandler /* HRTIM Timer C global Interrupt */ + .word HRTIM1_TIMD_IRQHandler /* HRTIM Timer D global Interrupt */ + .word HRTIM1_TIME_IRQHandler /* HRTIM Timer E global Interrupt */ + .word HRTIM1_FLT_IRQHandler /* HRTIM Fault global Interrupt */ + .word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */ + .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */ + .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */ + .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */ + .word SAI3_IRQHandler /* SAI3 global Interrupt */ + .word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */ + .word TIM15_IRQHandler /* TIM15 global Interrupt */ + .word TIM16_IRQHandler /* TIM16 global Interrupt */ + .word TIM17_IRQHandler /* TIM17 global Interrupt */ + .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */ + .word MDIOS_IRQHandler /* MDIOS global Interrupt */ + .word JPEG_IRQHandler /* JPEG global Interrupt */ + .word MDMA_IRQHandler /* MDMA global Interrupt */ + .word 0 /* Reserved */ + .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */ + .word HSEM1_IRQHandler /* HSEM1 global Interrupt */ + .word 0 /* Reserved */ + .word ADC3_IRQHandler /* ADC3 global Interrupt */ + .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */ + .word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */ + .word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */ + .word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */ + .word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */ + .word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */ + .word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */ + .word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */ + .word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */ + .word COMP1_IRQHandler /* COMP1 global Interrupt */ + .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */ + .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */ + .word LPTIM4_IRQHandler /* LP TIM4 global interrupt */ + .word LPTIM5_IRQHandler /* LP TIM5 global interrupt */ + .word LPUART1_IRQHandler /* LP UART1 interrupt */ + .word 0 /* Reserved */ + .word CRS_IRQHandler /* Clock Recovery Global Interrupt */ + .word ECC_IRQHandler /* ECC diagnostic Global Interrupt */ + .word SAI4_IRQHandler /* SAI4 global interrupt */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_AVD_IRQHandler + .thumb_set PVD_AVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak FDCAN1_IT0_IRQHandler + .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler + + .weak FDCAN2_IT0_IRQHandler + .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler + + .weak FDCAN1_IT1_IRQHandler + .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler + + .weak FDCAN2_IT1_IRQHandler + .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak FDCAN_CAL_IRQHandler + .thumb_set FDCAN_CAL_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak LTDC_IRQHandler + .thumb_set LTDC_IRQHandler,Default_Handler + + .weak LTDC_ER_IRQHandler + .thumb_set LTDC_ER_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set DMA2D_IRQHandler,Default_Handler + + .weak SAI2_IRQHandler + .thumb_set SAI2_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak I2C4_EV_IRQHandler + .thumb_set I2C4_EV_IRQHandler,Default_Handler + + .weak I2C4_ER_IRQHandler + .thumb_set I2C4_ER_IRQHandler,Default_Handler + + .weak SPDIF_RX_IRQHandler + .thumb_set SPDIF_RX_IRQHandler,Default_Handler + + .weak OTG_FS_EP1_OUT_IRQHandler + .thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_FS_EP1_IN_IRQHandler + .thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMAMUX1_OVR_IRQHandler + .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler + + .weak HRTIM1_Master_IRQHandler + .thumb_set HRTIM1_Master_IRQHandler,Default_Handler + + .weak HRTIM1_TIMA_IRQHandler + .thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler + + .weak HRTIM1_TIMB_IRQHandler + .thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler + + .weak HRTIM1_TIMC_IRQHandler + .thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler + + .weak HRTIM1_TIMD_IRQHandler + .thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler + + .weak HRTIM1_TIME_IRQHandler + .thumb_set HRTIM1_TIME_IRQHandler,Default_Handler + + .weak HRTIM1_FLT_IRQHandler + .thumb_set HRTIM1_FLT_IRQHandler,Default_Handler + + .weak DFSDM1_FLT0_IRQHandler + .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler + + .weak DFSDM1_FLT1_IRQHandler + .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler + + .weak DFSDM1_FLT2_IRQHandler + .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler + + .weak DFSDM1_FLT3_IRQHandler + .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler + + .weak SAI3_IRQHandler + .thumb_set SAI3_IRQHandler,Default_Handler + + .weak SWPMI1_IRQHandler + .thumb_set SWPMI1_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak MDIOS_WKUP_IRQHandler + .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler + + .weak MDIOS_IRQHandler + .thumb_set MDIOS_IRQHandler,Default_Handler + + .weak JPEG_IRQHandler + .thumb_set JPEG_IRQHandler,Default_Handler + + .weak MDMA_IRQHandler + .thumb_set MDMA_IRQHandler,Default_Handler + + .weak SDMMC2_IRQHandler + .thumb_set SDMMC2_IRQHandler,Default_Handler + + .weak HSEM1_IRQHandler + .thumb_set HSEM1_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak DMAMUX2_OVR_IRQHandler + .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler + + .weak BDMA_Channel0_IRQHandler + .thumb_set BDMA_Channel0_IRQHandler,Default_Handler + + .weak BDMA_Channel1_IRQHandler + .thumb_set BDMA_Channel1_IRQHandler,Default_Handler + + .weak BDMA_Channel2_IRQHandler + .thumb_set BDMA_Channel2_IRQHandler,Default_Handler + + .weak BDMA_Channel3_IRQHandler + .thumb_set BDMA_Channel3_IRQHandler,Default_Handler + + .weak BDMA_Channel4_IRQHandler + .thumb_set BDMA_Channel4_IRQHandler,Default_Handler + + .weak BDMA_Channel5_IRQHandler + .thumb_set BDMA_Channel5_IRQHandler,Default_Handler + + .weak BDMA_Channel6_IRQHandler + .thumb_set BDMA_Channel6_IRQHandler,Default_Handler + + .weak BDMA_Channel7_IRQHandler + .thumb_set BDMA_Channel7_IRQHandler,Default_Handler + + .weak COMP1_IRQHandler + .thumb_set COMP1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak LPTIM3_IRQHandler + .thumb_set LPTIM3_IRQHandler,Default_Handler + + .weak LPTIM4_IRQHandler + .thumb_set LPTIM4_IRQHandler,Default_Handler + + .weak LPTIM5_IRQHandler + .thumb_set LPTIM5_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak CRS_IRQHandler + .thumb_set CRS_IRQHandler,Default_Handler + + .weak ECC_IRQHandler + .thumb_set ECC_IRQHandler,Default_Handler + + .weak SAI4_IRQHandler + .thumb_set SAI4_IRQHandler,Default_Handler + + .weak WAKEUP_PIN_IRQHandler + .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/ports/stm/boards/stm32f411ce_blackpill/mpconfigboard.mk b/ports/stm/boards/stm32f411ce_blackpill/mpconfigboard.mk index 68c6a1eeaa56b..bf2dd55965682 100644 --- a/ports/stm/boards/stm32f411ce_blackpill/mpconfigboard.mk +++ b/ports/stm/boards/stm32f411ce_blackpill/mpconfigboard.mk @@ -10,12 +10,10 @@ USB_DEVICES = "CDC,MSC" # LONGINT_IMPL = MPZ INTERNAL_FLASH_FILESYSTEM = 1 -LONGINT_IMPL = NONE -MCU_SERIES = m4 -MCU_VARIANT = stm32f4 -MCU_SUB_VARIANT = stm32f411xe -MCU_PACKAGE = 48 -CMSIS_MCU = STM32F411xE +MCU_SERIES = F4 +MCU_VARIANT = STM32F411xE +MCU_PACKAGE = UFQFPN48 + LD_FILE = boards/STM32F411VETx_FLASH.ld diff --git a/ports/stm/boards/stm32f411ve_discovery/mpconfigboard.mk b/ports/stm/boards/stm32f411ve_discovery/mpconfigboard.mk index 64e2b4dc53c19..da24fe3f0acfe 100644 --- a/ports/stm/boards/stm32f411ve_discovery/mpconfigboard.mk +++ b/ports/stm/boards/stm32f411ve_discovery/mpconfigboard.mk @@ -5,12 +5,10 @@ USB_MANUFACTURER = "STMicroelectronics" USB_DEVICES = "CDC,MSC" INTERNAL_FLASH_FILESYSTEM = 1 -LONGINT_IMPL = NONE -MCU_SERIES = m4 -MCU_VARIANT = stm32f4 -MCU_SUB_VARIANT = stm32f411xe -MCU_PACKAGE = 100 -CMSIS_MCU = STM32F411xE +MCU_SERIES = F4 +MCU_VARIANT = STM32F411xE +MCU_PACKAGE = LQFP100_f4 + LD_FILE = boards/STM32F411VETx_FLASH.ld diff --git a/ports/stm/boards/stm32f412zg_discovery/mpconfigboard.mk b/ports/stm/boards/stm32f412zg_discovery/mpconfigboard.mk index b0205fc73309d..d227803de7331 100644 --- a/ports/stm/boards/stm32f412zg_discovery/mpconfigboard.mk +++ b/ports/stm/boards/stm32f412zg_discovery/mpconfigboard.mk @@ -5,18 +5,16 @@ USB_MANUFACTURER = "STMicroelectronics" USB_DEVICES = "CDC,MSC,HID" INTERNAL_FLASH_FILESYSTEM = 1 -LONGINT_IMPL = NONE # QSPI_FLASH_FILESYSTEM = 1 # EXTERNAL_FLASH_DEVICE_COUNT = 1 # EXTERNAL_FLASH_DEVICES = N25Q128A # LONGINT_IMPL = MPZ -MCU_SERIES = m4 -MCU_VARIANT = stm32f4 -MCU_SUB_VARIANT = stm32f412zx -MCU_PACKAGE = 144 -CMSIS_MCU = STM32F412Zx +MCU_SERIES = F4 +MCU_VARIANT = STM32F412Zx +MCU_PACKAGE = LQFP144 + LD_FILE = boards/STM32F412ZGTx_FLASH.ld diff --git a/ports/stm/boards/stm32f4_discovery/mpconfigboard.mk b/ports/stm/boards/stm32f4_discovery/mpconfigboard.mk index 312a20f65ada5..c8c424c0c493d 100644 --- a/ports/stm/boards/stm32f4_discovery/mpconfigboard.mk +++ b/ports/stm/boards/stm32f4_discovery/mpconfigboard.mk @@ -5,14 +5,10 @@ USB_MANUFACTURER = "STMicroelectronics" USB_DEVICES = "CDC,MSC" INTERNAL_FLASH_FILESYSTEM = 1 -LONGINT_IMPL = NONE -# This is technically a F407 but there's no difference -# other than the camera and ethernet, which aren't supported. -MCU_SERIES = m4 -MCU_VARIANT = stm32f4 -MCU_SUB_VARIANT = stm32f407xx -MCU_PACKAGE = 100 -CMSIS_MCU = STM32F407xx +MCU_SERIES = F4 +MCU_VARIANT = STM32F407xx +MCU_PACKAGE = LQFP100_f4 + LD_FILE = boards/STM32F407_fs.ld diff --git a/ports/stm/boards/stm32h743zi_discovery/board.c b/ports/stm/boards/stm32h743zi_discovery/board.c new file mode 100644 index 0000000000000..4421970eefe4d --- /dev/null +++ b/ports/stm/boards/stm32h743zi_discovery/board.c @@ -0,0 +1,38 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "boards/board.h" + +void board_init(void) { +} + +bool board_requests_safe_mode(void) { + return false; +} + +void reset_board(void) { + +} diff --git a/ports/stm/boards/stm32h743zi_discovery/mpconfigboard.h b/ports/stm/boards/stm32h743zi_discovery/mpconfigboard.h new file mode 100644 index 0000000000000..6a62ff512a2be --- /dev/null +++ b/ports/stm/boards/stm32h743zi_discovery/mpconfigboard.h @@ -0,0 +1,35 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +//Micropython setup + +#define MICROPY_HW_BOARD_NAME "STM32H743_DISCO" +#define MICROPY_HW_MCU_NAME "STM32H743" + +// #define FLASH_SIZE (0x200000) +#define FLASH_PAGE_SIZE (0x4000) + +#define BOARD_OSC_DIV (8) diff --git a/ports/stm/boards/stm32h743zi_discovery/mpconfigboard.mk b/ports/stm/boards/stm32h743zi_discovery/mpconfigboard.mk new file mode 100644 index 0000000000000..d2f89053683b7 --- /dev/null +++ b/ports/stm/boards/stm32h743zi_discovery/mpconfigboard.mk @@ -0,0 +1,14 @@ +USB_VID = 0x239A #REPLACE +USB_PID = 0x808A #REPLACE +USB_PRODUCT = "STM32H743ZI Discovery Board - CPy" +USB_MANUFACTURER = "STMicroelectronics" +USB_DEVICES = "CDC,HID" + +DISABLE_FILESYSTEM = 1 + +MCU_SERIES = H7 +MCU_VARIANT = STM32H743xx +MCU_PACKAGE = LQFP144 + +LD_FILE = boards/STM32H743_fs.ld + diff --git a/ports/stm/boards/stm32h743zi_discovery/pins.c b/ports/stm/boards/stm32h743zi_discovery/pins.c new file mode 100644 index 0000000000000..eceea93820c97 --- /dev/null +++ b/ports/stm/boards/stm32h743zi_discovery/pins.c @@ -0,0 +1,135 @@ +#include "shared-bindings/board/__init__.h" + +STATIC const mp_rom_map_elem_t board_module_globals_table[] = { + { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA03) }, + { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PC00) }, + { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PC03) }, + { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PB01) }, + { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PC02) }, + { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PF10) }, + { MP_ROM_QSTR(MP_QSTR_A6), MP_ROM_PTR(&pin_PF04) }, + { MP_ROM_QSTR(MP_QSTR_A7), MP_ROM_PTR(&pin_PF05) }, + { MP_ROM_QSTR(MP_QSTR_A8), MP_ROM_PTR(&pin_PF06) }, + { MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_PB07) }, + { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PB06) }, + { MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_PG14) }, + { MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_PE13) }, + { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PE14) }, + { MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PE11) }, + { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PE09) }, + { MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_PG12) }, + { MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PF03) }, + { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PD15) }, + { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PD14) }, + { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PB05) }, + { MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PA06) }, + { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA07) }, + { MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_PB09) }, + { MP_ROM_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_PB08) }, + { MP_ROM_QSTR(MP_QSTR_D16), MP_ROM_PTR(&pin_PC06) }, + { MP_ROM_QSTR(MP_QSTR_D17), MP_ROM_PTR(&pin_PB15) }, + { MP_ROM_QSTR(MP_QSTR_D18), MP_ROM_PTR(&pin_PB13) }, + { MP_ROM_QSTR(MP_QSTR_D19), MP_ROM_PTR(&pin_PB12) }, + { MP_ROM_QSTR(MP_QSTR_D20), MP_ROM_PTR(&pin_PA15) }, + { MP_ROM_QSTR(MP_QSTR_D21), MP_ROM_PTR(&pin_PC07) }, + { MP_ROM_QSTR(MP_QSTR_D22), MP_ROM_PTR(&pin_PB05) }, + { MP_ROM_QSTR(MP_QSTR_D23), MP_ROM_PTR(&pin_PB03) }, + { MP_ROM_QSTR(MP_QSTR_D24), MP_ROM_PTR(&pin_PA04) }, + { MP_ROM_QSTR(MP_QSTR_D25), MP_ROM_PTR(&pin_PB04) }, + { MP_ROM_QSTR(MP_QSTR_D26), MP_ROM_PTR(&pin_PG06) }, + { MP_ROM_QSTR(MP_QSTR_D27), MP_ROM_PTR(&pin_PB02) }, + { MP_ROM_QSTR(MP_QSTR_D28), MP_ROM_PTR(&pin_PD13) }, + { MP_ROM_QSTR(MP_QSTR_D29), MP_ROM_PTR(&pin_PD12) }, + { MP_ROM_QSTR(MP_QSTR_D30), MP_ROM_PTR(&pin_PD11) }, + { MP_ROM_QSTR(MP_QSTR_D31), MP_ROM_PTR(&pin_PE02) }, + { MP_ROM_QSTR(MP_QSTR_D32), MP_ROM_PTR(&pin_PA00) }, + { MP_ROM_QSTR(MP_QSTR_D33), MP_ROM_PTR(&pin_PB00) }, + { MP_ROM_QSTR(MP_QSTR_D34), MP_ROM_PTR(&pin_PE00) }, + { MP_ROM_QSTR(MP_QSTR_D35), MP_ROM_PTR(&pin_PB11) }, + { MP_ROM_QSTR(MP_QSTR_D36), MP_ROM_PTR(&pin_PB10) }, + { MP_ROM_QSTR(MP_QSTR_D37), MP_ROM_PTR(&pin_PE15) }, + { MP_ROM_QSTR(MP_QSTR_D38), MP_ROM_PTR(&pin_PE06) }, + { MP_ROM_QSTR(MP_QSTR_D39), MP_ROM_PTR(&pin_PE12) }, + { MP_ROM_QSTR(MP_QSTR_D40), MP_ROM_PTR(&pin_PE10) }, + { MP_ROM_QSTR(MP_QSTR_D41), MP_ROM_PTR(&pin_PE07) }, + { MP_ROM_QSTR(MP_QSTR_D42), MP_ROM_PTR(&pin_PE08) }, + { MP_ROM_QSTR(MP_QSTR_D43), MP_ROM_PTR(&pin_PC08) }, + { MP_ROM_QSTR(MP_QSTR_D44), MP_ROM_PTR(&pin_PC09) }, + { MP_ROM_QSTR(MP_QSTR_D45), MP_ROM_PTR(&pin_PC10) }, + { MP_ROM_QSTR(MP_QSTR_D46), MP_ROM_PTR(&pin_PC11) }, + { MP_ROM_QSTR(MP_QSTR_D47), MP_ROM_PTR(&pin_PC12) }, + { MP_ROM_QSTR(MP_QSTR_D48), MP_ROM_PTR(&pin_PD02) }, + { MP_ROM_QSTR(MP_QSTR_D49), MP_ROM_PTR(&pin_PG02) }, + { MP_ROM_QSTR(MP_QSTR_D50), MP_ROM_PTR(&pin_PG03) }, + { MP_ROM_QSTR(MP_QSTR_D51), MP_ROM_PTR(&pin_PD07) }, + { MP_ROM_QSTR(MP_QSTR_D52), MP_ROM_PTR(&pin_PD06) }, + { MP_ROM_QSTR(MP_QSTR_D53), MP_ROM_PTR(&pin_PD05) }, + { MP_ROM_QSTR(MP_QSTR_D54), MP_ROM_PTR(&pin_PD04) }, + { MP_ROM_QSTR(MP_QSTR_D55), MP_ROM_PTR(&pin_PD03) }, + { MP_ROM_QSTR(MP_QSTR_D56), MP_ROM_PTR(&pin_PE02) }, + { MP_ROM_QSTR(MP_QSTR_D57), MP_ROM_PTR(&pin_PE04) }, + { MP_ROM_QSTR(MP_QSTR_D58), MP_ROM_PTR(&pin_PE05) }, + { MP_ROM_QSTR(MP_QSTR_D59), MP_ROM_PTR(&pin_PE06) }, + { MP_ROM_QSTR(MP_QSTR_D60), MP_ROM_PTR(&pin_PE03) }, + { MP_ROM_QSTR(MP_QSTR_D61), MP_ROM_PTR(&pin_PF08) }, + { MP_ROM_QSTR(MP_QSTR_D62), MP_ROM_PTR(&pin_PF07) }, + { MP_ROM_QSTR(MP_QSTR_D63), MP_ROM_PTR(&pin_PF09) }, + { MP_ROM_QSTR(MP_QSTR_D64), MP_ROM_PTR(&pin_PG01) }, + { MP_ROM_QSTR(MP_QSTR_D65), MP_ROM_PTR(&pin_PG00) }, + { MP_ROM_QSTR(MP_QSTR_D66), MP_ROM_PTR(&pin_PD01) }, + { MP_ROM_QSTR(MP_QSTR_D67), MP_ROM_PTR(&pin_PD00) }, + { MP_ROM_QSTR(MP_QSTR_D68), MP_ROM_PTR(&pin_PF00) }, + { MP_ROM_QSTR(MP_QSTR_D69), MP_ROM_PTR(&pin_PF01) }, + { MP_ROM_QSTR(MP_QSTR_D70), MP_ROM_PTR(&pin_PF02) }, + { MP_ROM_QSTR(MP_QSTR_D71), MP_ROM_PTR(&pin_PE09) }, + { MP_ROM_QSTR(MP_QSTR_D72), MP_ROM_PTR(&pin_PB02) }, + { MP_ROM_QSTR(MP_QSTR_DAC1), MP_ROM_PTR(&pin_PA04) }, + { MP_ROM_QSTR(MP_QSTR_DAC2), MP_ROM_PTR(&pin_PA05) }, + { MP_ROM_QSTR(MP_QSTR_LED1), MP_ROM_PTR(&pin_PB00) }, + { MP_ROM_QSTR(MP_QSTR_LED2), MP_ROM_PTR(&pin_PB07) }, + { MP_ROM_QSTR(MP_QSTR_LED3), MP_ROM_PTR(&pin_PB14) }, + { MP_ROM_QSTR(MP_QSTR_SW), MP_ROM_PTR(&pin_PC13) }, + { MP_ROM_QSTR(MP_QSTR_I2C1_SDA), MP_ROM_PTR(&pin_PB09) }, + { MP_ROM_QSTR(MP_QSTR_I2C1_SCL), MP_ROM_PTR(&pin_PB08) }, + { MP_ROM_QSTR(MP_QSTR_I2C2_SDA), MP_ROM_PTR(&pin_PF00) }, + { MP_ROM_QSTR(MP_QSTR_I2C2_SCL), MP_ROM_PTR(&pin_PF01) }, + { MP_ROM_QSTR(MP_QSTR_I2C4_SCL), MP_ROM_PTR(&pin_PF14) }, + { MP_ROM_QSTR(MP_QSTR_I2C4_SDA), MP_ROM_PTR(&pin_PF15) }, + { MP_ROM_QSTR(MP_QSTR_SD_D0), MP_ROM_PTR(&pin_PC08) }, + { MP_ROM_QSTR(MP_QSTR_SD_D1), MP_ROM_PTR(&pin_PC09) }, + { MP_ROM_QSTR(MP_QSTR_SD_D2), MP_ROM_PTR(&pin_PC10) }, + { MP_ROM_QSTR(MP_QSTR_SD_D3), MP_ROM_PTR(&pin_PC11) }, + { MP_ROM_QSTR(MP_QSTR_SD_CMD), MP_ROM_PTR(&pin_PD02) }, + { MP_ROM_QSTR(MP_QSTR_SD_CK), MP_ROM_PTR(&pin_PC12) }, + { MP_ROM_QSTR(MP_QSTR_SD_SW), MP_ROM_PTR(&pin_PG02) }, + { MP_ROM_QSTR(MP_QSTR_OTG_FS_POWER), MP_ROM_PTR(&pin_PG06) }, + { MP_ROM_QSTR(MP_QSTR_OTG_FS_OVER_CURRENT), MP_ROM_PTR(&pin_PG07) }, + { MP_ROM_QSTR(MP_QSTR_USB_VBUS), MP_ROM_PTR(&pin_PA09) }, + { MP_ROM_QSTR(MP_QSTR_USB_ID), MP_ROM_PTR(&pin_PA10) }, + { MP_ROM_QSTR(MP_QSTR_USB_DM), MP_ROM_PTR(&pin_PA11) }, + { MP_ROM_QSTR(MP_QSTR_USB_DP), MP_ROM_PTR(&pin_PA12) }, + { MP_ROM_QSTR(MP_QSTR_UART2_TX), MP_ROM_PTR(&pin_PD05) }, + { MP_ROM_QSTR(MP_QSTR_UART2_RX), MP_ROM_PTR(&pin_PD06) }, + { MP_ROM_QSTR(MP_QSTR_UART2_RTS), MP_ROM_PTR(&pin_PD04) }, + { MP_ROM_QSTR(MP_QSTR_UART2_CTS), MP_ROM_PTR(&pin_PD03) }, + { MP_ROM_QSTR(MP_QSTR_UART3_TX), MP_ROM_PTR(&pin_PD08) }, + { MP_ROM_QSTR(MP_QSTR_UART3_RX), MP_ROM_PTR(&pin_PD09) }, + { MP_ROM_QSTR(MP_QSTR_UART5_TX), MP_ROM_PTR(&pin_PB06) }, + { MP_ROM_QSTR(MP_QSTR_UART5_RX), MP_ROM_PTR(&pin_PB12) }, + { MP_ROM_QSTR(MP_QSTR_UART6_TX), MP_ROM_PTR(&pin_PC06) }, + { MP_ROM_QSTR(MP_QSTR_UART6_RX), MP_ROM_PTR(&pin_PC07) }, + { MP_ROM_QSTR(MP_QSTR_UART7_TX), MP_ROM_PTR(&pin_PF07) }, + { MP_ROM_QSTR(MP_QSTR_UART7_RX), MP_ROM_PTR(&pin_PF06) }, + { MP_ROM_QSTR(MP_QSTR_UART8_TX), MP_ROM_PTR(&pin_PE01) }, + { MP_ROM_QSTR(MP_QSTR_UART8_RX), MP_ROM_PTR(&pin_PE00) }, + { MP_ROM_QSTR(MP_QSTR_ETH_MDC), MP_ROM_PTR(&pin_PC01) }, + { MP_ROM_QSTR(MP_QSTR_ETH_MDIO), MP_ROM_PTR(&pin_PA02) }, + { MP_ROM_QSTR(MP_QSTR_ETH_RMII_REF_CLK), MP_ROM_PTR(&pin_PA01) }, + { MP_ROM_QSTR(MP_QSTR_ETH_RMII_CRS_DV), MP_ROM_PTR(&pin_PA07) }, + { MP_ROM_QSTR(MP_QSTR_ETH_RMII_RXD0), MP_ROM_PTR(&pin_PC04) }, + { MP_ROM_QSTR(MP_QSTR_ETH_RMII_RXD1), MP_ROM_PTR(&pin_PC05) }, + { MP_ROM_QSTR(MP_QSTR_ETH_RMII_TX_EN), MP_ROM_PTR(&pin_PG11) }, + { MP_ROM_QSTR(MP_QSTR_ETH_RMII_TXD0), MP_ROM_PTR(&pin_PG13) }, + { MP_ROM_QSTR(MP_QSTR_ETH_RMII_TXD1), MP_ROM_PTR(&pin_PB13) }, +}; +MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table); diff --git a/ports/stm/boards/stm32h743zi_discovery/stm32h7xx_hal_conf.h b/ports/stm/boards/stm32h743zi_discovery/stm32h7xx_hal_conf.h new file mode 100644 index 0000000000000..e6a2dd5f80c1b --- /dev/null +++ b/ports/stm/boards/stm32h743zi_discovery/stm32h7xx_hal_conf.h @@ -0,0 +1,493 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_conf.h + * @author MCD Application Team + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32H7xx_HAL_CONF_H +#define __STM32H7xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED + + #define HAL_ADC_MODULE_ENABLED +/* #define HAL_FDCAN_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_COMP_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +#define HAL_DAC_MODULE_ENABLED +/* #define HAL_DCMI_MODULE_ENABLED */ +/* #define HAL_DMA2D_MODULE_ENABLED */ +#define HAL_ETH_MODULE_ENABLED +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_OTFDEC_MODULE_ENABLED */ +/* #define HAL_SRAM_MODULE_ENABLED */ +/* #define HAL_SDRAM_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ +/* #define HAL_HRTIM_MODULE_ENABLED */ +/* #define HAL_HSEM_MODULE_ENABLED */ +/* #define HAL_GFXMMU_MODULE_ENABLED */ +/* #define HAL_JPEG_MODULE_ENABLED */ +/* #define HAL_OPAMP_MODULE_ENABLED */ +/* #define HAL_OSPI_MODULE_ENABLED */ +/* #define HAL_OSPI_MODULE_ENABLED */ +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +/* #define HAL_LTDC_MODULE_ENABLED */ +/* #define HAL_QSPI_MODULE_ENABLED */ +#define HAL_RNG_MODULE_ENABLED +/* #define HAL_RTC_MODULE_ENABLED */ +/* #define HAL_SAI_MODULE_ENABLED */ +/* #define HAL_SD_MODULE_ENABLED */ +/* #define HAL_MMC_MODULE_ENABLED */ +/* #define HAL_SPDIFRX_MODULE_ENABLED */ +#define HAL_SPI_MODULE_ENABLED +/* #define HAL_SWPMI_MODULE_ENABLED */ +#define HAL_TIM_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +#define HAL_PCD_MODULE_ENABLED +/* #define HAL_HCD_MODULE_ENABLED */ +/* #define HAL_DFSDM_MODULE_ENABLED */ +/* #define HAL_DSI_MODULE_ENABLED */ +/* #define HAL_JPEG_MODULE_ENABLED */ +/* #define HAL_MDIOS_MODULE_ENABLED */ +/* #define HAL_PSSI_MODULE_ENABLED */ +/* #define HAL_DTS_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_MDMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED +#define HAL_HSEM_MODULE_ENABLED + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal oscillator (CSI) default value. + * This value is the default CSI value after Reset. + */ +#if !defined (CSI_VALUE) + #define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* CSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External clock in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define USE_SD_TRANSCEIVER 0U /*!< use uSD Transceiver */ + +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ +#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */ +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ +#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ +#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ +#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ +#define USE_HAL_DTS_REGISTER_CALLBACKS 0U /* DTS register callback disabled */ +#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ +#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */ +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ +#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ +#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U /* GFXMMU register callback disabled */ +#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U /* HRTIM register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U /* JPEG register callback disabled */ +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ +#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ +#define USE_HAL_MDIOS_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */ +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ +#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */ +#define USE_HAL_OSPI_REGISTER_CALLBACKS 0U /* OSPI register callback disabled */ +#define USE_HAL_OTFDEC_REGISTER_CALLBACKS 0U /* OTFDEC register callback disabled */ +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ +#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_SWPMI_REGISTER_CALLBACKS 0U /* SWPMI register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ + +/* ########################### Ethernet Configuration ######################### */ +#define ETH_TX_DESC_CNT 4 /* number of Ethernet Tx DMA descriptors */ +#define ETH_RX_DESC_CNT 4 /* number of Ethernet Rx DMA descriptors */ + +#define ETH_MAC_ADDR0 ((uint8_t)0x02) +#define ETH_MAC_ADDR1 ((uint8_t)0x00) +#define ETH_MAC_ADDR2 ((uint8_t)0x00) +#define ETH_MAC_ADDR3 ((uint8_t)0x00) +#define ETH_MAC_ADDR4 ((uint8_t)0x00) +#define ETH_MAC_ADDR5 ((uint8_t)0x00) + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32h7xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32h7xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32h7xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_MDMA_MODULE_ENABLED + #include "stm32h7xx_hal_mdma.h" +#endif /* HAL_MDMA_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32h7xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32h7xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32h7xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32h7xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32h7xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32h7xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32h7xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32h7xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32h7xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_FDCAN_MODULE_ENABLED + #include "stm32h7xx_hal_fdcan.h" +#endif /* HAL_FDCAN_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32h7xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_COMP_MODULE_ENABLED + #include "stm32h7xx_hal_comp.h" +#endif /* HAL_COMP_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32h7xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32h7xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32h7xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32h7xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_GFXMMU_MODULE_ENABLED + #include "stm32h7xx_hal_gfxmmu.h" +#endif /* HAL_GFXMMU_MODULE_ENABLED */ + +#ifdef HAL_HRTIM_MODULE_ENABLED + #include "stm32h7xx_hal_hrtim.h" +#endif /* HAL_HRTIM_MODULE_ENABLED */ + +#ifdef HAL_HSEM_MODULE_ENABLED + #include "stm32h7xx_hal_hsem.h" +#endif /* HAL_HSEM_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32h7xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32h7xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32h7xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32h7xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32h7xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32h7xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_JPEG_MODULE_ENABLED + #include "stm32h7xx_hal_jpeg.h" +#endif /* HAL_JPEG_MODULE_ENABLED */ + +#ifdef HAL_MDIOS_MODULE_ENABLED + #include "stm32h7xx_hal_mdios.h" +#endif /* HAL_MDIOS_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32h7xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED +#include "stm32h7xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED +#include "stm32h7xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_OPAMP_MODULE_ENABLED +#include "stm32h7xx_hal_opamp.h" +#endif /* HAL_OPAMP_MODULE_ENABLED */ + +#ifdef HAL_OSPI_MODULE_ENABLED + #include "stm32h7xx_hal_ospi.h" +#endif /* HAL_OSPI_MODULE_ENABLED */ + +#ifdef HAL_OTFDEC_MODULE_ENABLED +#include "stm32h7xx_hal_otfdec.h" +#endif /* HAL_OTFDEC_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32h7xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32h7xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_RAMECC_MODULE_ENABLED + #include "stm32h7xx_hal_ramecc.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32h7xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32h7xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32h7xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32h7xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32h7xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32h7xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32h7xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_SWPMI_MODULE_ENABLED + #include "stm32h7xx_hal_swpmi.h" +#endif /* HAL_SWPMI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32h7xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32h7xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32h7xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32h7xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32h7xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32h7xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32h7xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32h7xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32h7xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_PSSI_MODULE_ENABLED + #include "stm32h7xx_hal_pssi.h" +#endif /* HAL_PSSI_MODULE_ENABLED */ + +#ifdef HAL_DTS_MODULE_ENABLED + #include "stm32h7xx_hal_dts.h" +#endif /* HAL_DTS_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32H7xx_HAL_CONF_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/ports/stm/common-hal/analogio/AnalogOut.h b/ports/stm/common-hal/analogio/AnalogOut.h index 61591d0e6569c..46312b4609b5d 100644 --- a/ports/stm/common-hal/analogio/AnalogOut.h +++ b/ports/stm/common-hal/analogio/AnalogOut.h @@ -32,7 +32,7 @@ #include "py/obj.h" #include "stm32f4xx_hal.h" -#include "stm32f4/periph.h" +#include "peripherals/periph.h" typedef struct { mp_obj_base_t base; diff --git a/ports/stm/common-hal/busio/I2C.c b/ports/stm/common-hal/busio/I2C.c index 8e98b966d2414..4daefb58bcab6 100644 --- a/ports/stm/common-hal/busio/I2C.c +++ b/ports/stm/common-hal/busio/I2C.c @@ -29,7 +29,6 @@ #include "shared-bindings/busio/I2C.h" #include "py/mperrno.h" #include "py/runtime.h" -#include "stm32f4xx_hal.h" #include "shared-bindings/microcontroller/__init__.h" #include "supervisor/shared/translate.h" @@ -69,9 +68,9 @@ void common_hal_busio_i2c_construct(busio_i2c_obj_t *self, if (mcu_i2c_sda_list[i].pin == sda) { for (uint j = 0; j < scl_len; j++) { if ((mcu_i2c_scl_list[j].pin == scl) - && (mcu_i2c_scl_list[j].i2c_index == mcu_i2c_sda_list[i].i2c_index)) { + && (mcu_i2c_scl_list[j].periph_index == mcu_i2c_sda_list[i].periph_index)) { //keep looking if the I2C is taken, could be another SCL that works - if (reserved_i2c[mcu_i2c_scl_list[i].i2c_index - 1]) { + if (reserved_i2c[mcu_i2c_scl_list[i].periph_index - 1]) { i2c_taken = true; continue; } @@ -85,7 +84,7 @@ void common_hal_busio_i2c_construct(busio_i2c_obj_t *self, //handle typedef selection, errors if (self->sda != NULL && self->scl != NULL ) { - I2Cx = mcu_i2c_banks[self->sda->i2c_index - 1]; + I2Cx = mcu_i2c_banks[self->sda->periph_index - 1]; } else { if (i2c_taken) { mp_raise_ValueError(translate("Hardware busy, try alternative pins")); @@ -111,8 +110,8 @@ void common_hal_busio_i2c_construct(busio_i2c_obj_t *self, HAL_GPIO_Init(pin_port(scl->port), &GPIO_InitStruct); //Note: due to I2C soft reboot issue, do not relocate clock init. - i2c_clock_enable(1 << (self->sda->i2c_index - 1)); - reserved_i2c[self->sda->i2c_index - 1] = true; + i2c_clock_enable(1 << (self->sda->periph_index - 1)); + reserved_i2c[self->sda->periph_index - 1] = true; self->handle.Instance = I2Cx; self->handle.Init.ClockSpeed = 100000; @@ -152,9 +151,9 @@ void common_hal_busio_i2c_deinit(busio_i2c_obj_t *self) { return; } - i2c_clock_disable(1 << (self->sda->i2c_index - 1)); - reserved_i2c[self->sda->i2c_index - 1] = false; - never_reset_i2c[self->sda->i2c_index - 1] = false; + i2c_clock_disable(1 << (self->sda->periph_index - 1)); + reserved_i2c[self->sda->periph_index - 1] = false; + never_reset_i2c[self->sda->periph_index - 1] = false; reset_pin_number(self->sda->pin->port,self->sda->pin->number); reset_pin_number(self->scl->pin->port,self->scl->pin->number); diff --git a/ports/stm/common-hal/busio/I2C.h b/ports/stm/common-hal/busio/I2C.h index b5c891a98d10f..5ca2854eb81a0 100644 --- a/ports/stm/common-hal/busio/I2C.h +++ b/ports/stm/common-hal/busio/I2C.h @@ -25,13 +25,12 @@ * THE SOFTWARE. */ -#ifndef MICROPY_INCLUDED_STM32F4_COMMON_HAL_BUSIO_I2C_H -#define MICROPY_INCLUDED_STM32F4_COMMON_HAL_BUSIO_I2C_H +#ifndef MICROPY_INCLUDED_STM32_COMMON_HAL_BUSIO_I2C_H +#define MICROPY_INCLUDED_STM32_COMMON_HAL_BUSIO_I2C_H #include "common-hal/microcontroller/Pin.h" -#include "stm32f4xx_hal.h" -#include "stm32f4/periph.h" +#include "peripherals/periph.h" #include "py/obj.h" @@ -39,10 +38,10 @@ typedef struct { mp_obj_base_t base; I2C_HandleTypeDef handle; bool has_lock; - const mcu_i2c_scl_obj_t *scl; - const mcu_i2c_sda_obj_t *sda; + const mcu_periph_obj_t *scl; + const mcu_periph_obj_t *sda; } busio_i2c_obj_t; void i2c_reset(void); -#endif // MICROPY_INCLUDED_STM32F4_COMMON_HAL_BUSIO_I2C_H +#endif // MICROPY_INCLUDED_STM32_COMMON_HAL_BUSIO_I2C_H diff --git a/ports/stm/common-hal/busio/OneWire.h b/ports/stm/common-hal/busio/OneWire.h index 6e8c829793a26..0099593f03005 100644 --- a/ports/stm/common-hal/busio/OneWire.h +++ b/ports/stm/common-hal/busio/OneWire.h @@ -24,10 +24,10 @@ * THE SOFTWARE. */ -#ifndef MICROPY_INCLUDED_STM32F4_COMMON_HAL_BUSIO_ONEWIRE_H -#define MICROPY_INCLUDED_STM32F4_COMMON_HAL_BUSIO_ONEWIRE_H +#ifndef MICROPY_INCLUDED_STM32_COMMON_HAL_BUSIO_ONEWIRE_H +#define MICROPY_INCLUDED_STM32_COMMON_HAL_BUSIO_ONEWIRE_H // Use bitbangio. #include "shared-module/busio/OneWire.h" -#endif // MICROPY_INCLUDED_STM32F4_COMMON_HAL_BUSIO_ONEWIRE_H +#endif // MICROPY_INCLUDED_STM32F_COMMON_HAL_BUSIO_ONEWIRE_H diff --git a/ports/stm/common-hal/busio/SPI.c b/ports/stm/common-hal/busio/SPI.c index 7e25e0a5719f3..cf001556096f2 100644 --- a/ports/stm/common-hal/busio/SPI.c +++ b/ports/stm/common-hal/busio/SPI.c @@ -29,7 +29,6 @@ #include "shared-bindings/busio/SPI.h" #include "py/mperrno.h" #include "py/runtime.h" -#include "stm32f4xx_hal.h" #include "shared-bindings/microcontroller/__init__.h" #include "boards/board.h" @@ -120,10 +119,10 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self, //MISO for (uint k = 0; k < miso_len; k++) { if ((mcu_spi_miso_list[k].pin == miso) //everything needs the same index - && (mcu_spi_sck_list[i].spi_index == mcu_spi_mosi_list[j].spi_index) - && (mcu_spi_sck_list[i].spi_index == mcu_spi_miso_list[k].spi_index)) { + && (mcu_spi_sck_list[i].periph_index == mcu_spi_mosi_list[j].periph_index) + && (mcu_spi_sck_list[i].periph_index == mcu_spi_miso_list[k].periph_index)) { //keep looking if the SPI is taken, edge case - if (reserved_spi[mcu_spi_sck_list[i].spi_index - 1]) { + if (reserved_spi[mcu_spi_sck_list[i].periph_index - 1]) { spi_taken = true; continue; } @@ -140,9 +139,9 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self, } else if (miso != NULL) { for (uint j = 0; j < miso_len; j++) { if ((mcu_spi_miso_list[j].pin == miso) //only SCK and MISO need the same index - && (mcu_spi_sck_list[i].spi_index == mcu_spi_miso_list[j].spi_index)) { + && (mcu_spi_sck_list[i].periph_index == mcu_spi_miso_list[j].periph_index)) { //keep looking if the SPI is taken, edge case - if (reserved_spi[mcu_spi_sck_list[i].spi_index - 1]) { + if (reserved_spi[mcu_spi_sck_list[i].periph_index - 1]) { spi_taken = true; continue; } @@ -157,9 +156,9 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self, } else if (mosi != NULL) { for (uint j = 0; j < mosi_len; j++) { if ((mcu_spi_mosi_list[j].pin == mosi) //only SCK and MOSI need the same index - && (mcu_spi_sck_list[i].spi_index == mcu_spi_mosi_list[j].spi_index)) { + && (mcu_spi_sck_list[i].periph_index == mcu_spi_mosi_list[j].periph_index)) { //keep looking if the SPI is taken, edge case - if (reserved_spi[mcu_spi_sck_list[i].spi_index - 1]) { + if (reserved_spi[mcu_spi_sck_list[i].periph_index - 1]) { spi_taken = true; continue; } @@ -181,7 +180,7 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self, if ( (self->sck != NULL && self->mosi != NULL && self->miso != NULL) || (self->sck != NULL && self->mosi != NULL && miso == NULL) || (self->sck != NULL && self->miso != NULL && mosi == NULL)) { - SPIx = mcu_spi_banks[self->sck->spi_index - 1]; + SPIx = mcu_spi_banks[self->sck->periph_index - 1]; } else { if (spi_taken) { mp_raise_ValueError(translate("Hardware busy, try alternative pins")); @@ -217,8 +216,8 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self, HAL_GPIO_Init(pin_port(miso->port), &GPIO_InitStruct); } - spi_clock_enable(1 << (self->sck->spi_index - 1)); - reserved_spi[self->sck->spi_index - 1] = true; + spi_clock_enable(1 << (self->sck->periph_index - 1)); + reserved_spi[self->sck->periph_index - 1] = true; self->handle.Instance = SPIx; self->handle.Init.Mode = SPI_MODE_MASTER; @@ -276,9 +275,9 @@ void common_hal_busio_spi_deinit(busio_spi_obj_t *self) { if (common_hal_busio_spi_deinited(self)) { return; } - spi_clock_disable(1<<(self->sck->spi_index - 1)); - reserved_spi[self->sck->spi_index - 1] = false; - never_reset_spi[self->sck->spi_index - 1] = false; + spi_clock_disable(1<<(self->sck->periph_index - 1)); + reserved_spi[self->sck->periph_index - 1] = false; + never_reset_spi[self->sck->periph_index - 1] = false; reset_pin_number(self->sck->pin->port,self->sck->pin->number); if (self->mosi != NULL) { diff --git a/ports/stm/common-hal/busio/SPI.h b/ports/stm/common-hal/busio/SPI.h index 067d2fcb65d15..6483183678ee0 100644 --- a/ports/stm/common-hal/busio/SPI.h +++ b/ports/stm/common-hal/busio/SPI.h @@ -25,13 +25,12 @@ * THE SOFTWARE. */ -#ifndef MICROPY_INCLUDED_STM32F4_COMMON_HAL_BUSIO_SPI_H -#define MICROPY_INCLUDED_STM32F4_COMMON_HAL_BUSIO_SPI_H +#ifndef MICROPY_INCLUDED_STM32_COMMON_HAL_BUSIO_SPI_H +#define MICROPY_INCLUDED_STM32_COMMON_HAL_BUSIO_SPI_H #include "common-hal/microcontroller/Pin.h" -#include "stm32f4xx_hal.h" -#include "stm32f4/periph.h" +#include "peripherals/periph.h" #include "py/obj.h" @@ -39,10 +38,10 @@ typedef struct { mp_obj_base_t base; SPI_HandleTypeDef handle; bool has_lock; - const mcu_spi_sck_obj_t *sck; - const mcu_spi_mosi_obj_t *mosi; - const mcu_spi_miso_obj_t *miso; - const mcu_spi_nss_obj_t *nss; + const mcu_periph_obj_t *sck; + const mcu_periph_obj_t *mosi; + const mcu_periph_obj_t *miso; + const mcu_periph_obj_t *nss; uint32_t baudrate; uint16_t prescaler; uint8_t polarity; @@ -52,4 +51,4 @@ typedef struct { void spi_reset(void); -#endif // MICROPY_INCLUDED_STM32F4_COMMON_HAL_BUSIO_SPI_H +#endif // MICROPY_INCLUDED_STM32_COMMON_HAL_BUSIO_SPI_H diff --git a/ports/stm/common-hal/busio/UART.c b/ports/stm/common-hal/busio/UART.c index 0b434fd0236d0..df05a68cb4c3d 100644 --- a/ports/stm/common-hal/busio/UART.c +++ b/ports/stm/common-hal/busio/UART.c @@ -36,7 +36,6 @@ #include "supervisor/shared/translate.h" #include "tick.h" -#include "stm32f4xx_hal.h" #define ALL_UARTS 0xFFFF @@ -49,11 +48,11 @@ STATIC void uart_clock_disable(uint16_t mask); STATIC void uart_assign_irq(busio_uart_obj_t* self, USART_TypeDef* USARTx); STATIC USART_TypeDef * assign_uart_or_throw(busio_uart_obj_t* self, bool pin_eval, - int uart_index, bool uart_taken) { + int periph_index, bool uart_taken) { if (pin_eval) { //assign a root pointer pointer for IRQ - MP_STATE_PORT(cpy_uart_obj_all)[uart_index] = self; - return mcu_uart_banks[uart_index]; + MP_STATE_PORT(cpy_uart_obj_all)[periph_index] = self; + return mcu_uart_banks[periph_index]; } else { if (uart_taken) { mp_raise_ValueError(translate("Hardware in use, try alternative pins")); @@ -84,7 +83,7 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self, uint8_t tx_len = MP_ARRAY_SIZE(mcu_uart_tx_list); uint8_t rx_len = MP_ARRAY_SIZE(mcu_uart_rx_list); bool uart_taken = false; - uint8_t uart_index = 0; //origin 0 corrected + uint8_t periph_index = 0; //origin 0 corrected if ((rts != NULL) || (cts != NULL) || (rs485_dir != NULL) || (rs485_invert == true)) { mp_raise_ValueError(translate("RTS/CTS/RS485 Not yet supported on this device")); @@ -98,9 +97,9 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self, //rx for (uint j = 0; j < rx_len; j++) { if (mcu_uart_rx_list[j].pin == rx - && mcu_uart_rx_list[j].uart_index == mcu_uart_tx_list[i].uart_index) { + && mcu_uart_rx_list[j].periph_index == mcu_uart_tx_list[i].periph_index) { //keep looking if the UART is taken, edge case - if (reserved_uart[mcu_uart_tx_list[i].uart_index - 1]) { + if (reserved_uart[mcu_uart_tx_list[i].periph_index - 1]) { uart_taken = true; continue; } @@ -112,15 +111,15 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self, } } } - uart_index = self->tx->uart_index - 1; + periph_index = self->tx->periph_index - 1; USARTx = assign_uart_or_throw(self, (self->tx != NULL && self->rx != NULL), - uart_index, uart_taken); + periph_index, uart_taken); } else if (tx == NULL) { //If there is no tx, run only rx for (uint i = 0; i < rx_len; i++) { if (mcu_uart_rx_list[i].pin == rx) { //keep looking if the UART is taken, edge case - if (reserved_uart[mcu_uart_rx_list[i].uart_index - 1]) { + if (reserved_uart[mcu_uart_rx_list[i].periph_index - 1]) { uart_taken = true; continue; } @@ -129,15 +128,15 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self, break; } } - uart_index = self->rx->uart_index - 1; + periph_index = self->rx->periph_index - 1; USARTx = assign_uart_or_throw(self, (self->rx != NULL), - uart_index, uart_taken); + periph_index, uart_taken); } else if (rx == NULL) { //If there is no rx, run only tx for (uint i = 0; i < tx_len; i++) { if (mcu_uart_tx_list[i].pin == tx) { //keep looking if the UART is taken, edge case - if (reserved_uart[mcu_uart_tx_list[i].uart_index - 1]) { + if (reserved_uart[mcu_uart_tx_list[i].periph_index - 1]) { uart_taken = true; continue; } @@ -146,9 +145,9 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self, break; } } - uart_index = self->tx->uart_index - 1; + periph_index = self->tx->periph_index - 1; USARTx = assign_uart_or_throw(self, (self->tx != NULL), - uart_index, uart_taken); + periph_index, uart_taken); } else { //both pins cannot be empty mp_raise_ValueError(translate("Supply at least one UART pin")); @@ -185,8 +184,8 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self, } //reserve uart and enable the peripheral - reserved_uart[uart_index] = true; - uart_clock_enable(1 << (uart_index)); + reserved_uart[periph_index] = true; + uart_clock_enable(1 << (periph_index)); uart_assign_irq(self, USARTx); self->handle.Instance = USARTx; diff --git a/ports/stm/common-hal/busio/UART.h b/ports/stm/common-hal/busio/UART.h index cde5fadd00b50..5ac1d352cabfc 100644 --- a/ports/stm/common-hal/busio/UART.h +++ b/ports/stm/common-hal/busio/UART.h @@ -24,12 +24,11 @@ * THE SOFTWARE. */ -#ifndef MICROPY_INCLUDED_STM32F4_COMMON_HAL_BUSIO_UART_H -#define MICROPY_INCLUDED_STM32F4_COMMON_HAL_BUSIO_UART_H +#ifndef MICROPY_INCLUDED_STM32_COMMON_HAL_BUSIO_UART_H +#define MICROPY_INCLUDED_STM32_COMMON_HAL_BUSIO_UART_H #include "common-hal/microcontroller/Pin.h" -#include "stm32f4/periph.h" -#include "stm32f4xx_hal.h" +#include "peripherals/periph.h" #include "py/obj.h" #include "py/ringbuf.h" @@ -45,8 +44,8 @@ typedef struct { mp_obj_base_t base; UART_HandleTypeDef handle; IRQn_Type irq; - const mcu_uart_tx_obj_t *tx; - const mcu_uart_rx_obj_t *rx; + const mcu_periph_obj_t *tx; + const mcu_periph_obj_t *rx; ringbuf_t rbuf; uint8_t rx_char; diff --git a/ports/stm/common-hal/digitalio/DigitalInOut.c b/ports/stm/common-hal/digitalio/DigitalInOut.c index be2db4dace552..40e13ca3ba538 100644 --- a/ports/stm/common-hal/digitalio/DigitalInOut.c +++ b/ports/stm/common-hal/digitalio/DigitalInOut.c @@ -29,8 +29,12 @@ #include "py/runtime.h" #include "supervisor/shared/translate.h" -#include "stm32f4xx_hal.h" +//TODO: rework this module to use HAL only +#ifdef STM32H743xx +#include "stm32h7xx_ll_gpio.h" +#else #include "stm32f4xx_ll_gpio.h" +#endif void common_hal_digitalio_digitalinout_never_reset( digitalio_digitalinout_obj_t *self) { diff --git a/ports/stm/common-hal/digitalio/DigitalInOut.h b/ports/stm/common-hal/digitalio/DigitalInOut.h index 76aa2c85564d2..e810ca3c15daa 100644 --- a/ports/stm/common-hal/digitalio/DigitalInOut.h +++ b/ports/stm/common-hal/digitalio/DigitalInOut.h @@ -25,8 +25,8 @@ * THE SOFTWARE. */ -#ifndef MICROPY_INCLUDED_STM32F4_COMMON_HAL_DIGITALIO_DIGITALINOUT_H -#define MICROPY_INCLUDED_STM32F4_COMMON_HAL_DIGITALIO_DIGITALINOUT_H +#ifndef MICROPY_INCLUDED_STM32_COMMON_HAL_DIGITALIO_DIGITALINOUT_H +#define MICROPY_INCLUDED_STM32_COMMON_HAL_DIGITALIO_DIGITALINOUT_H #include "common-hal/microcontroller/Pin.h" @@ -35,4 +35,4 @@ typedef struct { const mcu_pin_obj_t *pin; } digitalio_digitalinout_obj_t; -#endif // MICROPY_INCLUDED_STM32F4_COMMON_HAL_DIGITALIO_DIGITALINOUT_H +#endif // MICROPY_INCLUDED_STM32_COMMON_HAL_DIGITALIO_DIGITALINOUT_H diff --git a/ports/stm/common-hal/microcontroller/Pin.c b/ports/stm/common-hal/microcontroller/Pin.c index 1d4d45b9785a0..2c513f4aadc6a 100644 --- a/ports/stm/common-hal/microcontroller/Pin.c +++ b/ports/stm/common-hal/microcontroller/Pin.c @@ -30,23 +30,22 @@ #include "supervisor/shared/rgb_led_status.h" #include "py/mphal.h" -#include "stm32f4/pins.h" -#include "stm32f4xx_hal.h" +#include "pins.h" #ifdef MICROPY_HW_NEOPIXEL bool neopixel_in_use; #endif -#if MCU_PACKAGE == 144 +#if defined(LQFP144) #define GPIO_PORT_COUNT 7 GPIO_TypeDef * ports[GPIO_PORT_COUNT] = {GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG}; -#elif MCU_PACKAGE == 100 +#elif defined(LQFP100_f4) || (LQFP100_x7) #define GPIO_PORT_COUNT 5 GPIO_TypeDef * ports[GPIO_PORT_COUNT] = {GPIOA, GPIOB, GPIOC, GPIOD, GPIOE}; -#elif MCU_PACKAGE == 64 +#elif defined(LQFP64) #define GPIO_PORT_COUNT 3 GPIO_TypeDef * ports[GPIO_PORT_COUNT] = {GPIOA, GPIOB, GPIOC}; -#elif MCU_PACKAGE == 48 +#elif defined(UFQFPN48) #define GPIO_PORT_COUNT 3 GPIO_TypeDef * ports[GPIO_PORT_COUNT] = {GPIOA, GPIOB, GPIOC}; #endif diff --git a/ports/stm/common-hal/microcontroller/Pin.h b/ports/stm/common-hal/microcontroller/Pin.h index c4c9be6a81ced..d69ddfb1dedd7 100644 --- a/ports/stm/common-hal/microcontroller/Pin.h +++ b/ports/stm/common-hal/microcontroller/Pin.h @@ -24,12 +24,12 @@ * THE SOFTWARE. */ -#ifndef MICROPY_INCLUDED_STM34F4_COMMON_HAL_MICROCONTROLLER_PIN_H -#define MICROPY_INCLUDED_STM34F4_COMMON_HAL_MICROCONTROLLER_PIN_H +#ifndef MICROPY_INCLUDED_STM32_COMMON_HAL_MICROCONTROLLER_PIN_H +#define MICROPY_INCLUDED_STM32_COMMON_HAL_MICROCONTROLLER_PIN_H #include "py/mphal.h" -#include "peripherals/stm32f4/pins.h" +#include "peripherals/pins.h" #ifdef MICROPY_HW_NEOPIXEL extern bool neopixel_in_use; @@ -49,4 +49,4 @@ void never_reset_pin_number(uint8_t pin_port, uint8_t pin_number); GPIO_TypeDef * pin_port(uint8_t pin_port); uint16_t pin_mask(uint8_t pin_number); -#endif // MICROPY_INCLUDED_STM34F4_COMMON_HAL_MICROCONTROLLER_PIN_H +#endif // MICROPY_INCLUDED_STM32_COMMON_HAL_MICROCONTROLLER_PIN_H diff --git a/ports/stm/common-hal/microcontroller/Processor.c b/ports/stm/common-hal/microcontroller/Processor.c index 324659cefa690..c8b07db3f0dc2 100644 --- a/ports/stm/common-hal/microcontroller/Processor.c +++ b/ports/stm/common-hal/microcontroller/Processor.c @@ -29,7 +29,7 @@ #include "py/runtime.h" #include "supervisor/shared/translate.h" -#include "stm32f4xx_hal.h" +#if defined(STM32F4) #define STM32_UUID ((uint32_t *)0x1FFF7A10) @@ -58,7 +58,10 @@ STATIC void set_adc_params(ADC_HandleTypeDef *AdcHandle) { AdcHandle->Init.EOCSelection = ADC_EOC_SINGLE_CONV; } +#endif + float common_hal_mcu_processor_get_temperature(void) { + #if defined(STM32F4) __HAL_RCC_ADC1_CLK_ENABLE(); //HAL Implementation @@ -85,9 +88,13 @@ float common_hal_mcu_processor_get_temperature(void) { //There's no F4 specific appnote for this but it works the same as the L1 in AN3964 float core_temp_avg_slope = (*ADC_CAL2 - *ADC_CAL1) / 80.0; return (((float)value * adc_refcor - *ADC_CAL1) / core_temp_avg_slope) + 30.0f; + #else + return false; + #endif } float common_hal_mcu_processor_get_voltage(void) { + #if defined(STM32F4) __HAL_RCC_ADC1_CLK_ENABLE(); //HAL Implementation @@ -114,6 +121,9 @@ float common_hal_mcu_processor_get_voltage(void) { adc_refcor = ((float)(*VREFIN_CAL)) / ((float)value); return adc_refcor * 3.3f; + #else + return false; + #endif } uint32_t common_hal_mcu_processor_get_frequency(void) { @@ -121,7 +131,9 @@ uint32_t common_hal_mcu_processor_get_frequency(void) { } void common_hal_mcu_processor_get_uid(uint8_t raw_id[]) { + #if defined(STM32F4) for (int i=0; i<3; i++) { ((uint32_t*) raw_id)[i] = STM32_UUID[i]; } + #endif } diff --git a/ports/stm/common-hal/microcontroller/Processor.h b/ports/stm/common-hal/microcontroller/Processor.h index 311333e7de512..1d22aa965000e 100644 --- a/ports/stm/common-hal/microcontroller/Processor.h +++ b/ports/stm/common-hal/microcontroller/Processor.h @@ -24,8 +24,8 @@ * THE SOFTWARE. */ -#ifndef MICROPY_INCLUDED_STM32F4_COMMON_HAL_MICROCONTROLLER_PROCESSOR_H -#define MICROPY_INCLUDED_STM32F4_COMMON_HAL_MICROCONTROLLER_PROCESSOR_H +#ifndef MICROPY_INCLUDED_STM32_COMMON_HAL_MICROCONTROLLER_PROCESSOR_H +#define MICROPY_INCLUDED_STM32_COMMON_HAL_MICROCONTROLLER_PROCESSOR_H #define COMMON_HAL_MCU_PROCESSOR_UID_LENGTH 12 @@ -36,4 +36,4 @@ typedef struct { // Stores no state currently. } mcu_processor_obj_t; -#endif // MICROPY_INCLUDED_STM32F4_COMMON_HAL_MICROCONTROLLER_PROCESSOR_H +#endif // MICROPY_INCLUDED_STM32_COMMON_HAL_MICROCONTROLLER_PROCESSOR_H diff --git a/ports/stm/common-hal/microcontroller/__init__.c b/ports/stm/common-hal/microcontroller/__init__.c index 0c680eb055680..6f16c3ef231a6 100644 --- a/ports/stm/common-hal/microcontroller/__init__.c +++ b/ports/stm/common-hal/microcontroller/__init__.c @@ -39,8 +39,6 @@ #include "supervisor/filesystem.h" #include "supervisor/shared/safe_mode.h" -#include "stm32f4xx_hal.h" - //tested divisor value for busy loop in us delay #define LOOP_TICKS 12 @@ -108,137 +106,3 @@ const mcu_processor_obj_t common_hal_mcu_processor_obj = { .type = &mcu_processor_type, }, }; - -STATIC const mp_rom_map_elem_t mcu_pin_globals_table[] = { -#if MCU_PACKAGE >= 100 - { MP_ROM_QSTR(MP_QSTR_PE02), MP_ROM_PTR(&pin_PE02) }, - { MP_ROM_QSTR(MP_QSTR_PE03), MP_ROM_PTR(&pin_PE03) }, - { MP_ROM_QSTR(MP_QSTR_PE04), MP_ROM_PTR(&pin_PE04) }, - { MP_ROM_QSTR(MP_QSTR_PE05), MP_ROM_PTR(&pin_PE05) }, - { MP_ROM_QSTR(MP_QSTR_PE06), MP_ROM_PTR(&pin_PE06) }, -#endif - { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) }, -#if MCU_PACKAGE == 144 - { MP_ROM_QSTR(MP_QSTR_PF00), MP_ROM_PTR(&pin_PF00) }, - { MP_ROM_QSTR(MP_QSTR_PF01), MP_ROM_PTR(&pin_PF01) }, - { MP_ROM_QSTR(MP_QSTR_PF02), MP_ROM_PTR(&pin_PF02) }, - { MP_ROM_QSTR(MP_QSTR_PF03), MP_ROM_PTR(&pin_PF03) }, - { MP_ROM_QSTR(MP_QSTR_PF04), MP_ROM_PTR(&pin_PF04) }, - { MP_ROM_QSTR(MP_QSTR_PF05), MP_ROM_PTR(&pin_PF05) }, - { MP_ROM_QSTR(MP_QSTR_PF06), MP_ROM_PTR(&pin_PF06) }, - { MP_ROM_QSTR(MP_QSTR_PF07), MP_ROM_PTR(&pin_PF07) }, - { MP_ROM_QSTR(MP_QSTR_PF08), MP_ROM_PTR(&pin_PF08) }, - { MP_ROM_QSTR(MP_QSTR_PF09), MP_ROM_PTR(&pin_PF09) }, - { MP_ROM_QSTR(MP_QSTR_PF10), MP_ROM_PTR(&pin_PF10) }, -#endif - { MP_ROM_QSTR(MP_QSTR_PC00), MP_ROM_PTR(&pin_PC00) }, - { MP_ROM_QSTR(MP_QSTR_PC01), MP_ROM_PTR(&pin_PC01) }, - { MP_ROM_QSTR(MP_QSTR_PC02), MP_ROM_PTR(&pin_PC02) }, - { MP_ROM_QSTR(MP_QSTR_PC03), MP_ROM_PTR(&pin_PC03) }, - { MP_ROM_QSTR(MP_QSTR_PA00), MP_ROM_PTR(&pin_PA00) }, - { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) }, - { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) }, - { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) }, - { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) }, - { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) }, - { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) }, - { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) }, - { MP_ROM_QSTR(MP_QSTR_PC04), MP_ROM_PTR(&pin_PC04) }, - { MP_ROM_QSTR(MP_QSTR_PC05), MP_ROM_PTR(&pin_PC05) }, - { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) }, - { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) }, - { MP_ROM_QSTR(MP_QSTR_PB02), MP_ROM_PTR(&pin_PB02) }, -#if MCU_PACKAGE == 144 - { MP_ROM_QSTR(MP_QSTR_PF11), MP_ROM_PTR(&pin_PF11) }, - { MP_ROM_QSTR(MP_QSTR_PF12), MP_ROM_PTR(&pin_PF12) }, - { MP_ROM_QSTR(MP_QSTR_PF13), MP_ROM_PTR(&pin_PF13) }, - { MP_ROM_QSTR(MP_QSTR_PF14), MP_ROM_PTR(&pin_PF14) }, - { MP_ROM_QSTR(MP_QSTR_PF15), MP_ROM_PTR(&pin_PF15) }, - { MP_ROM_QSTR(MP_QSTR_PG00), MP_ROM_PTR(&pin_PG00) }, - { MP_ROM_QSTR(MP_QSTR_PG01), MP_ROM_PTR(&pin_PG01) }, -#endif -#if MCU_PACKAGE >= 100 - { MP_ROM_QSTR(MP_QSTR_PE07), MP_ROM_PTR(&pin_PE07) }, - { MP_ROM_QSTR(MP_QSTR_PE08), MP_ROM_PTR(&pin_PE08) }, - { MP_ROM_QSTR(MP_QSTR_PE09), MP_ROM_PTR(&pin_PE09) }, - { MP_ROM_QSTR(MP_QSTR_PE10), MP_ROM_PTR(&pin_PE10) }, - { MP_ROM_QSTR(MP_QSTR_PE11), MP_ROM_PTR(&pin_PE11) }, - { MP_ROM_QSTR(MP_QSTR_PE12), MP_ROM_PTR(&pin_PE12) }, - { MP_ROM_QSTR(MP_QSTR_PE13), MP_ROM_PTR(&pin_PE13) }, - { MP_ROM_QSTR(MP_QSTR_PE14), MP_ROM_PTR(&pin_PE14) }, - { MP_ROM_QSTR(MP_QSTR_PE15), MP_ROM_PTR(&pin_PE15) }, -#endif - { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) }, -#if MCU_PACKAGE == 144 || defined STM32F405xx - { MP_ROM_QSTR(MP_QSTR_PB11), MP_ROM_PTR(&pin_PB11) }, -#endif - { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) }, - { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) }, - { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) }, - { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) }, -#if MCU_PACKAGE >= 100 - { MP_ROM_QSTR(MP_QSTR_PD08), MP_ROM_PTR(&pin_PD08) }, - { MP_ROM_QSTR(MP_QSTR_PD09), MP_ROM_PTR(&pin_PD09) }, - { MP_ROM_QSTR(MP_QSTR_PD10), MP_ROM_PTR(&pin_PD10) }, - { MP_ROM_QSTR(MP_QSTR_PD11), MP_ROM_PTR(&pin_PD11) }, - { MP_ROM_QSTR(MP_QSTR_PD12), MP_ROM_PTR(&pin_PD12) }, - { MP_ROM_QSTR(MP_QSTR_PD13), MP_ROM_PTR(&pin_PD13) }, - { MP_ROM_QSTR(MP_QSTR_PD14), MP_ROM_PTR(&pin_PD14) }, - { MP_ROM_QSTR(MP_QSTR_PD15), MP_ROM_PTR(&pin_PD15) }, -#endif -#if MCU_PACKAGE == 144 - { MP_ROM_QSTR(MP_QSTR_PG02), MP_ROM_PTR(&pin_PG02) }, - { MP_ROM_QSTR(MP_QSTR_PG03), MP_ROM_PTR(&pin_PG03) }, - { MP_ROM_QSTR(MP_QSTR_PG04), MP_ROM_PTR(&pin_PG04) }, - { MP_ROM_QSTR(MP_QSTR_PG05), MP_ROM_PTR(&pin_PG05) }, - { MP_ROM_QSTR(MP_QSTR_PG06), MP_ROM_PTR(&pin_PG06) }, - { MP_ROM_QSTR(MP_QSTR_PG07), MP_ROM_PTR(&pin_PG07) }, - { MP_ROM_QSTR(MP_QSTR_PG08), MP_ROM_PTR(&pin_PG08) }, -#endif - { MP_ROM_QSTR(MP_QSTR_PC06), MP_ROM_PTR(&pin_PC06) }, - { MP_ROM_QSTR(MP_QSTR_PC07), MP_ROM_PTR(&pin_PC07) }, - { MP_ROM_QSTR(MP_QSTR_PC08), MP_ROM_PTR(&pin_PC08) }, - { MP_ROM_QSTR(MP_QSTR_PC09), MP_ROM_PTR(&pin_PC09) }, - { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) }, - { MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) }, - { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) }, - { MP_ROM_QSTR(MP_QSTR_PA11), MP_ROM_PTR(&pin_PA11) }, - { MP_ROM_QSTR(MP_QSTR_PA12), MP_ROM_PTR(&pin_PA12) }, - { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) }, - { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) }, - { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) }, - { MP_ROM_QSTR(MP_QSTR_PC10), MP_ROM_PTR(&pin_PC10) }, - { MP_ROM_QSTR(MP_QSTR_PC11), MP_ROM_PTR(&pin_PC11) }, - { MP_ROM_QSTR(MP_QSTR_PC12), MP_ROM_PTR(&pin_PC12) }, -#if MCU_PACKAGE >= 100 - { MP_ROM_QSTR(MP_QSTR_PD00), MP_ROM_PTR(&pin_PD00) }, - { MP_ROM_QSTR(MP_QSTR_PD01), MP_ROM_PTR(&pin_PD01) }, - { MP_ROM_QSTR(MP_QSTR_PD02), MP_ROM_PTR(&pin_PD02) }, - { MP_ROM_QSTR(MP_QSTR_PD03), MP_ROM_PTR(&pin_PD03) }, - { MP_ROM_QSTR(MP_QSTR_PD04), MP_ROM_PTR(&pin_PD04) }, - { MP_ROM_QSTR(MP_QSTR_PD05), MP_ROM_PTR(&pin_PD05) }, - { MP_ROM_QSTR(MP_QSTR_PD06), MP_ROM_PTR(&pin_PD06) }, - { MP_ROM_QSTR(MP_QSTR_PD07), MP_ROM_PTR(&pin_PD07) }, -#endif -#if MCU_PACKAGE == 144 - { MP_ROM_QSTR(MP_QSTR_PG09), MP_ROM_PTR(&pin_PG09) }, - { MP_ROM_QSTR(MP_QSTR_PG10), MP_ROM_PTR(&pin_PG10) }, - { MP_ROM_QSTR(MP_QSTR_PG11), MP_ROM_PTR(&pin_PG11) }, - { MP_ROM_QSTR(MP_QSTR_PG12), MP_ROM_PTR(&pin_PG12) }, - { MP_ROM_QSTR(MP_QSTR_PG13), MP_ROM_PTR(&pin_PG13) }, - { MP_ROM_QSTR(MP_QSTR_PG14), MP_ROM_PTR(&pin_PG14) }, - { MP_ROM_QSTR(MP_QSTR_PG15), MP_ROM_PTR(&pin_PG15) }, -#endif - { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) }, - { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) }, - { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) }, - { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) }, - { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) }, - { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) }, - { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) }, -#if MCU_PACKAGE >= 100 - { MP_ROM_QSTR(MP_QSTR_PE00), MP_ROM_PTR(&pin_PE00) }, - { MP_ROM_QSTR(MP_QSTR_PE01), MP_ROM_PTR(&pin_PE01) }, -#endif -}; -MP_DEFINE_CONST_DICT(mcu_pin_globals, mcu_pin_globals_table); diff --git a/ports/stm/common-hal/os/__init__.c b/ports/stm/common-hal/os/__init__.c index 0b3153286aeec..1a1efef9ff406 100644 --- a/ports/stm/common-hal/os/__init__.c +++ b/ports/stm/common-hal/os/__init__.c @@ -33,7 +33,7 @@ #include "py/mperrno.h" #include "py/runtime.h" #include "stm32f4xx_hal.h" -#include "stm32f4/periph.h" +#include "peripherals/periph.h" STATIC const qstr os_uname_info_fields[] = { MP_QSTR_sysname, MP_QSTR_nodename, diff --git a/ports/stm/common-hal/pulseio/PWMOut.h b/ports/stm/common-hal/pulseio/PWMOut.h index 59fc04e5ff6bf..8519735c6210c 100644 --- a/ports/stm/common-hal/pulseio/PWMOut.h +++ b/ports/stm/common-hal/pulseio/PWMOut.h @@ -30,7 +30,7 @@ #include "common-hal/microcontroller/Pin.h" #include "stm32f4xx_hal.h" -#include "stm32f4/periph.h" +#include "peripherals/periph.h" #include "py/obj.h" diff --git a/ports/stm/common-hal/supervisor/Runtime.h b/ports/stm/common-hal/supervisor/Runtime.h index 9a798e05677b0..a357eb0c7ee4d 100755 --- a/ports/stm/common-hal/supervisor/Runtime.h +++ b/ports/stm/common-hal/supervisor/Runtime.h @@ -24,8 +24,8 @@ * THE SOFTWARE. */ -#ifndef MICROPY_INCLUDED_STM32F4_COMMON_HAL_SUPERVISOR_RUNTIME_H -#define MICROPY_INCLUDED_STM32F4_COMMON_HAL_SUPERVISOR_RUNTIME_H +#ifndef MICROPY_INCLUDED_STM32_COMMON_HAL_SUPERVISOR_RUNTIME_H +#define MICROPY_INCLUDED_STM32_COMMON_HAL_SUPERVISOR_RUNTIME_H #include "py/obj.h" @@ -34,4 +34,4 @@ typedef struct { // Stores no state currently. } super_runtime_obj_t; -#endif // MICROPY_INCLUDED_STM32F4_COMMON_HAL_SUPERVISOR_RUNTIME_H +#endif // MICROPY_INCLUDED_STM32_COMMON_HAL_SUPERVISOR_RUNTIME_H diff --git a/ports/stm/mpconfigport.h b/ports/stm/mpconfigport.h index 283984ea90396..297c7338ed777 100644 --- a/ports/stm/mpconfigport.h +++ b/ports/stm/mpconfigport.h @@ -25,8 +25,8 @@ * THE SOFTWARE. */ -#ifndef STM32F4_MPCONFIGPORT_H__ -#define STM32F4_MPCONFIGPORT_H__ +#ifndef STM32_MPCONFIGPORT_H__ +#define STM32_MPCONFIGPORT_H__ #define MICROPY_PY_COLLECTIONS_ORDEREDDICT (1) #define MICROPY_PY_FUNCTION_ATTRS (1) @@ -39,7 +39,10 @@ #include "py/circuitpy_mpconfig.h" -//Board flags: +// The STM32 HAL file is included virtually everywhere: +#include STM32_HAL_H + +// Board flags: #ifndef BOARD_OVERWRITE_SWD #define BOARD_OVERWRITE_SWD (0) #endif diff --git a/ports/stm/mpconfigport.mk b/ports/stm/mpconfigport.mk index 493f32c636b48..75cde0e388d4b 100644 --- a/ports/stm/mpconfigport.mk +++ b/ports/stm/mpconfigport.mk @@ -12,7 +12,7 @@ USB_SERIAL_NUMBER_LENGTH = 24 # Longints can be implemented as mpz, as longlong, or not LONGINT_IMPL = MPZ -#Reduced feature set for early port +# Reduced feature set for early port CIRCUITPY_MINIMAL_BUILD = 1 # The ifndef's allow overriding in mpconfigboard.mk. @@ -73,5 +73,18 @@ CFLAGS += -DMICROPY_CPYTHON_COMPAT=1 MICROPY_PY_ULAB = 1 -#ifeq ($(MCU_SUB_VARIANT), stm32f412zx) -#endif +ifeq ($(MCU_SERIES), H7) + CIRCUITPY_BOARD = 1 + CIRCUITPY_DIGITALIO = 1 + CIRCUITPY_ANALOGIO = 0 + CIRCUITPY_MICROCONTROLLER = 1 + CIRCUITPY_BUSIO = 0 + CIRCUITPY_PULSEIO = 0 + CIRCUITPY_OS = 0 + CIRCUITPY_STORAGE = 0 + CIRCUITPY_RANDOM = 0 + CIRCUITPY_USB_HID = 0 + CIRCUITPY_USB_MIDI = 0 + CIRCUITPY_NEOPIXEL_WRITE = 0 + CIRCUITPY_DISPLAYIO = 0 +endif diff --git a/ports/stm/mphalport.c b/ports/stm/mphalport.c index a3cf501c046b5..3ee56e22a9cbd 100644 --- a/ports/stm/mphalport.c +++ b/ports/stm/mphalport.c @@ -33,7 +33,6 @@ #include "shared-bindings/microcontroller/__init__.h" #include "supervisor/shared/tick.h" -#include "stm32f4xx_hal.h" void mp_hal_delay_ms(mp_uint_t delay) { uint64_t start_tick = supervisor_ticks_ms64(); diff --git a/ports/stm/mphalport.h b/ports/stm/mphalport.h index b392cb0f84e9b..69f2c489c55a6 100644 --- a/ports/stm/mphalport.h +++ b/ports/stm/mphalport.h @@ -24,8 +24,8 @@ * THE SOFTWARE. */ -#ifndef MICROPY_INCLUDED_STM32F4_MPHALPORT_H -#define MICROPY_INCLUDED_STM32F4_MPHALPORT_H +#ifndef MICROPY_INCLUDED_STM32_MPHALPORT_H +#define MICROPY_INCLUDED_STM32_MPHALPORT_H #include "py/obj.h" @@ -48,4 +48,4 @@ void mp_hal_set_interrupt_char(int c); void mp_hal_disable_all_interrupts(void); void mp_hal_enable_all_interrupts(void); -#endif // MICROPY_INCLUDED_STM32F4_MPHALPORT_H +#endif // MICROPY_INCLUDED_STM32_MPHALPORT_H diff --git a/ports/stm/packages/LQFP100_f4.c b/ports/stm/packages/LQFP100_f4.c new file mode 100644 index 0000000000000..a2219ccc087ec --- /dev/null +++ b/ports/stm/packages/LQFP100_f4.c @@ -0,0 +1,117 @@ +#include "shared-bindings/microcontroller/__init__.h" +#include "common-hal/microcontroller/Pin.h" +#include "py/obj.h" + +STATIC const mp_rom_map_elem_t mcu_pin_globals_table[] = { +// Pins 1-25 + { MP_ROM_QSTR(MP_QSTR_PE02), MP_ROM_PTR(&pin_PE02) }, + { MP_ROM_QSTR(MP_QSTR_PE03), MP_ROM_PTR(&pin_PE03) }, + { MP_ROM_QSTR(MP_QSTR_PE04), MP_ROM_PTR(&pin_PE04) }, + { MP_ROM_QSTR(MP_QSTR_PE05), MP_ROM_PTR(&pin_PE05) }, + { MP_ROM_QSTR(MP_QSTR_PE06), MP_ROM_PTR(&pin_PE06) }, + /* VBAT -------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) }, + // PC14 OSC32_IN ----------------------------------*/ + // PC15 OSC32_OUT ---------------------------------*/ + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ + // PH0 OSC_IN -------------------------------------*/ + // PH1 OSC_OUT ------------------------------------*/ + // NRST -------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PC00), MP_ROM_PTR(&pin_PC00) }, + { MP_ROM_QSTR(MP_QSTR_PC01), MP_ROM_PTR(&pin_PC01) }, + { MP_ROM_QSTR(MP_QSTR_PC02), MP_ROM_PTR(&pin_PC02) }, + { MP_ROM_QSTR(MP_QSTR_PC03), MP_ROM_PTR(&pin_PC03) }, + // VDD --------------------------------------------*/ + // VSSA -------------------------------------------*/ + // VREF+ ------------------------------------------*/ + // VDDA -------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PA00), MP_ROM_PTR(&pin_PA00) }, + { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) }, + { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) }, + +// Pins 26-50 + { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) }, + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) }, + { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) }, + { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) }, + { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) }, + { MP_ROM_QSTR(MP_QSTR_PC04), MP_ROM_PTR(&pin_PC04) }, + { MP_ROM_QSTR(MP_QSTR_PC05), MP_ROM_PTR(&pin_PC05) }, + { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) }, + { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) }, + { MP_ROM_QSTR(MP_QSTR_PB02), MP_ROM_PTR(&pin_PB02) }, + { MP_ROM_QSTR(MP_QSTR_PE07), MP_ROM_PTR(&pin_PE07) }, + { MP_ROM_QSTR(MP_QSTR_PE08), MP_ROM_PTR(&pin_PE08) }, + { MP_ROM_QSTR(MP_QSTR_PE09), MP_ROM_PTR(&pin_PE09) }, + { MP_ROM_QSTR(MP_QSTR_PE10), MP_ROM_PTR(&pin_PE10) }, + { MP_ROM_QSTR(MP_QSTR_PE11), MP_ROM_PTR(&pin_PE11) }, + { MP_ROM_QSTR(MP_QSTR_PE12), MP_ROM_PTR(&pin_PE12) }, + { MP_ROM_QSTR(MP_QSTR_PE13), MP_ROM_PTR(&pin_PE13) }, + { MP_ROM_QSTR(MP_QSTR_PE14), MP_ROM_PTR(&pin_PE14) }, + { MP_ROM_QSTR(MP_QSTR_PE15), MP_ROM_PTR(&pin_PE15) }, + { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) }, +#if MCU_LINE == FOUNDATION || MCU_LINE == ADVANCED + { MP_ROM_QSTR(MP_QSTR_PB11), MP_ROM_PTR(&pin_PB11) }, +#endif //or VCAP1 -----------------------------------*/ + // VCAP1 or VSS -----------------------------------*/ + // VDD --------------------------------------------*/ + +// Pins 51-75 + { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) }, + { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) }, + { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) }, + { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) }, + { MP_ROM_QSTR(MP_QSTR_PD08), MP_ROM_PTR(&pin_PD08) }, + { MP_ROM_QSTR(MP_QSTR_PD09), MP_ROM_PTR(&pin_PD09) }, + { MP_ROM_QSTR(MP_QSTR_PD10), MP_ROM_PTR(&pin_PD10) }, + { MP_ROM_QSTR(MP_QSTR_PD11), MP_ROM_PTR(&pin_PD11) }, + { MP_ROM_QSTR(MP_QSTR_PD12), MP_ROM_PTR(&pin_PD12) }, + { MP_ROM_QSTR(MP_QSTR_PD13), MP_ROM_PTR(&pin_PD13) }, + { MP_ROM_QSTR(MP_QSTR_PD14), MP_ROM_PTR(&pin_PD14) }, + { MP_ROM_QSTR(MP_QSTR_PD15), MP_ROM_PTR(&pin_PD15) }, + { MP_ROM_QSTR(MP_QSTR_PC06), MP_ROM_PTR(&pin_PC06) }, + { MP_ROM_QSTR(MP_QSTR_PC07), MP_ROM_PTR(&pin_PC07) }, + { MP_ROM_QSTR(MP_QSTR_PC08), MP_ROM_PTR(&pin_PC08) }, + { MP_ROM_QSTR(MP_QSTR_PC09), MP_ROM_PTR(&pin_PC09) }, + { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) }, + { MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) }, + { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) }, + { MP_ROM_QSTR(MP_QSTR_PA11), MP_ROM_PTR(&pin_PA11) }, + { MP_ROM_QSTR(MP_QSTR_PA12), MP_ROM_PTR(&pin_PA12) }, + { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) }, + // VCAP2 ------------------------------------------*/ + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ + +// Pins 76-100 + { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) }, + { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) }, + { MP_ROM_QSTR(MP_QSTR_PC10), MP_ROM_PTR(&pin_PC10) }, + { MP_ROM_QSTR(MP_QSTR_PC11), MP_ROM_PTR(&pin_PC11) }, + { MP_ROM_QSTR(MP_QSTR_PC12), MP_ROM_PTR(&pin_PC12) }, + { MP_ROM_QSTR(MP_QSTR_PD00), MP_ROM_PTR(&pin_PD00) }, + { MP_ROM_QSTR(MP_QSTR_PD01), MP_ROM_PTR(&pin_PD01) }, + { MP_ROM_QSTR(MP_QSTR_PD02), MP_ROM_PTR(&pin_PD02) }, + { MP_ROM_QSTR(MP_QSTR_PD03), MP_ROM_PTR(&pin_PD03) }, + { MP_ROM_QSTR(MP_QSTR_PD04), MP_ROM_PTR(&pin_PD04) }, + { MP_ROM_QSTR(MP_QSTR_PD05), MP_ROM_PTR(&pin_PD05) }, + { MP_ROM_QSTR(MP_QSTR_PD06), MP_ROM_PTR(&pin_PD06) }, + { MP_ROM_QSTR(MP_QSTR_PD07), MP_ROM_PTR(&pin_PD07) }, + { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) }, + { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) }, + { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) }, + { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) }, + { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) }, + // BOOT0 ------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) }, + { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) }, + { MP_ROM_QSTR(MP_QSTR_PE00), MP_ROM_PTR(&pin_PE00) }, + { MP_ROM_QSTR(MP_QSTR_PE01), MP_ROM_PTR(&pin_PE01) }, + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ + +}; +MP_DEFINE_CONST_DICT(mcu_pin_globals, mcu_pin_globals_table); \ No newline at end of file diff --git a/ports/stm/packages/stm32f4/LQFP100.h b/ports/stm/packages/LQFP100_x7.c similarity index 88% rename from ports/stm/packages/stm32f4/LQFP100.h rename to ports/stm/packages/LQFP100_x7.c index 3c0e244f99605..23d89a8268b2c 100644 --- a/ports/stm/packages/stm32f4/LQFP100.h +++ b/ports/stm/packages/LQFP100_x7.c @@ -1,3 +1,7 @@ +#include "shared-bindings/microcontroller/__init__.h" +#include "common-hal/microcontroller/Pin.h" +#include "py/obj.h" + STATIC const mp_rom_map_elem_t mcu_pin_globals_table[] = { // Pins 1-25 { MP_ROM_QSTR(MP_QSTR_PE02), MP_ROM_PTR(&pin_PE02) }, @@ -25,11 +29,11 @@ STATIC const mp_rom_map_elem_t mcu_pin_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) }, { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) }, { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) }, - { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) }, // Pins 26-50 // VSS --------------------------------------------*/ // VDD --------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) }, { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) }, { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) }, { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) }, @@ -48,11 +52,12 @@ STATIC const mp_rom_map_elem_t mcu_pin_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_PE14), MP_ROM_PTR(&pin_PE14) }, { MP_ROM_QSTR(MP_QSTR_PE15), MP_ROM_PTR(&pin_PE15) }, { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) }, -#if MCU_LINE == FOUNDATION || MCU_LINE == ADVANCED { MP_ROM_QSTR(MP_QSTR_PB11), MP_ROM_PTR(&pin_PB11) }, -#endif - + // VCAP1 ------------------------------------------*/ + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ +// Pins 51-75 { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) }, { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) }, { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) }, @@ -75,6 +80,11 @@ STATIC const mp_rom_map_elem_t mcu_pin_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_PA11), MP_ROM_PTR(&pin_PA11) }, { MP_ROM_QSTR(MP_QSTR_PA12), MP_ROM_PTR(&pin_PA12) }, { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) }, + // VCAP2 ------------------------------------------*/ + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ + +// Pins 76-100 { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) }, { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) }, { MP_ROM_QSTR(MP_QSTR_PC10), MP_ROM_PTR(&pin_PC10) }, @@ -93,9 +103,13 @@ STATIC const mp_rom_map_elem_t mcu_pin_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) }, { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) }, { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) }, + // BOOT0 ------------------------------------------*/ { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) }, { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) }, { MP_ROM_QSTR(MP_QSTR_PE00), MP_ROM_PTR(&pin_PE00) }, { MP_ROM_QSTR(MP_QSTR_PE01), MP_ROM_PTR(&pin_PE01) }, + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ + }; MP_DEFINE_CONST_DICT(mcu_pin_globals, mcu_pin_globals_table); \ No newline at end of file diff --git a/ports/stm/packages/LQFP144.c b/ports/stm/packages/LQFP144.c new file mode 100644 index 0000000000000..36683bb64862c --- /dev/null +++ b/ports/stm/packages/LQFP144.c @@ -0,0 +1,159 @@ +#include "shared-bindings/microcontroller/__init__.h" +#include "common-hal/microcontroller/Pin.h" +#include "py/obj.h" + +STATIC const mp_rom_map_elem_t mcu_pin_globals_table[] = { +// Pins 1-36 + { MP_ROM_QSTR(MP_QSTR_PE02), MP_ROM_PTR(&pin_PE02) }, + { MP_ROM_QSTR(MP_QSTR_PE03), MP_ROM_PTR(&pin_PE03) }, + { MP_ROM_QSTR(MP_QSTR_PE04), MP_ROM_PTR(&pin_PE04) }, + { MP_ROM_QSTR(MP_QSTR_PE05), MP_ROM_PTR(&pin_PE05) }, + { MP_ROM_QSTR(MP_QSTR_PE06), MP_ROM_PTR(&pin_PE06) }, + /* VBAT -------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) }, + // PC14 OSC32_IN ----------------------------------*/ + // PC15 OSC32_OUT ---------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PF00), MP_ROM_PTR(&pin_PF00) }, + { MP_ROM_QSTR(MP_QSTR_PF01), MP_ROM_PTR(&pin_PF01) }, + { MP_ROM_QSTR(MP_QSTR_PF02), MP_ROM_PTR(&pin_PF02) }, + { MP_ROM_QSTR(MP_QSTR_PF03), MP_ROM_PTR(&pin_PF03) }, + { MP_ROM_QSTR(MP_QSTR_PF04), MP_ROM_PTR(&pin_PF04) }, + { MP_ROM_QSTR(MP_QSTR_PF05), MP_ROM_PTR(&pin_PF05) }, + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PF06), MP_ROM_PTR(&pin_PF06) }, + { MP_ROM_QSTR(MP_QSTR_PF07), MP_ROM_PTR(&pin_PF07) }, + { MP_ROM_QSTR(MP_QSTR_PF08), MP_ROM_PTR(&pin_PF08) }, + { MP_ROM_QSTR(MP_QSTR_PF09), MP_ROM_PTR(&pin_PF09) }, + { MP_ROM_QSTR(MP_QSTR_PF10), MP_ROM_PTR(&pin_PF10) }, + // PH0 OSC_IN -------------------------------------*/ + // PH1 OSC_OUT ------------------------------------*/ + // NRST -------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PC00), MP_ROM_PTR(&pin_PC00) }, + { MP_ROM_QSTR(MP_QSTR_PC01), MP_ROM_PTR(&pin_PC01) }, + { MP_ROM_QSTR(MP_QSTR_PC02), MP_ROM_PTR(&pin_PC02) }, + { MP_ROM_QSTR(MP_QSTR_PC03), MP_ROM_PTR(&pin_PC03) }, + // VDD --------------------------------------------*/ + // VSSA -------------------------------------------*/ + // VREF+ ------------------------------------------*/ + // VDDA -------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PA00), MP_ROM_PTR(&pin_PA00) }, + { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) }, + { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) }, + +// Pins 37-72 + { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) }, + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) }, + { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) }, + { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) }, + { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) }, + { MP_ROM_QSTR(MP_QSTR_PC04), MP_ROM_PTR(&pin_PC04) }, + { MP_ROM_QSTR(MP_QSTR_PC05), MP_ROM_PTR(&pin_PC05) }, + { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) }, + { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) }, + { MP_ROM_QSTR(MP_QSTR_PB02), MP_ROM_PTR(&pin_PB02) }, + { MP_ROM_QSTR(MP_QSTR_PF11), MP_ROM_PTR(&pin_PF11) }, + { MP_ROM_QSTR(MP_QSTR_PF12), MP_ROM_PTR(&pin_PF12) }, + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PF13), MP_ROM_PTR(&pin_PF13) }, + { MP_ROM_QSTR(MP_QSTR_PF14), MP_ROM_PTR(&pin_PF14) }, + { MP_ROM_QSTR(MP_QSTR_PF15), MP_ROM_PTR(&pin_PF15) }, + { MP_ROM_QSTR(MP_QSTR_PG00), MP_ROM_PTR(&pin_PG00) }, + { MP_ROM_QSTR(MP_QSTR_PG01), MP_ROM_PTR(&pin_PG01) }, + { MP_ROM_QSTR(MP_QSTR_PE07), MP_ROM_PTR(&pin_PE07) }, + { MP_ROM_QSTR(MP_QSTR_PE08), MP_ROM_PTR(&pin_PE08) }, + { MP_ROM_QSTR(MP_QSTR_PE09), MP_ROM_PTR(&pin_PE09) }, + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PE10), MP_ROM_PTR(&pin_PE10) }, + { MP_ROM_QSTR(MP_QSTR_PE11), MP_ROM_PTR(&pin_PE11) }, + { MP_ROM_QSTR(MP_QSTR_PE12), MP_ROM_PTR(&pin_PE12) }, + { MP_ROM_QSTR(MP_QSTR_PE13), MP_ROM_PTR(&pin_PE13) }, + { MP_ROM_QSTR(MP_QSTR_PE14), MP_ROM_PTR(&pin_PE14) }, + { MP_ROM_QSTR(MP_QSTR_PE15), MP_ROM_PTR(&pin_PE15) }, + { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) }, + { MP_ROM_QSTR(MP_QSTR_PB11), MP_ROM_PTR(&pin_PB11) }, + // VCAP1 ------------------------------------------*/ + // VDD --------------------------------------------*/ + +// Pins 73-108 + { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) }, + { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) }, + { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) }, + { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) }, + { MP_ROM_QSTR(MP_QSTR_PD08), MP_ROM_PTR(&pin_PD08) }, + { MP_ROM_QSTR(MP_QSTR_PD09), MP_ROM_PTR(&pin_PD09) }, + { MP_ROM_QSTR(MP_QSTR_PD10), MP_ROM_PTR(&pin_PD10) }, + { MP_ROM_QSTR(MP_QSTR_PD11), MP_ROM_PTR(&pin_PD11) }, + { MP_ROM_QSTR(MP_QSTR_PD12), MP_ROM_PTR(&pin_PD12) }, + { MP_ROM_QSTR(MP_QSTR_PD13), MP_ROM_PTR(&pin_PD13) }, + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PD14), MP_ROM_PTR(&pin_PD14) }, + { MP_ROM_QSTR(MP_QSTR_PD15), MP_ROM_PTR(&pin_PD15) }, + { MP_ROM_QSTR(MP_QSTR_PG02), MP_ROM_PTR(&pin_PG02) }, + { MP_ROM_QSTR(MP_QSTR_PG03), MP_ROM_PTR(&pin_PG03) }, + { MP_ROM_QSTR(MP_QSTR_PG04), MP_ROM_PTR(&pin_PG04) }, + { MP_ROM_QSTR(MP_QSTR_PG05), MP_ROM_PTR(&pin_PG05) }, + { MP_ROM_QSTR(MP_QSTR_PG06), MP_ROM_PTR(&pin_PG06) }, + { MP_ROM_QSTR(MP_QSTR_PG07), MP_ROM_PTR(&pin_PG07) }, + { MP_ROM_QSTR(MP_QSTR_PG08), MP_ROM_PTR(&pin_PG08) }, + // VSS --------------------------------------------*/ + // VDD or VDD_USB (F412, F446) --------------------*/ + { MP_ROM_QSTR(MP_QSTR_PC06), MP_ROM_PTR(&pin_PC06) }, + { MP_ROM_QSTR(MP_QSTR_PC07), MP_ROM_PTR(&pin_PC07) }, + { MP_ROM_QSTR(MP_QSTR_PC08), MP_ROM_PTR(&pin_PC08) }, + { MP_ROM_QSTR(MP_QSTR_PC09), MP_ROM_PTR(&pin_PC09) }, + { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) }, + { MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) }, + { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) }, + { MP_ROM_QSTR(MP_QSTR_PA11), MP_ROM_PTR(&pin_PA11) }, + { MP_ROM_QSTR(MP_QSTR_PA12), MP_ROM_PTR(&pin_PA12) }, + { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) }, + // VCAP2 ------------------------------------------*/ + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ + +// Pins 109-144 + { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) }, + { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) }, + { MP_ROM_QSTR(MP_QSTR_PC10), MP_ROM_PTR(&pin_PC10) }, + { MP_ROM_QSTR(MP_QSTR_PC11), MP_ROM_PTR(&pin_PC11) }, + { MP_ROM_QSTR(MP_QSTR_PC12), MP_ROM_PTR(&pin_PC12) }, + { MP_ROM_QSTR(MP_QSTR_PD00), MP_ROM_PTR(&pin_PD00) }, + { MP_ROM_QSTR(MP_QSTR_PD01), MP_ROM_PTR(&pin_PD01) }, + { MP_ROM_QSTR(MP_QSTR_PD02), MP_ROM_PTR(&pin_PD02) }, + { MP_ROM_QSTR(MP_QSTR_PD03), MP_ROM_PTR(&pin_PD03) }, + { MP_ROM_QSTR(MP_QSTR_PD04), MP_ROM_PTR(&pin_PD04) }, + { MP_ROM_QSTR(MP_QSTR_PD05), MP_ROM_PTR(&pin_PD05) }, + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PD06), MP_ROM_PTR(&pin_PD06) }, + { MP_ROM_QSTR(MP_QSTR_PD07), MP_ROM_PTR(&pin_PD07) }, + { MP_ROM_QSTR(MP_QSTR_PG09), MP_ROM_PTR(&pin_PG09) }, + { MP_ROM_QSTR(MP_QSTR_PG10), MP_ROM_PTR(&pin_PG10) }, + { MP_ROM_QSTR(MP_QSTR_PG11), MP_ROM_PTR(&pin_PG11) }, + { MP_ROM_QSTR(MP_QSTR_PG12), MP_ROM_PTR(&pin_PG12) }, + { MP_ROM_QSTR(MP_QSTR_PG13), MP_ROM_PTR(&pin_PG13) }, + { MP_ROM_QSTR(MP_QSTR_PG14), MP_ROM_PTR(&pin_PG14) }, + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PG15), MP_ROM_PTR(&pin_PG15) }, + { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) }, + { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) }, + { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) }, + { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) }, + { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) }, + // BOOT0 ------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) }, + { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) }, + { MP_ROM_QSTR(MP_QSTR_PE00), MP_ROM_PTR(&pin_PE00) }, + { MP_ROM_QSTR(MP_QSTR_PE01), MP_ROM_PTR(&pin_PE01) }, + // PDR_ON -----------------------------------------*/ + // VDD --------------------------------------------*/ + +}; +MP_DEFINE_CONST_DICT(mcu_pin_globals, mcu_pin_globals_table); \ No newline at end of file diff --git a/ports/stm/packages/LQFP64.c b/ports/stm/packages/LQFP64.c new file mode 100644 index 0000000000000..02dcfa00ca931 --- /dev/null +++ b/ports/stm/packages/LQFP64.c @@ -0,0 +1,81 @@ +#include "shared-bindings/microcontroller/__init__.h" +#include "common-hal/microcontroller/Pin.h" +#include "py/obj.h" + +STATIC const mp_rom_map_elem_t mcu_pin_globals_table[] = { +// Pins 1-16 + /* VBAT -------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) }, + // PC14 OSC32_IN ----------------------------------*/ + // PC15 OSC32_OUT ---------------------------------*/ + // PH0 OSC_IN -------------------------------------*/ + // PH1 OSC_OUT ------------------------------------*/ + // NRST -------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PC00), MP_ROM_PTR(&pin_PC00) }, + { MP_ROM_QSTR(MP_QSTR_PC01), MP_ROM_PTR(&pin_PC01) }, + { MP_ROM_QSTR(MP_QSTR_PC02), MP_ROM_PTR(&pin_PC02) }, + { MP_ROM_QSTR(MP_QSTR_PC03), MP_ROM_PTR(&pin_PC03) }, + // VSSA -------------------------------------------*/ + // VDDA -------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PA00), MP_ROM_PTR(&pin_PA00) }, + { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) }, + { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) }, + +// Pins 17-32 + { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) }, + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) }, + { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) }, + { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) }, + { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) }, + { MP_ROM_QSTR(MP_QSTR_PC04), MP_ROM_PTR(&pin_PC04) }, + { MP_ROM_QSTR(MP_QSTR_PC05), MP_ROM_PTR(&pin_PC05) }, + { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) }, + { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) }, + { MP_ROM_QSTR(MP_QSTR_PB02), MP_ROM_PTR(&pin_PB02) }, + { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) }, +#if MCU_LINE == FOUNDATION || MCU_LINE == ADVANCED + { MP_ROM_QSTR(MP_QSTR_PB11), MP_ROM_PTR(&pin_PB11) }, +#endif //or VCAP1 -----------------------------------*/ + // VCAP1 or VSS -----------------------------------*/ + // VDD --------------------------------------------*/ + +// Pins 33-48 + { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) }, + { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) }, + { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) }, + { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) }, + { MP_ROM_QSTR(MP_QSTR_PC06), MP_ROM_PTR(&pin_PC06) }, + { MP_ROM_QSTR(MP_QSTR_PC07), MP_ROM_PTR(&pin_PC07) }, + { MP_ROM_QSTR(MP_QSTR_PC08), MP_ROM_PTR(&pin_PC08) }, + { MP_ROM_QSTR(MP_QSTR_PC09), MP_ROM_PTR(&pin_PC09) }, + { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) }, + { MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) }, + { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) }, + { MP_ROM_QSTR(MP_QSTR_PA11), MP_ROM_PTR(&pin_PA11) }, + { MP_ROM_QSTR(MP_QSTR_PA12), MP_ROM_PTR(&pin_PA12) }, + { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) }, + // VSS or VCAP (F405) -----------------------------*/ + // VDD --------------------------------------------*/ + +// Pins 49-64 + { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) }, + { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) }, + { MP_ROM_QSTR(MP_QSTR_PC10), MP_ROM_PTR(&pin_PC10) }, + { MP_ROM_QSTR(MP_QSTR_PC11), MP_ROM_PTR(&pin_PC11) }, + { MP_ROM_QSTR(MP_QSTR_PC12), MP_ROM_PTR(&pin_PC12) }, + { MP_ROM_QSTR(MP_QSTR_PD02), MP_ROM_PTR(&pin_PD02) }, + { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) }, + { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) }, + { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) }, + { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) }, + { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) }, + // BOOT0 ------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) }, + { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) }, + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ + +}; +MP_DEFINE_CONST_DICT(mcu_pin_globals, mcu_pin_globals_table); diff --git a/ports/stm/packages/UFQFPN48.c b/ports/stm/packages/UFQFPN48.c new file mode 100644 index 0000000000000..ae4bcf6cdadbc --- /dev/null +++ b/ports/stm/packages/UFQFPN48.c @@ -0,0 +1,63 @@ +#include "shared-bindings/microcontroller/__init__.h" +#include "common-hal/microcontroller/Pin.h" +#include "py/obj.h" + +STATIC const mp_rom_map_elem_t mcu_pin_globals_table[] = { +// Pins 1-12 + /* VBAT -------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) }, + // PC14 OSC32_IN ----------------------------------*/ + // PC15 OSC32_OUT ---------------------------------*/ + // PH0 OSC_IN -------------------------------------*/ + // PH1 OSC_OUT ------------------------------------*/ + // NRST -------------------------------------------*/ + // VSSA -------------------------------------------*/ + // VDDA -------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PA00), MP_ROM_PTR(&pin_PA00) }, + { MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) }, + { MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) }, + +// Pins 13-24 + { MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) }, + { MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) }, + { MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) }, + { MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) }, + { MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) }, + { MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) }, + { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) }, + { MP_ROM_QSTR(MP_QSTR_PB02), MP_ROM_PTR(&pin_PB02) }, + { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) }, + // VCAP1 ------------------------------------------*/ + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ + +// Pins 25-36 + { MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) }, + { MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) }, + { MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) }, + { MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) }, + { MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) }, + { MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) }, + { MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) }, + { MP_ROM_QSTR(MP_QSTR_PA11), MP_ROM_PTR(&pin_PA11) }, + { MP_ROM_QSTR(MP_QSTR_PA12), MP_ROM_PTR(&pin_PA12) }, + { MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) }, + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ + +// Pins 37-48 + { MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) }, + { MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) }, + { MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) }, + { MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) }, + { MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) }, + { MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) }, + { MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) }, + // BOOT0 ------------------------------------------*/ + { MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) }, + { MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) }, + // VSS --------------------------------------------*/ + // VDD --------------------------------------------*/ + +}; +MP_DEFINE_CONST_DICT(mcu_pin_globals, mcu_pin_globals_table); \ No newline at end of file diff --git a/ports/stm/peripherals/stm32f4/clocks.h b/ports/stm/peripherals/clocks.h similarity index 91% rename from ports/stm/peripherals/stm32f4/clocks.h rename to ports/stm/peripherals/clocks.h index c7ba846622ca2..1f837c79ee986 100644 --- a/ports/stm/peripherals/stm32f4/clocks.h +++ b/ports/stm/peripherals/clocks.h @@ -3,7 +3,7 @@ * * The MIT License (MIT) * - * Copyright (c) 2019 Lucian Copeland for Adafruit Industries + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -24,4 +24,4 @@ * THE SOFTWARE. */ -void stm32f4_peripherals_clocks_init(void); +void stm32_peripherals_clocks_init(void); diff --git a/ports/stm/peripherals/stm32f4/gpio.h b/ports/stm/peripherals/gpio.h similarity index 87% rename from ports/stm/peripherals/stm32f4/gpio.h rename to ports/stm/peripherals/gpio.h index 34f89e79212c1..a5dbe444cbd56 100644 --- a/ports/stm/peripherals/stm32f4/gpio.h +++ b/ports/stm/peripherals/gpio.h @@ -3,7 +3,7 @@ * * The MIT License (MIT) * - * Copyright (c) 2019 Lucian Copeland for Adafruit Industries + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -24,5 +24,4 @@ * THE SOFTWARE. */ -void stm32f4_peripherals_gpio_init(void); -void stm32f4_peripherals_status_led(uint8_t led, uint8_t state); +void stm32_peripherals_gpio_init(void); diff --git a/ports/stm/peripherals/periph.h b/ports/stm/peripherals/periph.h new file mode 100644 index 0000000000000..aaf41361e67b2 --- /dev/null +++ b/ports/stm/peripherals/periph.h @@ -0,0 +1,117 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef __MICROPY_INCLUDED_STM32_PERIPHERALS_PERIPH_H__ +#define __MICROPY_INCLUDED_STM32_PERIPHERALS_PERIPH_H__ + +#include +#include + +#include STM32_HAL_H +#include "pins.h" + +// PERIPH + +typedef struct { + uint8_t periph_index:4; // Index of the I2C unit (1 to 3) + uint8_t altfn_index:4; //Index of the altfn for this pin (0 to 15) + const mcu_pin_obj_t * pin; +} mcu_periph_obj_t; + +#define PERIPH(index, alt, p_pin) \ +{ \ + .periph_index = index, \ + .altfn_index = alt, \ + .pin = p_pin, \ +} + +//Timers +typedef struct { + uint8_t tim_index:4; + uint8_t altfn_index:4; + uint8_t channel_index:4; + const mcu_pin_obj_t * pin; +} mcu_tim_pin_obj_t; + +#define TIM(index, alt, channel, tim_pin) \ +{ \ + .tim_index = index, \ + .altfn_index = alt, \ + .channel_index = channel, \ + .pin = tim_pin, \ +} + +// F4 Series +// Access Lines + +#ifdef STM32F401xE +#define HAS_DAC 0 +#define HAS_TRNG 0 +#define HAS_BASIC_TIM 0 +#include "stm32f4/stm32f401xe/periph.h" +#endif + +#ifdef STM32F411xE +#define HAS_DAC 0 +#define HAS_TRNG 0 +#define HAS_BASIC_TIM 0 +#include "stm32f4/stm32f411xe/periph.h" +#endif + +#ifdef STM32F412Zx +#define HAS_DAC 0 +#define HAS_TRNG 1 +#define HAS_BASIC_TIM 1 +#include "stm32f4/stm32f412zx/periph.h" +#endif + +// Foundation Lines + +#ifdef STM32F405xx +#define HAS_DAC 1 +#define HAS_TRNG 1 +#define HAS_BASIC_TIM 1 +#include "stm32f4/stm32f405xx/periph.h" +#endif + +#ifdef STM32F407xx +#define HAS_DAC 1 +#define HAS_TRNG 1 +#define HAS_BASIC_TIM 1 +#include "stm32f4/stm32f407xx/periph.h" +#endif + +// H7 Series +// Single Core + +#ifdef STM32H743xx +#define HAS_DAC 0 +#define HAS_TRNG 0 +#define HAS_BASIC_TIM 0 +#include "stm32h7/stm32h743xx/periph.h" +#endif + +#endif // __MICROPY_INCLUDED_STM32_PERIPHERALS_PERIPH_H__ diff --git a/ports/stm/peripherals/stm32f4/pins.h b/ports/stm/peripherals/pins.h similarity index 82% rename from ports/stm/peripherals/stm32f4/pins.h rename to ports/stm/peripherals/pins.h index 44ef4c1baf789..c6f1ec322bbe9 100644 --- a/ports/stm/peripherals/stm32f4/pins.h +++ b/ports/stm/peripherals/pins.h @@ -3,8 +3,7 @@ * * The MIT License (MIT) * - * Copyright (c) 2018 Dan Halbert for Adafruit Industries - * Copyright (c) 2019 Lucian Copeland for Adafruit Industries + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -28,13 +27,13 @@ // DO NOT include this file directly. Use shared-bindings/microcontroller/Pin.h instead to ensure // that all necessary includes are already included. -#ifndef __MICROPY_INCLUDED_STM32F4_PERIPHERALS_PINS_H__ -#define __MICROPY_INCLUDED_STM32F4_PERIPHERALS_PINS_H__ +#ifndef __MICROPY_INCLUDED_STM32_PERIPHERALS_PINS_H__ +#define __MICROPY_INCLUDED_STM32_PERIPHERALS_PINS_H__ #include #include -#include "stm32f4xx_hal.h" +#include STM32_HAL_H typedef struct { mp_obj_base_t base; @@ -76,21 +75,26 @@ extern const mp_obj_type_t mcu_pin_type; // Use illegal pin value to mark unassigned pins. #define NO_PIN 0xff -// Choose based on chip +// F4 Series #ifdef STM32F401xE -#include "stm32f401xe/pins.h" +#include "stm32f4/stm32f401xe/pins.h" #endif #ifdef STM32F411xE -#include "stm32f411xe/pins.h" +#include "stm32f4/stm32f411xe/pins.h" #endif #ifdef STM32F412Zx -#include "stm32f412zx/pins.h" +#include "stm32f4/stm32f412zx/pins.h" #endif #ifdef STM32F405xx -#include "stm32f405xx/pins.h" +#include "stm32f4/stm32f405xx/pins.h" #endif #ifdef STM32F407xx -#include "stm32f407xx/pins.h" +#include "stm32f4/stm32f407xx/pins.h" #endif -#endif // __MICROPY_INCLUDED_STM32F4_PERIPHERALS_PINS_H__ +// H7 Series +#ifdef STM32H743xx +#include "stm32h7/stm32h743xx/pins.h" +#endif + +#endif // __MICROPY_INCLUDED_STM32_PERIPHERALS_PINS_H__ diff --git a/ports/stm/peripherals/stm32f4/periph.h b/ports/stm/peripherals/stm32f4/periph.h deleted file mode 100644 index d311afe4a1c23..0000000000000 --- a/ports/stm/peripherals/stm32f4/periph.h +++ /dev/null @@ -1,180 +0,0 @@ -/* - * This file is part of the MicroPython project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2019 Lucian Copeland for Adafruit Industries - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef __MICROPY_INCLUDED_STM32F4_PERIPHERALS_PERIPH_H__ -#define __MICROPY_INCLUDED_STM32F4_PERIPHERALS_PERIPH_H__ - -#include -#include - -#include "stm32f4xx_hal.h" -#include "stm32f4/pins.h" - -// I2C -// TODO: these objects should be condensed into a single 'periph_pin' unless we -// find a compelling reason to store more unique data in them. - -typedef struct { - uint8_t i2c_index:4; // Index of the I2C unit (1 to 3) - uint8_t altfn_index:4; //Index of the altfn for this pin (0 to 15) - const mcu_pin_obj_t * pin; -} mcu_i2c_sda_obj_t; - -typedef struct { - uint8_t i2c_index:4; - uint8_t altfn_index:4; - const mcu_pin_obj_t * pin; -} mcu_i2c_scl_obj_t; - - -#define I2C_SDA(index, alt, sda_pin) \ -{ \ - .i2c_index = index, \ - .altfn_index = alt, \ - .pin = sda_pin, \ -} - -#define I2C_SCL(index, alt, scl_pin) \ -{ \ - .i2c_index = index, \ - .altfn_index = alt, \ - .pin = scl_pin, \ -} - -// SPI -// TODO: these objects should be condensed into a single 'periph_pin' unless we -// find a compelling reason to store more unique data in them. - -typedef struct { - uint8_t spi_index:4; //Up to 6 SPI units - uint8_t altfn_index:4; //Up to 15 alt channels - const mcu_pin_obj_t * pin; -} mcu_spi_sck_obj_t; - -typedef struct { - uint8_t spi_index:4; - uint8_t altfn_index:4; - const mcu_pin_obj_t * pin; -} mcu_spi_mosi_obj_t; - -typedef struct { - uint8_t spi_index:4; - uint8_t altfn_index:4; - const mcu_pin_obj_t * pin; -} mcu_spi_miso_obj_t; - -typedef struct { - uint8_t spi_index:4; - uint8_t altfn_index:4; - const mcu_pin_obj_t * pin; -} mcu_spi_nss_obj_t; - -#define SPI(index, alt, spi_pin) \ -{ \ - .spi_index = index, \ - .altfn_index = alt, \ - .pin = spi_pin, \ -} - -// UART -// TODO: these objects should be condensed into a single 'periph_pin' unless we -// find a compelling reason to store more unique data in them. - -typedef struct { - uint8_t uart_index:4; - uint8_t altfn_index:4; - const mcu_pin_obj_t * pin; -} mcu_uart_tx_obj_t; - -typedef struct { - uint8_t uart_index:4; - uint8_t altfn_index:4; - const mcu_pin_obj_t * pin; -} mcu_uart_rx_obj_t; - -#define UART(index, alt, uart_pin) \ -{ \ - .uart_index = index, \ - .altfn_index = alt, \ - .pin = uart_pin, \ -} - -//Timers -typedef struct { - uint8_t tim_index:4; - uint8_t altfn_index:4; - uint8_t channel_index:4; - const mcu_pin_obj_t * pin; -} mcu_tim_pin_obj_t; - -#define TIM(index, alt, channel, tim_pin) \ -{ \ - .tim_index = index, \ - .altfn_index = alt, \ - .channel_index = channel, \ - .pin = tim_pin, \ -} - -//Access Lines - -#ifdef STM32F401xE -#define HAS_DAC 0 -#define HAS_TRNG 0 -#define HAS_BASIC_TIM 0 -#include "stm32f401xe/periph.h" -#endif - -#ifdef STM32F411xE -#define HAS_DAC 0 -#define HAS_TRNG 0 -#define HAS_BASIC_TIM 0 -#include "stm32f411xe/periph.h" -#endif - -#ifdef STM32F412Zx -#define HAS_DAC 0 -#define HAS_TRNG 1 -#define HAS_BASIC_TIM 1 -#include "stm32f412zx/periph.h" -#endif - -//Foundation Lines - -#ifdef STM32F405xx -#define HAS_DAC 1 -#define HAS_TRNG 1 -#define HAS_BASIC_TIM 1 -#include "stm32f405xx/periph.h" -#endif - -#ifdef STM32F407xx -#define HAS_DAC 1 -#define HAS_TRNG 1 -#define HAS_BASIC_TIM 1 -#include "stm32f407xx/periph.h" -#endif - -#endif // __MICROPY_INCLUDED_STM32F4_PERIPHERALS_PERIPH_H__ diff --git a/ports/stm/peripherals/stm32f4/stm32f401xe/clocks.c b/ports/stm/peripherals/stm32f4/stm32f401xe/clocks.c index 53810af26380b..d048d60e85f69 100644 --- a/ports/stm/peripherals/stm32f4/stm32f401xe/clocks.c +++ b/ports/stm/peripherals/stm32f4/stm32f401xe/clocks.c @@ -24,10 +24,10 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ -#include "stm32f4xx_hal.h" + #include "py/mpconfig.h" -void stm32f4_peripherals_clocks_init(void) { +void stm32_peripherals_clocks_init(void) { //System clock init RCC_ClkInitTypeDef RCC_ClkInitStruct; RCC_OscInitTypeDef RCC_OscInitStruct; diff --git a/ports/stm/peripherals/stm32f4/stm32f401xe/gpio.c b/ports/stm/peripherals/stm32f4/stm32f401xe/gpio.c index 7bd61966270e2..514bcc506e228 100644 --- a/ports/stm/peripherals/stm32f4/stm32f401xe/gpio.c +++ b/ports/stm/peripherals/stm32f4/stm32f401xe/gpio.c @@ -24,11 +24,10 @@ * THE SOFTWARE. */ -#include "stm32f4xx_hal.h" -#include "stm32f4/gpio.h" +#include "gpio.h" #include "common-hal/microcontroller/Pin.h" -void stm32f4_peripherals_gpio_init(void) { +void stm32_peripherals_gpio_init(void) { /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); @@ -44,8 +43,3 @@ void stm32f4_peripherals_gpio_init(void) { never_reset_pin_number(0,14); //PA14 SWCLK } -//LEDs are inverted on F411 DISCO -void stm32f4_peripherals_status_led(uint8_t led, uint8_t state) { -} - - diff --git a/ports/stm/peripherals/stm32f4/stm32f401xe/periph.c b/ports/stm/peripherals/stm32f4/stm32f401xe/periph.c index b1208418609b0..868945ecc3012 100644 --- a/ports/stm/peripherals/stm32f4/stm32f401xe/periph.c +++ b/ports/stm/peripherals/stm32f4/stm32f401xe/periph.c @@ -26,98 +26,98 @@ #include "py/obj.h" #include "py/mphal.h" -#include "stm32f4/pins.h" -#include "stm32f4/periph.h" +#include "peripherals/pins.h" +#include "peripherals/periph.h" // I2C I2C_TypeDef * mcu_i2c_banks[3] = {I2C1, I2C2, I2C3}; -const mcu_i2c_sda_obj_t mcu_i2c_sda_list[5] = { - I2C_SDA(1, 4, &pin_PB07), - I2C_SDA(1, 4, &pin_PB09), - I2C_SDA(2, 9, &pin_PB03), - I2C_SDA(3, 4, &pin_PC09), - I2C_SDA(3, 9, &pin_PB04), +const mcu_periph_obj_t mcu_i2c_sda_list[5] = { + PERIPH(1, 4, &pin_PB07), + PERIPH(1, 4, &pin_PB09), + PERIPH(2, 9, &pin_PB03), + PERIPH(3, 4, &pin_PC09), + PERIPH(3, 9, &pin_PB04), }; -const mcu_i2c_scl_obj_t mcu_i2c_scl_list[4] = { - I2C_SCL(1, 4, &pin_PB06), - I2C_SCL(1, 4, &pin_PB08), - I2C_SCL(2, 4, &pin_PB10), - I2C_SCL(3, 4, &pin_PA08) +const mcu_periph_obj_t mcu_i2c_scl_list[4] = { + PERIPH(1, 4, &pin_PB06), + PERIPH(1, 4, &pin_PB08), + PERIPH(2, 4, &pin_PB10), + PERIPH(3, 4, &pin_PA08) }; // SPI SPI_TypeDef * mcu_spi_banks[4] = {SPI1, SPI2, SPI3, SPI4}; -const mcu_spi_sck_obj_t mcu_spi_sck_list[9] = { - SPI(1, 5, &pin_PA05), - SPI(1, 5, &pin_PB03), - SPI(2, 5, &pin_PB10), - SPI(2, 5, &pin_PB13), - SPI(2, 5, &pin_PD03), - SPI(3, 6, &pin_PB03), - SPI(3, 6, &pin_PC10), - SPI(4, 5, &pin_PE02), - SPI(4, 5, &pin_PE12), +const mcu_periph_obj_t mcu_spi_sck_list[9] = { + PERIPH(1, 5, &pin_PA05), + PERIPH(1, 5, &pin_PB03), + PERIPH(2, 5, &pin_PB10), + PERIPH(2, 5, &pin_PB13), + PERIPH(2, 5, &pin_PD03), + PERIPH(3, 6, &pin_PB03), + PERIPH(3, 6, &pin_PC10), + PERIPH(4, 5, &pin_PE02), + PERIPH(4, 5, &pin_PE12), }; -const mcu_spi_mosi_obj_t mcu_spi_mosi_list[9] = { - SPI(1, 5, &pin_PA07), - SPI(1, 5, &pin_PB05), - SPI(2, 5, &pin_PB15), - SPI(2, 5, &pin_PC03), - SPI(3, 6, &pin_PB05), - SPI(3, 6, &pin_PC12), - SPI(3, 5, &pin_PD06), - SPI(4, 5, &pin_PE06), - SPI(4, 5, &pin_PE14), +const mcu_periph_obj_t mcu_spi_mosi_list[9] = { + PERIPH(1, 5, &pin_PA07), + PERIPH(1, 5, &pin_PB05), + PERIPH(2, 5, &pin_PB15), + PERIPH(2, 5, &pin_PC03), + PERIPH(3, 6, &pin_PB05), + PERIPH(3, 6, &pin_PC12), + PERIPH(3, 5, &pin_PD06), + PERIPH(4, 5, &pin_PE06), + PERIPH(4, 5, &pin_PE14), }; -const mcu_spi_miso_obj_t mcu_spi_miso_list[8] = { - SPI(1, 5, &pin_PA06), - SPI(1, 5, &pin_PB04), - SPI(2, 5, &pin_PB14), - SPI(2, 5, &pin_PC02), - SPI(3, 6, &pin_PB04), - SPI(3, 6, &pin_PC11), - SPI(4, 5, &pin_PE05), - SPI(4, 5, &pin_PE13), +const mcu_periph_obj_t mcu_spi_miso_list[8] = { + PERIPH(1, 5, &pin_PA06), + PERIPH(1, 5, &pin_PB04), + PERIPH(2, 5, &pin_PB14), + PERIPH(2, 5, &pin_PC02), + PERIPH(3, 6, &pin_PB04), + PERIPH(3, 6, &pin_PC11), + PERIPH(4, 5, &pin_PE05), + PERIPH(4, 5, &pin_PE13), }; -const mcu_spi_nss_obj_t mcu_spi_nss_list[9] = { - SPI(1, 5, &pin_PA04), - SPI(1, 5, &pin_PA15), - SPI(2, 5, &pin_PB09), - SPI(2, 5, &pin_PB12), - SPI(3, 6, &pin_PA04), - SPI(3, 6, &pin_PA15), - SPI(4, 6, &pin_PB12), - SPI(4, 5, &pin_PE04), - SPI(4, 5, &pin_PE11), +const mcu_periph_obj_t mcu_spi_nss_list[9] = { + PERIPH(1, 5, &pin_PA04), + PERIPH(1, 5, &pin_PA15), + PERIPH(2, 5, &pin_PB09), + PERIPH(2, 5, &pin_PB12), + PERIPH(3, 6, &pin_PA04), + PERIPH(3, 6, &pin_PA15), + PERIPH(4, 6, &pin_PB12), + PERIPH(4, 5, &pin_PE04), + PERIPH(4, 5, &pin_PE11), }; USART_TypeDef * mcu_uart_banks[MAX_UART] = {USART1, USART2, NULL, NULL, NULL, USART6}; bool mcu_uart_has_usart[MAX_UART] = {true, true, false, false, false, true}; -const mcu_uart_tx_obj_t mcu_uart_tx_list[6] = { - UART(2, 7, &pin_PA02), - UART(1, 7, &pin_PA09), - UART(6, 8, &pin_PA11), - UART(1, 7, &pin_PB06), - UART(6, 8, &pin_PC06), - UART(2, 7, &pin_PD05), +const mcu_periph_obj_t mcu_uart_tx_list[6] = { + PERIPH(2, 7, &pin_PA02), + PERIPH(1, 7, &pin_PA09), + PERIPH(6, 8, &pin_PA11), + PERIPH(1, 7, &pin_PB06), + PERIPH(6, 8, &pin_PC06), + PERIPH(2, 7, &pin_PD05), }; -const mcu_uart_rx_obj_t mcu_uart_rx_list[6] = { - UART(2, 7, &pin_PA03), - UART(1, 7, &pin_PA10), - UART(6, 8, &pin_PA12), - UART(1, 7, &pin_PB07), - UART(6, 8, &pin_PC07), - UART(2, 7, &pin_PD06), +const mcu_periph_obj_t mcu_uart_rx_list[6] = { + PERIPH(2, 7, &pin_PA03), + PERIPH(1, 7, &pin_PA10), + PERIPH(6, 8, &pin_PA12), + PERIPH(1, 7, &pin_PB07), + PERIPH(6, 8, &pin_PC07), + PERIPH(2, 7, &pin_PD06), }; //Timers diff --git a/ports/stm/peripherals/stm32f4/stm32f401xe/periph.h b/ports/stm/peripherals/stm32f4/stm32f401xe/periph.h index 6085f1ff2b571..334a14db57d51 100644 --- a/ports/stm/peripherals/stm32f4/stm32f401xe/periph.h +++ b/ports/stm/peripherals/stm32f4/stm32f401xe/periph.h @@ -24,29 +24,29 @@ * THE SOFTWARE. */ -#ifndef MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F401XE_PERIPH_H -#define MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F401XE_PERIPH_H +#ifndef MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F401XE_PERIPH_H +#define MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F401XE_PERIPH_H //I2C extern I2C_TypeDef * mcu_i2c_banks[3]; -extern const mcu_i2c_sda_obj_t mcu_i2c_sda_list[5]; -extern const mcu_i2c_scl_obj_t mcu_i2c_scl_list[4]; +extern const mcu_periph_obj_t mcu_i2c_sda_list[5]; +extern const mcu_periph_obj_t mcu_i2c_scl_list[4]; //SPI extern SPI_TypeDef * mcu_spi_banks[4]; -extern const mcu_spi_sck_obj_t mcu_spi_sck_list[9]; -extern const mcu_spi_mosi_obj_t mcu_spi_mosi_list[9]; -extern const mcu_spi_miso_obj_t mcu_spi_miso_list[8]; -extern const mcu_spi_nss_obj_t mcu_spi_nss_list[9]; +extern const mcu_periph_obj_t mcu_spi_sck_list[9]; +extern const mcu_periph_obj_t mcu_spi_mosi_list[9]; +extern const mcu_periph_obj_t mcu_spi_miso_list[8]; +extern const mcu_periph_obj_t mcu_spi_nss_list[9]; //UART extern USART_TypeDef * mcu_uart_banks[MAX_UART]; extern bool mcu_uart_has_usart[MAX_UART]; -extern const mcu_uart_tx_obj_t mcu_uart_tx_list[6]; -extern const mcu_uart_rx_obj_t mcu_uart_rx_list[6]; +extern const mcu_periph_obj_t mcu_uart_tx_list[6]; +extern const mcu_periph_obj_t mcu_uart_rx_list[6]; //Timers #define TIM_BANK_ARRAY_LEN 14 @@ -54,4 +54,4 @@ extern const mcu_uart_rx_obj_t mcu_uart_rx_list[6]; TIM_TypeDef * mcu_tim_banks[TIM_BANK_ARRAY_LEN]; const mcu_tim_pin_obj_t mcu_tim_pin_list[TIM_PIN_ARRAY_LEN]; -#endif // MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F401XE_PERIPH_H \ No newline at end of file +#endif // MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F401XE_PERIPH_H \ No newline at end of file diff --git a/ports/stm/peripherals/stm32f4/stm32f401xe/pins.c b/ports/stm/peripherals/stm32f4/stm32f401xe/pins.c index 7e88c3dcbab8e..eea2a1a1b3a96 100644 --- a/ports/stm/peripherals/stm32f4/stm32f401xe/pins.c +++ b/ports/stm/peripherals/stm32f4/stm32f401xe/pins.c @@ -26,7 +26,7 @@ #include "py/obj.h" #include "py/mphal.h" -#include "stm32f4/pins.h" +#include "peripherals/pins.h" const mcu_pin_obj_t pin_PE02 = PIN(4, 2, NO_ADC); const mcu_pin_obj_t pin_PE03 = PIN(4, 3, NO_ADC); diff --git a/ports/stm/peripherals/stm32f4/stm32f401xe/pins.h b/ports/stm/peripherals/stm32f4/stm32f401xe/pins.h index 09bc8f13e3861..c836df69a23a4 100644 --- a/ports/stm/peripherals/stm32f4/stm32f401xe/pins.h +++ b/ports/stm/peripherals/stm32f4/stm32f401xe/pins.h @@ -24,8 +24,8 @@ * THE SOFTWARE. */ -#ifndef MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F401XE_PINS_H -#define MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F401XE_PINS_H +#ifndef MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F401XE_PINS_H +#define MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F401XE_PINS_H //Pins in datasheet order: DocID026289 Rev 7 page 38. LQFP100 only //pg 38 @@ -118,4 +118,4 @@ extern const mcu_pin_obj_t pin_PE00; extern const mcu_pin_obj_t pin_PE01; -#endif // MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F401XE_PINS_H +#endif // MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F401XE_PINS_H diff --git a/ports/stm/peripherals/stm32f4/stm32f405xx/clocks.c b/ports/stm/peripherals/stm32f4/stm32f405xx/clocks.c index 2afca64e831b5..5f4fd2783d549 100644 --- a/ports/stm/peripherals/stm32f4/stm32f405xx/clocks.c +++ b/ports/stm/peripherals/stm32f4/stm32f405xx/clocks.c @@ -24,12 +24,10 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ -#include "stm32f4xx_hal.h" -#include "py/mpconfig.h" -void stm32f4_peripherals_clocks_init(void) { - //TODO: All parameters must be moved to board level, due to relationship with HSE Osc. +#include "py/mpconfig.h" +void stm32_peripherals_clocks_init(void) { //System clock init RCC_ClkInitTypeDef RCC_ClkInitStruct; RCC_OscInitTypeDef RCC_OscInitStruct; diff --git a/ports/stm/peripherals/stm32f4/stm32f405xx/gpio.c b/ports/stm/peripherals/stm32f4/stm32f405xx/gpio.c index d1eaa90d1b193..a5f4eae78ce3d 100644 --- a/ports/stm/peripherals/stm32f4/stm32f405xx/gpio.c +++ b/ports/stm/peripherals/stm32f4/stm32f405xx/gpio.c @@ -24,11 +24,10 @@ * THE SOFTWARE. */ -#include "stm32f4xx_hal.h" -#include "stm32f4/gpio.h" +#include "peripherals/gpio.h" #include "common-hal/microcontroller/Pin.h" -void stm32f4_peripherals_gpio_init(void) { +void stm32_peripherals_gpio_init(void) { //Enable all GPIO for now __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); diff --git a/ports/stm/peripherals/stm32f4/stm32f405xx/periph.c b/ports/stm/peripherals/stm32f4/stm32f405xx/periph.c index bc03f7c7bebd2..e75f0b20623b2 100644 --- a/ports/stm/peripherals/stm32f4/stm32f405xx/periph.c +++ b/ports/stm/peripherals/stm32f4/stm32f405xx/periph.c @@ -26,97 +26,97 @@ #include "py/obj.h" #include "py/mphal.h" -#include "stm32f4/pins.h" -#include "stm32f4/periph.h" +#include "peripherals/pins.h" +#include "peripherals/periph.h" // I2C I2C_TypeDef * mcu_i2c_banks[3] = {I2C1, I2C2, I2C3}; -const mcu_i2c_sda_obj_t mcu_i2c_sda_list[4] = { - I2C_SDA(1, 4, &pin_PB07), - I2C_SDA(1, 4, &pin_PB09), - I2C_SDA(2, 4, &pin_PB11), - I2C_SDA(3, 4, &pin_PC09), +const mcu_periph_obj_t mcu_i2c_sda_list[4] = { + PERIPH(1, 4, &pin_PB07), + PERIPH(1, 4, &pin_PB09), + PERIPH(2, 4, &pin_PB11), + PERIPH(3, 4, &pin_PC09), }; -const mcu_i2c_scl_obj_t mcu_i2c_scl_list[4] = { - I2C_SCL(1, 4, &pin_PB06), - I2C_SCL(1, 4, &pin_PB08), - I2C_SCL(2, 4, &pin_PB10), - I2C_SCL(3, 4, &pin_PA08) +const mcu_periph_obj_t mcu_i2c_scl_list[4] = { + PERIPH(1, 4, &pin_PB06), + PERIPH(1, 4, &pin_PB08), + PERIPH(2, 4, &pin_PB10), + PERIPH(3, 4, &pin_PA08) }; SPI_TypeDef * mcu_spi_banks[3] = {SPI1, SPI2, SPI3}; -const mcu_spi_sck_obj_t mcu_spi_sck_list[7] = { - SPI(1, 5, &pin_PA05), - SPI(1, 5, &pin_PB03), - SPI(2, 5, &pin_PB10), - SPI(2, 5, &pin_PB13), - SPI(2, 5, &pin_PC07), - SPI(3, 6, &pin_PB03), - SPI(3, 6, &pin_PC10), +const mcu_periph_obj_t mcu_spi_sck_list[7] = { + PERIPH(1, 5, &pin_PA05), + PERIPH(1, 5, &pin_PB03), + PERIPH(2, 5, &pin_PB10), + PERIPH(2, 5, &pin_PB13), + PERIPH(2, 5, &pin_PC07), + PERIPH(3, 6, &pin_PB03), + PERIPH(3, 6, &pin_PC10), }; -const mcu_spi_mosi_obj_t mcu_spi_mosi_list[6] = { - SPI(1, 5, &pin_PA07), - SPI(1, 5, &pin_PB05), - SPI(2, 5, &pin_PB15), - SPI(2, 5, &pin_PC03), - SPI(3, 6, &pin_PB05), - SPI(3, 6, &pin_PC12), +const mcu_periph_obj_t mcu_spi_mosi_list[6] = { + PERIPH(1, 5, &pin_PA07), + PERIPH(1, 5, &pin_PB05), + PERIPH(2, 5, &pin_PB15), + PERIPH(2, 5, &pin_PC03), + PERIPH(3, 6, &pin_PB05), + PERIPH(3, 6, &pin_PC12), }; -const mcu_spi_miso_obj_t mcu_spi_miso_list[6] = { - SPI(1, 5, &pin_PA06), - SPI(1, 5, &pin_PB04), - SPI(2, 5, &pin_PB14), - SPI(2, 5, &pin_PC02), - SPI(3, 6, &pin_PB04), - SPI(3, 6, &pin_PC11), +const mcu_periph_obj_t mcu_spi_miso_list[6] = { + PERIPH(1, 5, &pin_PA06), + PERIPH(1, 5, &pin_PB04), + PERIPH(2, 5, &pin_PB14), + PERIPH(2, 5, &pin_PC02), + PERIPH(3, 6, &pin_PB04), + PERIPH(3, 6, &pin_PC11), }; -const mcu_spi_nss_obj_t mcu_spi_nss_list[6] = { - SPI(1, 5, &pin_PA04), - SPI(1, 5, &pin_PA15), - SPI(2, 5, &pin_PB09), - SPI(2, 5, &pin_PB12), - SPI(3, 6, &pin_PA04), - SPI(3, 6, &pin_PA15), +const mcu_periph_obj_t mcu_spi_nss_list[6] = { + PERIPH(1, 5, &pin_PA04), + PERIPH(1, 5, &pin_PA15), + PERIPH(2, 5, &pin_PB09), + PERIPH(2, 5, &pin_PB12), + PERIPH(3, 6, &pin_PA04), + PERIPH(3, 6, &pin_PA15), }; USART_TypeDef * mcu_uart_banks[MAX_UART] = {USART1, USART2, USART3, UART4, UART5, USART6}; bool mcu_uart_has_usart[MAX_UART] = {true, true, true, false, false, true}; -const mcu_uart_tx_obj_t mcu_uart_tx_list[12] = { - UART(4, 8, &pin_PA00), - UART(2, 7, &pin_PA02), - UART(1, 7, &pin_PA09), - UART(1, 7, &pin_PB06), - UART(3, 7, &pin_PB10), - UART(6, 8, &pin_PC06), - UART(3, 7, &pin_PC10), - UART(4, 8, &pin_PC10), - UART(5, 8, &pin_PC12), - UART(2, 7, &pin_PD05), - UART(3, 7, &pin_PD08), - UART(6, 8, &pin_PG14), +const mcu_periph_obj_t mcu_uart_tx_list[12] = { + PERIPH(4, 8, &pin_PA00), + PERIPH(2, 7, &pin_PA02), + PERIPH(1, 7, &pin_PA09), + PERIPH(1, 7, &pin_PB06), + PERIPH(3, 7, &pin_PB10), + PERIPH(6, 8, &pin_PC06), + PERIPH(3, 7, &pin_PC10), + PERIPH(4, 8, &pin_PC10), + PERIPH(5, 8, &pin_PC12), + PERIPH(2, 7, &pin_PD05), + PERIPH(3, 7, &pin_PD08), + PERIPH(6, 8, &pin_PG14), }; -const mcu_uart_rx_obj_t mcu_uart_rx_list[12] = { - UART(4, 8, &pin_PA01), - UART(2, 7, &pin_PA03), - UART(1, 7, &pin_PA10), - UART(1, 7, &pin_PB07), - UART(3, 7, &pin_PB11), - UART(6, 8, &pin_PC07), - UART(3, 7, &pin_PC11), - UART(4, 8, &pin_PC11), - UART(5, 8, &pin_PD02), - UART(2, 7, &pin_PD06), - UART(3, 7, &pin_PD09), - UART(6, 8, &pin_PG09), +const mcu_periph_obj_t mcu_uart_rx_list[12] = { + PERIPH(4, 8, &pin_PA01), + PERIPH(2, 7, &pin_PA03), + PERIPH(1, 7, &pin_PA10), + PERIPH(1, 7, &pin_PB07), + PERIPH(3, 7, &pin_PB11), + PERIPH(6, 8, &pin_PC07), + PERIPH(3, 7, &pin_PC11), + PERIPH(4, 8, &pin_PC11), + PERIPH(5, 8, &pin_PD02), + PERIPH(2, 7, &pin_PD06), + PERIPH(3, 7, &pin_PD09), + PERIPH(6, 8, &pin_PG09), }; //Timers diff --git a/ports/stm/peripherals/stm32f4/stm32f405xx/periph.h b/ports/stm/peripherals/stm32f4/stm32f405xx/periph.h index e87e798574b93..98b4fab9c2e74 100644 --- a/ports/stm/peripherals/stm32f4/stm32f405xx/periph.h +++ b/ports/stm/peripherals/stm32f4/stm32f405xx/periph.h @@ -24,29 +24,29 @@ * THE SOFTWARE. */ -#ifndef MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F405XX_PERIPH_H -#define MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F405XX_PERIPH_H +#ifndef MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F405XX_PERIPH_H +#define MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F405XX_PERIPH_H //I2C extern I2C_TypeDef * mcu_i2c_banks[3]; -extern const mcu_i2c_sda_obj_t mcu_i2c_sda_list[4]; -extern const mcu_i2c_scl_obj_t mcu_i2c_scl_list[4]; +extern const mcu_periph_obj_t mcu_i2c_sda_list[4]; +extern const mcu_periph_obj_t mcu_i2c_scl_list[4]; //SPI extern SPI_TypeDef * mcu_spi_banks[3]; -extern const mcu_spi_sck_obj_t mcu_spi_sck_list[7]; -extern const mcu_spi_mosi_obj_t mcu_spi_mosi_list[6]; -extern const mcu_spi_miso_obj_t mcu_spi_miso_list[6]; -extern const mcu_spi_nss_obj_t mcu_spi_nss_list[6]; +extern const mcu_periph_obj_t mcu_spi_sck_list[7]; +extern const mcu_periph_obj_t mcu_spi_mosi_list[6]; +extern const mcu_periph_obj_t mcu_spi_miso_list[6]; +extern const mcu_periph_obj_t mcu_spi_nss_list[6]; //UART extern USART_TypeDef * mcu_uart_banks[MAX_UART]; extern bool mcu_uart_has_usart[MAX_UART]; -extern const mcu_uart_tx_obj_t mcu_uart_tx_list[12]; -extern const mcu_uart_rx_obj_t mcu_uart_rx_list[12]; +extern const mcu_periph_obj_t mcu_uart_tx_list[12]; +extern const mcu_periph_obj_t mcu_uart_rx_list[12]; //Timers #define TIM_BANK_ARRAY_LEN 14 @@ -54,4 +54,4 @@ extern const mcu_uart_rx_obj_t mcu_uart_rx_list[12]; TIM_TypeDef * mcu_tim_banks[TIM_BANK_ARRAY_LEN]; const mcu_tim_pin_obj_t mcu_tim_pin_list[TIM_PIN_ARRAY_LEN]; -#endif // MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F405XX_PERIPH_H \ No newline at end of file +#endif // MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F405XX_PERIPH_H \ No newline at end of file diff --git a/ports/stm/peripherals/stm32f4/stm32f405xx/pins.c b/ports/stm/peripherals/stm32f4/stm32f405xx/pins.c index 86445fe140d0d..0f669f1c6c034 100644 --- a/ports/stm/peripherals/stm32f4/stm32f405xx/pins.c +++ b/ports/stm/peripherals/stm32f4/stm32f405xx/pins.c @@ -26,7 +26,7 @@ #include "py/obj.h" #include "py/mphal.h" -#include "stm32f4/pins.h" +#include "peripherals/pins.h" const mcu_pin_obj_t pin_PE02 = PIN(4, 2, NO_ADC); const mcu_pin_obj_t pin_PE03 = PIN(4, 3, NO_ADC); diff --git a/ports/stm/peripherals/stm32f4/stm32f405xx/pins.h b/ports/stm/peripherals/stm32f4/stm32f405xx/pins.h index 180f5c316fa5e..b3e5e3344da9e 100644 --- a/ports/stm/peripherals/stm32f4/stm32f405xx/pins.h +++ b/ports/stm/peripherals/stm32f4/stm32f405xx/pins.h @@ -24,8 +24,8 @@ * THE SOFTWARE. */ -#ifndef MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F412ZG_PINS_H -#define MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F412ZG_PINS_H +#ifndef MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F405XX_PINS_H +#define MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F405XX_PINS_H //Pins in datasheet order: DocID028087 Rev 7 page 50. LQFP100 only //pg 50 @@ -155,4 +155,4 @@ extern const mcu_pin_obj_t pin_PB09; extern const mcu_pin_obj_t pin_PE00; extern const mcu_pin_obj_t pin_PE01; -#endif // MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F412ZG_PINS_H +#endif // MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F405XX_PINS_H diff --git a/ports/stm/peripherals/stm32f4/stm32f407xx/clocks.c b/ports/stm/peripherals/stm32f4/stm32f407xx/clocks.c index 2afca64e831b5..5f4fd2783d549 100644 --- a/ports/stm/peripherals/stm32f4/stm32f407xx/clocks.c +++ b/ports/stm/peripherals/stm32f4/stm32f407xx/clocks.c @@ -24,12 +24,10 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ -#include "stm32f4xx_hal.h" -#include "py/mpconfig.h" -void stm32f4_peripherals_clocks_init(void) { - //TODO: All parameters must be moved to board level, due to relationship with HSE Osc. +#include "py/mpconfig.h" +void stm32_peripherals_clocks_init(void) { //System clock init RCC_ClkInitTypeDef RCC_ClkInitStruct; RCC_OscInitTypeDef RCC_OscInitStruct; diff --git a/ports/stm/peripherals/stm32f4/stm32f407xx/gpio.c b/ports/stm/peripherals/stm32f4/stm32f407xx/gpio.c index d1eaa90d1b193..dfdd61fde4364 100644 --- a/ports/stm/peripherals/stm32f4/stm32f407xx/gpio.c +++ b/ports/stm/peripherals/stm32f4/stm32f407xx/gpio.c @@ -24,8 +24,7 @@ * THE SOFTWARE. */ -#include "stm32f4xx_hal.h" -#include "stm32f4/gpio.h" +#include "peripherals/gpio.h" #include "common-hal/microcontroller/Pin.h" void stm32f4_peripherals_gpio_init(void) { diff --git a/ports/stm/peripherals/stm32f4/stm32f407xx/periph.c b/ports/stm/peripherals/stm32f4/stm32f407xx/periph.c index bc03f7c7bebd2..e75f0b20623b2 100644 --- a/ports/stm/peripherals/stm32f4/stm32f407xx/periph.c +++ b/ports/stm/peripherals/stm32f4/stm32f407xx/periph.c @@ -26,97 +26,97 @@ #include "py/obj.h" #include "py/mphal.h" -#include "stm32f4/pins.h" -#include "stm32f4/periph.h" +#include "peripherals/pins.h" +#include "peripherals/periph.h" // I2C I2C_TypeDef * mcu_i2c_banks[3] = {I2C1, I2C2, I2C3}; -const mcu_i2c_sda_obj_t mcu_i2c_sda_list[4] = { - I2C_SDA(1, 4, &pin_PB07), - I2C_SDA(1, 4, &pin_PB09), - I2C_SDA(2, 4, &pin_PB11), - I2C_SDA(3, 4, &pin_PC09), +const mcu_periph_obj_t mcu_i2c_sda_list[4] = { + PERIPH(1, 4, &pin_PB07), + PERIPH(1, 4, &pin_PB09), + PERIPH(2, 4, &pin_PB11), + PERIPH(3, 4, &pin_PC09), }; -const mcu_i2c_scl_obj_t mcu_i2c_scl_list[4] = { - I2C_SCL(1, 4, &pin_PB06), - I2C_SCL(1, 4, &pin_PB08), - I2C_SCL(2, 4, &pin_PB10), - I2C_SCL(3, 4, &pin_PA08) +const mcu_periph_obj_t mcu_i2c_scl_list[4] = { + PERIPH(1, 4, &pin_PB06), + PERIPH(1, 4, &pin_PB08), + PERIPH(2, 4, &pin_PB10), + PERIPH(3, 4, &pin_PA08) }; SPI_TypeDef * mcu_spi_banks[3] = {SPI1, SPI2, SPI3}; -const mcu_spi_sck_obj_t mcu_spi_sck_list[7] = { - SPI(1, 5, &pin_PA05), - SPI(1, 5, &pin_PB03), - SPI(2, 5, &pin_PB10), - SPI(2, 5, &pin_PB13), - SPI(2, 5, &pin_PC07), - SPI(3, 6, &pin_PB03), - SPI(3, 6, &pin_PC10), +const mcu_periph_obj_t mcu_spi_sck_list[7] = { + PERIPH(1, 5, &pin_PA05), + PERIPH(1, 5, &pin_PB03), + PERIPH(2, 5, &pin_PB10), + PERIPH(2, 5, &pin_PB13), + PERIPH(2, 5, &pin_PC07), + PERIPH(3, 6, &pin_PB03), + PERIPH(3, 6, &pin_PC10), }; -const mcu_spi_mosi_obj_t mcu_spi_mosi_list[6] = { - SPI(1, 5, &pin_PA07), - SPI(1, 5, &pin_PB05), - SPI(2, 5, &pin_PB15), - SPI(2, 5, &pin_PC03), - SPI(3, 6, &pin_PB05), - SPI(3, 6, &pin_PC12), +const mcu_periph_obj_t mcu_spi_mosi_list[6] = { + PERIPH(1, 5, &pin_PA07), + PERIPH(1, 5, &pin_PB05), + PERIPH(2, 5, &pin_PB15), + PERIPH(2, 5, &pin_PC03), + PERIPH(3, 6, &pin_PB05), + PERIPH(3, 6, &pin_PC12), }; -const mcu_spi_miso_obj_t mcu_spi_miso_list[6] = { - SPI(1, 5, &pin_PA06), - SPI(1, 5, &pin_PB04), - SPI(2, 5, &pin_PB14), - SPI(2, 5, &pin_PC02), - SPI(3, 6, &pin_PB04), - SPI(3, 6, &pin_PC11), +const mcu_periph_obj_t mcu_spi_miso_list[6] = { + PERIPH(1, 5, &pin_PA06), + PERIPH(1, 5, &pin_PB04), + PERIPH(2, 5, &pin_PB14), + PERIPH(2, 5, &pin_PC02), + PERIPH(3, 6, &pin_PB04), + PERIPH(3, 6, &pin_PC11), }; -const mcu_spi_nss_obj_t mcu_spi_nss_list[6] = { - SPI(1, 5, &pin_PA04), - SPI(1, 5, &pin_PA15), - SPI(2, 5, &pin_PB09), - SPI(2, 5, &pin_PB12), - SPI(3, 6, &pin_PA04), - SPI(3, 6, &pin_PA15), +const mcu_periph_obj_t mcu_spi_nss_list[6] = { + PERIPH(1, 5, &pin_PA04), + PERIPH(1, 5, &pin_PA15), + PERIPH(2, 5, &pin_PB09), + PERIPH(2, 5, &pin_PB12), + PERIPH(3, 6, &pin_PA04), + PERIPH(3, 6, &pin_PA15), }; USART_TypeDef * mcu_uart_banks[MAX_UART] = {USART1, USART2, USART3, UART4, UART5, USART6}; bool mcu_uart_has_usart[MAX_UART] = {true, true, true, false, false, true}; -const mcu_uart_tx_obj_t mcu_uart_tx_list[12] = { - UART(4, 8, &pin_PA00), - UART(2, 7, &pin_PA02), - UART(1, 7, &pin_PA09), - UART(1, 7, &pin_PB06), - UART(3, 7, &pin_PB10), - UART(6, 8, &pin_PC06), - UART(3, 7, &pin_PC10), - UART(4, 8, &pin_PC10), - UART(5, 8, &pin_PC12), - UART(2, 7, &pin_PD05), - UART(3, 7, &pin_PD08), - UART(6, 8, &pin_PG14), +const mcu_periph_obj_t mcu_uart_tx_list[12] = { + PERIPH(4, 8, &pin_PA00), + PERIPH(2, 7, &pin_PA02), + PERIPH(1, 7, &pin_PA09), + PERIPH(1, 7, &pin_PB06), + PERIPH(3, 7, &pin_PB10), + PERIPH(6, 8, &pin_PC06), + PERIPH(3, 7, &pin_PC10), + PERIPH(4, 8, &pin_PC10), + PERIPH(5, 8, &pin_PC12), + PERIPH(2, 7, &pin_PD05), + PERIPH(3, 7, &pin_PD08), + PERIPH(6, 8, &pin_PG14), }; -const mcu_uart_rx_obj_t mcu_uart_rx_list[12] = { - UART(4, 8, &pin_PA01), - UART(2, 7, &pin_PA03), - UART(1, 7, &pin_PA10), - UART(1, 7, &pin_PB07), - UART(3, 7, &pin_PB11), - UART(6, 8, &pin_PC07), - UART(3, 7, &pin_PC11), - UART(4, 8, &pin_PC11), - UART(5, 8, &pin_PD02), - UART(2, 7, &pin_PD06), - UART(3, 7, &pin_PD09), - UART(6, 8, &pin_PG09), +const mcu_periph_obj_t mcu_uart_rx_list[12] = { + PERIPH(4, 8, &pin_PA01), + PERIPH(2, 7, &pin_PA03), + PERIPH(1, 7, &pin_PA10), + PERIPH(1, 7, &pin_PB07), + PERIPH(3, 7, &pin_PB11), + PERIPH(6, 8, &pin_PC07), + PERIPH(3, 7, &pin_PC11), + PERIPH(4, 8, &pin_PC11), + PERIPH(5, 8, &pin_PD02), + PERIPH(2, 7, &pin_PD06), + PERIPH(3, 7, &pin_PD09), + PERIPH(6, 8, &pin_PG09), }; //Timers diff --git a/ports/stm/peripherals/stm32f4/stm32f407xx/periph.h b/ports/stm/peripherals/stm32f4/stm32f407xx/periph.h index e87e798574b93..15cbfb16d29f3 100644 --- a/ports/stm/peripherals/stm32f4/stm32f407xx/periph.h +++ b/ports/stm/peripherals/stm32f4/stm32f407xx/periph.h @@ -24,29 +24,29 @@ * THE SOFTWARE. */ -#ifndef MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F405XX_PERIPH_H -#define MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F405XX_PERIPH_H +#ifndef MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F407XX_PERIPH_H +#define MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F407XX_PERIPH_H //I2C extern I2C_TypeDef * mcu_i2c_banks[3]; -extern const mcu_i2c_sda_obj_t mcu_i2c_sda_list[4]; -extern const mcu_i2c_scl_obj_t mcu_i2c_scl_list[4]; +extern const mcu_periph_obj_t mcu_i2c_sda_list[4]; +extern const mcu_periph_obj_t mcu_i2c_scl_list[4]; //SPI extern SPI_TypeDef * mcu_spi_banks[3]; -extern const mcu_spi_sck_obj_t mcu_spi_sck_list[7]; -extern const mcu_spi_mosi_obj_t mcu_spi_mosi_list[6]; -extern const mcu_spi_miso_obj_t mcu_spi_miso_list[6]; -extern const mcu_spi_nss_obj_t mcu_spi_nss_list[6]; +extern const mcu_periph_obj_t mcu_spi_sck_list[7]; +extern const mcu_periph_obj_t mcu_spi_mosi_list[6]; +extern const mcu_periph_obj_t mcu_spi_miso_list[6]; +extern const mcu_periph_obj_t mcu_spi_nss_list[6]; //UART extern USART_TypeDef * mcu_uart_banks[MAX_UART]; extern bool mcu_uart_has_usart[MAX_UART]; -extern const mcu_uart_tx_obj_t mcu_uart_tx_list[12]; -extern const mcu_uart_rx_obj_t mcu_uart_rx_list[12]; +extern const mcu_periph_obj_t mcu_uart_tx_list[12]; +extern const mcu_periph_obj_t mcu_uart_rx_list[12]; //Timers #define TIM_BANK_ARRAY_LEN 14 @@ -54,4 +54,4 @@ extern const mcu_uart_rx_obj_t mcu_uart_rx_list[12]; TIM_TypeDef * mcu_tim_banks[TIM_BANK_ARRAY_LEN]; const mcu_tim_pin_obj_t mcu_tim_pin_list[TIM_PIN_ARRAY_LEN]; -#endif // MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F405XX_PERIPH_H \ No newline at end of file +#endif // MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F407XX_PERIPH_H \ No newline at end of file diff --git a/ports/stm/peripherals/stm32f4/stm32f407xx/pins.c b/ports/stm/peripherals/stm32f4/stm32f407xx/pins.c index 86445fe140d0d..0f669f1c6c034 100644 --- a/ports/stm/peripherals/stm32f4/stm32f407xx/pins.c +++ b/ports/stm/peripherals/stm32f4/stm32f407xx/pins.c @@ -26,7 +26,7 @@ #include "py/obj.h" #include "py/mphal.h" -#include "stm32f4/pins.h" +#include "peripherals/pins.h" const mcu_pin_obj_t pin_PE02 = PIN(4, 2, NO_ADC); const mcu_pin_obj_t pin_PE03 = PIN(4, 3, NO_ADC); diff --git a/ports/stm/peripherals/stm32f4/stm32f407xx/pins.h b/ports/stm/peripherals/stm32f4/stm32f407xx/pins.h index 180f5c316fa5e..109dcb92269d6 100644 --- a/ports/stm/peripherals/stm32f4/stm32f407xx/pins.h +++ b/ports/stm/peripherals/stm32f4/stm32f407xx/pins.h @@ -24,8 +24,8 @@ * THE SOFTWARE. */ -#ifndef MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F412ZG_PINS_H -#define MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F412ZG_PINS_H +#ifndef MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F407XX_PINS_H +#define MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F407XX_PINS_H //Pins in datasheet order: DocID028087 Rev 7 page 50. LQFP100 only //pg 50 @@ -155,4 +155,4 @@ extern const mcu_pin_obj_t pin_PB09; extern const mcu_pin_obj_t pin_PE00; extern const mcu_pin_obj_t pin_PE01; -#endif // MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F412ZG_PINS_H +#endif // MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F407XX_PINS_H diff --git a/ports/stm/peripherals/stm32f4/stm32f411xe/clocks.c b/ports/stm/peripherals/stm32f4/stm32f411xe/clocks.c index 53810af26380b..d048d60e85f69 100644 --- a/ports/stm/peripherals/stm32f4/stm32f411xe/clocks.c +++ b/ports/stm/peripherals/stm32f4/stm32f411xe/clocks.c @@ -24,10 +24,10 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ -#include "stm32f4xx_hal.h" + #include "py/mpconfig.h" -void stm32f4_peripherals_clocks_init(void) { +void stm32_peripherals_clocks_init(void) { //System clock init RCC_ClkInitTypeDef RCC_ClkInitStruct; RCC_OscInitTypeDef RCC_OscInitStruct; diff --git a/ports/stm/peripherals/stm32f4/stm32f411xe/gpio.c b/ports/stm/peripherals/stm32f4/stm32f411xe/gpio.c index aee0bd5eb8696..201a90e347a12 100644 --- a/ports/stm/peripherals/stm32f4/stm32f411xe/gpio.c +++ b/ports/stm/peripherals/stm32f4/stm32f411xe/gpio.c @@ -24,12 +24,11 @@ * THE SOFTWARE. */ -#include "stm32f4xx_hal.h" -#include "stm32f4/gpio.h" +#include "peripherals/gpio.h" #include "py/mpconfig.h" #include "common-hal/microcontroller/Pin.h" -void stm32f4_peripherals_gpio_init(void) { +void stm32_peripherals_gpio_init(void) { //* GPIO Ports Clock Enable */ __HAL_RCC_GPIOE_CLK_ENABLE(); __HAL_RCC_GPIOC_CLK_ENABLE(); diff --git a/ports/stm/peripherals/stm32f4/stm32f411xe/periph.c b/ports/stm/peripherals/stm32f4/stm32f411xe/periph.c index b7d9edf4f7eec..0856637493d92 100644 --- a/ports/stm/peripherals/stm32f4/stm32f411xe/periph.c +++ b/ports/stm/peripherals/stm32f4/stm32f411xe/periph.c @@ -26,120 +26,120 @@ #include "py/obj.h" #include "py/mphal.h" -#include "stm32f4/pins.h" -#include "stm32f4/periph.h" +#include "peripherals/pins.h" +#include "peripherals/periph.h" // I2C I2C_TypeDef * mcu_i2c_banks[3] = {I2C1, I2C2, I2C3}; -const mcu_i2c_sda_obj_t mcu_i2c_sda_list[7] = { - I2C_SDA(1, 4, &pin_PB07), - I2C_SDA(1, 4, &pin_PB09), - I2C_SDA(2, 9, &pin_PB09), - I2C_SDA(2, 9, &pin_PB03), - I2C_SDA(3, 4, &pin_PC09), - I2C_SDA(3, 9, &pin_PB04), - I2C_SDA(3, 9, &pin_PB08) +const mcu_periph_obj_t mcu_i2c_sda_list[7] = { + PERIPH(1, 4, &pin_PB07), + PERIPH(1, 4, &pin_PB09), + PERIPH(2, 9, &pin_PB09), + PERIPH(2, 9, &pin_PB03), + PERIPH(3, 4, &pin_PC09), + PERIPH(3, 9, &pin_PB04), + PERIPH(3, 9, &pin_PB08) }; -const mcu_i2c_scl_obj_t mcu_i2c_scl_list[4] = { - I2C_SCL(1, 4, &pin_PB06), - I2C_SCL(1, 4, &pin_PB08), - I2C_SCL(2, 4, &pin_PB10), - I2C_SCL(3, 4, &pin_PA08) +const mcu_periph_obj_t mcu_i2c_scl_list[4] = { + PERIPH(1, 4, &pin_PB06), + PERIPH(1, 4, &pin_PB08), + PERIPH(2, 4, &pin_PB10), + PERIPH(3, 4, &pin_PA08) }; // SPI SPI_TypeDef * mcu_spi_banks[5] = {SPI1, SPI2, SPI3, SPI4, SPI5}; -const mcu_spi_sck_obj_t mcu_spi_sck_list[15] = { - SPI(1, 5, &pin_PA05), - SPI(1, 5, &pin_PB03), - SPI(2, 5, &pin_PB10), - SPI(2, 5, &pin_PB13), - SPI(2, 5, &pin_PC07), - SPI(2, 5, &pin_PD03), - SPI(3, 6, &pin_PB03), - SPI(3, 7, &pin_PB12), - SPI(3, 6, &pin_PC10), - SPI(4, 6, &pin_PB13), - SPI(4, 5, &pin_PE02), - SPI(4, 5, &pin_PE12), - SPI(5, 6, &pin_PB00), - SPI(5, 6, &pin_PE02), - SPI(5, 6, &pin_PE12) +const mcu_periph_obj_t mcu_spi_sck_list[15] = { + PERIPH(1, 5, &pin_PA05), + PERIPH(1, 5, &pin_PB03), + PERIPH(2, 5, &pin_PB10), + PERIPH(2, 5, &pin_PB13), + PERIPH(2, 5, &pin_PC07), + PERIPH(2, 5, &pin_PD03), + PERIPH(3, 6, &pin_PB03), + PERIPH(3, 7, &pin_PB12), + PERIPH(3, 6, &pin_PC10), + PERIPH(4, 6, &pin_PB13), + PERIPH(4, 5, &pin_PE02), + PERIPH(4, 5, &pin_PE12), + PERIPH(5, 6, &pin_PB00), + PERIPH(5, 6, &pin_PE02), + PERIPH(5, 6, &pin_PE12) }; -const mcu_spi_mosi_obj_t mcu_spi_mosi_list[14] = { - SPI(1, 5, &pin_PA07), - SPI(1, 5, &pin_PB05), - SPI(2, 5, &pin_PB15), - SPI(2, 5, &pin_PC03), - SPI(3, 6, &pin_PB05), - SPI(3, 6, &pin_PC12), - SPI(3, 5, &pin_PD06), - SPI(4, 5, &pin_PA01), - SPI(4, 5, &pin_PE06), - SPI(4, 5, &pin_PE14), - SPI(5, 6, &pin_PA10), - SPI(5, 6, &pin_PB08), - SPI(5, 6, &pin_PE06), - SPI(5, 6, &pin_PE14) +const mcu_periph_obj_t mcu_spi_mosi_list[14] = { + PERIPH(1, 5, &pin_PA07), + PERIPH(1, 5, &pin_PB05), + PERIPH(2, 5, &pin_PB15), + PERIPH(2, 5, &pin_PC03), + PERIPH(3, 6, &pin_PB05), + PERIPH(3, 6, &pin_PC12), + PERIPH(3, 5, &pin_PD06), + PERIPH(4, 5, &pin_PA01), + PERIPH(4, 5, &pin_PE06), + PERIPH(4, 5, &pin_PE14), + PERIPH(5, 6, &pin_PA10), + PERIPH(5, 6, &pin_PB08), + PERIPH(5, 6, &pin_PE06), + PERIPH(5, 6, &pin_PE14) }; -const mcu_spi_miso_obj_t mcu_spi_miso_list[12] = { - SPI(1, 5, &pin_PA06), - SPI(1, 5, &pin_PB04), - SPI(2, 5, &pin_PB14), - SPI(2, 5, &pin_PC02), - SPI(3, 6, &pin_PB04), - SPI(3, 6, &pin_PC11), - SPI(4, 6, &pin_PA11), - SPI(4, 5, &pin_PE05), - SPI(4, 5, &pin_PE13), - SPI(5, 6, &pin_PA12), - SPI(5, 6, &pin_PE05), - SPI(5, 6, &pin_PE13) +const mcu_periph_obj_t mcu_spi_miso_list[12] = { + PERIPH(1, 5, &pin_PA06), + PERIPH(1, 5, &pin_PB04), + PERIPH(2, 5, &pin_PB14), + PERIPH(2, 5, &pin_PC02), + PERIPH(3, 6, &pin_PB04), + PERIPH(3, 6, &pin_PC11), + PERIPH(4, 6, &pin_PA11), + PERIPH(4, 5, &pin_PE05), + PERIPH(4, 5, &pin_PE13), + PERIPH(5, 6, &pin_PA12), + PERIPH(5, 6, &pin_PE05), + PERIPH(5, 6, &pin_PE13) }; -const mcu_spi_nss_obj_t mcu_spi_nss_list[12] = { - SPI(1, 5, &pin_PA04), - SPI(1, 5, &pin_PA15), - SPI(2, 5, &pin_PB09), - SPI(2, 5, &pin_PB12), - SPI(3, 6, &pin_PA04), - SPI(3, 6, &pin_PA15), - SPI(4, 6, &pin_PB12), - SPI(4, 5, &pin_PE04), - SPI(4, 5, &pin_PE11), - SPI(5, 6, &pin_PB01), - SPI(5, 6, &pin_PE04), - SPI(5, 6, &pin_PE11) +const mcu_periph_obj_t mcu_spi_nss_list[12] = { + PERIPH(1, 5, &pin_PA04), + PERIPH(1, 5, &pin_PA15), + PERIPH(2, 5, &pin_PB09), + PERIPH(2, 5, &pin_PB12), + PERIPH(3, 6, &pin_PA04), + PERIPH(3, 6, &pin_PA15), + PERIPH(4, 6, &pin_PB12), + PERIPH(4, 5, &pin_PE04), + PERIPH(4, 5, &pin_PE11), + PERIPH(5, 6, &pin_PB01), + PERIPH(5, 6, &pin_PE04), + PERIPH(5, 6, &pin_PE11) }; USART_TypeDef * mcu_uart_banks[MAX_UART] = {USART1, USART2, NULL, NULL, NULL, USART6}; bool mcu_uart_has_usart[MAX_UART] = {true, true, false, false, false, true}; -const mcu_uart_tx_obj_t mcu_uart_tx_list[7] = { - UART(2, 7, &pin_PA02), - UART(1, 7, &pin_PA09), - UART(1, 7, &pin_PA15), - UART(6, 8, &pin_PA11), - UART(1, 7, &pin_PB06), - UART(6, 8, &pin_PC06), - UART(2, 7, &pin_PD05), +const mcu_periph_obj_t mcu_uart_tx_list[7] = { + PERIPH(2, 7, &pin_PA02), + PERIPH(1, 7, &pin_PA09), + PERIPH(1, 7, &pin_PA15), + PERIPH(6, 8, &pin_PA11), + PERIPH(1, 7, &pin_PB06), + PERIPH(6, 8, &pin_PC06), + PERIPH(2, 7, &pin_PD05), }; -const mcu_uart_rx_obj_t mcu_uart_rx_list[7] = { - UART(2, 7, &pin_PA03), - UART(1, 7, &pin_PA10), - UART(6, 8, &pin_PA12), - UART(1, 7, &pin_PB03), - UART(1, 7, &pin_PB07), - UART(6, 8, &pin_PC07), - UART(2, 7, &pin_PD06), +const mcu_periph_obj_t mcu_uart_rx_list[7] = { + PERIPH(2, 7, &pin_PA03), + PERIPH(1, 7, &pin_PA10), + PERIPH(6, 8, &pin_PA12), + PERIPH(1, 7, &pin_PB03), + PERIPH(1, 7, &pin_PB07), + PERIPH(6, 8, &pin_PC07), + PERIPH(2, 7, &pin_PD06), }; //Timers diff --git a/ports/stm/peripherals/stm32f4/stm32f411xe/periph.h b/ports/stm/peripherals/stm32f4/stm32f411xe/periph.h index d657d73b68475..2c5e5dd56480a 100644 --- a/ports/stm/peripherals/stm32f4/stm32f411xe/periph.h +++ b/ports/stm/peripherals/stm32f4/stm32f411xe/periph.h @@ -24,29 +24,29 @@ * THE SOFTWARE. */ -#ifndef MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F411VE_PERIPH_H -#define MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F411VE_PERIPH_H +#ifndef MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F411XE_PERIPH_H +#define MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F411XE_PERIPH_H //I2C extern I2C_TypeDef * mcu_i2c_banks[3]; -extern const mcu_i2c_sda_obj_t mcu_i2c_sda_list[7]; -extern const mcu_i2c_scl_obj_t mcu_i2c_scl_list[4]; +extern const mcu_periph_obj_t mcu_i2c_sda_list[7]; +extern const mcu_periph_obj_t mcu_i2c_scl_list[4]; //SPI extern SPI_TypeDef * mcu_spi_banks[5]; -extern const mcu_spi_sck_obj_t mcu_spi_sck_list[15]; -extern const mcu_spi_mosi_obj_t mcu_spi_mosi_list[14]; -extern const mcu_spi_miso_obj_t mcu_spi_miso_list[12]; -extern const mcu_spi_nss_obj_t mcu_spi_nss_list[12]; +extern const mcu_periph_obj_t mcu_spi_sck_list[15]; +extern const mcu_periph_obj_t mcu_spi_mosi_list[14]; +extern const mcu_periph_obj_t mcu_spi_miso_list[12]; +extern const mcu_periph_obj_t mcu_spi_nss_list[12]; //UART extern USART_TypeDef * mcu_uart_banks[MAX_UART]; extern bool mcu_uart_has_usart[MAX_UART]; -extern const mcu_uart_tx_obj_t mcu_uart_tx_list[7]; -extern const mcu_uart_rx_obj_t mcu_uart_rx_list[7]; +extern const mcu_periph_obj_t mcu_uart_tx_list[7]; +extern const mcu_periph_obj_t mcu_uart_rx_list[7]; //Timers #define TIM_BANK_ARRAY_LEN 14 @@ -54,4 +54,4 @@ extern const mcu_uart_rx_obj_t mcu_uart_rx_list[7]; TIM_TypeDef * mcu_tim_banks[TIM_BANK_ARRAY_LEN]; const mcu_tim_pin_obj_t mcu_tim_pin_list[TIM_PIN_ARRAY_LEN]; -#endif // MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F411VE_PERIPH_H \ No newline at end of file +#endif // MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F411XE_PERIPH_H \ No newline at end of file diff --git a/ports/stm/peripherals/stm32f4/stm32f411xe/pins.c b/ports/stm/peripherals/stm32f4/stm32f411xe/pins.c index 7e88c3dcbab8e..eea2a1a1b3a96 100644 --- a/ports/stm/peripherals/stm32f4/stm32f411xe/pins.c +++ b/ports/stm/peripherals/stm32f4/stm32f411xe/pins.c @@ -26,7 +26,7 @@ #include "py/obj.h" #include "py/mphal.h" -#include "stm32f4/pins.h" +#include "peripherals/pins.h" const mcu_pin_obj_t pin_PE02 = PIN(4, 2, NO_ADC); const mcu_pin_obj_t pin_PE03 = PIN(4, 3, NO_ADC); diff --git a/ports/stm/peripherals/stm32f4/stm32f411xe/pins.h b/ports/stm/peripherals/stm32f4/stm32f411xe/pins.h index 37d3a5cf11953..b6c18b02e3a86 100644 --- a/ports/stm/peripherals/stm32f4/stm32f411xe/pins.h +++ b/ports/stm/peripherals/stm32f4/stm32f411xe/pins.h @@ -24,8 +24,8 @@ * THE SOFTWARE. */ -#ifndef MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F411VE_PINS_H -#define MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F411VE_PINS_H +#ifndef MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F411XE_PINS_H +#define MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F411XE_PINS_H //Pins in datasheet order: DocID026289 Rev 7 page 38. LQFP100 only //pg 38 diff --git a/ports/stm/peripherals/stm32f4/stm32f412zx/clocks.c b/ports/stm/peripherals/stm32f4/stm32f412zx/clocks.c index b208f9dfb3754..ad45abed226e4 100644 --- a/ports/stm/peripherals/stm32f4/stm32f412zx/clocks.c +++ b/ports/stm/peripherals/stm32f4/stm32f412zx/clocks.c @@ -24,12 +24,12 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ -#include "stm32f4xx_hal.h" + #include "py/mpconfig.h" -void stm32f4_peripherals_clocks_init(void) { +void stm32_peripherals_clocks_init(void) { //System clock init - RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_ClkInitTypeDef RCC_ClkInitStruct; RCC_OscInitTypeDef RCC_OscInitStruct; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; diff --git a/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c b/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c index d17ab4e0181e6..97ec933eabeed 100644 --- a/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c +++ b/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c @@ -24,193 +24,23 @@ * THE SOFTWARE. */ -/* GPIO PIN REFERENCE -#define LED3_Pin GPIO_PIN_2 -#define LED3_GPIO_Port GPIOE -#define LED4_Pin GPIO_PIN_3 -#define LED4_GPIO_Port GPIOE -#define DFSDM_DATIN3_Pin GPIO_PIN_4 -#define DFSDM_DATIN3_GPIO_Port GPIOE -#define A0_Pin GPIO_PIN_0 -#define A0_GPIO_Port GPIOF -#define LCD_BLCTRL_Pin GPIO_PIN_5 -#define LCD_BLCTRL_GPIO_Port GPIOF -#define QSPI_BK1_IO3_Pin GPIO_PIN_6 -#define QSPI_BK1_IO3_GPIO_Port GPIOF -#define QSPI_BK1_IO2_Pin GPIO_PIN_7 -#define QSPI_BK1_IO2_GPIO_Port GPIOF -#define QSPI_BK1_IO0_Pin GPIO_PIN_8 -#define QSPI_BK1_IO0_GPIO_Port GPIOF -#define QSPI_BK1_IO1_Pin GPIO_PIN_9 -#define QSPI_BK1_IO1_GPIO_Port GPIOF -#define STLK_MCO_Pin GPIO_PIN_0 -#define STLK_MCO_GPIO_Port GPIOH -#define DFSDM_CKOUT_Pin GPIO_PIN_2 -#define DFSDM_CKOUT_GPIO_Port GPIOC -#define JOY_SEL_Pin GPIO_PIN_0 -#define JOY_SEL_GPIO_Port GPIOA -#define STLINK_RX_Pin GPIO_PIN_2 -#define STLINK_RX_GPIO_Port GPIOA -#define STLINK_TX_Pin GPIO_PIN_3 -#define STLINK_TX_GPIO_Port GPIOA -#define CODEC_I2S3_WS_Pin GPIO_PIN_4 -#define CODEC_I2S3_WS_GPIO_Port GPIOA -#define DFSDM_DATIN0_Pin GPIO_PIN_1 -#define DFSDM_DATIN0_GPIO_Port GPIOB -#define QSPI_CLK_Pin GPIO_PIN_2 -#define QSPI_CLK_GPIO_Port GPIOB -#define EXT_RESET_Pin GPIO_PIN_11 -#define EXT_RESET_GPIO_Port GPIOF -#define CTP_RST_Pin GPIO_PIN_12 -#define CTP_RST_GPIO_Port GPIOF -#define JOY_RIGHT_Pin GPIO_PIN_14 -#define JOY_RIGHT_GPIO_Port GPIOF -#define JOY_LEFT_Pin GPIO_PIN_15 -#define JOY_LEFT_GPIO_Port GPIOF -#define JOY_UP_Pin GPIO_PIN_0 -#define JOY_UP_GPIO_Port GPIOG -#define JOY_DOWN_Pin GPIO_PIN_1 -#define JOY_DOWN_GPIO_Port GPIOG -#define D4_Pin GPIO_PIN_7 -#define D4_GPIO_Port GPIOE -#define D5_Pin GPIO_PIN_8 -#define D5_GPIO_Port GPIOE -#define D6_Pin GPIO_PIN_9 -#define D6_GPIO_Port GPIOE -#define D7_Pin GPIO_PIN_10 -#define D7_GPIO_Port GPIOE -#define D8_Pin GPIO_PIN_11 -#define D8_GPIO_Port GPIOE -#define D9_Pin GPIO_PIN_12 -#define D9_GPIO_Port GPIOE -#define D10_Pin GPIO_PIN_13 -#define D10_GPIO_Port GPIOE -#define D11_Pin GPIO_PIN_14 -#define D11_GPIO_Port GPIOE -#define D12_Pin GPIO_PIN_15 -#define D12_GPIO_Port GPIOE -#define I2C2_SCL_Pin GPIO_PIN_10 -#define I2C2_SCL_GPIO_Port GPIOB -#define M2_CKIN_Pin GPIO_PIN_11 -#define M2_CKIN_GPIO_Port GPIOB -#define CODEC_I2S3_SCK_Pin GPIO_PIN_12 -#define CODEC_I2S3_SCK_GPIO_Port GPIOB -#define D13_Pin GPIO_PIN_8 -#define D13_GPIO_Port GPIOD -#define D14_Pin GPIO_PIN_9 -#define D14_GPIO_Port GPIOD -#define D15_Pin GPIO_PIN_10 -#define D15_GPIO_Port GPIOD -#define LCD_RESET_Pin GPIO_PIN_11 -#define LCD_RESET_GPIO_Port GPIOD -#define D0_Pin GPIO_PIN_14 -#define D0_GPIO_Port GPIOD -#define D1_Pin GPIO_PIN_15 -#define D1_GPIO_Port GPIOD -#define CODEC_INT_Pin GPIO_PIN_2 -#define CODEC_INT_GPIO_Port GPIOG -#define LCD_TE_Pin GPIO_PIN_4 -#define LCD_TE_GPIO_Port GPIOG -#define CTP_INT_Pin GPIO_PIN_5 -#define CTP_INT_GPIO_Port GPIOG -#define QSPI_BK1_NCS_Pin GPIO_PIN_6 -#define QSPI_BK1_NCS_GPIO_Port GPIOG -#define USB_OTGFS_OVRCR_Pin GPIO_PIN_7 -#define USB_OTGFS_OVRCR_GPIO_Port GPIOG -#define USB_OTGFS_PPWR_EN_Pin GPIO_PIN_8 -#define USB_OTGFS_PPWR_EN_GPIO_Port GPIOG -#define CODEC_I2S3_MCK_Pin GPIO_PIN_7 -#define CODEC_I2S3_MCK_GPIO_Port GPIOC -#define uSD_D0_Pin GPIO_PIN_8 -#define uSD_D0_GPIO_Port GPIOC -#define uSD_D1_Pin GPIO_PIN_9 -#define uSD_D1_GPIO_Port GPIOC -#define M2_CKINA8_Pin GPIO_PIN_8 -#define M2_CKINA8_GPIO_Port GPIOA -#define USB_OTGFS_VBUS_Pin GPIO_PIN_9 -#define USB_OTGFS_VBUS_GPIO_Port GPIOA -#define USB_OTGFS_ID_Pin GPIO_PIN_10 -#define USB_OTGFS_ID_GPIO_Port GPIOA -#define USB_OTGFS_DM_Pin GPIO_PIN_11 -#define USB_OTGFS_DM_GPIO_Port GPIOA -#define USB_OTGFS_DP_Pin GPIO_PIN_12 -#define USB_OTGFS_DP_GPIO_Port GPIOA -#define SWDIO_Pin GPIO_PIN_13 -#define SWDIO_GPIO_Port GPIOA -#define SWCLK_Pin GPIO_PIN_14 -#define SWCLK_GPIO_Port GPIOA -#define uSD_D2_Pin GPIO_PIN_10 -#define uSD_D2_GPIO_Port GPIOC -#define uSD_D3_Pin GPIO_PIN_11 -#define uSD_D3_GPIO_Port GPIOC -#define uSD_CLK_Pin GPIO_PIN_12 -#define uSD_CLK_GPIO_Port GPIOC -#define D2_Pin GPIO_PIN_0 -#define D2_GPIO_Port GPIOD -#define D3_Pin GPIO_PIN_1 -#define D3_GPIO_Port GPIOD -#define uSD_CMD_Pin GPIO_PIN_2 -#define uSD_CMD_GPIO_Port GPIOD -#define uSD_DETECT_Pin GPIO_PIN_3 -#define uSD_DETECT_GPIO_Port GPIOD -#define FMC_NOE_Pin GPIO_PIN_4 -#define FMC_NOE_GPIO_Port GPIOD -#define FMC_NWE_Pin GPIO_PIN_5 -#define FMC_NWE_GPIO_Port GPIOD -#define FMC_NE1_Pin GPIO_PIN_7 -#define FMC_NE1_GPIO_Port GPIOD -#define SWO_Pin GPIO_PIN_3 -#define SWO_GPIO_Port GPIOB -#define CODEC_I2S3ext_SD_Pin GPIO_PIN_4 -#define CODEC_I2S3ext_SD_GPIO_Port GPIOB -#define CODEC_I2S3_SD_Pin GPIO_PIN_5 -#define CODEC_I2S3_SD_GPIO_Port GPIOB -#define I2C1_SCL_Pin GPIO_PIN_6 -#define I2C1_SCL_GPIO_Port GPIOB -#define I2C1_SDA_Pin GPIO_PIN_7 -#define I2C1_SDA_GPIO_Port GPIOB -#define I2C2_SDA_Pin GPIO_PIN_9 -#define I2C2_SDA_GPIO_Port GPIOB -#define LED1_Pin GPIO_PIN_0 -#define LED1_GPIO_Port GPIOE -#define LED2_Pin GPIO_PIN_1 -#define LED2_GPIO_Port GPIOE -*/ - -#include "stm32f4xx_hal.h" -#include "stm32f4/gpio.h" +#include "peripherals/gpio.h" #include "common-hal/microcontroller/Pin.h" -void stm32f4_peripherals_gpio_init(void) { - //Enable all GPIO for now - GPIO_InitTypeDef GPIO_InitStruct = {0}; - __HAL_RCC_GPIOE_CLK_ENABLE(); - __HAL_RCC_GPIOC_CLK_ENABLE(); - __HAL_RCC_GPIOF_CLK_ENABLE(); - __HAL_RCC_GPIOH_CLK_ENABLE(); - __HAL_RCC_GPIOA_CLK_ENABLE(); - __HAL_RCC_GPIOB_CLK_ENABLE(); - __HAL_RCC_GPIOG_CLK_ENABLE(); - __HAL_RCC_GPIOD_CLK_ENABLE(); - - HAL_GPIO_WritePin(GPIOE, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3, GPIO_PIN_RESET); - //HAL_GPIO_WritePin(USB_OTGFS_PPWR_EN_GPIO_Port, USB_OTGFS_PPWR_EN_Pin, GPIO_PIN_SET); +void stm32_peripherals_gpio_init(void) { - //Configure LED pins - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + GPIO_InitTypeDef GPIO_InitStruct = {0}; + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); - //Status LED chain - stm32f4_peripherals_status_led(0,1); - stm32f4_peripherals_status_led(1,0); - stm32f4_peripherals_status_led(2,0); - stm32f4_peripherals_status_led(3,0); - - //Never reset pins - never_reset_pin_number(2,13); //PC13 anti tamp + //Never reset pins + never_reset_pin_number(2,13); //PC13 anti tamp never_reset_pin_number(2,14); //PC14 OSC32_IN never_reset_pin_number(2,15); //PC15 OSC32_OUT never_reset_pin_number(0,13); //PA13 SWDIO @@ -223,21 +53,3 @@ void stm32f4_peripherals_gpio_init(void) { // never_reset_pin_number(5,0); //PH0 JTDO // never_reset_pin_number(5,1); //PH1 JTRST } - -//LEDs are inverted on F411 DISCO -void stm32f4_peripherals_status_led(uint8_t led, uint8_t state) { - switch(led) - { - case 0: HAL_GPIO_WritePin(GPIOE, GPIO_PIN_0, (state ^ 1)); - break; - case 1: HAL_GPIO_WritePin(GPIOE, GPIO_PIN_1, (state ^ 1)); - break; - case 2: HAL_GPIO_WritePin(GPIOE, GPIO_PIN_2, (state ^ 1)); - break; - case 3: HAL_GPIO_WritePin(GPIOE, GPIO_PIN_3, (state ^ 1)); - break; - default: break; - } -} - - diff --git a/ports/stm/peripherals/stm32f4/stm32f412zx/periph.c b/ports/stm/peripherals/stm32f4/stm32f412zx/periph.c index f5effa80ed0f0..e92c88ce55fa2 100644 --- a/ports/stm/peripherals/stm32f4/stm32f412zx/periph.c +++ b/ports/stm/peripherals/stm32f4/stm32f412zx/periph.c @@ -26,98 +26,98 @@ #include "py/obj.h" #include "py/mphal.h" -#include "stm32f4/pins.h" -#include "stm32f4/periph.h" +#include "peripherals/pins.h" +#include "peripherals/periph.h" // I2C I2C_TypeDef * mcu_i2c_banks[3] = {I2C1, I2C2, I2C3}; -const mcu_i2c_sda_obj_t mcu_i2c_sda_list[8] = { - I2C_SDA(1, 4, &pin_PB07), - I2C_SDA(1, 4, &pin_PB09), - I2C_SDA(2, 4, &pin_PB11), //not on LQFP100 - I2C_SDA(2, 9, &pin_PB09), - I2C_SDA(2, 9, &pin_PB03), - I2C_SDA(3, 4, &pin_PC09), - I2C_SDA(3, 9, &pin_PB04), - I2C_SDA(3, 9, &pin_PB08) +const mcu_periph_obj_t mcu_i2c_sda_list[8] = { + PERIPH(1, 4, &pin_PB07), + PERIPH(1, 4, &pin_PB09), + PERIPH(2, 4, &pin_PB11), //not on LQFP100 + PERIPH(2, 9, &pin_PB09), + PERIPH(2, 9, &pin_PB03), + PERIPH(3, 4, &pin_PC09), + PERIPH(3, 9, &pin_PB04), + PERIPH(3, 9, &pin_PB08) }; -const mcu_i2c_scl_obj_t mcu_i2c_scl_list[4] = { - I2C_SCL(1, 4, &pin_PB06), - I2C_SCL(1, 4, &pin_PB08), - I2C_SCL(2, 4, &pin_PB10), - I2C_SCL(3, 4, &pin_PA08) +const mcu_periph_obj_t mcu_i2c_scl_list[4] = { + PERIPH(1, 4, &pin_PB06), + PERIPH(1, 4, &pin_PB08), + PERIPH(2, 4, &pin_PB10), + PERIPH(3, 4, &pin_PA08) }; // SPI SPI_TypeDef * mcu_spi_banks[5] = {SPI1, SPI2, SPI3, SPI4, SPI5}; -const mcu_spi_sck_obj_t mcu_spi_sck_list[15] = { - SPI(1, 5, &pin_PA05), - SPI(1, 5, &pin_PB03), - SPI(2, 5, &pin_PB10), - SPI(2, 5, &pin_PB13), - SPI(2, 5, &pin_PC07), - SPI(2, 5, &pin_PD03), - SPI(3, 6, &pin_PB03), - SPI(3, 7, &pin_PB12), - SPI(3, 6, &pin_PC10), - SPI(4, 6, &pin_PB13), - SPI(4, 5, &pin_PE02), - SPI(4, 5, &pin_PE12), - SPI(5, 6, &pin_PB00), - SPI(5, 6, &pin_PE02), - SPI(5, 6, &pin_PE12) +const mcu_periph_obj_t mcu_spi_sck_list[15] = { + PERIPH(1, 5, &pin_PA05), + PERIPH(1, 5, &pin_PB03), + PERIPH(2, 5, &pin_PB10), + PERIPH(2, 5, &pin_PB13), + PERIPH(2, 5, &pin_PC07), + PERIPH(2, 5, &pin_PD03), + PERIPH(3, 6, &pin_PB03), + PERIPH(3, 7, &pin_PB12), + PERIPH(3, 6, &pin_PC10), + PERIPH(4, 6, &pin_PB13), + PERIPH(4, 5, &pin_PE02), + PERIPH(4, 5, &pin_PE12), + PERIPH(5, 6, &pin_PB00), + PERIPH(5, 6, &pin_PE02), + PERIPH(5, 6, &pin_PE12) }; -const mcu_spi_mosi_obj_t mcu_spi_mosi_list[14] = { - SPI(1, 5, &pin_PA07), - SPI(1, 5, &pin_PB05), - SPI(2, 5, &pin_PB15), - SPI(2, 5, &pin_PC03), - SPI(3, 6, &pin_PB05), - SPI(3, 6, &pin_PC12), - SPI(3, 5, &pin_PD06), - SPI(4, 5, &pin_PA01), - SPI(4, 5, &pin_PE06), - SPI(4, 5, &pin_PE14), - SPI(5, 6, &pin_PA10), - SPI(5, 6, &pin_PB08), - SPI(5, 6, &pin_PE06), - SPI(5, 6, &pin_PE14) +const mcu_periph_obj_t mcu_spi_mosi_list[14] = { + PERIPH(1, 5, &pin_PA07), + PERIPH(1, 5, &pin_PB05), + PERIPH(2, 5, &pin_PB15), + PERIPH(2, 5, &pin_PC03), + PERIPH(3, 6, &pin_PB05), + PERIPH(3, 6, &pin_PC12), + PERIPH(3, 5, &pin_PD06), + PERIPH(4, 5, &pin_PA01), + PERIPH(4, 5, &pin_PE06), + PERIPH(4, 5, &pin_PE14), + PERIPH(5, 6, &pin_PA10), + PERIPH(5, 6, &pin_PB08), + PERIPH(5, 6, &pin_PE06), + PERIPH(5, 6, &pin_PE14) }; -const mcu_spi_miso_obj_t mcu_spi_miso_list[12] = { - SPI(1, 5, &pin_PA06), - SPI(1, 5, &pin_PB04), - SPI(2, 5, &pin_PB14), - SPI(2, 5, &pin_PC02), - SPI(3, 6, &pin_PB04), - SPI(3, 6, &pin_PC11), - SPI(4, 6, &pin_PA11), - SPI(4, 5, &pin_PE05), - SPI(4, 5, &pin_PE13), - SPI(5, 6, &pin_PA12), - SPI(5, 6, &pin_PE05), - SPI(5, 6, &pin_PE13) +const mcu_periph_obj_t mcu_spi_miso_list[12] = { + PERIPH(1, 5, &pin_PA06), + PERIPH(1, 5, &pin_PB04), + PERIPH(2, 5, &pin_PB14), + PERIPH(2, 5, &pin_PC02), + PERIPH(3, 6, &pin_PB04), + PERIPH(3, 6, &pin_PC11), + PERIPH(4, 6, &pin_PA11), + PERIPH(4, 5, &pin_PE05), + PERIPH(4, 5, &pin_PE13), + PERIPH(5, 6, &pin_PA12), + PERIPH(5, 6, &pin_PE05), + PERIPH(5, 6, &pin_PE13) }; -const mcu_spi_nss_obj_t mcu_spi_nss_list[12] = { - SPI(1, 5, &pin_PA04), - SPI(1, 5, &pin_PA15), - SPI(2, 5, &pin_PB09), - SPI(2, 5, &pin_PB12), - SPI(3, 6, &pin_PA04), - SPI(3, 6, &pin_PA15), - SPI(4, 6, &pin_PB12), - SPI(4, 5, &pin_PE04), - SPI(4, 5, &pin_PE11), - SPI(5, 6, &pin_PB01), - SPI(5, 6, &pin_PE04), - SPI(5, 6, &pin_PE11) +const mcu_periph_obj_t mcu_spi_nss_list[12] = { + PERIPH(1, 5, &pin_PA04), + PERIPH(1, 5, &pin_PA15), + PERIPH(2, 5, &pin_PB09), + PERIPH(2, 5, &pin_PB12), + PERIPH(3, 6, &pin_PA04), + PERIPH(3, 6, &pin_PA15), + PERIPH(4, 6, &pin_PB12), + PERIPH(4, 5, &pin_PE04), + PERIPH(4, 5, &pin_PE11), + PERIPH(5, 6, &pin_PB01), + PERIPH(5, 6, &pin_PE04), + PERIPH(5, 6, &pin_PE11) }; //UART @@ -125,33 +125,33 @@ const mcu_spi_nss_obj_t mcu_spi_nss_list[12] = { USART_TypeDef * mcu_uart_banks[MAX_UART] = {USART1, USART2, USART3, NULL, NULL, USART6}; bool mcu_uart_has_usart[MAX_UART] = {true, true, true, false, false, true}; -const mcu_uart_tx_obj_t mcu_uart_tx_list[11] = { - UART(2, 7, &pin_PA02), - UART(1, 7, &pin_PA09), - UART(1, 7, &pin_PA15), - UART(6, 8, &pin_PA11), - UART(1, 7, &pin_PB06), - UART(3, 7, &pin_PB10), - UART(6, 8, &pin_PC06), - UART(3, 7, &pin_PC10), - UART(2, 7, &pin_PD05), - UART(3, 7, &pin_PD08), - UART(6, 8, &pin_PG14), +const mcu_periph_obj_t mcu_uart_tx_list[11] = { + PERIPH(2, 7, &pin_PA02), + PERIPH(1, 7, &pin_PA09), + PERIPH(1, 7, &pin_PA15), + PERIPH(6, 8, &pin_PA11), + PERIPH(1, 7, &pin_PB06), + PERIPH(3, 7, &pin_PB10), + PERIPH(6, 8, &pin_PC06), + PERIPH(3, 7, &pin_PC10), + PERIPH(2, 7, &pin_PD05), + PERIPH(3, 7, &pin_PD08), + PERIPH(6, 8, &pin_PG14), }; -const mcu_uart_rx_obj_t mcu_uart_rx_list[12] = { - UART(2, 7, &pin_PA03), - UART(1, 7, &pin_PA10), - UART(6, 8, &pin_PA12), - UART(1, 7, &pin_PB03), - UART(1, 7, &pin_PB07), - UART(3, 7, &pin_PB11), - UART(3, 7, &pin_PC05), - UART(6, 8, &pin_PC07), - UART(3, 7, &pin_PC11), - UART(2, 7, &pin_PD06), - UART(3, 7, &pin_PD09), - UART(6, 8, &pin_PG09), +const mcu_periph_obj_t mcu_uart_rx_list[12] = { + PERIPH(2, 7, &pin_PA03), + PERIPH(1, 7, &pin_PA10), + PERIPH(6, 8, &pin_PA12), + PERIPH(1, 7, &pin_PB03), + PERIPH(1, 7, &pin_PB07), + PERIPH(3, 7, &pin_PB11), + PERIPH(3, 7, &pin_PC05), + PERIPH(6, 8, &pin_PC07), + PERIPH(3, 7, &pin_PC11), + PERIPH(2, 7, &pin_PD06), + PERIPH(3, 7, &pin_PD09), + PERIPH(6, 8, &pin_PG09), }; //Timers diff --git a/ports/stm/peripherals/stm32f4/stm32f412zx/periph.h b/ports/stm/peripherals/stm32f4/stm32f412zx/periph.h index e0141e6dab7cc..f668ace752f45 100644 --- a/ports/stm/peripherals/stm32f4/stm32f412zx/periph.h +++ b/ports/stm/peripherals/stm32f4/stm32f412zx/periph.h @@ -24,30 +24,30 @@ * THE SOFTWARE. */ -#ifndef MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F411VE_PERIPH_H -#define MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F411VE_PERIPH_H +#ifndef MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F412ZX_PERIPH_H +#define MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F412ZX_PERIPH_H //I2C extern I2C_TypeDef * mcu_i2c_banks[3]; -extern const mcu_i2c_sda_obj_t mcu_i2c_sda_list[8]; -extern const mcu_i2c_scl_obj_t mcu_i2c_scl_list[4]; +extern const mcu_periph_obj_t mcu_i2c_sda_list[8]; +extern const mcu_periph_obj_t mcu_i2c_scl_list[4]; //SPI extern SPI_TypeDef * mcu_spi_banks[5]; -extern const mcu_spi_sck_obj_t mcu_spi_sck_list[15]; -extern const mcu_spi_mosi_obj_t mcu_spi_mosi_list[14]; -extern const mcu_spi_miso_obj_t mcu_spi_miso_list[12]; -extern const mcu_spi_nss_obj_t mcu_spi_nss_list[12]; +extern const mcu_periph_obj_t mcu_spi_sck_list[15]; +extern const mcu_periph_obj_t mcu_spi_mosi_list[14]; +extern const mcu_periph_obj_t mcu_spi_miso_list[12]; +extern const mcu_periph_obj_t mcu_spi_nss_list[12]; //UART extern USART_TypeDef * mcu_uart_banks[MAX_UART]; extern bool mcu_uart_has_usart[MAX_UART]; -extern const mcu_uart_tx_obj_t mcu_uart_tx_list[11]; -extern const mcu_uart_rx_obj_t mcu_uart_rx_list[12]; +extern const mcu_periph_obj_t mcu_uart_tx_list[11]; +extern const mcu_periph_obj_t mcu_uart_rx_list[12]; //Timers #define TIM_BANK_ARRAY_LEN 14 @@ -55,4 +55,4 @@ extern const mcu_uart_rx_obj_t mcu_uart_rx_list[12]; TIM_TypeDef * mcu_tim_banks[TIM_BANK_ARRAY_LEN]; const mcu_tim_pin_obj_t mcu_tim_pin_list[TIM_PIN_ARRAY_LEN]; -#endif // MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F411VE_PERIPH_H \ No newline at end of file +#endif // MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F412ZX_PERIPH_H \ No newline at end of file diff --git a/ports/stm/peripherals/stm32f4/stm32f412zx/pins.c b/ports/stm/peripherals/stm32f4/stm32f412zx/pins.c index c56de5a2950cc..ef3ce6d0ed864 100644 --- a/ports/stm/peripherals/stm32f4/stm32f412zx/pins.c +++ b/ports/stm/peripherals/stm32f4/stm32f412zx/pins.c @@ -26,7 +26,7 @@ #include "py/obj.h" #include "py/mphal.h" -#include "stm32f4/pins.h" +#include "peripherals/pins.h" const mcu_pin_obj_t pin_PE02 = PIN(4, 2, NO_ADC); const mcu_pin_obj_t pin_PE03 = PIN(4, 3, NO_ADC); diff --git a/ports/stm/peripherals/stm32f4/stm32f412zx/pins.h b/ports/stm/peripherals/stm32f4/stm32f412zx/pins.h index 180f5c316fa5e..5cf99345ceeea 100644 --- a/ports/stm/peripherals/stm32f4/stm32f412zx/pins.h +++ b/ports/stm/peripherals/stm32f4/stm32f412zx/pins.h @@ -24,10 +24,9 @@ * THE SOFTWARE. */ -#ifndef MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F412ZG_PINS_H -#define MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F412ZG_PINS_H +#ifndef MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F412ZX_PINS_H +#define MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F412ZX_PINS_H -//Pins in datasheet order: DocID028087 Rev 7 page 50. LQFP100 only //pg 50 extern const mcu_pin_obj_t pin_PE02; extern const mcu_pin_obj_t pin_PE03; @@ -155,4 +154,4 @@ extern const mcu_pin_obj_t pin_PB09; extern const mcu_pin_obj_t pin_PE00; extern const mcu_pin_obj_t pin_PE01; -#endif // MICROPY_INCLUDED_STM32F4_PERIPHERALS_STM32F412ZG_PINS_H +#endif // MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F412ZX_PINS_H diff --git a/ports/stm/peripherals/stm32h7/stm32h743xx/clocks.c b/ports/stm/peripherals/stm32h7/stm32h743xx/clocks.c new file mode 100644 index 0000000000000..494b7709e6b70 --- /dev/null +++ b/ports/stm/peripherals/stm32h7/stm32h743xx/clocks.c @@ -0,0 +1,162 @@ + +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/mpconfig.h" + +void stm32_peripherals_clocks_init(void) { + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + + /* The PWR block is always enabled on the H7 series- there is no clock + enable. For now, use the default VOS3 scale mode (lowest) and limit clock + frequencies to avoid potential current draw problems from bus + power when using the max clock speeds throughout the chip. */ + + /* Enable HSE Oscillator and activate PLL1 with HSE as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.HSIState = RCC_HSI_OFF; + RCC_OscInitStruct.CSIState = RCC_CSI_OFF; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000; + RCC_OscInitStruct.PLL.PLLN = 336; + RCC_OscInitStruct.PLL.PLLP = 2; + RCC_OscInitStruct.PLL.PLLQ = 7; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_0; + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOMEDIUM; + RCC_OscInitStruct.PLL.PLLFRACN = 0; + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | \ + RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | \ + RCC_CLOCKTYPE_D3PCLK1); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1; + + /* Unlike on the STM32F4 family, it appears the maximum APB frequencies are + device-dependent- 120 MHz for this board according to Figure 2 of + the datasheet. Dividing by half will be safe for now. */ + RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; + RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; + RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; + + /* 4 wait states required for 168MHz and VOS3. */ + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4); + + /* Like on F4, on H7, USB's actual peripheral clock and bus clock are + separate. However, the main system PLL (PLL1) doesn't have a direct + connection to the USB peripheral clock to generate 48 MHz, so we do this + dance. This will connect PLL1's Q output to the USB peripheral clock. */ + RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct; + + RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; + RCC_PeriphCLKInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL; + HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct); + + // RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + // RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + // RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + // /** Supply configuration update enable + // */ + // HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); + // /** Configure the main internal regulator output voltage + // */ + // __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + // while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + // /** Macro to configure the PLL clock source + // */ + // __HAL_RCC_PLL_PLLSOURCE_CONFIG(RCC_PLLSOURCE_HSE); + // /** Initializes the CPU, AHB and APB busses clocks + // */ + // RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + // RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; + // RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + // RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + // RCC_OscInitStruct.PLL.PLLM = 4; + // RCC_OscInitStruct.PLL.PLLN = 400; + // RCC_OscInitStruct.PLL.PLLP = 2; + // RCC_OscInitStruct.PLL.PLLQ = 4; + // RCC_OscInitStruct.PLL.PLLR = 2; + // RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_1; + // RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; + // RCC_OscInitStruct.PLL.PLLFRACN = 0; + // if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + // { + + // } + // /** Initializes the CPU, AHB and APB busses clocks + // */ + // RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + // |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 + // |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1; + // RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + // RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; + // RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; + // RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; + // RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; + // RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; + // RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; + + // if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) + // { + + // } + // PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; /*RCC_PERIPHCLK_USART3|RCC_PERIPHCLK_UART4 + // |RCC_PERIPHCLK_SPI1|RCC_PERIPHCLK_ADC + // |RCC_PERIPHCLK_I2C1| */ + // // PeriphClkInitStruct.PLL2.PLL2M = 1; + // // PeriphClkInitStruct.PLL2.PLL2N = 19; + // // PeriphClkInitStruct.PLL2.PLL2P = 2; + // // PeriphClkInitStruct.PLL2.PLL2Q = 2; + // // PeriphClkInitStruct.PLL2.PLL2R = 2; + // // PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3; + // // PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOMEDIUM; + // // PeriphClkInitStruct.PLL2.PLL2FRACN = 0; + // PeriphClkInitStruct.PLL3.PLL3M = 4; + // PeriphClkInitStruct.PLL3.PLL3N = 120; + // PeriphClkInitStruct.PLL3.PLL3P = 2; + // PeriphClkInitStruct.PLL3.PLL3Q = 5; + // PeriphClkInitStruct.PLL3.PLL3R = 2; + // PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_1; + // PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE; + // PeriphClkInitStruct.PLL3.PLL3FRACN = 0; + // PeriphClkInitStruct.Spi123ClockSelection = RCC_SPI123CLKSOURCE_PLL; + // PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1; + // PeriphClkInitStruct.I2c123ClockSelection = RCC_I2C123CLKSOURCE_D2PCLK1; + // PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3; + // PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLL2; + // if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + // { + + // } + +} diff --git a/ports/stm/peripherals/stm32h7/stm32h743xx/gpio.c b/ports/stm/peripherals/stm32h7/stm32h743xx/gpio.c new file mode 100644 index 0000000000000..d51ff53c1f0df --- /dev/null +++ b/ports/stm/peripherals/stm32h7/stm32h743xx/gpio.c @@ -0,0 +1,48 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "gpio.h" +#include "common-hal/microcontroller/Pin.h" + +void stm32_peripherals_gpio_init(void) { + //Enable all GPIO for now + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + + //Never reset pins + never_reset_pin_number(2,14); //PC14 OSC32_IN + never_reset_pin_number(2,15); //PC15 OSC32_OUT + never_reset_pin_number(0,13); //PA13 SWDIO + never_reset_pin_number(0,14); //PA14 SWCLK +} + + diff --git a/ports/stm/peripherals/stm32h7/stm32h743xx/periph.c b/ports/stm/peripherals/stm32h7/stm32h743xx/periph.c new file mode 100644 index 0000000000000..89216460011db --- /dev/null +++ b/ports/stm/peripherals/stm32h7/stm32h743xx/periph.c @@ -0,0 +1,260 @@ + /* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/obj.h" +#include "py/mphal.h" +#include "peripherals/pins.h" +#include "peripherals/periph.h" + +// I2C + +I2C_TypeDef * mcu_i2c_banks[4] = {I2C1, I2C2, I2C3, I2C4}; + +const mcu_periph_obj_t mcu_i2c_sda_list[12] = { + PERIPH(1, 4, &pin_PB07), + PERIPH(4, 6, &pin_PB07), + PERIPH(1, 4, &pin_PB09), + PERIPH(4, 6, &pin_PB09), + PERIPH(2, 4, &pin_PB11), + PERIPH(3, 4, &pin_PC09), + PERIPH(4, 4, &pin_PD13), + PERIPH(2, 4, &pin_PF00), + PERIPH(4, 4, &pin_PF15), + PERIPH(2, 4, &pin_PH05), + PERIPH(3, 4, &pin_PH08), + PERIPH(4, 4, &pin_PH12) +}; + +const mcu_periph_obj_t mcu_i2c_scl_list[12] = { + PERIPH(3, 4, &pin_PA08), + PERIPH(1, 4, &pin_PB06), + PERIPH(4, 6, &pin_PB06), + PERIPH(1, 4, &pin_PB08), + PERIPH(4, 6, &pin_PB08), + PERIPH(2, 4, &pin_PB10), + PERIPH(4, 4, &pin_PD12), + PERIPH(2, 4, &pin_PF01), + PERIPH(4, 4, &pin_PF14), + PERIPH(2, 4, &pin_PH04), + PERIPH(3, 4, &pin_PH07), + PERIPH(4, 4, &pin_PH11) +}; + +// SPI + +SPI_TypeDef * mcu_spi_banks[6] = {SPI1, SPI2, SPI3, SPI4, SPI5, SPI6}; + +const mcu_periph_obj_t mcu_spi_sck_list[19] = { + PERIPH(1, 5, &pin_PA05), + PERIPH(6, 8, &pin_PA05), + PERIPH(2, 5, &pin_PA09), + PERIPH(2, 5, &pin_PA12), + PERIPH(1, 5, &pin_PB03), + PERIPH(3, 6, &pin_PB03), + PERIPH(6, 8, &pin_PB03), + PERIPH(2, 5, &pin_PB10), + PERIPH(2, 5, &pin_PB13), + PERIPH(3, 6, &pin_PC10), + PERIPH(2, 5, &pin_PD03), + PERIPH(4, 5, &pin_PE02), + PERIPH(4, 5, &pin_PE12), + PERIPH(5, 5, &pin_PF07), + PERIPH(1, 5, &pin_PG11), + PERIPH(6, 5, &pin_PG13), + PERIPH(5, 5, &pin_PH06), + PERIPH(2, 5, &pin_PI01), + PERIPH(5, 5, &pin_PK00), +}; + +const mcu_periph_obj_t mcu_spi_mosi_list[19] = { + PERIPH(1, 5, &pin_PA07), + PERIPH(6, 8, &pin_PA07), + PERIPH(3, 7, &pin_PB02), + PERIPH(1, 5, &pin_PB05), + PERIPH(3, 7, &pin_PB05), + PERIPH(6, 8, &pin_PB05), + PERIPH(2, 5, &pin_PB15), + PERIPH(2, 5, &pin_PC01), + PERIPH(2, 5, &pin_PC03), + PERIPH(3, 6, &pin_PC12), + PERIPH(3, 5, &pin_PD06), + PERIPH(1, 5, &pin_PD07), + PERIPH(4, 5, &pin_PE06), + PERIPH(4, 5, &pin_PE14), + PERIPH(5, 5, &pin_PF09), + PERIPH(5, 5, &pin_PF11), + PERIPH(6, 5, &pin_PG14), + PERIPH(2, 5, &pin_PI03), + PERIPH(5, 5, &pin_PJ10), +}; + +const mcu_periph_obj_t mcu_spi_miso_list[16] = { + PERIPH(1, 5, &pin_PA06), + PERIPH(6, 8, &pin_PA06), + PERIPH(1, 5, &pin_PB04), + PERIPH(3, 6, &pin_PB04), + PERIPH(6, 8, &pin_PB04), + PERIPH(2, 5, &pin_PB14), + PERIPH(2, 5, &pin_PC02), + PERIPH(3, 6, &pin_PC11), + PERIPH(4, 5, &pin_PE05), + PERIPH(4, 5, &pin_PE13), + PERIPH(5, 5, &pin_PF08), + PERIPH(1, 5, &pin_PG09), + PERIPH(6, 5, &pin_PG12), + PERIPH(5, 5, &pin_PH07), + PERIPH(2, 5, &pin_PI02), + PERIPH(5, 5, &pin_PJ11), +}; + +//UART + +USART_TypeDef * mcu_uart_banks[MAX_UART] = {USART1, USART2, USART3, UART4, UART5, USART6, UART7, UART8}; +bool mcu_uart_has_usart[MAX_UART] = {true, true, true, true, true, true, true, true}; + +const mcu_periph_obj_t mcu_uart_tx_list[25] = { + PERIPH(4, 8, &pin_PA00), + PERIPH(2, 7, &pin_PA02), + PERIPH(1, 7, &pin_PA09), + PERIPH(4, 6, &pin_PA12), + PERIPH(7, 11, &pin_PA15), + PERIPH(7, 11, &pin_PB04), + PERIPH(1, 7, &pin_PB06), + PERIPH(5, 14, &pin_PB06), + PERIPH(4, 8, &pin_PB09), + PERIPH(3, 7, &pin_PB10), + PERIPH(5, 14, &pin_PB13), + PERIPH(1, 4, &pin_PB14), + PERIPH(6, 7, &pin_PC06), + PERIPH(3, 7, &pin_PC10), + PERIPH(4, 8, &pin_PC10), + PERIPH(5, 8, &pin_PC12), + PERIPH(4, 8, &pin_PD01), + PERIPH(2, 7, &pin_PD05), + PERIPH(3, 7, &pin_PD08), + PERIPH(8, 8, &pin_PE01), + PERIPH(7, 7, &pin_PE08), + PERIPH(7, 7, &pin_PF07), + PERIPH(6, 7, &pin_PG14), + PERIPH(4, 8, &pin_PH13), + PERIPH(8, 8, &pin_PJ08), +}; + +const mcu_periph_obj_t mcu_uart_rx_list[26] = { + PERIPH(4, 8, &pin_PA01), + PERIPH(2, 7, &pin_PA03), + PERIPH(7, 11, &pin_PA08), + PERIPH(1, 7, &pin_PA10), + PERIPH(4, 6, &pin_PA11), + PERIPH(7, 11, &pin_PB03), + PERIPH(5, 14, &pin_PB05), + PERIPH(1, 7, &pin_PB07), + PERIPH(4, 8, &pin_PB08), + PERIPH(3, 7, &pin_PB11), + PERIPH(5, 14, &pin_PB12), + PERIPH(1, 4, &pin_PB15), + PERIPH(6, 7, &pin_PC07), + PERIPH(3, 7, &pin_PC11), + PERIPH(4, 8, &pin_PC11), + PERIPH(4, 8, &pin_PD00), + PERIPH(5, 8, &pin_PD02), + PERIPH(2, 7, &pin_PD06), + PERIPH(3, 7, &pin_PD09), + PERIPH(8, 8, &pin_PE00), + PERIPH(7, 7, &pin_PE07), + PERIPH(7, 7, &pin_PF06), + PERIPH(6, 7, &pin_PG09), + PERIPH(4, 8, &pin_PH14), + PERIPH(4, 8, &pin_PI09), + PERIPH(8, 8, &pin_PJ09), +}; + +//Timers +//TIM6 and TIM7 are basic timers that are only used by DAC, and don't have pins +//TODO: H7 has more timers than this, but are they tied to pins? +TIM_TypeDef * mcu_tim_banks[14] = {TIM1, TIM2, TIM3, TIM4, TIM5, NULL, NULL, TIM8, NULL, NULL, + NULL, TIM12, TIM13, TIM14}; + +const mcu_tim_pin_obj_t mcu_tim_pin_list[58] = { + TIM(2, 1, 1, &pin_PA00), + TIM(5, 2, 1, &pin_PA00), + TIM(2, 1, 2, &pin_PA01), + TIM(5, 2, 2, &pin_PA01), + TIM(2, 1, 3, &pin_PA02), + TIM(5, 2, 3, &pin_PA02), + TIM(2, 1, 4, &pin_PA03), + TIM(5, 2, 4, &pin_PA03), + TIM(2, 1, 1, &pin_PA05), + TIM(3, 2, 1, &pin_PA06), + TIM(3, 2, 2, &pin_PA07), + TIM(1, 1, 1, &pin_PA08), + TIM(1, 1, 2, &pin_PA09), + TIM(1, 1, 3, &pin_PA10), + TIM(1, 1, 4, &pin_PA11), + TIM(2, 1, 1, &pin_PA15), + TIM(3, 2, 3, &pin_PB00), + TIM(3, 2, 4, &pin_PB01), + TIM(2, 1, 2, &pin_PB03), + TIM(3, 2, 1, &pin_PB04), + TIM(3, 2, 2, &pin_PB05), + TIM(4, 2, 1, &pin_PB06), + TIM(4, 2, 2, &pin_PB07), + TIM(4, 2, 3, &pin_PB08), + TIM(4, 2, 4, &pin_PB09), + TIM(2, 1, 3, &pin_PB10), + TIM(2, 1, 4, &pin_PB11), + TIM(3, 2, 1, &pin_PC06), + TIM(8, 3, 1, &pin_PC06), + TIM(3, 2, 2, &pin_PC07), + TIM(8, 3, 2, &pin_PC07), + TIM(3, 2, 3, &pin_PC08), + TIM(8, 3, 3, &pin_PC08), + TIM(3, 2, 4, &pin_PC09), + TIM(8, 3, 4, &pin_PC09), + TIM(4, 2, 1, &pin_PD12), + TIM(4, 2, 2, &pin_PD13), + TIM(4, 2, 3, &pin_PD14), + TIM(4, 2, 4, &pin_PD15), + TIM(1, 1, 1, &pin_PE09), + TIM(1, 1, 2, &pin_PE11), + TIM(1, 1, 3, &pin_PE13), + TIM(1, 1, 4, &pin_PE14), + TIM(5, 2, 1, &pin_PH10), + TIM(5, 2, 2, &pin_PH11), + TIM(5, 2, 3, &pin_PH12), + TIM(5, 2, 4, &pin_PI00), + TIM(8, 3, 4, &pin_PI02), + TIM(8, 3, 1, &pin_PI05), + TIM(8, 3, 2, &pin_PI06), + TIM(8, 3, 3, &pin_PI07), + TIM(8, 3, 2, &pin_PJ06), + TIM(8, 3, 1, &pin_PJ08), + TIM(1, 1, 3, &pin_PJ09), + TIM(8, 3, 2, &pin_PJ10), + TIM(1, 1, 2, &pin_PJ11), + TIM(8, 3, 3, &pin_PK00), + TIM(1, 1, 1, &pin_PK01), +}; diff --git a/ports/stm/peripherals/stm32h7/stm32h743xx/periph.h b/ports/stm/peripherals/stm32h7/stm32h743xx/periph.h new file mode 100644 index 0000000000000..4b852413b3e9d --- /dev/null +++ b/ports/stm/peripherals/stm32h7/stm32h743xx/periph.h @@ -0,0 +1,55 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MICROPY_INCLUDED_STM32_PERIPHERALS_STM32H743XX_PERIPH_H +#define MICROPY_INCLUDED_STM32_PERIPHERALS_STM32H743XX_PERIPH_H + +//I2C +extern I2C_TypeDef * mcu_i2c_banks[4]; + +const mcu_periph_obj_t mcu_i2c_sda_list[12]; +const mcu_periph_obj_t mcu_i2c_scl_list[12]; + +//SPI +extern SPI_TypeDef * mcu_spi_banks[6]; + +const mcu_periph_obj_t mcu_spi_sck_list[19]; +const mcu_periph_obj_t mcu_spi_mosi_list[19]; +const mcu_periph_obj_t mcu_spi_miso_list[16]; + +//UART +extern USART_TypeDef * mcu_uart_banks[MAX_UART]; +extern bool mcu_uart_has_usart[MAX_UART]; + +const mcu_periph_obj_t mcu_uart_tx_list[25]; +const mcu_periph_obj_t mcu_uart_rx_list[26]; + +//Timers +#define TIM_BANK_ARRAY_LEN 14 +#define TIM_PIN_ARRAY_LEN 58 +TIM_TypeDef * mcu_tim_banks[TIM_BANK_ARRAY_LEN]; + +#endif // MICROPY_INCLUDED_STM32_PERIPHERALS_STM32H743XX_PERIPH_H \ No newline at end of file diff --git a/ports/stm/peripherals/stm32h7/stm32h743xx/pins.c b/ports/stm/peripherals/stm32h7/stm32h743xx/pins.c new file mode 100644 index 0000000000000..491fe693854e7 --- /dev/null +++ b/ports/stm/peripherals/stm32h7/stm32h743xx/pins.c @@ -0,0 +1,210 @@ + /* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/obj.h" +#include "py/mphal.h" +#include "peripherals/pins.h" + +// Todo: some pins do have ADCs, but the module isn't set up yet. + +const mcu_pin_obj_t pin_PA00 = PIN(0, 0, NO_ADC); +const mcu_pin_obj_t pin_PA01 = PIN(0, 1, NO_ADC); +const mcu_pin_obj_t pin_PA02 = PIN(0, 2, NO_ADC); +const mcu_pin_obj_t pin_PA03 = PIN(0, 3, NO_ADC); +const mcu_pin_obj_t pin_PA04 = PIN(0, 4, NO_ADC); +const mcu_pin_obj_t pin_PA05 = PIN(0, 5, NO_ADC); +const mcu_pin_obj_t pin_PA06 = PIN(0, 6, NO_ADC); +const mcu_pin_obj_t pin_PA07 = PIN(0, 7, NO_ADC); +const mcu_pin_obj_t pin_PA08 = PIN(0, 8, NO_ADC); +const mcu_pin_obj_t pin_PA09 = PIN(0, 9, NO_ADC); +const mcu_pin_obj_t pin_PA10 = PIN(0, 10, NO_ADC); +const mcu_pin_obj_t pin_PA11 = PIN(0, 11, NO_ADC); +const mcu_pin_obj_t pin_PA12 = PIN(0, 12, NO_ADC); +const mcu_pin_obj_t pin_PA13 = PIN(0, 13, NO_ADC); +const mcu_pin_obj_t pin_PA14 = PIN(0, 14, NO_ADC); +const mcu_pin_obj_t pin_PA15 = PIN(0, 15, NO_ADC); + +const mcu_pin_obj_t pin_PB00 = PIN(1, 0, NO_ADC); +const mcu_pin_obj_t pin_PB01 = PIN(1, 1, NO_ADC); +const mcu_pin_obj_t pin_PB02 = PIN(1, 2, NO_ADC); +const mcu_pin_obj_t pin_PB03 = PIN(1, 3, NO_ADC); +const mcu_pin_obj_t pin_PB04 = PIN(1, 4, NO_ADC); +const mcu_pin_obj_t pin_PB05 = PIN(1, 5, NO_ADC); +const mcu_pin_obj_t pin_PB06 = PIN(1, 6, NO_ADC); +const mcu_pin_obj_t pin_PB07 = PIN(1, 7, NO_ADC); +const mcu_pin_obj_t pin_PB08 = PIN(1, 8, NO_ADC); +const mcu_pin_obj_t pin_PB09 = PIN(1, 9, NO_ADC); +const mcu_pin_obj_t pin_PB10 = PIN(1, 10, NO_ADC); +const mcu_pin_obj_t pin_PB11 = PIN(1, 11, NO_ADC); +const mcu_pin_obj_t pin_PB12 = PIN(1, 12, NO_ADC); +const mcu_pin_obj_t pin_PB13 = PIN(1, 13, NO_ADC); +const mcu_pin_obj_t pin_PB14 = PIN(1, 14, NO_ADC); +const mcu_pin_obj_t pin_PB15 = PIN(1, 15, NO_ADC); + +const mcu_pin_obj_t pin_PC00 = PIN(2, 0, NO_ADC); +const mcu_pin_obj_t pin_PC01 = PIN(2, 1, NO_ADC); +const mcu_pin_obj_t pin_PC02 = PIN(2, 2, NO_ADC); +const mcu_pin_obj_t pin_PC03 = PIN(2, 3, NO_ADC); +const mcu_pin_obj_t pin_PC04 = PIN(2, 4, NO_ADC); +const mcu_pin_obj_t pin_PC05 = PIN(2, 5, NO_ADC); +const mcu_pin_obj_t pin_PC06 = PIN(2, 6, NO_ADC); +const mcu_pin_obj_t pin_PC07 = PIN(2, 7, NO_ADC); +const mcu_pin_obj_t pin_PC08 = PIN(2, 8, NO_ADC); +const mcu_pin_obj_t pin_PC09 = PIN(2, 9, NO_ADC); +const mcu_pin_obj_t pin_PC10 = PIN(2, 10, NO_ADC); +const mcu_pin_obj_t pin_PC11 = PIN(2, 11, NO_ADC); +const mcu_pin_obj_t pin_PC12 = PIN(2, 12, NO_ADC); +const mcu_pin_obj_t pin_PC13 = PIN(2, 13, NO_ADC); +const mcu_pin_obj_t pin_PC14 = PIN(2, 14, NO_ADC); +const mcu_pin_obj_t pin_PC15 = PIN(2, 15, NO_ADC); + +const mcu_pin_obj_t pin_PD00 = PIN(3, 0, NO_ADC); +const mcu_pin_obj_t pin_PD01 = PIN(3, 1, NO_ADC); +const mcu_pin_obj_t pin_PD02 = PIN(3, 2, NO_ADC); +const mcu_pin_obj_t pin_PD03 = PIN(3, 3, NO_ADC); +const mcu_pin_obj_t pin_PD04 = PIN(3, 4, NO_ADC); +const mcu_pin_obj_t pin_PD05 = PIN(3, 5, NO_ADC); +const mcu_pin_obj_t pin_PD06 = PIN(3, 6, NO_ADC); +const mcu_pin_obj_t pin_PD07 = PIN(3, 7, NO_ADC); +const mcu_pin_obj_t pin_PD08 = PIN(3, 8, NO_ADC); +const mcu_pin_obj_t pin_PD09 = PIN(3, 9, NO_ADC); +const mcu_pin_obj_t pin_PD10 = PIN(3, 10, NO_ADC); +const mcu_pin_obj_t pin_PD11 = PIN(3, 11, NO_ADC); +const mcu_pin_obj_t pin_PD12 = PIN(3, 12, NO_ADC); +const mcu_pin_obj_t pin_PD13 = PIN(3, 13, NO_ADC); +const mcu_pin_obj_t pin_PD14 = PIN(3, 14, NO_ADC); +const mcu_pin_obj_t pin_PD15 = PIN(3, 15, NO_ADC); + +const mcu_pin_obj_t pin_PE00 = PIN(4, 0, NO_ADC); +const mcu_pin_obj_t pin_PE01 = PIN(4, 1, NO_ADC); +const mcu_pin_obj_t pin_PE02 = PIN(4, 2, NO_ADC); +const mcu_pin_obj_t pin_PE03 = PIN(4, 3, NO_ADC); +const mcu_pin_obj_t pin_PE04 = PIN(4, 4, NO_ADC); +const mcu_pin_obj_t pin_PE05 = PIN(4, 5, NO_ADC); +const mcu_pin_obj_t pin_PE06 = PIN(4, 6, NO_ADC); +const mcu_pin_obj_t pin_PE07 = PIN(4, 7, NO_ADC); +const mcu_pin_obj_t pin_PE08 = PIN(4, 8, NO_ADC); +const mcu_pin_obj_t pin_PE09 = PIN(4, 9, NO_ADC); +const mcu_pin_obj_t pin_PE10 = PIN(4, 10, NO_ADC); +const mcu_pin_obj_t pin_PE11 = PIN(4, 11, NO_ADC); +const mcu_pin_obj_t pin_PE12 = PIN(4, 12, NO_ADC); +const mcu_pin_obj_t pin_PE13 = PIN(4, 13, NO_ADC); +const mcu_pin_obj_t pin_PE14 = PIN(4, 14, NO_ADC); +const mcu_pin_obj_t pin_PE15 = PIN(4, 15, NO_ADC); + +const mcu_pin_obj_t pin_PF00 = PIN(5, 0, NO_ADC); +const mcu_pin_obj_t pin_PF01 = PIN(5, 1, NO_ADC); +const mcu_pin_obj_t pin_PF02 = PIN(5, 2, NO_ADC); +const mcu_pin_obj_t pin_PF03 = PIN(5, 3, NO_ADC); +const mcu_pin_obj_t pin_PF04 = PIN(5, 4, NO_ADC); +const mcu_pin_obj_t pin_PF05 = PIN(5, 5, NO_ADC); +const mcu_pin_obj_t pin_PF06 = PIN(5, 6, NO_ADC); +const mcu_pin_obj_t pin_PF07 = PIN(5, 7, NO_ADC); +const mcu_pin_obj_t pin_PF08 = PIN(5, 8, NO_ADC); +const mcu_pin_obj_t pin_PF09 = PIN(5, 9, NO_ADC); +const mcu_pin_obj_t pin_PF10 = PIN(5, 10, NO_ADC); +const mcu_pin_obj_t pin_PF11 = PIN(5, 11, NO_ADC); +const mcu_pin_obj_t pin_PF12 = PIN(5, 12, NO_ADC); +const mcu_pin_obj_t pin_PF13 = PIN(5, 13, NO_ADC); +const mcu_pin_obj_t pin_PF14 = PIN(5, 14, NO_ADC); +const mcu_pin_obj_t pin_PF15 = PIN(5, 15, NO_ADC); + +const mcu_pin_obj_t pin_PG00 = PIN(6, 0, NO_ADC); +const mcu_pin_obj_t pin_PG01 = PIN(6, 1, NO_ADC); +const mcu_pin_obj_t pin_PG02 = PIN(6, 2, NO_ADC); +const mcu_pin_obj_t pin_PG03 = PIN(6, 3, NO_ADC); +const mcu_pin_obj_t pin_PG04 = PIN(6, 4, NO_ADC); +const mcu_pin_obj_t pin_PG05 = PIN(6, 5, NO_ADC); +const mcu_pin_obj_t pin_PG06 = PIN(6, 6, NO_ADC); +const mcu_pin_obj_t pin_PG07 = PIN(6, 7, NO_ADC); +const mcu_pin_obj_t pin_PG08 = PIN(6, 8, NO_ADC); +const mcu_pin_obj_t pin_PG09 = PIN(6, 9, NO_ADC); +const mcu_pin_obj_t pin_PG10 = PIN(6, 10, NO_ADC); +const mcu_pin_obj_t pin_PG11 = PIN(6, 11, NO_ADC); +const mcu_pin_obj_t pin_PG12 = PIN(6, 12, NO_ADC); +const mcu_pin_obj_t pin_PG13 = PIN(6, 13, NO_ADC); +const mcu_pin_obj_t pin_PG14 = PIN(6, 14, NO_ADC); +const mcu_pin_obj_t pin_PG15 = PIN(6, 15, NO_ADC); + +const mcu_pin_obj_t pin_PH00 = PIN(7, 0, NO_ADC); +const mcu_pin_obj_t pin_PH01 = PIN(7, 1, NO_ADC); +const mcu_pin_obj_t pin_PH02 = PIN(7, 2, NO_ADC); +const mcu_pin_obj_t pin_PH03 = PIN(7, 3, NO_ADC); +const mcu_pin_obj_t pin_PH04 = PIN(7, 4, NO_ADC); +const mcu_pin_obj_t pin_PH05 = PIN(7, 5, NO_ADC); +const mcu_pin_obj_t pin_PH06 = PIN(7, 6, NO_ADC); +const mcu_pin_obj_t pin_PH07 = PIN(7, 7, NO_ADC); +const mcu_pin_obj_t pin_PH08 = PIN(7, 8, NO_ADC); +const mcu_pin_obj_t pin_PH09 = PIN(7, 9, NO_ADC); +const mcu_pin_obj_t pin_PH10 = PIN(7, 10, NO_ADC); +const mcu_pin_obj_t pin_PH11 = PIN(7, 11, NO_ADC); +const mcu_pin_obj_t pin_PH12 = PIN(7, 12, NO_ADC); +const mcu_pin_obj_t pin_PH13 = PIN(7, 13, NO_ADC); +const mcu_pin_obj_t pin_PH14 = PIN(7, 14, NO_ADC); +const mcu_pin_obj_t pin_PH15 = PIN(7, 15, NO_ADC); + +const mcu_pin_obj_t pin_PI00 = PIN(8, 0, NO_ADC); +const mcu_pin_obj_t pin_PI01 = PIN(8, 1, NO_ADC); +const mcu_pin_obj_t pin_PI02 = PIN(8, 2, NO_ADC); +const mcu_pin_obj_t pin_PI03 = PIN(8, 3, NO_ADC); +const mcu_pin_obj_t pin_PI04 = PIN(8, 4, NO_ADC); +const mcu_pin_obj_t pin_PI05 = PIN(8, 5, NO_ADC); +const mcu_pin_obj_t pin_PI06 = PIN(8, 6, NO_ADC); +const mcu_pin_obj_t pin_PI07 = PIN(8, 7, NO_ADC); +const mcu_pin_obj_t pin_PI08 = PIN(8, 8, NO_ADC); +const mcu_pin_obj_t pin_PI09 = PIN(8, 9, NO_ADC); +const mcu_pin_obj_t pin_PI10 = PIN(8, 10, NO_ADC); +const mcu_pin_obj_t pin_PI11 = PIN(8, 11, NO_ADC); +const mcu_pin_obj_t pin_PI12 = PIN(8, 12, NO_ADC); +const mcu_pin_obj_t pin_PI13 = PIN(8, 13, NO_ADC); +const mcu_pin_obj_t pin_PI14 = PIN(8, 14, NO_ADC); +const mcu_pin_obj_t pin_PI15 = PIN(8, 15, NO_ADC); + +const mcu_pin_obj_t pin_PJ00 = PIN(9, 0, NO_ADC); +const mcu_pin_obj_t pin_PJ01 = PIN(9, 1, NO_ADC); +const mcu_pin_obj_t pin_PJ02 = PIN(9, 2, NO_ADC); +const mcu_pin_obj_t pin_PJ03 = PIN(9, 3, NO_ADC); +const mcu_pin_obj_t pin_PJ04 = PIN(9, 4, NO_ADC); +const mcu_pin_obj_t pin_PJ05 = PIN(9, 5, NO_ADC); +const mcu_pin_obj_t pin_PJ06 = PIN(9, 6, NO_ADC); +const mcu_pin_obj_t pin_PJ07 = PIN(9, 7, NO_ADC); +const mcu_pin_obj_t pin_PJ08 = PIN(9, 8, NO_ADC); +const mcu_pin_obj_t pin_PJ09 = PIN(9, 9, NO_ADC); +const mcu_pin_obj_t pin_PJ10 = PIN(9, 10, NO_ADC); +const mcu_pin_obj_t pin_PJ11 = PIN(9, 11, NO_ADC); +const mcu_pin_obj_t pin_PJ12 = PIN(9, 12, NO_ADC); +const mcu_pin_obj_t pin_PJ13 = PIN(9, 13, NO_ADC); +const mcu_pin_obj_t pin_PJ14 = PIN(9, 14, NO_ADC); +const mcu_pin_obj_t pin_PJ15 = PIN(9, 15, NO_ADC); + +const mcu_pin_obj_t pin_PK00 = PIN(10, 0, NO_ADC); +const mcu_pin_obj_t pin_PK01 = PIN(10, 1, NO_ADC); +const mcu_pin_obj_t pin_PK02 = PIN(10, 2, NO_ADC); +const mcu_pin_obj_t pin_PK03 = PIN(10, 3, NO_ADC); +const mcu_pin_obj_t pin_PK04 = PIN(10, 4, NO_ADC); +const mcu_pin_obj_t pin_PK05 = PIN(10, 5, NO_ADC); +const mcu_pin_obj_t pin_PK06 = PIN(10, 6, NO_ADC); +const mcu_pin_obj_t pin_PK07 = PIN(10, 7, NO_ADC); diff --git a/ports/stm/peripherals/stm32h7/stm32h743xx/pins.h b/ports/stm/peripherals/stm32h7/stm32h743xx/pins.h new file mode 100644 index 0000000000000..7c4650dca3e12 --- /dev/null +++ b/ports/stm/peripherals/stm32h7/stm32h743xx/pins.h @@ -0,0 +1,199 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MICROPY_INCLUDED_STM32_PERIPHERALS_STM32H743XX_PINS_H +#define MICROPY_INCLUDED_STM32_PERIPHERALS_STM32H743XX_PINS_H + +extern const mcu_pin_obj_t pin_PA00; +extern const mcu_pin_obj_t pin_PA01; +extern const mcu_pin_obj_t pin_PA02; +extern const mcu_pin_obj_t pin_PA03; +extern const mcu_pin_obj_t pin_PA04; +extern const mcu_pin_obj_t pin_PA05; +extern const mcu_pin_obj_t pin_PA06; +extern const mcu_pin_obj_t pin_PA07; +extern const mcu_pin_obj_t pin_PA08; +extern const mcu_pin_obj_t pin_PA09; +extern const mcu_pin_obj_t pin_PA10; +extern const mcu_pin_obj_t pin_PA11; +extern const mcu_pin_obj_t pin_PA12; +extern const mcu_pin_obj_t pin_PA13; +extern const mcu_pin_obj_t pin_PA14; +extern const mcu_pin_obj_t pin_PA15; +extern const mcu_pin_obj_t pin_PB00; +extern const mcu_pin_obj_t pin_PB01; +extern const mcu_pin_obj_t pin_PB02; +extern const mcu_pin_obj_t pin_PB03; +extern const mcu_pin_obj_t pin_PB04; +extern const mcu_pin_obj_t pin_PB05; +extern const mcu_pin_obj_t pin_PB06; +extern const mcu_pin_obj_t pin_PB07; +extern const mcu_pin_obj_t pin_PB08; +extern const mcu_pin_obj_t pin_PB09; +extern const mcu_pin_obj_t pin_PB10; +extern const mcu_pin_obj_t pin_PB11; +extern const mcu_pin_obj_t pin_PB12; +extern const mcu_pin_obj_t pin_PB13; +extern const mcu_pin_obj_t pin_PB14; +extern const mcu_pin_obj_t pin_PB15; +extern const mcu_pin_obj_t pin_PC00; +extern const mcu_pin_obj_t pin_PC01; +extern const mcu_pin_obj_t pin_PC02; +extern const mcu_pin_obj_t pin_PC03; +extern const mcu_pin_obj_t pin_PC04; +extern const mcu_pin_obj_t pin_PC05; +extern const mcu_pin_obj_t pin_PC06; +extern const mcu_pin_obj_t pin_PC07; +extern const mcu_pin_obj_t pin_PC08; +extern const mcu_pin_obj_t pin_PC09; +extern const mcu_pin_obj_t pin_PC10; +extern const mcu_pin_obj_t pin_PC11; +extern const mcu_pin_obj_t pin_PC12; +extern const mcu_pin_obj_t pin_PC13; +extern const mcu_pin_obj_t pin_PC14; +extern const mcu_pin_obj_t pin_PC15; +extern const mcu_pin_obj_t pin_PD00; +extern const mcu_pin_obj_t pin_PD01; +extern const mcu_pin_obj_t pin_PD02; +extern const mcu_pin_obj_t pin_PD03; +extern const mcu_pin_obj_t pin_PD04; +extern const mcu_pin_obj_t pin_PD05; +extern const mcu_pin_obj_t pin_PD06; +extern const mcu_pin_obj_t pin_PD07; +extern const mcu_pin_obj_t pin_PD08; +extern const mcu_pin_obj_t pin_PD09; +extern const mcu_pin_obj_t pin_PD10; +extern const mcu_pin_obj_t pin_PD11; +extern const mcu_pin_obj_t pin_PD12; +extern const mcu_pin_obj_t pin_PD13; +extern const mcu_pin_obj_t pin_PD14; +extern const mcu_pin_obj_t pin_PD15; +extern const mcu_pin_obj_t pin_PE00; +extern const mcu_pin_obj_t pin_PE01; +extern const mcu_pin_obj_t pin_PE02; +extern const mcu_pin_obj_t pin_PE03; +extern const mcu_pin_obj_t pin_PE04; +extern const mcu_pin_obj_t pin_PE05; +extern const mcu_pin_obj_t pin_PE06; +extern const mcu_pin_obj_t pin_PE07; +extern const mcu_pin_obj_t pin_PE08; +extern const mcu_pin_obj_t pin_PE09; +extern const mcu_pin_obj_t pin_PE10; +extern const mcu_pin_obj_t pin_PE11; +extern const mcu_pin_obj_t pin_PE12; +extern const mcu_pin_obj_t pin_PE13; +extern const mcu_pin_obj_t pin_PE14; +extern const mcu_pin_obj_t pin_PE15; +extern const mcu_pin_obj_t pin_PF00; +extern const mcu_pin_obj_t pin_PF01; +extern const mcu_pin_obj_t pin_PF02; +extern const mcu_pin_obj_t pin_PF03; +extern const mcu_pin_obj_t pin_PF04; +extern const mcu_pin_obj_t pin_PF05; +extern const mcu_pin_obj_t pin_PF06; +extern const mcu_pin_obj_t pin_PF07; +extern const mcu_pin_obj_t pin_PF08; +extern const mcu_pin_obj_t pin_PF09; +extern const mcu_pin_obj_t pin_PF10; +extern const mcu_pin_obj_t pin_PF11; +extern const mcu_pin_obj_t pin_PF12; +extern const mcu_pin_obj_t pin_PF13; +extern const mcu_pin_obj_t pin_PF14; +extern const mcu_pin_obj_t pin_PF15; +extern const mcu_pin_obj_t pin_PG00; +extern const mcu_pin_obj_t pin_PG01; +extern const mcu_pin_obj_t pin_PG02; +extern const mcu_pin_obj_t pin_PG03; +extern const mcu_pin_obj_t pin_PG04; +extern const mcu_pin_obj_t pin_PG05; +extern const mcu_pin_obj_t pin_PG06; +extern const mcu_pin_obj_t pin_PG07; +extern const mcu_pin_obj_t pin_PG08; +extern const mcu_pin_obj_t pin_PG09; +extern const mcu_pin_obj_t pin_PG10; +extern const mcu_pin_obj_t pin_PG11; +extern const mcu_pin_obj_t pin_PG12; +extern const mcu_pin_obj_t pin_PG13; +extern const mcu_pin_obj_t pin_PG14; +extern const mcu_pin_obj_t pin_PG15; +extern const mcu_pin_obj_t pin_PH00; +extern const mcu_pin_obj_t pin_PH01; +extern const mcu_pin_obj_t pin_PH02; +extern const mcu_pin_obj_t pin_PH03; +extern const mcu_pin_obj_t pin_PH04; +extern const mcu_pin_obj_t pin_PH05; +extern const mcu_pin_obj_t pin_PH06; +extern const mcu_pin_obj_t pin_PH07; +extern const mcu_pin_obj_t pin_PH08; +extern const mcu_pin_obj_t pin_PH09; +extern const mcu_pin_obj_t pin_PH10; +extern const mcu_pin_obj_t pin_PH11; +extern const mcu_pin_obj_t pin_PH12; +extern const mcu_pin_obj_t pin_PH13; +extern const mcu_pin_obj_t pin_PH14; +extern const mcu_pin_obj_t pin_PH15; +extern const mcu_pin_obj_t pin_PI00; +extern const mcu_pin_obj_t pin_PI01; +extern const mcu_pin_obj_t pin_PI02; +extern const mcu_pin_obj_t pin_PI03; +extern const mcu_pin_obj_t pin_PI04; +extern const mcu_pin_obj_t pin_PI05; +extern const mcu_pin_obj_t pin_PI06; +extern const mcu_pin_obj_t pin_PI07; +extern const mcu_pin_obj_t pin_PI08; +extern const mcu_pin_obj_t pin_PI09; +extern const mcu_pin_obj_t pin_PI10; +extern const mcu_pin_obj_t pin_PI11; +extern const mcu_pin_obj_t pin_PI12; +extern const mcu_pin_obj_t pin_PI13; +extern const mcu_pin_obj_t pin_PI14; +extern const mcu_pin_obj_t pin_PI15; +extern const mcu_pin_obj_t pin_PJ00; +extern const mcu_pin_obj_t pin_PJ01; +extern const mcu_pin_obj_t pin_PJ02; +extern const mcu_pin_obj_t pin_PJ03; +extern const mcu_pin_obj_t pin_PJ04; +extern const mcu_pin_obj_t pin_PJ05; +extern const mcu_pin_obj_t pin_PJ06; +extern const mcu_pin_obj_t pin_PJ07; +extern const mcu_pin_obj_t pin_PJ08; +extern const mcu_pin_obj_t pin_PJ09; +extern const mcu_pin_obj_t pin_PJ10; +extern const mcu_pin_obj_t pin_PJ11; +extern const mcu_pin_obj_t pin_PJ12; +extern const mcu_pin_obj_t pin_PJ13; +extern const mcu_pin_obj_t pin_PJ14; +extern const mcu_pin_obj_t pin_PJ15; +extern const mcu_pin_obj_t pin_PK00; +extern const mcu_pin_obj_t pin_PK01; +extern const mcu_pin_obj_t pin_PK02; +extern const mcu_pin_obj_t pin_PK03; +extern const mcu_pin_obj_t pin_PK04; +extern const mcu_pin_obj_t pin_PK05; +extern const mcu_pin_obj_t pin_PK06; +extern const mcu_pin_obj_t pin_PK07; + +#endif // MICROPY_INCLUDED_STM32_PERIPHERALS_STM32H743XX_PINS_H diff --git a/ports/stm/supervisor/port.c b/ports/stm/supervisor/port.c index 948e9f2e4a67e..fa377e74a9b1f 100644 --- a/ports/stm/supervisor/port.c +++ b/ports/stm/supervisor/port.c @@ -31,25 +31,29 @@ #include "tick.h" #include "common-hal/microcontroller/Pin.h" -#include "common-hal/busio/I2C.h" -#include "common-hal/busio/SPI.h" -#include "common-hal/busio/UART.h" -#include "common-hal/pulseio/PWMOut.h" -#include "common-hal/pulseio/PulseOut.h" -#include "common-hal/pulseio/PulseIn.h" -#include "stm32f4/clocks.h" -#include "stm32f4/gpio.h" +#if defined(STM32F4) + #include "common-hal/busio/I2C.h" + #include "common-hal/busio/SPI.h" + #include "common-hal/busio/UART.h" + #include "common-hal/pulseio/PWMOut.h" + #include "common-hal/pulseio/PulseOut.h" + #include "common-hal/pulseio/PulseIn.h" +#endif -#include "stm32f4xx_hal.h" +#include "clocks.h" +#include "gpio.h" safe_mode_t port_init(void) { HAL_Init(); __HAL_RCC_SYSCFG_CLK_ENABLE(); - __HAL_RCC_PWR_CLK_ENABLE(); + + #if defined(STM32F4) + __HAL_RCC_PWR_CLK_ENABLE(); + #endif - stm32f4_peripherals_clocks_init(); - stm32f4_peripherals_gpio_init(); + stm32_peripherals_clocks_init(); + stm32_peripherals_gpio_init(); tick_init(); @@ -58,12 +62,15 @@ safe_mode_t port_init(void) { void reset_port(void) { reset_all_pins(); - i2c_reset(); - spi_reset(); - uart_reset(); - pwmout_reset(); - pulseout_reset(); - pulsein_reset(); + + #if defined(STM32F4) + i2c_reset(); + spi_reset(); + uart_reset(); + pwmout_reset(); + pulseout_reset(); + pulsein_reset(); + #endif } void reset_to_bootloader(void) { diff --git a/ports/stm/supervisor/usb.c b/ports/stm/supervisor/usb.c index 358c2de5b37f3..a0c907a3d1746 100644 --- a/ports/stm/supervisor/usb.c +++ b/ports/stm/supervisor/usb.c @@ -30,7 +30,6 @@ #include "supervisor/usb.h" #include "lib/utils/interrupt_char.h" #include "lib/mp-readline/readline.h" -#include "stm32f4xx_hal.h" #include "py/mpconfig.h" @@ -74,7 +73,11 @@ void init_usb_hardware(void) { GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; + #if defined(STM32H7) + GPIO_InitStruct.Alternate = GPIO_AF10_OTG1_FS; + #else GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; + #endif HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); never_reset_pin_number(0, 11); never_reset_pin_number(0, 12); @@ -91,7 +94,11 @@ void init_usb_hardware(void) { GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + #if defined(STM32H7) + GPIO_InitStruct.Alternate = GPIO_AF10_OTG1_FS; + #else GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; + #endif HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); never_reset_pin_number(0, 10); @@ -103,10 +110,16 @@ void init_usb_hardware(void) { HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); never_reset_pin_number(0, 8); #endif - + + +#if defined(STM32H7) + HAL_PWREx_EnableUSBVoltageDetector(); + __HAL_RCC_USB2_OTG_FS_CLK_ENABLE(); +#else /* Peripheral clock enable */ __HAL_RCC_USB_OTG_FS_CLK_DISABLE(); __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); +#endif init_usb_vbus_sense(); } diff --git a/ports/stm/system_stm32h7xx.c b/ports/stm/system_stm32h7xx.c new file mode 100644 index 0000000000000..2132f26a0c61c --- /dev/null +++ b/ports/stm/system_stm32h7xx.c @@ -0,0 +1,425 @@ +/* + * Taken from ST Cube library and modified. See below for original header. + * + * Modifications copyright (c) 2020 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +/** + ****************************************************************************** + * @file system_stm32h7xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-Mx Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32h7xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock, it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32h7xx_system + * @{ + */ + +/** @addtogroup STM32H7xx_System_Private_Includes + * @{ + */ + +#include "stm32h7xx.h" +#include +#if !defined (HSE_VALUE) +#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (CSI_VALUE) + #define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* CSI_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to use initialized data in D2 domain SRAM (AHB SRAM) */ +/* #define DATA_IN_D2_SRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00000000UL /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 64000000; + uint32_t SystemD2Clock = 64000000; + const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the FPU setting and vector table location + * configuration. + * @param None + * @retval None + */ +void SystemInit (void) +{ +#if defined (DATA_IN_D2_SRAM) + __IO uint32_t tmpreg; +#endif /* DATA_IN_D2_SRAM */ + + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ + #endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= RCC_CR_HSION; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON , CSION,RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */ + RCC->CR &= 0xEAF6ED7FU; + +#if defined(D3_SRAM_BASE) + /* Reset D1CFGR register */ + RCC->D1CFGR = 0x00000000; + + /* Reset D2CFGR register */ + RCC->D2CFGR = 0x00000000; + + /* Reset D3CFGR register */ + RCC->D3CFGR = 0x00000000; +#else + /* Reset CDCFGR1 register */ + RCC->CDCFGR1 = 0x00000000; + + /* Reset CDCFGR2 register */ + RCC->CDCFGR2 = 0x00000000; + + /* Reset SRDCFGR register */ + RCC->SRDCFGR = 0x00000000; +#endif + /* Reset PLLCKSELR register */ + RCC->PLLCKSELR = 0x00000000; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x00000000; + /* Reset PLL1DIVR register */ + RCC->PLL1DIVR = 0x00000000; + /* Reset PLL1FRACR register */ + RCC->PLL1FRACR = 0x00000000; + + /* Reset PLL2DIVR register */ + RCC->PLL2DIVR = 0x00000000; + + /* Reset PLL2FRACR register */ + + RCC->PLL2FRACR = 0x00000000; + /* Reset PLL3DIVR register */ + RCC->PLL3DIVR = 0x00000000; + + /* Reset PLL3FRACR register */ + RCC->PLL3FRACR = 0x00000000; + + /* Reset HSEBYP bit */ + RCC->CR &= 0xFFFBFFFFU; + + /* Disable all interrupts */ + RCC->CIER = 0x00000000; + +#if (STM32H7_DEV_ID == 0x450UL) + /* dual core CM7 or single core line */ + if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U) + { + /* if stm32h7 revY*/ + /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ + *((__IO uint32_t*)0x51008108) = 0x000000001U; + } +#endif + +#if defined (DATA_IN_D2_SRAM) + /* in case of initialized data in D2 SRAM (AHB SRAM) , enable the D2 SRAM clock (AHB SRAM clock) */ +#if defined(RCC_AHB2ENR_D2SRAM3EN) + RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN); +#elif defined(RCC_AHB2ENR_D2SRAM2EN) + RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN); +#else + RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN); +#endif /* RCC_AHB2ENR_D2SRAM3EN */ + + tmpreg = RCC->AHB2ENR; + (void) tmpreg; +#endif /* DATA_IN_D2_SRAM */ + +#if defined(DUAL_CORE) && defined(CORE_CM4) + /* Configure the Vector Table location add offset address for cortex-M4 ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = D2_AHBSRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BANK2_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif /* VECT_TAB_SRAM */ + +#else + + /* Configure the Vector Table location add offset address for cortex-M7 ------------------*/ +#if !(BOARD_VTOR_DEFER) //only set VTOR if the bootloader hasn't already + #ifdef VECT_TAB_SRAM + SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal AXI-RAM */ + #else + SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ + #endif +#endif + +#endif /*DUAL_CORE && CORE_CM4*/ + +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock , it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*) + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*), + * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. + * + * (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value + * 64 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp; + uint32_t common_system_clock; + float_t fracn1, pllvco; + + + /* Get SYSCLK source -------------------------------------------------------*/ + + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ + common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); + break; + + case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ + common_system_clock = CSI_VALUE; + break; + + case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ + common_system_clock = HSE_VALUE; + break; + + case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); + pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ; + pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos); + fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3)); + + if (pllm != 0U) + { + switch (pllsource) + { + case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */ + + hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ; + pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + + break; + + case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */ + pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + break; + + case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */ + pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + break; + + default: + pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + break; + } + pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ; + common_system_clock = (uint32_t)(float_t)(pllvco/(float_t)pllp); + } + else + { + common_system_clock = 0U; + } + break; + + default: + common_system_clock = CSI_VALUE; + break; + } + + /* Compute SystemClock frequency --------------------------------------------------*/ +#if defined (RCC_D1CFGR_D1CPRE) + tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]; + + /* common_system_clock frequency : CM7 CPU frequency */ + common_system_clock >>= tmp; + + /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */ + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); + +#else + tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]; + + /* common_system_clock frequency : CM7 CPU frequency */ + common_system_clock >>= tmp; + + /* SystemD2Clock frequency : AXI and AHBs Clock frequency */ + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); + +#endif + +#if defined(DUAL_CORE) && defined(CORE_CM4) + SystemCoreClock = SystemD2Clock; +#else + SystemCoreClock = common_system_clock; +#endif /* DUAL_CORE && CORE_CM4 */ +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/ports/stm/tick.c b/ports/stm/tick.c index f4adf183aa66d..67adc84e30c65 100644 --- a/ports/stm/tick.c +++ b/ports/stm/tick.c @@ -30,8 +30,6 @@ #include "supervisor/shared/tick.h" #include "shared-bindings/microcontroller/Processor.h" -#include "stm32f4xx.h" - void SysTick_Handler(void) { // SysTick interrupt handler called when the SysTick timer reaches zero // (every millisecond). diff --git a/ports/stm/tick.h b/ports/stm/tick.h index 999acc7a3c989..17e96362dd600 100644 --- a/ports/stm/tick.h +++ b/ports/stm/tick.h @@ -23,8 +23,8 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ -#ifndef MICROPY_INCLUDED_STM32F4_TICK_H -#define MICROPY_INCLUDED_STM32F4_TICK_H +#ifndef MICROPY_INCLUDED_STM32_TICK_H +#define MICROPY_INCLUDED_STM32_TICK_H #include "py/mpconfig.h" @@ -41,4 +41,4 @@ void current_tick(uint64_t* ms, uint32_t* us_until_ms); // ticks_ms to increment. void wait_until(uint64_t ms, uint32_t us_until_ms); -#endif // MICROPY_INCLUDED_STM32F4_TICK_H +#endif // MICROPY_INCLUDED_STM32_TICK_H diff --git a/ports/stm/tools/parse_af_csv.py b/ports/stm/tools/parse_af_csv.py new file mode 100644 index 0000000000000..4ab636d79f7a4 --- /dev/null +++ b/ports/stm/tools/parse_af_csv.py @@ -0,0 +1,137 @@ +# This file is part of the MicroPython project, http://micropython.org/ +# +# The MIT License (MIT) +# +# Copyright (c) 2020 Lucian Copeland for Adafruit Industries +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +import csv +import sys + +# Use: parse_af_csf.py Filename.csv -pins-only + +# Most peripherals (SPI, I2C) output 3 values: +# peripheral index, alt function, pin string +def evaluate_periph(inper, inlist, periph, subtype, altfn, pin): + # ex) SPI1_SCK,SPI3_SCK/I2S3_CK + # Clean anything after a '\' due to SPI/I2S mixing + if not inper.find('/') == -1: + inper = inper[:inper.find('/')] + + if inper[:len(periph)] == periph and inper[-len(subtype):] == subtype: + inlist.append([inper[len(periph):len(periph)+1], altfn, pin]) + +# Timers (TIM) are a special case with 4 values +# timer index, alt function, channel, pin string +def evaluate_tim(inper, inlist, altfn, pin): + # ex) TIM2_CH1/TIM2_ETR, TIM5_CH1 + # Clean anything after a '\' to filter ETR + if not inper.find('/') == -1: + inper = inper[:inper.find('/')] + + if inper[:3] == "TIM" and inper[5:7] == "CH" and inper[-1:] != 'N': + inlist.append([inper[3:4],altfn,inper[-1:],pin]) + +# Open target file +with open(sys.argv[1]) as csv_file: + csv_reader = csv.reader(csv_file, delimiter=',') + line_count = 0 + + if sys.argv[2] != "-pins-only": + # List of peripheral pin types to read + todo = [ + ["I2C","SDA"], + ["I2C","SCL"], + ["SPI","SCK"], + ["SPI","MOSI"], + ["SPI","MISO"], + ["UART","TX"], + ["UART","RX"]] + + # Make a list of empty lists to populate + outlist = [] + for items in todo: + empty = [] + outlist.append(empty) + # TIM + empty = [] + outlist.append(empty) + + # Each line is a list of strings + for row in csv_reader: + altfn = 0 + pin = row[1] + if len(pin) < 4: + pin = pin[:2] + '0' + pin[2:] + for col in row: + array_index = 0 + # Evaluate the string for every possible todo entry + for item in todo: + evaluate_periph(col, outlist[array_index], item[0], item[1], altfn - 2, pin) + # UART special case, run again for USART variant + if item[0] == "UART": + evaluate_periph(col, outlist[array_index], "USART", item[1], altfn - 2, pin) + array_index += 1 + # TIM special case + evaluate_tim(col, outlist[-1], altfn - 2, pin) + altfn += 1 + line_count += 1 + + # Print formatted output + for i in range(len(todo)): + ins = (todo[i][0]).lower() + '_' + (todo[i][1]).lower() + '_' + # const mcu_i2c_sda_obj_t mcu_i2c_sda_list[4] = { + print("const mcu_" + ins + "obj_t mcu_" + ins + "list[" + str(len(outlist[i])) + "] = {") + for row in outlist[i]: + print(" PERIPH(" + row[0] + ", " + str(row[1]) + ", &pin_" + row[2] + "),") + print("};") + + # Timer special case: + print("const mcu_tim_pin_obj_t mcu_tim_pin_list[" + str(len(outlist[-1])) + "] = {") + for row in outlist[-1]: + print(" TIM(" + row[0] + ", " + str(row[1]) + ", " + str(row[2]) + ", &pin_" + row[3] + "),") + print("};") + + else: + # Format all viable pins listed + # ex) const mcu_pin_obj_t pin_PE02 = PIN(4, 2, NO_ADC); + # ex 2) extern const mcu_pin_obj_t pin_PE02; + # TODO: add ADC detection + outlist = [] + + for row in csv_reader: + altfn = 0 + pin = row[1] + if len(pin) < 4: + pin = pin[:2] + '0' + pin[2:] + outlist.append([pin, str(ord(row[1][1:2]) - 65), row[1][2:4]]) + line_count += 1 + + for line in outlist: + print("const mcu_pin_obj_t pin_" + line[0] + " = PIN(" + line[1] + ", " + line[2] + ", NO_ADC);") + + for line in outlist: + print("extern const mcu_pin_obj_t pin_" + line[0] + ";") + + + + + print(f'Processed {line_count} lines.') + From 7995bcac4009d2b3e20f42a26de72d5411e7e462 Mon Sep 17 00:00:00 2001 From: Lucian Copeland Date: Fri, 27 Mar 2020 14:15:33 -0400 Subject: [PATCH 03/17] Flash additions --- ports/stm/supervisor/internal_flash.c | 107 ++++++++++++++++++++++++-- 1 file changed, 101 insertions(+), 6 deletions(-) diff --git a/ports/stm/supervisor/internal_flash.c b/ports/stm/supervisor/internal_flash.c index 046b26baf2786..46ccd218cd083 100644 --- a/ports/stm/supervisor/internal_flash.c +++ b/ports/stm/supervisor/internal_flash.c @@ -36,8 +36,6 @@ #include "py/runtime.h" #include "lib/oofatfs/ff.h" -#include "stm32f4xx_hal.h" - typedef struct { uint32_t base_address; uint32_t sector_size; @@ -62,7 +60,11 @@ static const flash_layout_t flash_layout[] = { #endif }; -static uint8_t sector_copy[0x4000] __attribute__((aligned(4))); +#define NO_CACHE 0xffffffff +#define MAX_CACHE 0x4000 + +static uint8_t _flash_cache[0x4000] __attribute__((aligned(4))); +static uint32_t _cache_flash_addr = NO_CACHE; //Return the sector of a given flash address. uint32_t flash_get_sector_info(uint32_t addr, uint32_t *start_addr, uint32_t *size) { @@ -101,6 +103,56 @@ uint32_t supervisor_flash_get_block_count(void) { } void supervisor_flash_flush(void) { + if (_cache_flash_addr == NO_CACHE) return; + + // Skip if data is the same + if (memcmp(_flash_cache, (void *)_flash_page_addr, FLASH_PAGE_SIZE) != 0) { + // unlock flash + HAL_FLASH_Unlock(); + + // set up for erase + FLASH_EraseInitTypeDef EraseInitStruct; + EraseInitStruct.TypeErase = TYPEERASE_SECTORS; + EraseInitStruct.VoltageRange = VOLTAGE_RANGE_3; // voltage range needs to be 2.7V to 3.6V + // get the sector information + uint32_t sector_size; + uint32_t sector_start_addr; + EraseInitStruct.Sector = flash_get_sector_info(_cache_flash_addr, §or_start_addr, §or_size); + EraseInitStruct.NbSectors = 1; + if (sector_size>0x4000) return false; + + // erase the sector + uint32_t SectorError = 0; + if (HAL_FLASHEx_Erase(&EraseInitStruct, &SectorError) != HAL_OK) { + // error occurred during sector erase + HAL_FLASH_Lock(); // lock the flash + mp_printf(&mp_plat_print, "FLASH SECTOR ERASE ERROR"); + return false; + } + + __HAL_FLASH_DATA_CACHE_DISABLE(); + __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); + + __HAL_FLASH_DATA_CACHE_RESET(); + __HAL_FLASH_INSTRUCTION_CACHE_RESET(); + + __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); + __HAL_FLASH_DATA_CACHE_ENABLE(); + + // reprogram the sector + for (uint32_t i = 0; i < sector_size; i++) { + if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_BYTE, sector_start_addr, (uint64_t)_flash_cache[i]) != HAL_OK) { + // error occurred during flash write + HAL_FLASH_Lock(); // lock the flash + mp_printf(&mp_plat_print, "FLASH WRITE ERROR"); + return false; + } + sector_start_addr += 1; + } + + // lock the flash + HAL_FLASH_Lock(); + } } static int32_t convert_block_to_flash_addr(uint32_t block) { @@ -189,13 +241,56 @@ bool supervisor_flash_write_block(const uint8_t *src, uint32_t block) { return true; } +// mp_uint_t supervisor_flash_write_blocks(const uint8_t *src, uint32_t block_num, uint32_t num_blocks) { + +// for (size_t i = 0; i < num_blocks; i++) { +// if (!supervisor_flash_write_block(src + i * FILESYSTEM_BLOCK_SIZE, block_num + i)) { +// return 1; // error +// } +// } +// return 0; // success +// } + mp_uint_t supervisor_flash_write_blocks(const uint8_t *src, uint32_t block_num, uint32_t num_blocks) { + while (num_blocks) { + int32_t dest = convert_block_to_flash_addr(block); + if (dest == -1) { + // bad block number + mp_printf(&mp_plat_print, "BAD FLASH BLOCK ERROR"); + return false; + } + + // unlock flash + HAL_FLASH_Unlock(); + + flash_get_sector_info(dest, §or_start_addr, §or_size); - for (size_t i = 0; i < num_blocks; i++) { - if (!supervisor_flash_write_block(src + i * FILESYSTEM_BLOCK_SIZE, block_num + i)) { - return 1; // error + // Fail for any sector outside the 16k ones for now + if (sector_size > 0x4000) return false; + + // Find how many blocks are left in the sector + uint32_t count = (sector_size - (dest - sector_start_addr))/FILESYSTEM_BLOCK_SIZE; + count = MIN(num_blocks, count); ` + + if (_cache_flash_addr != sector_start_addr) { + // Write out anything in cache before overwriting it. + supervisor_flash_flush(); + + _cache_flash_addr = sector_start_addr; + + // Copy the current contents of the entire page into the cache. + memcpy(_flash_cache, (void *)sector_start_addr, sector_size); } + + // Overwrite part or all of the sector cache with the src data. + memcpy(_flash_cache + (dest-sector_start_addr), src, count * FILESYSTEM_BLOCK_SIZE); + + // adjust for next run + block_num += count; + src += count * FILESYSTEM_BLOCK_SIZE; + num_blocks -= count; } + return 0; // success } From e2be0696865992cda67f5bdeba5aeb5b4c2fdcd4 Mon Sep 17 00:00:00 2001 From: Lucian Copeland Date: Sat, 28 Mar 2020 18:30:46 -0400 Subject: [PATCH 04/17] Support cached internal flash on the H743 --- ports/stm/Makefile | 5 +- .../board.c | 0 .../mpconfigboard.h | 0 .../mpconfigboard.mk | 4 +- .../pins.c | 2 +- .../stm32h7xx_hal_conf.h | 0 ports/stm/peripherals/periph.h | 11 +- ports/stm/supervisor/internal_flash.c | 241 ++++++++++-------- ports/stm/supervisor/internal_flash.h | 28 +- ports/stm/tools/examples/nucleo_h743.csv | 130 ++++++++++ ports/stm/tools/examples/stm32f405.csv | 142 +++++++++++ ports/stm/tools/parse_af_csv.py | 8 +- ports/stm/tools/parse_pins_csv.py | 49 ++++ 13 files changed, 485 insertions(+), 135 deletions(-) rename ports/stm/boards/{stm32h743zi_discovery => stm32h743zi2_discovery}/board.c (100%) rename ports/stm/boards/{stm32h743zi_discovery => stm32h743zi2_discovery}/mpconfigboard.h (100%) rename ports/stm/boards/{stm32h743zi_discovery => stm32h743zi2_discovery}/mpconfigboard.mk (81%) rename ports/stm/boards/{stm32h743zi_discovery => stm32h743zi2_discovery}/pins.c (99%) rename ports/stm/boards/{stm32h743zi_discovery => stm32h743zi2_discovery}/stm32h7xx_hal_conf.h (100%) create mode 100644 ports/stm/tools/examples/nucleo_h743.csv create mode 100644 ports/stm/tools/examples/stm32f405.csv create mode 100644 ports/stm/tools/parse_pins_csv.py diff --git a/ports/stm/Makefile b/ports/stm/Makefile index 2eedcca1133b1..ef70cad81e07f 100755 --- a/ports/stm/Makefile +++ b/ports/stm/Makefile @@ -187,10 +187,7 @@ SRC_STM32 = $(addprefix $(HAL_DIR)/Src/stm32$(MCU_SERIES_LOWER)xx_,\ ll_rcc.c \ ll_utils.c \ ll_exti.c \ - ) -#removed: -# hal_flash_ramfunc.c \ -# ll_fsmc.c \ +) SRC_STM32 += system_stm32$(MCU_SERIES_LOWER)xx.c diff --git a/ports/stm/boards/stm32h743zi_discovery/board.c b/ports/stm/boards/stm32h743zi2_discovery/board.c similarity index 100% rename from ports/stm/boards/stm32h743zi_discovery/board.c rename to ports/stm/boards/stm32h743zi2_discovery/board.c diff --git a/ports/stm/boards/stm32h743zi_discovery/mpconfigboard.h b/ports/stm/boards/stm32h743zi2_discovery/mpconfigboard.h similarity index 100% rename from ports/stm/boards/stm32h743zi_discovery/mpconfigboard.h rename to ports/stm/boards/stm32h743zi2_discovery/mpconfigboard.h diff --git a/ports/stm/boards/stm32h743zi_discovery/mpconfigboard.mk b/ports/stm/boards/stm32h743zi2_discovery/mpconfigboard.mk similarity index 81% rename from ports/stm/boards/stm32h743zi_discovery/mpconfigboard.mk rename to ports/stm/boards/stm32h743zi2_discovery/mpconfigboard.mk index d2f89053683b7..3a37ffe75df92 100644 --- a/ports/stm/boards/stm32h743zi_discovery/mpconfigboard.mk +++ b/ports/stm/boards/stm32h743zi2_discovery/mpconfigboard.mk @@ -2,9 +2,9 @@ USB_VID = 0x239A #REPLACE USB_PID = 0x808A #REPLACE USB_PRODUCT = "STM32H743ZI Discovery Board - CPy" USB_MANUFACTURER = "STMicroelectronics" -USB_DEVICES = "CDC,HID" +USB_DEVICES = "CDC,MSC" -DISABLE_FILESYSTEM = 1 +INTERNAL_FLASH_FILESYSTEM = 1 MCU_SERIES = H7 MCU_VARIANT = STM32H743xx diff --git a/ports/stm/boards/stm32h743zi_discovery/pins.c b/ports/stm/boards/stm32h743zi2_discovery/pins.c similarity index 99% rename from ports/stm/boards/stm32h743zi_discovery/pins.c rename to ports/stm/boards/stm32h743zi2_discovery/pins.c index eceea93820c97..dc2db9e184ee1 100644 --- a/ports/stm/boards/stm32h743zi_discovery/pins.c +++ b/ports/stm/boards/stm32h743zi2_discovery/pins.c @@ -86,7 +86,7 @@ STATIC const mp_rom_map_elem_t board_module_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_DAC1), MP_ROM_PTR(&pin_PA04) }, { MP_ROM_QSTR(MP_QSTR_DAC2), MP_ROM_PTR(&pin_PA05) }, { MP_ROM_QSTR(MP_QSTR_LED1), MP_ROM_PTR(&pin_PB00) }, - { MP_ROM_QSTR(MP_QSTR_LED2), MP_ROM_PTR(&pin_PB07) }, + { MP_ROM_QSTR(MP_QSTR_LED2), MP_ROM_PTR(&pin_PE01) }, { MP_ROM_QSTR(MP_QSTR_LED3), MP_ROM_PTR(&pin_PB14) }, { MP_ROM_QSTR(MP_QSTR_SW), MP_ROM_PTR(&pin_PC13) }, { MP_ROM_QSTR(MP_QSTR_I2C1_SDA), MP_ROM_PTR(&pin_PB09) }, diff --git a/ports/stm/boards/stm32h743zi_discovery/stm32h7xx_hal_conf.h b/ports/stm/boards/stm32h743zi2_discovery/stm32h7xx_hal_conf.h similarity index 100% rename from ports/stm/boards/stm32h743zi_discovery/stm32h7xx_hal_conf.h rename to ports/stm/boards/stm32h743zi2_discovery/stm32h7xx_hal_conf.h diff --git a/ports/stm/peripherals/periph.h b/ports/stm/peripherals/periph.h index aaf41361e67b2..394ab25b119eb 100644 --- a/ports/stm/peripherals/periph.h +++ b/ports/stm/peripherals/periph.h @@ -33,12 +33,12 @@ #include STM32_HAL_H #include "pins.h" -// PERIPH +// Comm Peripherals typedef struct { - uint8_t periph_index:4; // Index of the I2C unit (1 to 3) - uint8_t altfn_index:4; //Index of the altfn for this pin (0 to 15) - const mcu_pin_obj_t * pin; + uint8_t periph_index:4; // Index of the peripheral instance + uint8_t altfn_index:4; // Index of the altfn for this pin (0 to 15) + const mcu_pin_obj_t * pin; // Pin Object } mcu_periph_obj_t; #define PERIPH(index, alt, p_pin) \ @@ -48,7 +48,8 @@ typedef struct { .pin = p_pin, \ } -//Timers +// Timer Peripheral + typedef struct { uint8_t tim_index:4; uint8_t altfn_index:4; diff --git a/ports/stm/supervisor/internal_flash.c b/ports/stm/supervisor/internal_flash.c index 46ccd218cd083..003ccdd908e80 100644 --- a/ports/stm/supervisor/internal_flash.c +++ b/ports/stm/supervisor/internal_flash.c @@ -4,7 +4,7 @@ * The MIT License (MIT) * * Copyright (c) 2013, 2014 Damien P. George - * Copyright (c) 2019 Lucian Copeland for Adafruit Industries + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -35,6 +35,7 @@ #include "py/obj.h" #include "py/runtime.h" #include "lib/oofatfs/ff.h" +#include "supervisor/shared/safe_mode.h" typedef struct { uint32_t base_address; @@ -46,7 +47,9 @@ typedef struct { /* Internal Flash API *------------------------------------------------------------------*/ -static const flash_layout_t flash_layout[] = { +#if defined(STM32F4) + +STATIC const flash_layout_t flash_layout[] = { { 0x08000000, 0x04000, 4 }, { 0x08010000, 0x10000, 1 }, { 0x08020000, 0x20000, 3 }, @@ -59,12 +62,45 @@ static const flash_layout_t flash_layout[] = { { 0x08120000, 0x20000, 7 }, #endif }; +STATIC uint8_t _flash_cache[0x4000] __attribute__((aligned(4))); + +#elif defined(STM32H7) + +STATIC const flash_layout_t flash_layout[] = { + { 0x08000000, 0x20000, 16 }, +}; +STATIC uint8_t _flash_cache[0x20000] __attribute__((aligned(4))); + +#else + #error Unsupported processor +#endif #define NO_CACHE 0xffffffff #define MAX_CACHE 0x4000 -static uint8_t _flash_cache[0x4000] __attribute__((aligned(4))); -static uint32_t _cache_flash_addr = NO_CACHE; + +STATIC uint32_t _cache_flash_addr = NO_CACHE; + +#if defined(STM32H7) +// get the bank of a given flash address +STATIC uint32_t get_bank(uint32_t addr) { + if (READ_BIT(FLASH->OPTCR, FLASH_OPTCR_SWAP_BANK) == 0) { + // no bank swap + if (addr < (FLASH_BASE + FLASH_BANK_SIZE)) { + return FLASH_BANK_1; + } else { + return FLASH_BANK_2; + } + } else { + // bank swap + if (addr < (FLASH_BASE + FLASH_BANK_SIZE)) { + return FLASH_BANK_2; + } else { + return FLASH_BANK_1; + } + } +} +#endif //Return the sector of a given flash address. uint32_t flash_get_sector_info(uint32_t addr, uint32_t *start_addr, uint32_t *size) { @@ -105,50 +141,98 @@ uint32_t supervisor_flash_get_block_count(void) { void supervisor_flash_flush(void) { if (_cache_flash_addr == NO_CACHE) return; + #if defined(STM32H7) + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS_BANK1 | FLASH_FLAG_ALL_ERRORS_BANK2); + #else + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | + FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR); + #endif + + // set up for erase + FLASH_EraseInitTypeDef EraseInitStruct; + EraseInitStruct.TypeErase = TYPEERASE_SECTORS; + EraseInitStruct.VoltageRange = VOLTAGE_RANGE_3; // voltage range needs to be 2.7V to 3.6V + // get the sector information + uint32_t sector_size; + uint32_t sector_start_addr; + #if defined(STM32H7) + EraseInitStruct.Banks = get_bank(_cache_flash_addr); + #endif + EraseInitStruct.Sector = flash_get_sector_info(_cache_flash_addr, §or_start_addr, §or_size); + EraseInitStruct.NbSectors = 1; + if (sector_size > sizeof(_flash_cache)) { + __ASM volatile ("bkpt"); + mp_printf(&mp_plat_print, "FLASH ERR: invalid sector\n"); + reset_into_safe_mode(FLASH_WRITE_FAIL); + } + // Skip if data is the same - if (memcmp(_flash_cache, (void *)_flash_page_addr, FLASH_PAGE_SIZE) != 0) { + if (memcmp(_flash_cache, (void *)_cache_flash_addr, sector_size) != 0) { // unlock flash HAL_FLASH_Unlock(); - // set up for erase - FLASH_EraseInitTypeDef EraseInitStruct; - EraseInitStruct.TypeErase = TYPEERASE_SECTORS; - EraseInitStruct.VoltageRange = VOLTAGE_RANGE_3; // voltage range needs to be 2.7V to 3.6V - // get the sector information - uint32_t sector_size; - uint32_t sector_start_addr; - EraseInitStruct.Sector = flash_get_sector_info(_cache_flash_addr, §or_start_addr, §or_size); - EraseInitStruct.NbSectors = 1; - if (sector_size>0x4000) return false; - // erase the sector uint32_t SectorError = 0; if (HAL_FLASHEx_Erase(&EraseInitStruct, &SectorError) != HAL_OK) { // error occurred during sector erase HAL_FLASH_Lock(); // lock the flash - mp_printf(&mp_plat_print, "FLASH SECTOR ERASE ERROR"); - return false; + __ASM volatile ("bkpt"); + mp_printf(&mp_plat_print, "FLASH ERR: erase failure\n"); + reset_into_safe_mode(FLASH_WRITE_FAIL); } - __HAL_FLASH_DATA_CACHE_DISABLE(); - __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); - - __HAL_FLASH_DATA_CACHE_RESET(); - __HAL_FLASH_INSTRUCTION_CACHE_RESET(); - - __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); - __HAL_FLASH_DATA_CACHE_ENABLE(); + // __HAL_FLASH_DATA_CACHE_DISABLE(); + // __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); + + // __HAL_FLASH_DATA_CACHE_RESET(); + // __HAL_FLASH_INSTRUCTION_CACHE_RESET(); + + // __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); + // __HAL_FLASH_DATA_CACHE_ENABLE(); + + // // reprogram the sector + // for (uint32_t i = 0; i < sector_size; i++) { + // if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_BYTE, sector_start_addr, (uint64_t)_flash_cache[i]) != HAL_OK) { + // // error occurred during flash write + // HAL_FLASH_Lock(); // lock the flash + // mp_printf(&mp_plat_print, "FLASH WRITE ERROR"); + // } + // sector_start_addr += 1; + // } + + uint32_t * cache_addr = (uint32_t*)_flash_cache; + + #if defined(STM32H7) + for (uint32_t i = 0; i < (sector_size / 32); i++) { + // Note that the STM32H7 HAL interface differs by taking an address, not 64 bit data + // This is because ST's code is written by a large room of chimpanzees + if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_FLASHWORD, sector_start_addr, + (uint32_t)cache_addr) != HAL_OK) { + // error occurred during flash write + HAL_FLASH_Lock(); // lock the flash + __ASM volatile ("bkpt"); + reset_into_safe_mode(FLASH_WRITE_FAIL); + } + // RAM memory is by word (4 byte), but flash memory is by byte + cache_addr += 8; + sector_start_addr += 32; + } - // reprogram the sector - for (uint32_t i = 0; i < sector_size; i++) { - if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_BYTE, sector_start_addr, (uint64_t)_flash_cache[i]) != HAL_OK) { + #else // STM32F4 + // program the flash word by word + for (uint32_t i = 0; i < sector_size / 4; i++) { + if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, sector_start_addr, + (uint64_t)*cache_addr) != HAL_OK) { // error occurred during flash write HAL_FLASH_Lock(); // lock the flash - mp_printf(&mp_plat_print, "FLASH WRITE ERROR"); - return false; + __ASM volatile ("bkpt"); + reset_into_safe_mode(FLASH_WRITE_FAIL); } - sector_start_addr += 1; + // RAM memory is by word (4 byte), but flash memory is by byte + cache_addr += 1; + sector_start_addr += 4; } + #endif // lock the flash HAL_FLASH_Lock(); @@ -165,6 +249,9 @@ static int32_t convert_block_to_flash_addr(uint32_t block) { } mp_uint_t supervisor_flash_read_blocks(uint8_t *dest, uint32_t block, uint32_t num_blocks) { + // Must write out anything in cache before trying to read. + supervisor_flash_flush(); + int32_t src = convert_block_to_flash_addr(block); if (src == -1) { // bad block number @@ -174,88 +261,12 @@ mp_uint_t supervisor_flash_read_blocks(uint8_t *dest, uint32_t block, uint32_t n return 0; // success } -bool supervisor_flash_write_block(const uint8_t *src, uint32_t block) { - int32_t dest = convert_block_to_flash_addr(block); - if (dest == -1) { - // bad block number - mp_printf(&mp_plat_print, "BAD FLASH BLOCK ERROR"); - return false; - } - - // unlock flash - HAL_FLASH_Unlock(); - - // set up for erase - FLASH_EraseInitTypeDef EraseInitStruct; - EraseInitStruct.TypeErase = TYPEERASE_SECTORS; - EraseInitStruct.VoltageRange = VOLTAGE_RANGE_3; // voltage range needs to be 2.7V to 3.6V - // get the sector information - uint32_t sector_size; - uint32_t sector_start_addr; - EraseInitStruct.Sector = flash_get_sector_info(dest, §or_start_addr, §or_size); - EraseInitStruct.NbSectors = 1; - if (sector_size>0x4000) return false; - - // copy the sector - memcpy(sector_copy,(void *)sector_start_addr,sector_size); - - // // overwrite sector data - memcpy(sector_copy+(dest-sector_start_addr),src,FILESYSTEM_BLOCK_SIZE); - - // find end address, subtract for number of sectors - // Shouldn't be required since blocks will always fit in a single sector, they should never overlap - //EraseInitStruct.NbSectors = flash_get_sector_info(dest + FILESYSTEM_BLOCK_SIZE - 1, NULL, NULL) - EraseInitStruct.Sector + 1; - - // erase the sector - uint32_t SectorError = 0; - if (HAL_FLASHEx_Erase(&EraseInitStruct, &SectorError) != HAL_OK) { - // error occurred during sector erase - HAL_FLASH_Lock(); // lock the flash - mp_printf(&mp_plat_print, "FLASH SECTOR ERASE ERROR"); - return false; - } - - __HAL_FLASH_DATA_CACHE_DISABLE(); - __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); - - __HAL_FLASH_DATA_CACHE_RESET(); - __HAL_FLASH_INSTRUCTION_CACHE_RESET(); - - __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); - __HAL_FLASH_DATA_CACHE_ENABLE(); - - // reprogram the sector - for (uint32_t i = 0; i < sector_size; i++) { - if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_BYTE, sector_start_addr, (uint64_t)sector_copy[i]) != HAL_OK) { - // error occurred during flash write - HAL_FLASH_Lock(); // lock the flash - mp_printf(&mp_plat_print, "FLASH WRITE ERROR"); - return false; - } - sector_start_addr += 1; - } - - // lock the flash - HAL_FLASH_Lock(); - - return true; -} - -// mp_uint_t supervisor_flash_write_blocks(const uint8_t *src, uint32_t block_num, uint32_t num_blocks) { - -// for (size_t i = 0; i < num_blocks; i++) { -// if (!supervisor_flash_write_block(src + i * FILESYSTEM_BLOCK_SIZE, block_num + i)) { -// return 1; // error -// } -// } -// return 0; // success -// } - mp_uint_t supervisor_flash_write_blocks(const uint8_t *src, uint32_t block_num, uint32_t num_blocks) { while (num_blocks) { - int32_t dest = convert_block_to_flash_addr(block); + int32_t dest = convert_block_to_flash_addr(block_num); if (dest == -1) { // bad block number + __ASM volatile ("bkpt"); mp_printf(&mp_plat_print, "BAD FLASH BLOCK ERROR"); return false; } @@ -263,14 +274,20 @@ mp_uint_t supervisor_flash_write_blocks(const uint8_t *src, uint32_t block_num, // unlock flash HAL_FLASH_Unlock(); + uint32_t sector_size; + uint32_t sector_start_addr; flash_get_sector_info(dest, §or_start_addr, §or_size); // Fail for any sector outside the 16k ones for now - if (sector_size > 0x4000) return false; + if (sector_size > sizeof(_flash_cache)) { + __ASM volatile ("bkpt"); + mp_printf(&mp_plat_print, "FLASH ERR: invalid sector\n"); + reset_into_safe_mode(FLASH_WRITE_FAIL); + } // Find how many blocks are left in the sector uint32_t count = (sector_size - (dest - sector_start_addr))/FILESYSTEM_BLOCK_SIZE; - count = MIN(num_blocks, count); ` + count = MIN(num_blocks, count); if (_cache_flash_addr != sector_start_addr) { // Write out anything in cache before overwriting it. diff --git a/ports/stm/supervisor/internal_flash.h b/ports/stm/supervisor/internal_flash.h index 859470ff0983f..37f0b25e46a34 100644 --- a/ports/stm/supervisor/internal_flash.h +++ b/ports/stm/supervisor/internal_flash.h @@ -4,7 +4,7 @@ * The MIT License (MIT) * * Copyright (c) 2013, 2014 Damien P. George - * Copyright (c) 2019 Lucian Copeland for Adafruit Industries + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -24,8 +24,8 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ -#ifndef MICROPY_INCLUDED_STM32F4_INTERNAL_FLASH_H -#define MICROPY_INCLUDED_STM32F4_INTERNAL_FLASH_H +#ifndef MICROPY_INCLUDED_STM32_INTERNAL_FLASH_H +#define MICROPY_INCLUDED_STM32_INTERNAL_FLASH_H #include #include @@ -35,6 +35,8 @@ #ifdef STM32F401xE #define STM32_FLASH_SIZE 0x80000 //512KiB #define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB +#define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08004000 +#define INTERNAL_FLASH_FILESYSTEM_NUM_BLOCKS (INTERNAL_FLASH_FILESYSTEM_SIZE / FILESYSTEM_BLOCK_SIZE) #endif #ifdef STM32F411xE @@ -43,30 +45,42 @@ #define INTERNAL_FLASH_FILESYSTEM_SIZE 0x8000 //32KiB #else #define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB +#define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08004000 +#define INTERNAL_FLASH_FILESYSTEM_NUM_BLOCKS (INTERNAL_FLASH_FILESYSTEM_SIZE / FILESYSTEM_BLOCK_SIZE) #endif #endif #ifdef STM32F412Zx #define STM32_FLASH_SIZE 0x100000 //1MB #define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB +#define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08004000 +#define INTERNAL_FLASH_FILESYSTEM_NUM_BLOCKS (INTERNAL_FLASH_FILESYSTEM_SIZE / FILESYSTEM_BLOCK_SIZE) #endif #ifdef STM32F405xx #define STM32_FLASH_SIZE 0x100000 //1MB #define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB +#define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08004000 +#define INTERNAL_FLASH_FILESYSTEM_NUM_BLOCKS (INTERNAL_FLASH_FILESYSTEM_SIZE / FILESYSTEM_BLOCK_SIZE) #endif #ifdef STM32F407xx #define STM32_FLASH_SIZE 0x100000 //1MB #define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB +#define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08004000 +#define INTERNAL_FLASH_FILESYSTEM_NUM_BLOCKS (INTERNAL_FLASH_FILESYSTEM_SIZE / FILESYSTEM_BLOCK_SIZE) #endif -#define STM32_FLASH_OFFSET 0x8000000 //All STM32 chips map to this flash location - -#define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08004000 +#ifdef STM32H743xx +#define STM32_FLASH_SIZE 0x200000 //2MB +#define INTERNAL_FLASH_FILESYSTEM_SIZE 0x20000 //128KiB +#define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08020000 #define INTERNAL_FLASH_FILESYSTEM_NUM_BLOCKS (INTERNAL_FLASH_FILESYSTEM_SIZE / FILESYSTEM_BLOCK_SIZE) +#endif + +#define STM32_FLASH_OFFSET 0x8000000 //All STM32 chips map to this flash location #define INTERNAL_FLASH_SYSTICK_MASK (0x1ff) // 512ms #define INTERNAL_FLASH_IDLE_TICK(tick) (((tick) & INTERNAL_FLASH_SYSTICK_MASK) == 2) -#endif // MICROPY_INCLUDED_STM32F4_INTERNAL_FLASH_H +#endif // MICROPY_INCLUDED_STM32_INTERNAL_FLASH_H diff --git a/ports/stm/tools/examples/nucleo_h743.csv b/ports/stm/tools/examples/nucleo_h743.csv new file mode 100644 index 0000000000000..2481415b30de1 --- /dev/null +++ b/ports/stm/tools/examples/nucleo_h743.csv @@ -0,0 +1,130 @@ +A0,PA3 +A1,PC0 +A2,PC3 +A3,PB1 +A4,PC2 +A5,PF10 +A6,PF4 +A7,PF5 +A8,PF6 +D0,PB7 +D1,PB6 +D2,PG14 +D3,PE13 +D4,PE14 +D5,PE11 +D6,PE9 +D7,PG12 +D8,PF3 +D9,PD15 +D10,PD14 +D11,PB5 +D12,PA6 +D13,PA7 +D14,PB9 +D15,PB8 +D16,PC6 +D17,PB15 +D18,PB13 +D19,PB12 +D20,PA15 +D21,PC7 +D22,PB5 +D23,PB3 +D24,PA4 +D25,PB4 +D26,PG6 +D27,PB2 +D28,PD13 +D29,PD12 +D30,PD11 +D31,PE2 +D32,PA0 +D33,PB0 +D34,PE0 +D35,PB11 +D36,PB10 +D37,PE15 +D38,PE6 +D39,PE12 +D40,PE10 +D41,PE7 +D42,PE8 +D43,PC8 +D44,PC9 +D45,PC10 +D46,PC11 +D47,PC12 +D48,PD2 +D49,PG2 +D50,PG3 +D51,PD7 +D52,PD6 +D53,PD5 +D54,PD4 +D55,PD3 +D56,PE2 +D57,PE4 +D58,PE5 +D59,PE6 +D60,PE3 +D61,PF8 +D62,PF7 +D63,PF9 +D64,PG1 +D65,PG0 +D66,PD1 +D67,PD0 +D68,PF0 +D69,PF1 +D70,PF2 +D71,PE9 +D72,PB2 +DAC1,PA4 +DAC2,PA5 +LED1,PB0 +LED2,PB7 +LED3,PB14 +SW,PC13 +I2C1_SDA,PB9 +I2C1_SCL,PB8 +I2C2_SDA,PF0 +I2C2_SCL,PF1 +I2C4_SCL,PF14 +I2C4_SDA,PF15 +SD_D0,PC8 +SD_D1,PC9 +SD_D2,PC10 +SD_D3,PC11 +SD_CMD,PD2 +SD_CK,PC12 +SD_SW,PG2 +OTG_FS_POWER,PG6 +OTG_FS_OVER_CURRENT,PG7 +USB_VBUS,PA9 +USB_ID,PA10 +USB_DM,PA11 +USB_DP,PA12 +UART2_TX,PD5 +UART2_RX,PD6 +UART2_RTS,PD4 +UART2_CTS,PD3 +UART3_TX,PD8 +UART3_RX,PD9 +UART5_TX,PB6 +UART5_RX,PB12 +UART6_TX,PC6 +UART6_RX,PC7 +UART7_TX,PF7 +UART7_RX,PF6 +UART8_TX,PE1 +UART8_RX,PE0 +ETH_MDC,PC1 +ETH_MDIO,PA2 +ETH_RMII_REF_CLK,PA1 +ETH_RMII_CRS_DV,PA7 +ETH_RMII_RXD0,PC4 +ETH_RMII_RXD1,PC5 +ETH_RMII_TX_EN,PG11 +ETH_RMII_TXD0,PG13 +ETH_RMII_TXD1,PB13 \ No newline at end of file diff --git a/ports/stm/tools/examples/stm32f405.csv b/ports/stm/tools/examples/stm32f405.csv new file mode 100644 index 0000000000000..2602db877504d --- /dev/null +++ b/ports/stm/tools/examples/stm32f405.csv @@ -0,0 +1,142 @@ +Port,,AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15, +,,SYS,TIM1/2,TIM3/4/5,TIM8/9/10/11,I2C1/2/3,SPI1/SPI2/I2S2/I2S2ext,SPI3/I2Sext/I2S3,USART1/2/3/I2S3ext,UART4/5/USART6,CAN1/CAN2/TIM12/13/14,OTG_FS/OTG_HS,ETH,FSMC/SDIO/OTG_FS,DCMI,,,ADC +PortA,PA0,,TIM2_CH1/TIM2_ETR,TIM5_CH1,TIM8_ETR,,,,USART2_CTS,UART4_TX,,,ETH_MII_CRS,,,,EVENTOUT,ADC123_IN0 +PortA,PA1,,TIM2_CH2,TIM5_CH2,,,,,USART2_RTS,UART4_RX,,,ETH_MII_RX_CLK/ETH_RMII_REF_CLK,,,,EVENTOUT,ADC123_IN1 +PortA,PA2,,TIM2_CH3,TIM5_CH3,TIM9_CH1,,,,USART2_TX,,,,ETH_MDIO,,,,EVENTOUT,ADC123_IN2 +PortA,PA3,,TIM2_CH4,TIM5_CH4,TIM9_CH2,,,,USART2_RX,,,OTG_HS_ULPI_D0,ETH_MII_COL,,,,EVENTOUT,ADC123_IN3 +PortA,PA4,,,,,,SPI1_NSS,SPI3_NSS/I2S3_WS,USART2_CK,,,,,OTG_HS_SOF,DCMI_HSYNC,,EVENTOUT,ADC12_IN4 +PortA,PA5,,TIM2_CH1/TIM2_ETR,,TIM8_CH1N,,SPI1_SCK,,,,,OTG_HS_ULPI_CK,,,,,EVENTOUT,ADC12_IN5 +PortA,PA6,,TIM1_BKIN,TIM3_CH1,TIM8_BKIN,,SPI1_MISO,,,,TIM13_CH1,,,,DCMI_PIXCK,,EVENTOUT,ADC12_IN6 +PortA,PA7,,TIM1_CH1N,TIM3_CH2,TIM8_CH1N,,SPI1_MOSI,,,,TIM14_CH1,,ETH_MII_RX_DV/ETH_RMII_CRS_DV,,,,EVENTOUT,ADC12_IN7 +PortA,PA8,MCO1,TIM1_CH1,,,I2C3_SCL,,,USART1_CK,,,OTG_FS_SOF,,,,,EVENTOUT, +PortA,PA9,,TIM1_CH2,,,I2C3_SMBA,,,USART1_TX,,,,,,DCMI_D0,,EVENTOUT, +PortA,PA10,,TIM1_CH3,,,,,,USART1_RX,,,OTG_FS_ID,,,DCMI_D1,,EVENTOUT, +PortA,PA11,,TIM1_CH4,,,,,,USART1_CTS,,CAN1_RX,OTG_FS_DM,,,,,EVENTOUT, +PortA,PA12,,TIM1_ETR,,,,,,USART1_RTS,,CAN1_TX,OTG_FS_DP,,,,,EVENTOUT, +PortA,PA13,JTMS/SWDIO,,,,,,,,,,,,,,,EVENTOUT, +PortA,PA14,JTCK/SWCLK,,,,,,,,,,,,,,,EVENTOUT, +PortA,PA15,JTDI,TIM2_CH1/TIM2_ETR,,,,SPI1_NSS,SPI3_NSS/I2S3_WS,,,,,,,,,EVENTOUT, +PortB,PB0,,TIM1_CH2N,TIM3_CH3,TIM8_CH2N,,,,,,,OTG_HS_ULPI_D1,ETH_MII_RXD2,,,,EVENTOUT,ADC12_IN8 +PortB,PB1,,TIM1_CH3N,TIM3_CH4,TIM8_CH3N,,,,,,,OTG_HS_ULPI_D2,ETH_MII_RXD3,,,,EVENTOUT,ADC12_IN9 +PortB,PB2,,,,,,,,,,,,,,,,EVENTOUT, +PortB,PB3,JTDO/TRACESWO,TIM2_CH2,,,,SPI1_SCK,SPI3_SCK/I2S3_CK,,,,,,,,,EVENTOUT, +PortB,PB4,NJTRST,,TIM3_CH1,,,SPI1_MISO,SPI3_MISO,I2S3ext_SD,,,,,,,,EVENTOUT, +PortB,PB5,,,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI,SPI3_MOSI/I2S3_SD,,,CAN2_RX,OTG_HS_ULPI_D7,ETH_PPS_OUT,,DCMI_D10,,EVENTOUT, +PortB,PB6,,,TIM4_CH1,,I2C1_SCL,,,USART1_TX,,CAN2_TX,,,,DCMI_D5,,EVENTOUT, +PortB,PB7,,,TIM4_CH2,,I2C1_SDA,,,USART1_RX,,,,,FSMC_NL,DCMI_VSYNC,,EVENTOUT, +PortB,PB8,,,TIM4_CH3,TIM10_CH1,I2C1_SCL,,,,,CAN1_RX,,ETH_MII_TXD3,SDIO_D4,DCMI_D6,,EVENTOUT, +PortB,PB9,,,TIM4_CH4,TIM11_CH1,I2C1_SDA,SPI2_NSS/I2S2_WS,,,,CAN1_TX,,,SDIO_D5,DCMI_D7,,EVENTOUT, +PortB,PB10,,TIM2_CH3,,,I2C2_SCL,SPI2_SCK/I2S2_CK,,USART3_TX,,,OTG_HS_ULPI_D3,ETH_MII_RX_ER,,,,EVENTOUT, +PortB,PB11,,TIM2_CH4,,,I2C2_SDA,,,USART3_RX,,,OTG_HS_ULPI_D4,ETH_MII_TX_EN/ETH_RMII_TX_EN,,,,EVENTOUT, +PortB,PB12,,TIM1_BKIN,,,I2C2_SMBA,SPI2_NSS/I2S2_WS,,USART3_CK,,CAN2_RX,OTG_HS_ULPI_D5,ETH_MII_TXD0/ETH_RMII_TXD0,OTG_HS_ID,,,EVENTOUT, +PortB,PB13,,TIM1_CH1N,,,,SPI2_SCK/I2S2_CK,,USART3_CTS,,CAN2_TX,OTG_HS_ULPI_D6,ETH_MII_TXD1/ETH_RMII_TXD1,,,,EVENTOUT, +PortB,PB14,,TIM1_CH2N,,TIM8_CH2N,,SPI2_MISO,I2S2ext_SD,USART3_RTS,,TIM12_CH1,,,OTG_HS_DM,,,EVENTOUT, +PortB,PB15,RTC_REFIN,TIM1_CH3N,,TIM8_CH3N,,SPI2_MOSI/I2S2_SD,,,,TIM12_CH2,,,OTG_HS_DP,,,EVENTOUT, +PortC,PC0,,,,,,,,,,,OTG_HS_ULPI_STP,,,,,EVENTOUT,ADC123_IN10 +PortC,PC1,,,,,,,,,,,,ETH_MDC,,,,EVENTOUT,ADC123_IN11 +PortC,PC2,,,,,,SPI2_MISO,I2S2ext_SD,,,,OTG_HS_ULPI_DIR,ETH_MII_TXD2,,,,EVENTOUT,ADC123_IN12 +PortC,PC3,,,,,,SPI2_MOSI/I2S2_SD,,,,,OTG_HS_ULPI_NXT,ETH_MII_TX_CLK,,,,EVENTOUT,ADC123_IN13 +PortC,PC4,,,,,,,,,,,,ETH_MII_RXD0/ETH_RMII_RXD0,,,,EVENTOUT,ADC123_IN14 +PortC,PC5,,,,,,,,,,,,ETH_MII_RXD1/ETH_RMII_RXD1,,,,EVENTOUT,ADC123_IN15 +PortC,PC6,,,TIM3_CH1,TIM8_CH1,,I2S2_MCK,,,USART6_TX,,,,SDIO_D6,DCMI_D0,,EVENTOUT, +PortC,PC7,,,TIM3_CH2,TIM8_CH2,,,I2S3_MCK,,USART6_RX,,,,SDIO_D7,DCMI_D1,,EVENTOUT, +PortC,PC8,,,TIM3_CH3,TIM8_CH3,,,,,USART6_CK,,,,SDIO_D0,DCMI_D2,,EVENTOUT, +PortC,PC9,MCO2,,TIM3_CH4,TIM8_CH4,I2C3_SDA,I2S_CKIN,,,,,,,SDIO_D1,DCMI_D3,,EVENTOUT, +PortC,PC10,,,,,,,SPI3_SCK/I2S3_CK,USART3_TX,UART4_TX,,,,SDIO_D2,DCMI_D8,,EVENTOUT, +PortC,PC11,,,,,,I2S3ext_SD,SPI3_MISO,USART3_RX,UART4_RX,,,,SDIO_D3,DCMI_D4,,EVENTOUT, +PortC,PC12,,,,,,,SPI3_MOSI/I2S3_SD,USART3_CK,UART5_TX,,,,SDIO_CK,DCMI_D9,,EVENTOUT, +PortC,PC13,,,,,,,,,,,,,,,,EVENTOUT, +PortC,PC14,,,,,,,,,,,,,,,,EVENTOUT, +PortC,PC15,,,,,,,,,,,,,,,,EVENTOUT, +PortD,PD0,,,,,,,,,,CAN1_RX,,,FSMC_D2,,,EVENTOUT, +PortD,PD1,,,,,,,,,,CAN1_TX,,,FSMC_D3,,,EVENTOUT, +PortD,PD2,,,TIM3_ETR,,,,,,UART5_RX,,,,SDIO_CMD,DCMI_D11,,EVENTOUT, +PortD,PD3,,,,,,,,USART2_CTS,,,,,FSMC_CLK,,,EVENTOUT, +PortD,PD4,,,,,,,,USART2_RTS,,,,,FSMC_NOE,,,EVENTOUT, +PortD,PD5,,,,,,,,USART2_TX,,,,,FSMC_NWE,,,EVENTOUT, +PortD,PD6,,,,,,,,USART2_RX,,,,,FSMC_NWAIT,,,EVENTOUT, +PortD,PD7,,,,,,,,USART2_CK,,,,,FSMC_NE1/FSMC_NCE2,,,EVENTOUT, +PortD,PD8,,,,,,,,USART3_TX,,,,,FSMC_D13,,,EVENTOUT, +PortD,PD9,,,,,,,,USART3_RX,,,,,FSMC_D14,,,EVENTOUT, +PortD,PD10,,,,,,,,USART3_CK,,,,,FSMC_D15,,,EVENTOUT, +PortD,PD11,,,,,,,,USART3_CTS,,,,,FSMC_A16,,,EVENTOUT, +PortD,PD12,,,TIM4_CH1,,,,,USART3_RTS,,,,,FSMC_A17,,,EVENTOUT, +PortD,PD13,,,TIM4_CH2,,,,,,,,,,FSMC_A18,,,EVENTOUT, +PortD,PD14,,,TIM4_CH3,,,,,,,,,,FSMC_D0,,,EVENTOUT, +PortD,PD15,,,TIM4_CH4,,,,,,,,,,FSMC_D1,,,EVENTOUT, +PortE,PE0,,,TIM4_ETR,,,,,,,,,,FSMC_NBL0,DCMI_D2,,EVENTOUT, +PortE,PE1,,,,,,,,,,,,,FSMC_NBL1,DCMI_D3,,EVENTOUT, +PortE,PE2,TRACECLK,,,,,,,,,,,ETH_MII_TXD3,FSMC_A23,,,EVENTOUT, +PortE,PE3,TRACED0,,,,,,,,,,,,FSMC_A19,,,EVENTOUT, +PortE,PE4,TRACED1,,,,,,,,,,,,FSMC_A20,DCMI_D4,,EVENTOUT, +PortE,PE5,TRACED2,,,TIM9_CH1,,,,,,,,,FSMC_A21,DCMI_D6,,EVENTOUT, +PortE,PE6,TRACED3,,,TIM9_CH2,,,,,,,,,FSMC_A22,DCMI_D7,,EVENTOUT, +PortE,PE7,,TIM1_ETR,,,,,,,,,,,FSMC_D4,,,EVENTOUT, +PortE,PE8,,TIM1_CH1N,,,,,,,,,,,FSMC_D5,,,EVENTOUT, +PortE,PE9,,TIM1_CH1,,,,,,,,,,,FSMC_D6,,,EVENTOUT, +PortE,PE10,,TIM1_CH2N,,,,,,,,,,,FSMC_D7,,,EVENTOUT, +PortE,PE11,,TIM1_CH2,,,,,,,,,,,FSMC_D8,,,EVENTOUT, +PortE,PE12,,TIM1_CH3N,,,,,,,,,,,FSMC_D9,,,EVENTOUT, +PortE,PE13,,TIM1_CH3,,,,,,,,,,,FSMC_D10,,,EVENTOUT, +PortE,PE14,,TIM1_CH4,,,,,,,,,,,FSMC_D11,,,EVENTOUT, +PortE,PE15,,TIM1_BKIN,,,,,,,,,,,FSMC_D12,,,EVENTOUT, +PortF,PF0,,,,,I2C2_SDA,,,,,,,,FSMC_A0,,,EVENTOUT, +PortF,PF1,,,,,I2C2_SCL,,,,,,,,FSMC_A1,,,EVENTOUT, +PortF,PF2,,,,,I2C2_SMBA,,,,,,,,FSMC_A2,,,EVENTOUT, +PortF,PF3,,,,,,,,,,,,,FSMC_A3,,,EVENTOUT,ADC3_IN9 +PortF,PF4,,,,,,,,,,,,,FSMC_A4,,,EVENTOUT,ADC3_IN14 +PortF,PF5,,,,,,,,,,,,,FSMC_A5,,,EVENTOUT,ADC3_IN15 +PortF,PF6,,,,TIM10_CH1,,,,,,,,,FSMC_NIORD,,,EVENTOUT,ADC3_IN4 +PortF,PF7,,,,TIM11_CH1,,,,,,,,,FSMC_NREG,,,EVENTOUT,ADC3_IN5 +PortF,PF8,,,,,,,,,,TIM13_CH1,,,FSMC_NIOWR,,,EVENTOUT,ADC3_IN6 +PortF,PF9,,,,,,,,,,TIM14_CH1,,,FSMC_CD,,,EVENTOUT,ADC3_IN7 +PortF,PF10,,,,,,,,,,,,,FSMC_INTR,,,EVENTOUT,ADC3_IN8 +PortF,PF11,,,,,,,,,,,,,,DCMI_D12,,EVENTOUT, +PortF,PF12,,,,,,,,,,,,,FSMC_A6,,,EVENTOUT, +PortF,PF13,,,,,,,,,,,,,FSMC_A7,,,EVENTOUT, +PortF,PF14,,,,,,,,,,,,,FSMC_A8,,,EVENTOUT, +PortF,PF15,,,,,,,,,,,,,FSMC_A9,,,EVENTOUT, +PortG,PG0,,,,,,,,,,,,,FSMC_A10,,,EVENTOUT, +PortG,PG1,,,,,,,,,,,,,FSMC_A11,,,EVENTOUT, +PortG,PG2,,,,,,,,,,,,,FSMC_A12,,,EVENTOUT, +PortG,PG3,,,,,,,,,,,,,FSMC_A13,,,EVENTOUT, +PortG,PG4,,,,,,,,,,,,,FSMC_A14,,,EVENTOUT, +PortG,PG5,,,,,,,,,,,,,FSMC_A15,,,EVENTOUT, +PortG,PG6,,,,,,,,,,,,,FSMC_INT2,,,EVENTOUT, +PortG,PG7,,,,,,,,,USART6_CK,,,,FSMC_INT3,,,EVENTOUT, +PortG,PG8,,,,,,,,,USART6_RTS,,,ETH_PPS_OUT,,,,EVENTOUT, +PortG,PG9,,,,,,,,,USART6_RX,,,,FSMC_NE2/FSMC_NCE3,,,EVENTOUT, +PortG,PG10,,,,,,,,,,,,,FSMC_NCE4_1/FSMC_NE3,,,EVENTOUT, +PortG,PG11,,,,,,,,,,,,ETH_MII_TX_EN/ETH_RMII_TX_EN,FSMC_NCE4_2,,,EVENTOUT, +PortG,PG12,,,,,,,,,USART6_RTS,,,,FSMC_NE4,,,EVENTOUT, +PortG,PG13,,,,,,,,,USART6_CTS,,,ETH_MII_TXD0/ETH_RMII_TXD0,FSMC_A24,,,EVENTOUT, +PortG,PG14,,,,,,,,,USART6_TX,,,ETH_MII_TXD1/ETH_RMII_TXD1,FSMC_A25,,,EVENTOUT, +PortG,PG15,,,,,,,,,USART6_CTS,,,,,DCMI_D13,,EVENTOUT, +PortH,PH0,,,,,,,,,,,,,,,,EVENTOUT, +PortH,PH1,,,,,,,,,,,,,,,,EVENTOUT, +PortH,PH2,,,,,,,,,,,,ETH_MII_CRS,,,,EVENTOUT, +PortH,PH3,,,,,,,,,,,,ETH_MII_COL,,,,EVENTOUT, +PortH,PH4,,,,,I2C2_SCL,,,,,,OTG_HS_ULPI_NXT,,,,,EVENTOUT, +PortH,PH5,,,,,I2C2_SDA,,,,,,,,,,,EVENTOUT, +PortH,PH6,,,,,I2C2_SMBA,,,,,TIM12_CH1,,ETH_MII_RXD2,,,,EVENTOUT, +PortH,PH7,,,,,I2C3_SCL,,,,,,,ETH_MII_RXD3,,,,EVENTOUT, +PortH,PH8,,,,,I2C3_SDA,,,,,,,,,DCMI_HSYNC,,EVENTOUT, +PortH,PH9,,,,,I2C3_SMBA,,,,,TIM12_CH2,,,,DCMI_D0,,EVENTOUT, +PortH,PH10,,,TIM5_CH1,,,,,,,,,,,DCMI_D1,,EVENTOUT, +PortH,PH11,,,TIM5_CH2,,,,,,,,,,,DCMI_D2,,EVENTOUT, +PortH,PH12,,,TIM5_CH3,,,,,,,,,,,DCMI_D3,,EVENTOUT, +PortH,PH13,,,,TIM8_CH1N,,,,,,CAN1_TX,,,,,,EVENTOUT, +PortH,PH14,,,,TIM8_CH2N,,,,,,,,,,DCMI_D4,,EVENTOUT, +PortH,PH15,,,,TIM8_CH3N,,,,,,,,,,DCMI_D11,,EVENTOUT, +PortI,PI0,,,TIM5_CH4,,,SPI2_NSS/I2S2_WS,,,,,,,,DCMI_D13,,EVENTOUT, +PortI,PI1,,,,,,SPI2_SCK/I2S2_CK,,,,,,,,DCMI_D8,,EVENTOUT, +PortI,PI2,,,,TIM8_CH4,,SPI2_MISO,I2S2ext_SD,,,,,,,DCMI_D9,,EVENTOUT, +PortI,PI3,,,,TIM8_ETR,,SPI2_MOSI/I2S2_SD,,,,,,,,DCMI_D10,,EVENTOUT, +PortI,PI4,,,,TIM8_BKIN,,,,,,,,,,DCMI_D5,,EVENTOUT, +PortI,PI5,,,,TIM8_CH1,,,,,,,,,,DCMI_VSYNC,,EVENTOUT, +PortI,PI6,,,,TIM8_CH2,,,,,,,,,,DCMI_D6,,EVENTOUT, +PortI,PI7,,,,TIM8_CH3,,,,,,,,,,DCMI_D7,,EVENTOUT, +PortI,PI8,,,,,,,,,,,,,,,,EVENTOUT, +PortI,PI9,,,,,,,,,,CAN1_RX,,,,,,EVENTOUT, +PortI,PI10,,,,,,,,,,,,ETH_MII_RX_ER,,,,EVENTOUT, +PortI,PI11,,,,,,,,,,,OTG_HS_ULPI_DIR,,,,,EVENTOUT, diff --git a/ports/stm/tools/parse_af_csv.py b/ports/stm/tools/parse_af_csv.py index 4ab636d79f7a4..56baf8c7654ce 100644 --- a/ports/stm/tools/parse_af_csv.py +++ b/ports/stm/tools/parse_af_csv.py @@ -26,6 +26,10 @@ import sys # Use: parse_af_csf.py Filename.csv -pins-only +# Designed for use with .csv files from Micropython, or in identical format +# created via Datasheet peripheral tables with a Sheets program. +# +# See examples/stm32f405.csv for example formatting. # Most peripherals (SPI, I2C) output 3 values: # peripheral index, alt function, pin string @@ -130,8 +134,4 @@ def evaluate_tim(inper, inlist, altfn, pin): for line in outlist: print("extern const mcu_pin_obj_t pin_" + line[0] + ";") - - - print(f'Processed {line_count} lines.') - diff --git a/ports/stm/tools/parse_pins_csv.py b/ports/stm/tools/parse_pins_csv.py new file mode 100644 index 0000000000000..b69b4791be0cb --- /dev/null +++ b/ports/stm/tools/parse_pins_csv.py @@ -0,0 +1,49 @@ +# This file is part of the MicroPython project, http://micropython.org/ +# +# The MIT License (MIT) +# +# Copyright (c) 2020 Lucian Copeland for Adafruit Industries +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +import csv +import sys + +# Use: parse_pins_csv.py Filename.csv +# Designed for use with .csv files from Micropython, or in identical format +# created via Datasheet peripheral tables with a Sheets program. +# +# See examples/nucleo_h743.csv for example formatting. + +# Open target file +with open(sys.argv[1]) as csv_file: + csv_reader = csv.reader(csv_file, delimiter=',') + line_count = 0 + + print("STATIC const mp_rom_map_elem_t board_module_globals_table[] = {") + + for row in csv_reader: + label = row[0] + pin = row[1] + if len(pin) < 4: + pin = pin[:2] + '0' + pin[2:] + print("{ MP_ROM_QSTR(MP_QSTR_" + label + "), MP_ROM_PTR(&pin_" + pin + ") },") + line_count += 1 + + print(f'Processed {line_count} lines.') From a89928c13c748b7f25bd4e734cfe487b0020a25d Mon Sep 17 00:00:00 2001 From: Lucian Copeland Date: Wed, 1 Apr 2020 13:02:05 -0400 Subject: [PATCH 05/17] Implement requested changes --- .github/workflows/build.yml | 1 + extmod/ulab | 2 +- locale/ID.po | 2 +- locale/circuitpython.pot | 2 +- locale/de_DE.po | 2 +- locale/en_US.po | 2 +- locale/en_x_pirate.po | 2 +- locale/es.po | 2 +- locale/fil.po | 2 +- locale/fr.po | 2 +- locale/it_IT.po | 2 +- locale/ko.po | 2 +- locale/pl.po | 2 +- locale/pt_BR.po | 2 +- locale/zh_Latn_pinyin.po | 2 +- ports/stm/Makefile | 7 +- ports/stm/boards/STM32H743_fs.ld | 56 ++++++++++++- .../board.c | 0 .../mpconfigboard.h | 3 +- .../mpconfigboard.mk | 2 +- .../pins.c | 0 .../stm32h7xx_hal_conf.h | 0 .../peripherals/stm32h7/stm32h743xx/clocks.c | 79 ------------------- ports/stm/supervisor/internal_flash.c | 19 ----- ports/stm/supervisor/internal_flash.h | 8 +- ports/stm/supervisor/usb.c | 8 +- supervisor/linker.h | 2 +- 27 files changed, 81 insertions(+), 132 deletions(-) rename ports/stm/boards/{stm32h743zi2_discovery => nucleo_h743zi_2}/board.c (100%) rename ports/stm/boards/{stm32h743zi2_discovery => nucleo_h743zi_2}/mpconfigboard.h (93%) rename ports/stm/boards/{stm32h743zi2_discovery => nucleo_h743zi_2}/mpconfigboard.mk (83%) rename ports/stm/boards/{stm32h743zi2_discovery => nucleo_h743zi_2}/pins.c (100%) rename ports/stm/boards/{stm32h743zi2_discovery => nucleo_h743zi_2}/stm32h7xx_hal_conf.h (100%) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index bb6bb28da346e..2e1a6188becd8 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -188,6 +188,7 @@ jobs: - "mini_sam_m4" - "monster_m4sk" - "ndgarage_ndbit6" + - "nucleo_h743zi_2" - "ohs2020_badge" - "openbook_m4" - "particle_argon" diff --git a/extmod/ulab b/extmod/ulab index 66b89de8c7147..a91b36986d81f 160000 --- a/extmod/ulab +++ b/extmod/ulab @@ -1 +1 @@ -Subproject commit 66b89de8c714790de8647dc55f59430002044171 +Subproject commit a91b36986d81fd906a6232010778f2a93d690f8e diff --git a/locale/ID.po b/locale/ID.po index 8c5725428eca2..567fe5ff3e720 100644 --- a/locale/ID.po +++ b/locale/ID.po @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-03-20 17:57-0500\n" +"POT-Creation-Date: 2020-04-01 12:29-0400\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" diff --git a/locale/circuitpython.pot b/locale/circuitpython.pot index 53ee64795738e..a6dabdaec06cf 100644 --- a/locale/circuitpython.pot +++ b/locale/circuitpython.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-03-20 17:57-0500\n" +"POT-Creation-Date: 2020-04-01 12:29-0400\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" diff --git a/locale/de_DE.po b/locale/de_DE.po index df62a978c66ca..5d4bec87232bc 100644 --- a/locale/de_DE.po +++ b/locale/de_DE.po @@ -7,7 +7,7 @@ msgid "" msgstr "" "Project-Id-Version: \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-03-20 17:57-0500\n" +"POT-Creation-Date: 2020-04-01 12:29-0400\n" "PO-Revision-Date: 2018-07-27 11:55-0700\n" "Last-Translator: Pascal Deneaux\n" "Language-Team: Sebastian Plamauer, Pascal Deneaux\n" diff --git a/locale/en_US.po b/locale/en_US.po index 0a2f870e72d92..17a4fb9dc1d70 100644 --- a/locale/en_US.po +++ b/locale/en_US.po @@ -7,7 +7,7 @@ msgid "" msgstr "" "Project-Id-Version: \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-03-20 17:57-0500\n" +"POT-Creation-Date: 2020-04-01 12:29-0400\n" "PO-Revision-Date: 2018-07-27 11:55-0700\n" "Last-Translator: \n" "Language-Team: \n" diff --git a/locale/en_x_pirate.po b/locale/en_x_pirate.po index ae56216d7fdc6..f356c6e163ed7 100644 --- a/locale/en_x_pirate.po +++ b/locale/en_x_pirate.po @@ -7,7 +7,7 @@ msgid "" msgstr "" "Project-Id-Version: \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-03-20 17:57-0500\n" +"POT-Creation-Date: 2020-04-01 12:29-0400\n" "PO-Revision-Date: 2018-07-27 11:55-0700\n" "Last-Translator: \n" "Language-Team: @sommersoft, @MrCertainly\n" diff --git a/locale/es.po b/locale/es.po index 2f2b206b26a1a..417a0126ac6c6 100644 --- a/locale/es.po +++ b/locale/es.po @@ -7,7 +7,7 @@ msgid "" msgstr "" "Project-Id-Version: \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-03-20 17:57-0500\n" +"POT-Creation-Date: 2020-04-01 12:29-0400\n" "PO-Revision-Date: 2018-08-24 22:56-0500\n" "Last-Translator: \n" "Language-Team: \n" diff --git a/locale/fil.po b/locale/fil.po index f8c1471d59f07..12baeea9ddfd5 100644 --- a/locale/fil.po +++ b/locale/fil.po @@ -7,7 +7,7 @@ msgid "" msgstr "" "Project-Id-Version: \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-03-20 17:57-0500\n" +"POT-Creation-Date: 2020-04-01 12:29-0400\n" "PO-Revision-Date: 2018-12-20 22:15-0800\n" "Last-Translator: Timothy \n" "Language-Team: fil\n" diff --git a/locale/fr.po b/locale/fr.po index 56f20106bc87d..a8d896b52554c 100644 --- a/locale/fr.po +++ b/locale/fr.po @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: 0.1\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-03-20 17:57-0500\n" +"POT-Creation-Date: 2020-04-01 12:29-0400\n" "PO-Revision-Date: 2019-04-14 20:05+0100\n" "Last-Translator: Pierrick Couturier \n" "Language-Team: fr\n" diff --git a/locale/it_IT.po b/locale/it_IT.po index 1b31c5645bcdf..901ced7e4738f 100644 --- a/locale/it_IT.po +++ b/locale/it_IT.po @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-03-20 17:57-0500\n" +"POT-Creation-Date: 2020-04-01 12:29-0400\n" "PO-Revision-Date: 2018-10-02 16:27+0200\n" "Last-Translator: Enrico Paganin \n" "Language-Team: \n" diff --git a/locale/ko.po b/locale/ko.po index 575a88b62a9f7..f84979c645fb6 100644 --- a/locale/ko.po +++ b/locale/ko.po @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-03-20 17:57-0500\n" +"POT-Creation-Date: 2020-04-01 12:29-0400\n" "PO-Revision-Date: 2019-05-06 14:22-0700\n" "Last-Translator: \n" "Language-Team: LANGUAGE \n" diff --git a/locale/pl.po b/locale/pl.po index ad726ac7fc1e7..12bd980bd83b1 100644 --- a/locale/pl.po +++ b/locale/pl.po @@ -7,7 +7,7 @@ msgid "" msgstr "" "Project-Id-Version: \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-03-20 17:57-0500\n" +"POT-Creation-Date: 2020-04-01 12:29-0400\n" "PO-Revision-Date: 2019-03-19 18:37-0700\n" "Last-Translator: Radomir Dopieralski \n" "Language-Team: pl\n" diff --git a/locale/pt_BR.po b/locale/pt_BR.po index 48af7b7978980..3291296972113 100644 --- a/locale/pt_BR.po +++ b/locale/pt_BR.po @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-03-20 17:57-0500\n" +"POT-Creation-Date: 2020-04-01 12:29-0400\n" "PO-Revision-Date: 2018-10-02 21:14-0000\n" "Last-Translator: \n" "Language-Team: \n" diff --git a/locale/zh_Latn_pinyin.po b/locale/zh_Latn_pinyin.po index 5e545a66f870d..7cf00580b4184 100644 --- a/locale/zh_Latn_pinyin.po +++ b/locale/zh_Latn_pinyin.po @@ -7,7 +7,7 @@ msgid "" msgstr "" "Project-Id-Version: circuitpython-cn\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-03-20 17:57-0500\n" +"POT-Creation-Date: 2020-04-01 12:29-0400\n" "PO-Revision-Date: 2019-04-13 10:10-0700\n" "Last-Translator: hexthat\n" "Language-Team: Chinese Hanyu Pinyin\n" diff --git a/ports/stm/Makefile b/ports/stm/Makefile index ef70cad81e07f..a654feac01f5e 100755 --- a/ports/stm/Makefile +++ b/ports/stm/Makefile @@ -78,7 +78,6 @@ INC += -I../../lib/mp-readline INC += -I../../lib/tinyusb/src INC += -I../../supervisor/shared/usb - #Debugging/Optimization ifeq ($(DEBUG), 1) CFLAGS += -ggdb @@ -106,9 +105,9 @@ CFLAGS += -Wno-cast-align CFLAGS += -mthumb -mabi=aapcs-linux # Arm core selection -MCU_FLAGS_F4 = -mtune=cortex-m4 -mcpu=cortex-m4 -MCU_FLAGS_F7 = -mtune=cortex-m7 -mcpu=cortex-m7 -MCU_FLAGS_H7 = -mtune=cortex-m7 -mcpu=cortex-m7 +MCU_FLAGS_F4 = -mcpu=cortex-m4 +MCU_FLAGS_F7 = -mcpu=cortex-m7 +MCU_FLAGS_H7 = -mcpu=cortex-m7 CFLAGS += $(MCU_FLAGS_$(MCU_SERIES)) CFLAGS += -DSTM32_HAL_H='' diff --git a/ports/stm/boards/STM32H743_fs.ld b/ports/stm/boards/STM32H743_fs.ld index 395a074d3249c..fdeab9a3d0f9c 100644 --- a/ports/stm/boards/STM32H743_fs.ld +++ b/ports/stm/boards/STM32H743_fs.ld @@ -54,9 +54,6 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = 0x20020000; /* end of RAM */ -/* Generate a link error if heap and stack don't fit into RAM */ -_Min_Heap_Size = 0x200; /* required amount of heap */ -_Min_Stack_Size = 0x400; /* required amount of stack */ /* Specify the memory areas */ MEMORY @@ -65,14 +62,20 @@ MEMORY FLASH_ISR (rx) : ORIGIN = 0x08000000, LENGTH = 128K /* sector 0, 128K */ FLASH_FS (r) : ORIGIN = 0x08020000, LENGTH = 128K /* sector 1, 128K */ FLASH_TEXT (rx) : ORIGIN = 0x08040000, LENGTH = 1792K /* sectors 6*128 + 8*128 */ - DTCM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K /* Used for storage cache */ + DTCM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K RAM (xrw) : ORIGIN = 0x24000000, LENGTH = 512K /* AXI SRAM */ + SRAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K /* AHB1 SRAM */ + SRAM_D3 (xrw) : ORIGIN = 0x30040000, LENGTH = 64K /* AHB2 SRAM */ + ITCM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K } /* produce a link error if there is not this amount of RAM for these sections */ _minimum_stack_size = 2K; _minimum_heap_size = 16K; +/* brainless copy paste for stack code. Results in ambiguous hard crash */ +/* _ld_default_stack_size = 20K; */ + /* Define tho top end of the stack. The stack is full descending so begins just above last byte of RAM. Note that EABI requires the stack to be 8-byte aligned for a call. */ @@ -158,6 +161,51 @@ SECTIONS . = ALIGN(4); } >RAM + /* itcm stuff doesn't work, results in arcane hard crashes + .itcm : + { + . = ALIGN(4); + + *(.itcm.*) + + . = ALIGN(4); + } > ITCM AT> FLASH_TEXT + _ld_itcm_destination = ADDR(.itcm); + _ld_itcm_flash_copy = LOADADDR(.itcm); + _ld_itcm_size = SIZEOF(.itcm); + + .dtcm_data : + { + . = ALIGN(4); + + *(.dtcm_data.*) + + . = ALIGN(4); + } > DTCM AT> FLASH_TEXT + _ld_dtcm_data_destination = ADDR(.dtcm_data); + _ld_dtcm_data_flash_copy = LOADADDR(.dtcm_data); + _ld_dtcm_data_size = SIZEOF(.dtcm_data); + + .dtcm_bss : + { + . = ALIGN(4); + + *(.dtcm_bss.*) + + . = ALIGN(4); + } > DTCM AT> DTCM + _ld_dtcm_bss_start = ADDR(.dtcm_bss); + _ld_dtcm_bss_size = SIZEOF(.dtcm_bss); + + .stack : + { + . = ALIGN(8); + _ld_stack_bottom = .; + . += _ld_default_stack_size; + } > DTCM + _ld_stack_top = ORIGIN(DTCM) + LENGTH(DTCM); + */ + .ARM.attributes 0 : { *(.ARM.attributes) } } diff --git a/ports/stm/boards/stm32h743zi2_discovery/board.c b/ports/stm/boards/nucleo_h743zi_2/board.c similarity index 100% rename from ports/stm/boards/stm32h743zi2_discovery/board.c rename to ports/stm/boards/nucleo_h743zi_2/board.c diff --git a/ports/stm/boards/stm32h743zi2_discovery/mpconfigboard.h b/ports/stm/boards/nucleo_h743zi_2/mpconfigboard.h similarity index 93% rename from ports/stm/boards/stm32h743zi2_discovery/mpconfigboard.h rename to ports/stm/boards/nucleo_h743zi_2/mpconfigboard.h index 6a62ff512a2be..3678d8a39ef56 100644 --- a/ports/stm/boards/stm32h743zi2_discovery/mpconfigboard.h +++ b/ports/stm/boards/nucleo_h743zi_2/mpconfigboard.h @@ -26,10 +26,9 @@ //Micropython setup -#define MICROPY_HW_BOARD_NAME "STM32H743_DISCO" +#define MICROPY_HW_BOARD_NAME "NUCLEO STM32H743" #define MICROPY_HW_MCU_NAME "STM32H743" -// #define FLASH_SIZE (0x200000) #define FLASH_PAGE_SIZE (0x4000) #define BOARD_OSC_DIV (8) diff --git a/ports/stm/boards/stm32h743zi2_discovery/mpconfigboard.mk b/ports/stm/boards/nucleo_h743zi_2/mpconfigboard.mk similarity index 83% rename from ports/stm/boards/stm32h743zi2_discovery/mpconfigboard.mk rename to ports/stm/boards/nucleo_h743zi_2/mpconfigboard.mk index 3a37ffe75df92..0f003d5fe3e0b 100644 --- a/ports/stm/boards/stm32h743zi2_discovery/mpconfigboard.mk +++ b/ports/stm/boards/nucleo_h743zi_2/mpconfigboard.mk @@ -1,6 +1,6 @@ USB_VID = 0x239A #REPLACE USB_PID = 0x808A #REPLACE -USB_PRODUCT = "STM32H743ZI Discovery Board - CPy" +USB_PRODUCT = "Nucleo H743ZI - CPy" USB_MANUFACTURER = "STMicroelectronics" USB_DEVICES = "CDC,MSC" diff --git a/ports/stm/boards/stm32h743zi2_discovery/pins.c b/ports/stm/boards/nucleo_h743zi_2/pins.c similarity index 100% rename from ports/stm/boards/stm32h743zi2_discovery/pins.c rename to ports/stm/boards/nucleo_h743zi_2/pins.c diff --git a/ports/stm/boards/stm32h743zi2_discovery/stm32h7xx_hal_conf.h b/ports/stm/boards/nucleo_h743zi_2/stm32h7xx_hal_conf.h similarity index 100% rename from ports/stm/boards/stm32h743zi2_discovery/stm32h7xx_hal_conf.h rename to ports/stm/boards/nucleo_h743zi_2/stm32h7xx_hal_conf.h diff --git a/ports/stm/peripherals/stm32h7/stm32h743xx/clocks.c b/ports/stm/peripherals/stm32h7/stm32h743xx/clocks.c index 494b7709e6b70..a961362aa009e 100644 --- a/ports/stm/peripherals/stm32h7/stm32h743xx/clocks.c +++ b/ports/stm/peripherals/stm32h7/stm32h743xx/clocks.c @@ -79,84 +79,5 @@ void stm32_peripherals_clocks_init(void) { RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; RCC_PeriphCLKInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL; HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct); - - // RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - // RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - // RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - - // /** Supply configuration update enable - // */ - // HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); - // /** Configure the main internal regulator output voltage - // */ - // __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - - // while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} - // /** Macro to configure the PLL clock source - // */ - // __HAL_RCC_PLL_PLLSOURCE_CONFIG(RCC_PLLSOURCE_HSE); - // /** Initializes the CPU, AHB and APB busses clocks - // */ - // RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - // RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; - // RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - // RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - // RCC_OscInitStruct.PLL.PLLM = 4; - // RCC_OscInitStruct.PLL.PLLN = 400; - // RCC_OscInitStruct.PLL.PLLP = 2; - // RCC_OscInitStruct.PLL.PLLQ = 4; - // RCC_OscInitStruct.PLL.PLLR = 2; - // RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_1; - // RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; - // RCC_OscInitStruct.PLL.PLLFRACN = 0; - // if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - // { - - // } - // /** Initializes the CPU, AHB and APB busses clocks - // */ - // RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - // |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 - // |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1; - // RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - // RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; - // RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; - // RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; - // RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; - // RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; - // RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; - - // if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) - // { - - // } - // PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; /*RCC_PERIPHCLK_USART3|RCC_PERIPHCLK_UART4 - // |RCC_PERIPHCLK_SPI1|RCC_PERIPHCLK_ADC - // |RCC_PERIPHCLK_I2C1| */ - // // PeriphClkInitStruct.PLL2.PLL2M = 1; - // // PeriphClkInitStruct.PLL2.PLL2N = 19; - // // PeriphClkInitStruct.PLL2.PLL2P = 2; - // // PeriphClkInitStruct.PLL2.PLL2Q = 2; - // // PeriphClkInitStruct.PLL2.PLL2R = 2; - // // PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3; - // // PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOMEDIUM; - // // PeriphClkInitStruct.PLL2.PLL2FRACN = 0; - // PeriphClkInitStruct.PLL3.PLL3M = 4; - // PeriphClkInitStruct.PLL3.PLL3N = 120; - // PeriphClkInitStruct.PLL3.PLL3P = 2; - // PeriphClkInitStruct.PLL3.PLL3Q = 5; - // PeriphClkInitStruct.PLL3.PLL3R = 2; - // PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_1; - // PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE; - // PeriphClkInitStruct.PLL3.PLL3FRACN = 0; - // PeriphClkInitStruct.Spi123ClockSelection = RCC_SPI123CLKSOURCE_PLL; - // PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1; - // PeriphClkInitStruct.I2c123ClockSelection = RCC_I2C123CLKSOURCE_D2PCLK1; - // PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3; - // PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLL2; - // if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) - // { - - // } } diff --git a/ports/stm/supervisor/internal_flash.c b/ports/stm/supervisor/internal_flash.c index 003ccdd908e80..5bd6e8758e9a4 100644 --- a/ports/stm/supervisor/internal_flash.c +++ b/ports/stm/supervisor/internal_flash.c @@ -181,25 +181,6 @@ void supervisor_flash_flush(void) { reset_into_safe_mode(FLASH_WRITE_FAIL); } - // __HAL_FLASH_DATA_CACHE_DISABLE(); - // __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); - - // __HAL_FLASH_DATA_CACHE_RESET(); - // __HAL_FLASH_INSTRUCTION_CACHE_RESET(); - - // __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); - // __HAL_FLASH_DATA_CACHE_ENABLE(); - - // // reprogram the sector - // for (uint32_t i = 0; i < sector_size; i++) { - // if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_BYTE, sector_start_addr, (uint64_t)_flash_cache[i]) != HAL_OK) { - // // error occurred during flash write - // HAL_FLASH_Lock(); // lock the flash - // mp_printf(&mp_plat_print, "FLASH WRITE ERROR"); - // } - // sector_start_addr += 1; - // } - uint32_t * cache_addr = (uint32_t*)_flash_cache; #if defined(STM32H7) diff --git a/ports/stm/supervisor/internal_flash.h b/ports/stm/supervisor/internal_flash.h index 37f0b25e46a34..665b194c5fabf 100644 --- a/ports/stm/supervisor/internal_flash.h +++ b/ports/stm/supervisor/internal_flash.h @@ -36,7 +36,6 @@ #define STM32_FLASH_SIZE 0x80000 //512KiB #define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB #define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08004000 -#define INTERNAL_FLASH_FILESYSTEM_NUM_BLOCKS (INTERNAL_FLASH_FILESYSTEM_SIZE / FILESYSTEM_BLOCK_SIZE) #endif #ifdef STM32F411xE @@ -46,7 +45,6 @@ #else #define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB #define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08004000 -#define INTERNAL_FLASH_FILESYSTEM_NUM_BLOCKS (INTERNAL_FLASH_FILESYSTEM_SIZE / FILESYSTEM_BLOCK_SIZE) #endif #endif @@ -54,30 +52,28 @@ #define STM32_FLASH_SIZE 0x100000 //1MB #define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB #define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08004000 -#define INTERNAL_FLASH_FILESYSTEM_NUM_BLOCKS (INTERNAL_FLASH_FILESYSTEM_SIZE / FILESYSTEM_BLOCK_SIZE) #endif #ifdef STM32F405xx #define STM32_FLASH_SIZE 0x100000 //1MB #define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB #define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08004000 -#define INTERNAL_FLASH_FILESYSTEM_NUM_BLOCKS (INTERNAL_FLASH_FILESYSTEM_SIZE / FILESYSTEM_BLOCK_SIZE) #endif #ifdef STM32F407xx #define STM32_FLASH_SIZE 0x100000 //1MB #define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB #define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08004000 -#define INTERNAL_FLASH_FILESYSTEM_NUM_BLOCKS (INTERNAL_FLASH_FILESYSTEM_SIZE / FILESYSTEM_BLOCK_SIZE) #endif #ifdef STM32H743xx #define STM32_FLASH_SIZE 0x200000 //2MB #define INTERNAL_FLASH_FILESYSTEM_SIZE 0x20000 //128KiB #define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08020000 -#define INTERNAL_FLASH_FILESYSTEM_NUM_BLOCKS (INTERNAL_FLASH_FILESYSTEM_SIZE / FILESYSTEM_BLOCK_SIZE) #endif +#define INTERNAL_FLASH_FILESYSTEM_NUM_BLOCKS (INTERNAL_FLASH_FILESYSTEM_SIZE / FILESYSTEM_BLOCK_SIZE) + #define STM32_FLASH_OFFSET 0x8000000 //All STM32 chips map to this flash location #define INTERNAL_FLASH_SYSTICK_MASK (0x1ff) // 512ms diff --git a/ports/stm/supervisor/usb.c b/ports/stm/supervisor/usb.c index 66c55d7605e5f..997bf413f8fa3 100644 --- a/ports/stm/supervisor/usb.c +++ b/ports/stm/supervisor/usb.c @@ -80,8 +80,10 @@ void init_usb_hardware(void) { GPIO_InitStruct.Pull = GPIO_NOPULL; #if defined(STM32H7) GPIO_InitStruct.Alternate = GPIO_AF10_OTG1_FS; - #else + #elif defined(STM32F4) GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; + #else + #error Unsupported processor #endif HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); never_reset_pin_number(0, 11); @@ -103,8 +105,10 @@ void init_usb_hardware(void) { GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; #if defined(STM32H7) GPIO_InitStruct.Alternate = GPIO_AF10_OTG1_FS; - #else + #elif defined(STM32F4) GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; + #else + #error Unsupported processor #endif HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); never_reset_pin_number(0, 10); diff --git a/supervisor/linker.h b/supervisor/linker.h index b58414433825a..57ae1461587ed 100755 --- a/supervisor/linker.h +++ b/supervisor/linker.h @@ -29,7 +29,7 @@ #ifndef MICROPY_INCLUDED_SUPERVISOR_LINKER_H #define MICROPY_INCLUDED_SUPERVISOR_LINKER_H -#if defined(IMXRT10XX) +#if defined(IMXRT10XX) // || defined(STM32H7) #define PLACE_IN_DTCM_DATA(name) name __attribute__((section(".dtcm_data." #name ))) #define PLACE_IN_DTCM_BSS(name) name __attribute__((section(".dtcm_bss." #name ))) #define PLACE_IN_ITCM(name) __attribute__((section(".itcm." #name ))) name From 2f764ded6379786d8d17322fa2e859fd102d5397 Mon Sep 17 00:00:00 2001 From: Lucian Copeland Date: Wed, 1 Apr 2020 13:52:53 -0400 Subject: [PATCH 06/17] merge and docs --- .github/workflows/build.yml | 47 ++ conf.py | 2 + locale/ID.po | 5 + locale/circuitpython.pot | 5 + locale/de_DE.po | 5 + locale/en_US.po | 5 + locale/en_x_pirate.po | 5 + locale/es.po | 5 + locale/fil.po | 5 + locale/fr.po | 5 + locale/it_IT.po | 5 + locale/ko.po | 5 + locale/pl.po | 5 + locale/pt_BR.po | 5 + locale/zh_Latn_pinyin.po | 5 + .../atmel-samd/boards/bdmicro_vina_m0/board.c | 48 ++ .../boards/bdmicro_vina_m0/mpconfigboard.h | 35 + .../boards/bdmicro_vina_m0/mpconfigboard.mk | 18 + .../atmel-samd/boards/bdmicro_vina_m0/pins.c | 39 ++ .../boards/hallowing_m0_express/board.c | 4 +- .../boards/hallowing_m4_express/board.c | 4 +- ports/atmel-samd/boards/monster_m4sk/board.c | 4 +- ports/atmel-samd/boards/openbook_m4/board.c | 4 +- ports/atmel-samd/boards/pewpew_m4/board.c | 4 +- ports/atmel-samd/boards/pybadge/board.c | 4 +- .../atmel-samd/boards/pybadge_airlift/board.c | 4 +- ports/atmel-samd/boards/pygamer/board.c | 4 +- .../atmel-samd/boards/pygamer_advance/board.c | 4 +- ports/atmel-samd/boards/ugame10/board.c | 4 +- ports/litex/Makefile | 200 ++++++ ports/litex/background.c | 60 ++ ports/litex/background.h | 35 + ports/litex/boards/board.h | 45 ++ ports/litex/boards/fomu/board.c | 75 ++ ports/litex/boards/fomu/csr.h | 647 ++++++++++++++++++ ports/litex/boards/fomu/fomu-spi.ld | 82 +++ ports/litex/boards/fomu/generated/soc.h | 58 ++ ports/litex/boards/fomu/mpconfigboard.h | 37 + ports/litex/boards/fomu/mpconfigboard.mk | 20 + ports/litex/boards/fomu/pins.c | 9 + ports/litex/boards/fomu/profiling.gdb.txt | 16 + .../litex/common-hal/digitalio/DigitalInOut.c | 119 ++++ .../litex/common-hal/digitalio/DigitalInOut.h | 38 + ports/litex/common-hal/digitalio/__init__.c | 1 + ports/litex/common-hal/microcontroller/Pin.c | 56 ++ ports/litex/common-hal/microcontroller/Pin.h | 59 ++ .../common-hal/microcontroller/Processor.c | 64 ++ .../common-hal/microcontroller/Processor.h | 39 ++ .../common-hal/microcontroller/__init__.c | 111 +++ .../common-hal/neopixel_write/__init__.c | 93 +++ ports/litex/common-hal/supervisor/Runtime.c | 38 + ports/litex/common-hal/supervisor/Runtime.h | 37 + ports/litex/common-hal/supervisor/__init__.c | 40 ++ ports/litex/common-hal/time/__init__.c | 45 ++ ports/litex/crt0-vexriscv.S | 94 +++ ports/litex/fatfs_port.c | 33 + ports/litex/hw/common.h | 33 + ports/litex/irq.h | 71 ++ ports/litex/mpconfigport.h | 43 ++ ports/litex/mpconfigport.mk | 31 + ports/litex/mphalport.c | 81 +++ ports/litex/mphalport.h | 42 ++ ports/litex/qstrdefsport.h | 1 + ports/litex/supervisor/internal_flash.c | 350 ++++++++++ ports/litex/supervisor/internal_flash.h | 38 + .../supervisor/internal_flash_root_pointers.h | 31 + ports/litex/supervisor/port.c | 85 +++ ports/litex/supervisor/usb.c | 36 + ports/litex/tick.c | 82 +++ ports/litex/tick.h | 46 ++ .../common-hal/neopixel_write/__init__.c | 19 +- .../nrf/boards/clue_nrf52840_express/board.c | 4 +- ports/nrf/boards/ohs2020_badge/board.c | 4 +- ports/nrf/common-hal/_bleio/Connection.c | 3 +- ports/nrf/common-hal/_bleio/PacketBuffer.c | 14 +- ports/stm/boards/meowbit_v121/board.c | 6 +- shared-bindings/_bleio/PacketBuffer.c | 7 +- shared-bindings/displayio/FourWire.c | 20 +- shared-bindings/displayio/FourWire.h | 3 +- shared-module/displayio/FourWire.c | 7 +- supervisor/linker.h | 2 +- tools/build_board_info.py | 5 +- tools/dfu.py | 84 +-- 83 files changed, 3497 insertions(+), 96 deletions(-) create mode 100644 ports/atmel-samd/boards/bdmicro_vina_m0/board.c create mode 100644 ports/atmel-samd/boards/bdmicro_vina_m0/mpconfigboard.h create mode 100644 ports/atmel-samd/boards/bdmicro_vina_m0/mpconfigboard.mk create mode 100644 ports/atmel-samd/boards/bdmicro_vina_m0/pins.c create mode 100644 ports/litex/Makefile create mode 100644 ports/litex/background.c create mode 100644 ports/litex/background.h create mode 100644 ports/litex/boards/board.h create mode 100644 ports/litex/boards/fomu/board.c create mode 100644 ports/litex/boards/fomu/csr.h create mode 100644 ports/litex/boards/fomu/fomu-spi.ld create mode 100644 ports/litex/boards/fomu/generated/soc.h create mode 100644 ports/litex/boards/fomu/mpconfigboard.h create mode 100644 ports/litex/boards/fomu/mpconfigboard.mk create mode 100644 ports/litex/boards/fomu/pins.c create mode 100644 ports/litex/boards/fomu/profiling.gdb.txt create mode 100644 ports/litex/common-hal/digitalio/DigitalInOut.c create mode 100644 ports/litex/common-hal/digitalio/DigitalInOut.h create mode 100644 ports/litex/common-hal/digitalio/__init__.c create mode 100644 ports/litex/common-hal/microcontroller/Pin.c create mode 100644 ports/litex/common-hal/microcontroller/Pin.h create mode 100644 ports/litex/common-hal/microcontroller/Processor.c create mode 100644 ports/litex/common-hal/microcontroller/Processor.h create mode 100644 ports/litex/common-hal/microcontroller/__init__.c create mode 100644 ports/litex/common-hal/neopixel_write/__init__.c create mode 100644 ports/litex/common-hal/supervisor/Runtime.c create mode 100644 ports/litex/common-hal/supervisor/Runtime.h create mode 100644 ports/litex/common-hal/supervisor/__init__.c create mode 100644 ports/litex/common-hal/time/__init__.c create mode 100644 ports/litex/crt0-vexriscv.S create mode 100644 ports/litex/fatfs_port.c create mode 100644 ports/litex/hw/common.h create mode 100644 ports/litex/irq.h create mode 100644 ports/litex/mpconfigport.h create mode 100644 ports/litex/mpconfigport.mk create mode 100644 ports/litex/mphalport.c create mode 100644 ports/litex/mphalport.h create mode 100644 ports/litex/qstrdefsport.h create mode 100644 ports/litex/supervisor/internal_flash.c create mode 100644 ports/litex/supervisor/internal_flash.h create mode 100644 ports/litex/supervisor/internal_flash_root_pointers.h create mode 100644 ports/litex/supervisor/port.c create mode 100644 ports/litex/supervisor/usb.c create mode 100644 ports/litex/tick.c create mode 100644 ports/litex/tick.h mode change 100755 => 100644 tools/dfu.py diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 2e1a6188becd8..847cdf0249755 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -131,6 +131,7 @@ jobs: - "arduino_nano_33_iot" - "arduino_zero" - "bast_pro_mini_m0" + - "bdmicro_vina_m0" - "capablerobot_usbhub" - "catwan_usbstick" - "circuitbrains_basic_m0" @@ -279,3 +280,49 @@ jobs: AWS_ACCESS_KEY_ID: ${{ secrets.AWS_ACCESS_KEY_ID }} AWS_SECRET_ACCESS_KEY: ${{ secrets.AWS_SECRET_ACCESS_KEY }} if: github.event_name == 'push' || (github.event_name == 'release' && (github.event.action == 'published' || github.event.action == 'rerequested')) + + build-riscv: + runs-on: ubuntu-16.04 + needs: test + strategy: + fail-fast: false + matrix: + board: + - "fomu" + + steps: + - name: Set up Python 3.5 + uses: actions/setup-python@v1 + with: + python-version: 3.5 + - name: Install deps + run: | + sudo apt-get install -y gettext + pip install requests sh click setuptools awscli + wget https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-linux-centos6.tar.gz + sudo tar -C /usr --strip-components=1 -xaf riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-linux-centos6.tar.gz + - name: Versions + run: | + gcc --version + riscv64-unknown-elf-gcc --version + python3 --version + - uses: actions/checkout@v1 + with: + submodules: true + - name: mpy-cross + run: make -C mpy-cross -j2 + - name: build + run: python3 -u build_release_files.py + working-directory: tools + env: + BOARDS: ${{ matrix.board }} + - uses: actions/upload-artifact@v1.0.0 + with: + name: ${{ matrix.board }} + path: bin/${{ matrix.board }} + - name: Upload to S3 + run: "[ -z \"$AWS_ACCESS_KEY_ID\" ] || aws s3 cp bin/ s3://adafruit-circuit-python/bin/ --recursive --no-progress --region us-east-1" + env: + AWS_ACCESS_KEY_ID: ${{ secrets.AWS_ACCESS_KEY_ID }} + AWS_SECRET_ACCESS_KEY: ${{ secrets.AWS_SECRET_ACCESS_KEY }} + if: github.event_name == 'push' || (github.event_name == 'release' && (github.event.action == 'published' || github.event.action == 'rerequested')) diff --git a/conf.py b/conf.py index 2ea0e8dc0f655..6f0cd8b03b36a 100644 --- a/conf.py +++ b/conf.py @@ -123,6 +123,7 @@ "ports/atmel-samd/tools", "ports/cxd56/mkspk", "ports/cxd56/spresense-exported-sdk", + "ports/litex/hw", "ports/minimal", "ports/mimxrt10xx/peripherals", "ports/mimxrt10xx/sdk", @@ -133,6 +134,7 @@ "ports/nrf/peripherals", "ports/nrf/usb", "ports/stm/st_driver", + "ports/stm/packages", "ports/stm/peripherals", "ports/stm/ref", "ports/unix", diff --git a/locale/ID.po b/locale/ID.po index 567fe5ff3e720..de158c568ac3f 100644 --- a/locale/ID.po +++ b/locale/ID.po @@ -398,6 +398,11 @@ msgstr "" msgid "Buffer too large and unable to allocate" msgstr "" +#: shared-bindings/_bleio/PacketBuffer.c +#, c-format +msgid "Buffer too short by %d bytes" +msgstr "" + #: ports/atmel-samd/common-hal/displayio/ParallelBus.c #: ports/nrf/common-hal/displayio/ParallelBus.c #, fuzzy, c-format diff --git a/locale/circuitpython.pot b/locale/circuitpython.pot index a6dabdaec06cf..7e9b3aadf20e8 100644 --- a/locale/circuitpython.pot +++ b/locale/circuitpython.pot @@ -394,6 +394,11 @@ msgstr "" msgid "Buffer too large and unable to allocate" msgstr "" +#: shared-bindings/_bleio/PacketBuffer.c +#, c-format +msgid "Buffer too short by %d bytes" +msgstr "" + #: ports/atmel-samd/common-hal/displayio/ParallelBus.c #: ports/nrf/common-hal/displayio/ParallelBus.c #, c-format diff --git a/locale/de_DE.po b/locale/de_DE.po index 5d4bec87232bc..709a34ed57adf 100644 --- a/locale/de_DE.po +++ b/locale/de_DE.po @@ -398,6 +398,11 @@ msgstr "Der Puffer muss eine Mindestenslänge von 1 haben" msgid "Buffer too large and unable to allocate" msgstr "" +#: shared-bindings/_bleio/PacketBuffer.c +#, c-format +msgid "Buffer too short by %d bytes" +msgstr "" + #: ports/atmel-samd/common-hal/displayio/ParallelBus.c #: ports/nrf/common-hal/displayio/ParallelBus.c #, c-format diff --git a/locale/en_US.po b/locale/en_US.po index 17a4fb9dc1d70..d516d41d9b9f3 100644 --- a/locale/en_US.po +++ b/locale/en_US.po @@ -394,6 +394,11 @@ msgstr "" msgid "Buffer too large and unable to allocate" msgstr "" +#: shared-bindings/_bleio/PacketBuffer.c +#, c-format +msgid "Buffer too short by %d bytes" +msgstr "" + #: ports/atmel-samd/common-hal/displayio/ParallelBus.c #: ports/nrf/common-hal/displayio/ParallelBus.c #, c-format diff --git a/locale/en_x_pirate.po b/locale/en_x_pirate.po index f356c6e163ed7..e3f02c246ff6f 100644 --- a/locale/en_x_pirate.po +++ b/locale/en_x_pirate.po @@ -398,6 +398,11 @@ msgstr "" msgid "Buffer too large and unable to allocate" msgstr "" +#: shared-bindings/_bleio/PacketBuffer.c +#, c-format +msgid "Buffer too short by %d bytes" +msgstr "" + #: ports/atmel-samd/common-hal/displayio/ParallelBus.c #: ports/nrf/common-hal/displayio/ParallelBus.c #, c-format diff --git a/locale/es.po b/locale/es.po index 417a0126ac6c6..115fc8037e907 100644 --- a/locale/es.po +++ b/locale/es.po @@ -400,6 +400,11 @@ msgstr "Buffer debe ser de longitud 1 como minimo" msgid "Buffer too large and unable to allocate" msgstr "" +#: shared-bindings/_bleio/PacketBuffer.c +#, c-format +msgid "Buffer too short by %d bytes" +msgstr "" + #: ports/atmel-samd/common-hal/displayio/ParallelBus.c #: ports/nrf/common-hal/displayio/ParallelBus.c #, c-format diff --git a/locale/fil.po b/locale/fil.po index 12baeea9ddfd5..da2bc9459e2aa 100644 --- a/locale/fil.po +++ b/locale/fil.po @@ -400,6 +400,11 @@ msgstr "Buffer dapat ay hindi baba sa 1 na haba" msgid "Buffer too large and unable to allocate" msgstr "" +#: shared-bindings/_bleio/PacketBuffer.c +#, c-format +msgid "Buffer too short by %d bytes" +msgstr "" + #: ports/atmel-samd/common-hal/displayio/ParallelBus.c #: ports/nrf/common-hal/displayio/ParallelBus.c #, fuzzy, c-format diff --git a/locale/fr.po b/locale/fr.po index a8d896b52554c..100fc2b9c210e 100644 --- a/locale/fr.po +++ b/locale/fr.po @@ -404,6 +404,11 @@ msgstr "Le tampon doit être de longueur au moins 1" msgid "Buffer too large and unable to allocate" msgstr "" +#: shared-bindings/_bleio/PacketBuffer.c +#, c-format +msgid "Buffer too short by %d bytes" +msgstr "" + #: ports/atmel-samd/common-hal/displayio/ParallelBus.c #: ports/nrf/common-hal/displayio/ParallelBus.c #, fuzzy, c-format diff --git a/locale/it_IT.po b/locale/it_IT.po index 901ced7e4738f..8b868f83fa269 100644 --- a/locale/it_IT.po +++ b/locale/it_IT.po @@ -400,6 +400,11 @@ msgstr "Il buffer deve essere lungo almeno 1" msgid "Buffer too large and unable to allocate" msgstr "" +#: shared-bindings/_bleio/PacketBuffer.c +#, c-format +msgid "Buffer too short by %d bytes" +msgstr "" + #: ports/atmel-samd/common-hal/displayio/ParallelBus.c #: ports/nrf/common-hal/displayio/ParallelBus.c #, fuzzy, c-format diff --git a/locale/ko.po b/locale/ko.po index f84979c645fb6..5cc2bcf3a6ab2 100644 --- a/locale/ko.po +++ b/locale/ko.po @@ -398,6 +398,11 @@ msgstr "잘못된 크기의 버퍼. >1 여야합니다" msgid "Buffer too large and unable to allocate" msgstr "" +#: shared-bindings/_bleio/PacketBuffer.c +#, c-format +msgid "Buffer too short by %d bytes" +msgstr "" + #: ports/atmel-samd/common-hal/displayio/ParallelBus.c #: ports/nrf/common-hal/displayio/ParallelBus.c #, c-format diff --git a/locale/pl.po b/locale/pl.po index 12bd980bd83b1..659d6330136bd 100644 --- a/locale/pl.po +++ b/locale/pl.po @@ -397,6 +397,11 @@ msgstr "Bufor musi mieć długość 1 lub więcej" msgid "Buffer too large and unable to allocate" msgstr "" +#: shared-bindings/_bleio/PacketBuffer.c +#, c-format +msgid "Buffer too short by %d bytes" +msgstr "" + #: ports/atmel-samd/common-hal/displayio/ParallelBus.c #: ports/nrf/common-hal/displayio/ParallelBus.c #, c-format diff --git a/locale/pt_BR.po b/locale/pt_BR.po index 3291296972113..511f0a5bb618b 100644 --- a/locale/pt_BR.po +++ b/locale/pt_BR.po @@ -397,6 +397,11 @@ msgstr "" msgid "Buffer too large and unable to allocate" msgstr "" +#: shared-bindings/_bleio/PacketBuffer.c +#, c-format +msgid "Buffer too short by %d bytes" +msgstr "" + #: ports/atmel-samd/common-hal/displayio/ParallelBus.c #: ports/nrf/common-hal/displayio/ParallelBus.c #, fuzzy, c-format diff --git a/locale/zh_Latn_pinyin.po b/locale/zh_Latn_pinyin.po index 7cf00580b4184..2319bf4d7d93a 100644 --- a/locale/zh_Latn_pinyin.po +++ b/locale/zh_Latn_pinyin.po @@ -403,6 +403,11 @@ msgstr "Huǎnchōng qū bìxū zhìshǎo chángdù 1" msgid "Buffer too large and unable to allocate" msgstr "huǎn chōng qū tài dà ， wú fǎ fēn pèi" +#: shared-bindings/_bleio/PacketBuffer.c +#, c-format +msgid "Buffer too short by %d bytes" +msgstr "" + #: ports/atmel-samd/common-hal/displayio/ParallelBus.c #: ports/nrf/common-hal/displayio/ParallelBus.c #, c-format diff --git a/ports/atmel-samd/boards/bdmicro_vina_m0/board.c b/ports/atmel-samd/boards/bdmicro_vina_m0/board.c new file mode 100644 index 0000000000000..bd63baa6fd558 --- /dev/null +++ b/ports/atmel-samd/boards/bdmicro_vina_m0/board.c @@ -0,0 +1,48 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "boards/board.h" +#include "mpconfigboard.h" + +void board_init(void) +{ + // struct port_config pin_conf; + // port_get_config_defaults(&pin_conf); + // + // pin_conf.direction = PORT_PIN_DIR_OUTPUT; + // port_pin_set_config(MICROPY_HW_LED_TX, &pin_conf); + // port_pin_set_output_level(MICROPY_HW_LED_TX, true); + // + // port_pin_set_config(MICROPY_HW_LED_RX, &pin_conf); + // port_pin_set_output_level(MICROPY_HW_LED_RX, true); +} + +bool board_requests_safe_mode(void) { + return false; +} + +void reset_board(void) { +} diff --git a/ports/atmel-samd/boards/bdmicro_vina_m0/mpconfigboard.h b/ports/atmel-samd/boards/bdmicro_vina_m0/mpconfigboard.h new file mode 100644 index 0000000000000..458b1e12a6ac7 --- /dev/null +++ b/ports/atmel-samd/boards/bdmicro_vina_m0/mpconfigboard.h @@ -0,0 +1,35 @@ +#define MICROPY_HW_BOARD_NAME "BDMICRO Vina M0" +#define MICROPY_HW_MCU_NAME "samd21g18" + +#define MICROPY_HW_LED_STATUS (&pin_PA28) +#define MICROPY_HW_LED_TX &pin_PA27 +#define MICROPY_HW_LED_RX &pin_PA31 + +// Clock rates are off: Salae reads 12MHz which is the limit even though we set it to the safer 8MHz. +#define SPI_FLASH_BAUDRATE (8000000) + +#define SPI_FLASH_MOSI_PIN &pin_PB22 +#define SPI_FLASH_MISO_PIN &pin_PB03 +#define SPI_FLASH_SCK_PIN &pin_PB23 +#define SPI_FLASH_CS_PIN &pin_PA13 + +// These are pins not to reset. +#define MICROPY_PORT_A (0) +#define MICROPY_PORT_B (0) +#define MICROPY_PORT_C (0) + +#define BOARD_HAS_CRYSTAL 0 + +#define DEFAULT_I2C_BUS_SCL (&pin_PA23) +#define DEFAULT_I2C_BUS_SDA (&pin_PA22) + +#define DEFAULT_SPI_BUS_SCK (&pin_PB11) +#define DEFAULT_SPI_BUS_MOSI (&pin_PB10) +#define DEFAULT_SPI_BUS_MISO (&pin_PA12) + +#define DEFAULT_UART_BUS_RX (&pin_PA11) +#define DEFAULT_UART_BUS_TX (&pin_PA10) + +// USB is always used internally so skip the pin objects for it. +#define IGNORE_PIN_PA24 1 +#define IGNORE_PIN_PA25 1 diff --git a/ports/atmel-samd/boards/bdmicro_vina_m0/mpconfigboard.mk b/ports/atmel-samd/boards/bdmicro_vina_m0/mpconfigboard.mk new file mode 100644 index 0000000000000..1537540424b49 --- /dev/null +++ b/ports/atmel-samd/boards/bdmicro_vina_m0/mpconfigboard.mk @@ -0,0 +1,18 @@ +USB_VID = 0x31e2 +USB_PID = 0x2002 +USB_PRODUCT = "Vina M0" +USB_MANUFACTURER = "BDMICRO LLC" + +CHIP_VARIANT = SAMD21G18A +CHIP_FAMILY = samd21 + +SPI_FLASH_FILESYSTEM = 1 +EXTERNAL_FLASH_DEVICE_COUNT = 1 +EXTERNAL_FLASH_DEVICES = "MX25L51245G" +LONGINT_IMPL = MPZ + +CIRCUITPY_BITBANGIO = 0 +CIRCUITPY_I2CSLAVE = 0 + +CFLAGS_INLINE_LIMIT = 60 +SUPEROPT_GC = 0 diff --git a/ports/atmel-samd/boards/bdmicro_vina_m0/pins.c b/ports/atmel-samd/boards/bdmicro_vina_m0/pins.c new file mode 100644 index 0000000000000..0ebceb28ddc5e --- /dev/null +++ b/ports/atmel-samd/boards/bdmicro_vina_m0/pins.c @@ -0,0 +1,39 @@ +#include "shared-bindings/board/__init__.h" + +STATIC const mp_rom_map_elem_t board_global_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR_RTC_INT), MP_ROM_PTR(&pin_PA00) }, + { MP_ROM_QSTR(MP_QSTR_RTC_CLK), MP_ROM_PTR(&pin_PA01) }, + { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA02) }, + { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PB08) }, + { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PB09) }, + { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PA04) }, + { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PA05) }, + { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PB02) }, + { MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_PA11) }, + { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_PA11) }, + { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PA10) }, + { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_PA10) }, + { MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_PA14) }, + { MP_ROM_QSTR(MP_QSTR_RTC_TS), MP_ROM_PTR(&pin_PA14) }, + { MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_PA09) }, + { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PA08) }, + { MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PA15) }, + { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PA20) }, + { MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_PA21) }, + { MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PA06) }, + { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PA07) }, + { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PA18) }, + { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PA16) }, + { MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PA19) }, + { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA17) }, + { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PA22) }, + { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PA23) }, + { MP_ROM_QSTR(MP_QSTR_PGM_LED), MP_ROM_PTR(&pin_PA28) }, + { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_PB11) }, + { MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_PB10) }, + { MP_ROM_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_PA12) }, + { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) }, + { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) }, + { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) }, +}; +MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table); diff --git a/ports/atmel-samd/boards/hallowing_m0_express/board.c b/ports/atmel-samd/boards/hallowing_m0_express/board.c index 07546abf5ca90..0b44bd4bb16d0 100644 --- a/ports/atmel-samd/boards/hallowing_m0_express/board.c +++ b/ports/atmel-samd/boards/hallowing_m0_express/board.c @@ -79,7 +79,9 @@ void board_init(void) { &pin_PA28, // Command or data &pin_PA01, // Chip select &pin_PA27, // Reset - 12000000); + 12000000, // Baudrate + 0, // Polarity + 0); // Phase displayio_display_obj_t* display = &displays[0].display; display->base.type = &displayio_display_type; diff --git a/ports/atmel-samd/boards/hallowing_m4_express/board.c b/ports/atmel-samd/boards/hallowing_m4_express/board.c index 6822368d728a4..5dbdd499afd59 100644 --- a/ports/atmel-samd/boards/hallowing_m4_express/board.c +++ b/ports/atmel-samd/boards/hallowing_m4_express/board.c @@ -59,7 +59,9 @@ void board_init(void) { &pin_PB31, // TFT_DC Command or data &pin_PA27, // TFT_CS Chip select &pin_PB30, // TFT_RST Reset - 60000000); + 60000000, // Baudrate + 0, // Polarity + 0); // Phase displayio_display_obj_t* display = &displays[0].display; display->base.type = &displayio_display_type; diff --git a/ports/atmel-samd/boards/monster_m4sk/board.c b/ports/atmel-samd/boards/monster_m4sk/board.c index eeafdb4b80552..684639c3097ae 100644 --- a/ports/atmel-samd/boards/monster_m4sk/board.c +++ b/ports/atmel-samd/boards/monster_m4sk/board.c @@ -60,7 +60,9 @@ void board_init(void) { &pin_PA07, // TFT_DC Command or data &pin_PA06, // TFT_CS Chip select &pin_PA04, // TFT_RST Reset - 60000000); + 60000000, // Baudrate + 0, // Polarity + 0); // Phase displayio_display_obj_t* display = &displays[0].display; display->base.type = &displayio_display_type; diff --git a/ports/atmel-samd/boards/openbook_m4/board.c b/ports/atmel-samd/boards/openbook_m4/board.c index 2d9b3164749f1..02270e7e5741d 100644 --- a/ports/atmel-samd/boards/openbook_m4/board.c +++ b/ports/atmel-samd/boards/openbook_m4/board.c @@ -65,7 +65,9 @@ void board_init(void) { &pin_PB05, // EPD_DC Command or data &pin_PB07, // EPD_CS Chip select &pin_PA00, // EPD_RST Reset - 1000000); + 1000000, // Baudrate + 0, // Polarity + 0); // Phase displayio_epaperdisplay_obj_t* display = &displays[0].epaper_display; display->base.type = &displayio_epaperdisplay_type; diff --git a/ports/atmel-samd/boards/pewpew_m4/board.c b/ports/atmel-samd/boards/pewpew_m4/board.c index ef259e27a61f9..0f8936696f22b 100644 --- a/ports/atmel-samd/boards/pewpew_m4/board.c +++ b/ports/atmel-samd/boards/pewpew_m4/board.c @@ -107,7 +107,9 @@ void board_init(void) { &pin_PA16, // TFT_DC Command or data &pin_PA11, // TFT_CS Chip select &pin_PA17, // TFT_RST Reset - 60000000); + 60000000, // Baudrate + 0, // Polarity + 0); // Phase uint32_t cfg0 = lookupCfg(CFG_DISPLAY_CFG0, 0x000000); uint32_t offX = (cfg0 >> 8) & 0xff; diff --git a/ports/atmel-samd/boards/pybadge/board.c b/ports/atmel-samd/boards/pybadge/board.c index 1209c027eeaf8..257d72e30d36c 100644 --- a/ports/atmel-samd/boards/pybadge/board.c +++ b/ports/atmel-samd/boards/pybadge/board.c @@ -82,7 +82,9 @@ void board_init(void) { &pin_PB05, // TFT_DC Command or data &pin_PB07, // TFT_CS Chip select &pin_PA00, // TFT_RST Reset - 60000000); + 60000000, // Baudrate + 0, // Polarity + 0); // Phase displayio_display_obj_t* display = &displays[0].display; display->base.type = &displayio_display_type; diff --git a/ports/atmel-samd/boards/pybadge_airlift/board.c b/ports/atmel-samd/boards/pybadge_airlift/board.c index dfbf7023fa0b9..7df245a724763 100644 --- a/ports/atmel-samd/boards/pybadge_airlift/board.c +++ b/ports/atmel-samd/boards/pybadge_airlift/board.c @@ -60,7 +60,9 @@ void board_init(void) { &pin_PB05, // TFT_DC Command or data &pin_PB06, // TFT_CS Chip select &pin_PB07, // TFT_RST Reset - 60000000); + 60000000, // Baudrate + 0, // Polarity + 0); // Phase displayio_display_obj_t* display = &displays[0].display; display->base.type = &displayio_display_type; diff --git a/ports/atmel-samd/boards/pygamer/board.c b/ports/atmel-samd/boards/pygamer/board.c index 6df485fa9eff7..7c3ca6e335354 100644 --- a/ports/atmel-samd/boards/pygamer/board.c +++ b/ports/atmel-samd/boards/pygamer/board.c @@ -82,7 +82,9 @@ void board_init(void) { &pin_PB05, // TFT_DC Command or data &pin_PB12, // TFT_CS Chip select &pin_PA00, // TFT_RST Reset - 60000000); + 60000000, // Baudrate + 0, // Polarity + 0); // Phase displayio_display_obj_t* display = &displays[0].display; display->base.type = &displayio_display_type; diff --git a/ports/atmel-samd/boards/pygamer_advance/board.c b/ports/atmel-samd/boards/pygamer_advance/board.c index ad5abd3f6ceb8..7fd3ebc5e150d 100644 --- a/ports/atmel-samd/boards/pygamer_advance/board.c +++ b/ports/atmel-samd/boards/pygamer_advance/board.c @@ -60,7 +60,9 @@ void board_init(void) { &pin_PA00, // TFT_DC Command or data &pin_PB15, // TFT_CS Chip select &pin_PB05, // TFT_RST Reset - 60000000); + 60000000, // Baudrate + 0, // Polarity + 0); // Phase displayio_display_obj_t* display = &displays[0].display; display->base.type = &displayio_display_type; diff --git a/ports/atmel-samd/boards/ugame10/board.c b/ports/atmel-samd/boards/ugame10/board.c index 96f2361fd6d55..07814d558b649 100644 --- a/ports/atmel-samd/boards/ugame10/board.c +++ b/ports/atmel-samd/boards/ugame10/board.c @@ -79,7 +79,9 @@ void board_init(void) { &pin_PA09, // Command or data &pin_PA08, // Chip select NULL, // Reset - 24000000); + 24000000, // Baudrate + 0, // Polarity + 0); // Phase displayio_display_obj_t* display = &displays[0].display; display->base.type = &displayio_display_type; diff --git a/ports/litex/Makefile b/ports/litex/Makefile new file mode 100644 index 0000000000000..51cb186356c94 --- /dev/null +++ b/ports/litex/Makefile @@ -0,0 +1,200 @@ +# This file is part of the MicroPython project, http://micropython.org/ +# +# The MIT License (MIT) +# +# Copyright (c) 2019 Scott Shawcroft for Adafruit Industries +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +# Select the board to build for. +ifeq ($(BOARD),) + $(error You must provide a BOARD parameter) +else + ifeq ($(wildcard boards/$(BOARD)/.),) + $(error Invalid BOARD specified) + endif +endif + +# If the build directory is not given, make it reflect the board name. +BUILD ?= build-$(BOARD) + +include ../../py/mkenv.mk +# Board-specific +include boards/$(BOARD)/mpconfigboard.mk +# Port-specific +include mpconfigport.mk + +# CircuitPython-specific +include $(TOP)/py/circuitpy_mpconfig.mk + +# qstr definitions (must come before including py.mk) +QSTR_DEFS = qstrdefsport.h + +# include py core make definitions +include $(TOP)/py/py.mk + +include $(TOP)/supervisor/supervisor.mk + +# Include make rules and variables common across CircuitPython builds. +include $(TOP)/py/circuitpy_defns.mk + +CROSS_COMPILE = riscv64-unknown-elf- + +####################################### +# CFLAGS +####################################### + +INC += -I. +INC += -I../.. +INC += -I$(BUILD) +INC += -I$(BUILD)/genhdr +INC += -I./boards +INC += -I./boards/$(BOARD) +INC += -I./peripherals +INC += -I../../lib/mp-readline +INC += -I../../lib/tinyusb/src +INC += -I../../supervisor/shared/usb + + +#Debugging/Optimization +ifeq ($(DEBUG), 1) + CFLAGS += -ggdb + # You may want to enable these flags to make setting breakpoints easier. + CFLAGS += -fno-inline -fno-ipa-sra +else + CFLAGS += -Os -DNDEBUG -ggdb3 + # TODO: Test with -flto + ### CFLAGS += -flto +endif + +CFLAGS += $(INC) -Werror -Wall -std=gnu11 -nostdlib $(BASE_CFLAGS) $(C_DEFS) $(CFLAGS_MOD) $(COPT) + +# TODO: check this +CFLAGS += -D__START=main -DFOMU + +LD_FILE := boards/$(BOARD)/$(BOARD)-spi.ld + +LDFLAGS = $(CFLAGS) -fshort-enums -Wl,-nostdlib -Wl,-T,$(LD_FILE) -Wl,-Map=$@.map -Wl,-cref -Wl,-gc-sections -specs=nano.specs -Wl,-melf32lriscv +LIBS := -lgcc -lc + + +LDFLAGS += -flto -ffreestanding -nostartfiles -Wl,--gc-section -Wl,-Bstatic -Wl,-melf32lriscv -nostartfiles \ + -Wl,--no-warn-mismatch \ + -Wl,--build-id=none + +# Use toolchain libm if we're not using our own. +ifndef INTERNAL_LIBM +LIBS += -lm +endif + +# TinyUSB defines +CFLAGS += -DCFG_TUSB_MCU=OPT_MCU_VALENTYUSB_EPTRI -DCFG_TUD_CDC_RX_BUFSIZE=1024 -DCFG_TUD_CDC_TX_BUFSIZE=1024 -DCFG_TUD_MSC_BUFSIZE=4096 -DCFG_TUD_MIDI_RX_BUFSIZE=128 -DCFG_TUD_MIDI_TX_BUFSIZE=128 + + +###################################### +# source +###################################### + + +SRC_C += \ + background.c \ + fatfs_port.c \ + mphalport.c \ + tick.c \ + boards/$(BOARD)/board.c \ + boards/$(BOARD)/pins.c \ + lib/libc/string0.c \ + lib/mp-readline/readline.c \ + lib/oofatfs/ff.c \ + lib/oofatfs/option/ccsbcs.c \ + lib/timeutils/timeutils.c \ + lib/utils/buffer_helper.c \ + lib/utils/context_manager_helpers.c \ + lib/utils/interrupt_char.c \ + lib/utils/pyexec.c \ + lib/utils/stdout_helpers.c \ + lib/utils/sys_stdio_mphal.c \ + supervisor/shared/memory.c + +ifneq ($(USB),FALSE) +SRC_C += lib/tinyusb/src/portable/valentyusb/eptri/dcd_eptri.c +endif + +SRC_S = \ + crt0-vexriscv.S + +SRC_COMMON_HAL_EXPANDED = $(addprefix shared-bindings/, $(SRC_COMMON_HAL)) \ + $(addprefix shared-bindings/, $(SRC_BINDINGS_ENUMS)) \ + $(addprefix common-hal/, $(SRC_COMMON_HAL)) + +SRC_SHARED_MODULE_EXPANDED = $(addprefix shared-bindings/, $(SRC_SHARED_MODULE)) \ + $(addprefix shared-module/, $(SRC_SHARED_MODULE)) \ + $(addprefix shared-module/, $(SRC_SHARED_MODULE_INTERNAL)) + + +ifneq ($(FROZEN_MPY_DIR),) +FROZEN_MPY_PY_FILES := $(shell find -L $(FROZEN_MPY_DIR) -type f -name '*.py') +FROZEN_MPY_MPY_FILES := $(addprefix $(BUILD)/,$(FROZEN_MPY_PY_FILES:.py=.mpy)) +endif + +OBJ += $(PY_O) $(SUPERVISOR_O) $(addprefix $(BUILD)/, $(SRC_C:.c=.o)) +OBJ += $(addprefix $(BUILD)/, $(SRC_COMMON_HAL_EXPANDED:.c=.o)) +OBJ += $(addprefix $(BUILD)/, $(SRC_SHARED_MODULE_EXPANDED:.c=.o)) +ifeq ($(INTERNAL_LIBM),1) +OBJ += $(addprefix $(BUILD)/, $(SRC_LIBM:.c=.o)) +endif +OBJ += $(addprefix $(BUILD)/, $(SRC_S:.S=.o)) +OBJ += $(addprefix $(BUILD)/, $(SRC_MOD:.c=.o)) + +$(BUILD)/$(FATFS_DIR)/ff.o: COPT += -Os +$(filter $(PY_BUILD)/../extmod/vfs_fat_%.o, $(PY_O)): COPT += -Os + +# List of sources for qstr extraction +SRC_QSTR += $(SRC_C) $(SRC_SUPERVISOR) $(SRC_MOD) $(SRC_COMMON_HAL_EXPANDED) $(SRC_SHARED_MODULE_EXPANDED) +# Sources that only hold QSTRs after pre-processing. +SRC_QSTR_PREPROCESSOR += + + +all: $(BUILD)/firmware.bin $(BUILD)/firmware.dfu + +$(BUILD)/firmware.elf: $(OBJ) + $(STEPECHO) "LINK $@" + $(Q)$(CC) -o $@ $(LDFLAGS) $^ -Wl,--start-group $(LIBS) -Wl,--end-group + $(Q)$(SIZE) $@ | $(PYTHON3) $(TOP)/tools/build_memory_info.py $(LD_FILE) + +$(BUILD)/firmware.bin: $(BUILD)/firmware.elf + $(STEPECHO) "Create $@" + $(Q)$(OBJCOPY) -O binary $^ $@ +# $(Q)$(OBJCOPY) -O binary -j .vectors -j .text -j .data $^ $@ + +$(BUILD)/firmware.hex: $(BUILD)/firmware.elf + $(STEPECHO) "Create $@" + $(Q)$(OBJCOPY) -O ihex $^ $@ +# $(Q)$(OBJCOPY) -O ihex -j .vectors -j .text -j .data $^ $@ + +$(BUILD)/firmware.dfu: $(BUILD)/firmware.bin + $(ECHO) "Create $@" + $(PYTHON3) $(TOP)/tools/dfu.py -b $^ -D 0x1209:0x5bf0 "$(BUILD)/firmware.dfu" + +include $(TOP)/py/mkrules.mk + +# Print out the value of a make variable. +# https://stackoverflow.com/questions/16467718/how-to-print-out-a-variable-in-makefile +print-%: + @echo $* = $($*) diff --git a/ports/litex/background.c b/ports/litex/background.c new file mode 100644 index 0000000000000..8c1897043455e --- /dev/null +++ b/ports/litex/background.c @@ -0,0 +1,60 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/runtime.h" +#include "supervisor/filesystem.h" +#include "supervisor/usb.h" +#include "supervisor/shared/stack.h" + +#if CIRCUITPY_DISPLAYIO +#include "shared-module/displayio/__init__.h" +#endif + +static bool running_background_tasks = false; + +void background_tasks_reset(void) { + running_background_tasks = false; +} + +void run_background_tasks(void) { + // Don't call ourselves recursively. + if (running_background_tasks) { + return; + } + running_background_tasks = true; + filesystem_background(); + + #if USB_AVAILABLE + usb_background(); + #endif + + #if CIRCUITPY_DISPLAYIO + displayio_background(); + #endif + running_background_tasks = false; + + assert_heap_ok(); +} diff --git a/ports/litex/background.h b/ports/litex/background.h new file mode 100644 index 0000000000000..09551c7fbb2d0 --- /dev/null +++ b/ports/litex/background.h @@ -0,0 +1,35 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2019 Dan Halbert for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MICROPY_INCLUDED_LITEX_BACKGROUND_H +#define MICROPY_INCLUDED_LITEX_BACKGROUND_H + +#include + +void background_tasks_reset(void); +void run_background_tasks(void); + +#endif // MICROPY_INCLUDED_LITEX_BACKGROUND_H diff --git a/ports/litex/boards/board.h b/ports/litex/boards/board.h new file mode 100644 index 0000000000000..837b371904523 --- /dev/null +++ b/ports/litex/boards/board.h @@ -0,0 +1,45 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +// This file defines board specific functions. + +#ifndef MICROPY_INCLUDED_LITEX_BOARDS_BOARD_H +#define MICROPY_INCLUDED_LITEX_BOARDS_BOARD_H + +#include + +// Initializes board related state once on start up. +void board_init(void); + +// Returns true if the user initiates safe mode in a board specific way. +// Also add BOARD_USER_SAFE_MODE in mpconfigboard.h to explain the board specific +// way. +bool board_requests_safe_mode(void); + +// Reset the state of off MCU components such as neopixels. +void reset_board(void); + +#endif // MICROPY_INCLUDED_LITEX_BOARDS_BOARD_H diff --git a/ports/litex/boards/fomu/board.c b/ports/litex/boards/fomu/board.c new file mode 100644 index 0000000000000..97e1ecadd6cde --- /dev/null +++ b/ports/litex/boards/fomu/board.c @@ -0,0 +1,75 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "boards/board.h" +#include "mpconfigboard.h" +#include "csr.h" + +// ICE40 LED Driver hard macro. +// See http://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/IK/ICE40LEDDriverUsageGuide.ashx?document_id=50668 +enum led_registers { + LEDDCR0 = 8, + LEDDBR = 9, + LEDDONR = 10, + LEDDOFR = 11, + LEDDBCRR = 5, + LEDDBCFR = 6, + LEDDPWRR = 1, + LEDDPWRG = 2, + LEDDPWRB = 3, +}; + +#define BREATHE_ENABLE (1 << 7) +#define BREATHE_EDGE_ON (0 << 6) +#define BREATHE_EDGE_BOTH (1 << 6) +#define BREATHE_MODE_MODULATE (1 << 5) +#define BREATHE_RATE(x) ((x & 7) << 0) + +// Write a value into the LEDDA_IP register. +static void ledda_write(uint8_t value, uint8_t addr) { + rgb_addr_write(addr); + rgb_dat_write(value); +} + +void board_init(void) { + uint8_t onrate = 15; + uint8_t offrate = 1; + + ledda_write(BREATHE_ENABLE | BREATHE_MODE_MODULATE | BREATHE_RATE(onrate), LEDDBCRR); + ledda_write(BREATHE_ENABLE | BREATHE_MODE_MODULATE | BREATHE_RATE(offrate), LEDDBCFR); + + ledda_write(123, LEDDPWRR); // Red + ledda_write(3, LEDDPWRG); // Green + ledda_write(98, LEDDPWRB); // Blue +} + +bool board_requests_safe_mode(void) { + return false; +} + +void reset_board(void) { + +} diff --git a/ports/litex/boards/fomu/csr.h b/ports/litex/boards/fomu/csr.h new file mode 100644 index 0000000000000..bf66fe3a17b4b --- /dev/null +++ b/ports/litex/boards/fomu/csr.h @@ -0,0 +1,647 @@ +//-------------------------------------------------------------------------------- +// Auto-generated by Migen (f4fcd10) & LiteX (de205d4a) on 2019-11-25 14:57:34 +//-------------------------------------------------------------------------------- +#include +#ifndef __GENERATED_CSR_H +#define __GENERATED_CSR_H +#include +#ifdef CSR_ACCESSORS_DEFINED +extern void csr_writeb(uint8_t value, unsigned long addr); +extern uint8_t csr_readb(unsigned long addr); +extern void csr_writew(uint16_t value, unsigned long addr); +extern uint16_t csr_readw(unsigned long addr); +extern void csr_writel(uint32_t value, unsigned long addr); +extern uint32_t csr_readl(unsigned long addr); +#else /* ! CSR_ACCESSORS_DEFINED */ +#include +#endif /* ! CSR_ACCESSORS_DEFINED */ + +/* ctrl */ +#define CSR_CTRL_BASE 0xe0000000L +#define CSR_CTRL_RESET_ADDR 0xe0000000L +#define CSR_CTRL_RESET_SIZE 1 +static inline unsigned char ctrl_reset_read(void) { + unsigned char r = csr_readl(0xe0000000L); + return r; +} +static inline void ctrl_reset_write(unsigned char value) { + csr_writel(value, 0xe0000000L); +} +#define CSR_CTRL_SCRATCH_ADDR 0xe0000004L +#define CSR_CTRL_SCRATCH_SIZE 4 +static inline unsigned int ctrl_scratch_read(void) { + unsigned int r = csr_readl(0xe0000004L); + r <<= 8; + r |= csr_readl(0xe0000008L); + r <<= 8; + r |= csr_readl(0xe000000cL); + r <<= 8; + r |= csr_readl(0xe0000010L); + return r; +} +static inline void ctrl_scratch_write(unsigned int value) { + csr_writel(value >> 24, 0xe0000004L); + csr_writel(value >> 16, 0xe0000008L); + csr_writel(value >> 8, 0xe000000cL); + csr_writel(value, 0xe0000010L); +} +#define CSR_CTRL_BUS_ERRORS_ADDR 0xe0000014L +#define CSR_CTRL_BUS_ERRORS_SIZE 4 +static inline unsigned int ctrl_bus_errors_read(void) { + unsigned int r = csr_readl(0xe0000014L); + r <<= 8; + r |= csr_readl(0xe0000018L); + r <<= 8; + r |= csr_readl(0xe000001cL); + r <<= 8; + r |= csr_readl(0xe0000020L); + return r; +} + +/* lxspi */ +#define CSR_LXSPI_BASE 0xe0007800L +#define CSR_LXSPI_BITBANG_ADDR 0xe0007800L +#define CSR_LXSPI_BITBANG_SIZE 1 +static inline unsigned char lxspi_bitbang_read(void) { + unsigned char r = csr_readl(0xe0007800L); + return r; +} +static inline void lxspi_bitbang_write(unsigned char value) { + csr_writel(value, 0xe0007800L); +} +#define CSR_LXSPI_BITBANG_MOSI_OFFSET 0 +#define CSR_LXSPI_BITBANG_MOSI_SIZE 1 +#define CSR_LXSPI_BITBANG_CLK_OFFSET 1 +#define CSR_LXSPI_BITBANG_CLK_SIZE 1 +#define CSR_LXSPI_BITBANG_CS_N_OFFSET 2 +#define CSR_LXSPI_BITBANG_CS_N_SIZE 1 +#define CSR_LXSPI_BITBANG_DIR_OFFSET 3 +#define CSR_LXSPI_BITBANG_DIR_SIZE 1 +#define CSR_LXSPI_MISO_ADDR 0xe0007804L +#define CSR_LXSPI_MISO_SIZE 1 +static inline unsigned char lxspi_miso_read(void) { + unsigned char r = csr_readl(0xe0007804L); + return r; +} +#define CSR_LXSPI_BITBANG_EN_ADDR 0xe0007808L +#define CSR_LXSPI_BITBANG_EN_SIZE 1 +static inline unsigned char lxspi_bitbang_en_read(void) { + unsigned char r = csr_readl(0xe0007808L); + return r; +} +static inline void lxspi_bitbang_en_write(unsigned char value) { + csr_writel(value, 0xe0007808L); +} + +/* messible */ +#define CSR_MESSIBLE_BASE 0xe0008000L +#define CSR_MESSIBLE_IN_ADDR 0xe0008000L +#define CSR_MESSIBLE_IN_SIZE 1 +static inline unsigned char messible_in_read(void) { + unsigned char r = csr_readl(0xe0008000L); + return r; +} +static inline void messible_in_write(unsigned char value) { + csr_writel(value, 0xe0008000L); +} +#define CSR_MESSIBLE_OUT_ADDR 0xe0008004L +#define CSR_MESSIBLE_OUT_SIZE 1 +static inline unsigned char messible_out_read(void) { + unsigned char r = csr_readl(0xe0008004L); + return r; +} +#define CSR_MESSIBLE_STATUS_ADDR 0xe0008008L +#define CSR_MESSIBLE_STATUS_SIZE 1 +static inline unsigned char messible_status_read(void) { + unsigned char r = csr_readl(0xe0008008L); + return r; +} +#define CSR_MESSIBLE_STATUS_FULL_OFFSET 0 +#define CSR_MESSIBLE_STATUS_FULL_SIZE 1 +#define CSR_MESSIBLE_STATUS_HAVE_OFFSET 1 +#define CSR_MESSIBLE_STATUS_HAVE_SIZE 1 + +/* reboot */ +#define CSR_REBOOT_BASE 0xe0006000L +#define CSR_REBOOT_CTRL_ADDR 0xe0006000L +#define CSR_REBOOT_CTRL_SIZE 1 +static inline unsigned char reboot_ctrl_read(void) { + unsigned char r = csr_readl(0xe0006000L); + return r; +} +static inline void reboot_ctrl_write(unsigned char value) { + csr_writel(value, 0xe0006000L); +} +#define CSR_REBOOT_CTRL_IMAGE_OFFSET 0 +#define CSR_REBOOT_CTRL_IMAGE_SIZE 2 +#define CSR_REBOOT_CTRL_KEY_OFFSET 2 +#define CSR_REBOOT_CTRL_KEY_SIZE 6 +#define CSR_REBOOT_ADDR_ADDR 0xe0006004L +#define CSR_REBOOT_ADDR_SIZE 4 +static inline unsigned int reboot_addr_read(void) { + unsigned int r = csr_readl(0xe0006004L); + r <<= 8; + r |= csr_readl(0xe0006008L); + r <<= 8; + r |= csr_readl(0xe000600cL); + r <<= 8; + r |= csr_readl(0xe0006010L); + return r; +} +static inline void reboot_addr_write(unsigned int value) { + csr_writel(value >> 24, 0xe0006004L); + csr_writel(value >> 16, 0xe0006008L); + csr_writel(value >> 8, 0xe000600cL); + csr_writel(value, 0xe0006010L); +} + +/* rgb */ +#define CSR_RGB_BASE 0xe0006800L +#define CSR_RGB_DAT_ADDR 0xe0006800L +#define CSR_RGB_DAT_SIZE 1 +static inline unsigned char rgb_dat_read(void) { + unsigned char r = csr_readl(0xe0006800L); + return r; +} +static inline void rgb_dat_write(unsigned char value) { + csr_writel(value, 0xe0006800L); +} +#define CSR_RGB_ADDR_ADDR 0xe0006804L +#define CSR_RGB_ADDR_SIZE 1 +static inline unsigned char rgb_addr_read(void) { + unsigned char r = csr_readl(0xe0006804L); + return r; +} +static inline void rgb_addr_write(unsigned char value) { + csr_writel(value, 0xe0006804L); +} +#define CSR_RGB_CTRL_ADDR 0xe0006808L +#define CSR_RGB_CTRL_SIZE 1 +static inline unsigned char rgb_ctrl_read(void) { + unsigned char r = csr_readl(0xe0006808L); + return r; +} +static inline void rgb_ctrl_write(unsigned char value) { + csr_writel(value, 0xe0006808L); +} +#define CSR_RGB_CTRL_EXE_OFFSET 0 +#define CSR_RGB_CTRL_EXE_SIZE 1 +#define CSR_RGB_CTRL_CURREN_OFFSET 1 +#define CSR_RGB_CTRL_CURREN_SIZE 1 +#define CSR_RGB_CTRL_RGBLEDEN_OFFSET 2 +#define CSR_RGB_CTRL_RGBLEDEN_SIZE 1 +#define CSR_RGB_CTRL_RRAW_OFFSET 3 +#define CSR_RGB_CTRL_RRAW_SIZE 1 +#define CSR_RGB_CTRL_GRAW_OFFSET 4 +#define CSR_RGB_CTRL_GRAW_SIZE 1 +#define CSR_RGB_CTRL_BRAW_OFFSET 5 +#define CSR_RGB_CTRL_BRAW_SIZE 1 +#define CSR_RGB_RAW_ADDR 0xe000680cL +#define CSR_RGB_RAW_SIZE 1 +static inline unsigned char rgb_raw_read(void) { + unsigned char r = csr_readl(0xe000680cL); + return r; +} +static inline void rgb_raw_write(unsigned char value) { + csr_writel(value, 0xe000680cL); +} +#define CSR_RGB_RAW_R_OFFSET 0 +#define CSR_RGB_RAW_R_SIZE 1 +#define CSR_RGB_RAW_G_OFFSET 1 +#define CSR_RGB_RAW_G_SIZE 1 +#define CSR_RGB_RAW_B_OFFSET 2 +#define CSR_RGB_RAW_B_SIZE 1 + +/* timer0 */ +#define CSR_TIMER0_BASE 0xe0002800L +#define CSR_TIMER0_LOAD_ADDR 0xe0002800L +#define CSR_TIMER0_LOAD_SIZE 4 +static inline unsigned int timer0_load_read(void) { + unsigned int r = csr_readl(0xe0002800L); + r <<= 8; + r |= csr_readl(0xe0002804L); + r <<= 8; + r |= csr_readl(0xe0002808L); + r <<= 8; + r |= csr_readl(0xe000280cL); + return r; +} +static inline void timer0_load_write(unsigned int value) { + csr_writel(value >> 24, 0xe0002800L); + csr_writel(value >> 16, 0xe0002804L); + csr_writel(value >> 8, 0xe0002808L); + csr_writel(value, 0xe000280cL); +} +#define CSR_TIMER0_RELOAD_ADDR 0xe0002810L +#define CSR_TIMER0_RELOAD_SIZE 4 +static inline unsigned int timer0_reload_read(void) { + unsigned int r = csr_readl(0xe0002810L); + r <<= 8; + r |= csr_readl(0xe0002814L); + r <<= 8; + r |= csr_readl(0xe0002818L); + r <<= 8; + r |= csr_readl(0xe000281cL); + return r; +} +static inline void timer0_reload_write(unsigned int value) { + csr_writel(value >> 24, 0xe0002810L); + csr_writel(value >> 16, 0xe0002814L); + csr_writel(value >> 8, 0xe0002818L); + csr_writel(value, 0xe000281cL); +} +#define CSR_TIMER0_EN_ADDR 0xe0002820L +#define CSR_TIMER0_EN_SIZE 1 +static inline unsigned char timer0_en_read(void) { + unsigned char r = csr_readl(0xe0002820L); + return r; +} +static inline void timer0_en_write(unsigned char value) { + csr_writel(value, 0xe0002820L); +} +#define CSR_TIMER0_UPDATE_VALUE_ADDR 0xe0002824L +#define CSR_TIMER0_UPDATE_VALUE_SIZE 1 +static inline unsigned char timer0_update_value_read(void) { + unsigned char r = csr_readl(0xe0002824L); + return r; +} +static inline void timer0_update_value_write(unsigned char value) { + csr_writel(value, 0xe0002824L); +} +#define CSR_TIMER0_VALUE_ADDR 0xe0002828L +#define CSR_TIMER0_VALUE_SIZE 4 +static inline unsigned int timer0_value_read(void) { + unsigned int r = csr_readl(0xe0002828L); + r <<= 8; + r |= csr_readl(0xe000282cL); + r <<= 8; + r |= csr_readl(0xe0002830L); + r <<= 8; + r |= csr_readl(0xe0002834L); + return r; +} +#define CSR_TIMER0_EV_STATUS_ADDR 0xe0002838L +#define CSR_TIMER0_EV_STATUS_SIZE 1 +static inline unsigned char timer0_ev_status_read(void) { + unsigned char r = csr_readl(0xe0002838L); + return r; +} +static inline void timer0_ev_status_write(unsigned char value) { + csr_writel(value, 0xe0002838L); +} +#define CSR_TIMER0_EV_PENDING_ADDR 0xe000283cL +#define CSR_TIMER0_EV_PENDING_SIZE 1 +static inline unsigned char timer0_ev_pending_read(void) { + unsigned char r = csr_readl(0xe000283cL); + return r; +} +static inline void timer0_ev_pending_write(unsigned char value) { + csr_writel(value, 0xe000283cL); +} +#define CSR_TIMER0_EV_ENABLE_ADDR 0xe0002840L +#define CSR_TIMER0_EV_ENABLE_SIZE 1 +static inline unsigned char timer0_ev_enable_read(void) { + unsigned char r = csr_readl(0xe0002840L); + return r; +} +static inline void timer0_ev_enable_write(unsigned char value) { + csr_writel(value, 0xe0002840L); +} + +/* touch */ +#define CSR_TOUCH_BASE 0xe0005800L +#define CSR_TOUCH_O_ADDR 0xe0005800L +#define CSR_TOUCH_O_SIZE 1 +static inline unsigned char touch_o_read(void) { + unsigned char r = csr_readl(0xe0005800L); + return r; +} +static inline void touch_o_write(unsigned char value) { + csr_writel(value, 0xe0005800L); +} +#define CSR_TOUCH_OE_ADDR 0xe0005804L +#define CSR_TOUCH_OE_SIZE 1 +static inline unsigned char touch_oe_read(void) { + unsigned char r = csr_readl(0xe0005804L); + return r; +} +static inline void touch_oe_write(unsigned char value) { + csr_writel(value, 0xe0005804L); +} +#define CSR_TOUCH_I_ADDR 0xe0005808L +#define CSR_TOUCH_I_SIZE 1 +static inline unsigned char touch_i_read(void) { + unsigned char r = csr_readl(0xe0005808L); + return r; +} + +/* usb */ +#define CSR_USB_BASE 0xe0004800L +#define CSR_USB_PULLUP_OUT_ADDR 0xe0004800L +#define CSR_USB_PULLUP_OUT_SIZE 1 +static inline unsigned char usb_pullup_out_read(void) { + unsigned char r = csr_readl(0xe0004800L); + return r; +} +static inline void usb_pullup_out_write(unsigned char value) { + csr_writel(value, 0xe0004800L); +} +#define CSR_USB_ADDRESS_ADDR 0xe0004804L +#define CSR_USB_ADDRESS_SIZE 1 +static inline unsigned char usb_address_read(void) { + unsigned char r = csr_readl(0xe0004804L); + return r; +} +static inline void usb_address_write(unsigned char value) { + csr_writel(value, 0xe0004804L); +} +#define CSR_USB_ADDRESS_ADDR_OFFSET 0 +#define CSR_USB_ADDRESS_ADDR_SIZE 7 +#define CSR_USB_NEXT_EV_ADDR 0xe0004808L +#define CSR_USB_NEXT_EV_SIZE 1 +static inline unsigned char usb_next_ev_read(void) { + unsigned char r = csr_readl(0xe0004808L); + return r; +} +#define CSR_USB_NEXT_EV_IN_OFFSET 0 +#define CSR_USB_NEXT_EV_IN_SIZE 1 +#define CSR_USB_NEXT_EV_OUT_OFFSET 1 +#define CSR_USB_NEXT_EV_OUT_SIZE 1 +#define CSR_USB_NEXT_EV_SETUP_OFFSET 2 +#define CSR_USB_NEXT_EV_SETUP_SIZE 1 +#define CSR_USB_NEXT_EV_RESET_OFFSET 3 +#define CSR_USB_NEXT_EV_RESET_SIZE 1 +#define CSR_USB_SETUP_DATA_ADDR 0xe000480cL +#define CSR_USB_SETUP_DATA_SIZE 1 +static inline unsigned char usb_setup_data_read(void) { + unsigned char r = csr_readl(0xe000480cL); + return r; +} +#define CSR_USB_SETUP_DATA_DATA_OFFSET 0 +#define CSR_USB_SETUP_DATA_DATA_SIZE 8 +#define CSR_USB_SETUP_CTRL_ADDR 0xe0004810L +#define CSR_USB_SETUP_CTRL_SIZE 1 +static inline unsigned char usb_setup_ctrl_read(void) { + unsigned char r = csr_readl(0xe0004810L); + return r; +} +static inline void usb_setup_ctrl_write(unsigned char value) { + csr_writel(value, 0xe0004810L); +} +#define CSR_USB_SETUP_CTRL_RESET_OFFSET 5 +#define CSR_USB_SETUP_CTRL_RESET_SIZE 1 +#define CSR_USB_SETUP_STATUS_ADDR 0xe0004814L +#define CSR_USB_SETUP_STATUS_SIZE 1 +static inline unsigned char usb_setup_status_read(void) { + unsigned char r = csr_readl(0xe0004814L); + return r; +} +#define CSR_USB_SETUP_STATUS_EPNO_OFFSET 0 +#define CSR_USB_SETUP_STATUS_EPNO_SIZE 4 +#define CSR_USB_SETUP_STATUS_HAVE_OFFSET 4 +#define CSR_USB_SETUP_STATUS_HAVE_SIZE 1 +#define CSR_USB_SETUP_STATUS_PEND_OFFSET 5 +#define CSR_USB_SETUP_STATUS_PEND_SIZE 1 +#define CSR_USB_SETUP_STATUS_IS_IN_OFFSET 6 +#define CSR_USB_SETUP_STATUS_IS_IN_SIZE 1 +#define CSR_USB_SETUP_STATUS_DATA_OFFSET 7 +#define CSR_USB_SETUP_STATUS_DATA_SIZE 1 +#define CSR_USB_SETUP_EV_STATUS_ADDR 0xe0004818L +#define CSR_USB_SETUP_EV_STATUS_SIZE 1 +static inline unsigned char usb_setup_ev_status_read(void) { + unsigned char r = csr_readl(0xe0004818L); + return r; +} +static inline void usb_setup_ev_status_write(unsigned char value) { + csr_writel(value, 0xe0004818L); +} +#define CSR_USB_SETUP_EV_PENDING_ADDR 0xe000481cL +#define CSR_USB_SETUP_EV_PENDING_SIZE 1 +static inline unsigned char usb_setup_ev_pending_read(void) { + unsigned char r = csr_readl(0xe000481cL); + return r; +} +static inline void usb_setup_ev_pending_write(unsigned char value) { + csr_writel(value, 0xe000481cL); +} +#define CSR_USB_SETUP_EV_ENABLE_ADDR 0xe0004820L +#define CSR_USB_SETUP_EV_ENABLE_SIZE 1 +static inline unsigned char usb_setup_ev_enable_read(void) { + unsigned char r = csr_readl(0xe0004820L); + return r; +} +static inline void usb_setup_ev_enable_write(unsigned char value) { + csr_writel(value, 0xe0004820L); +} +#define CSR_USB_IN_DATA_ADDR 0xe0004824L +#define CSR_USB_IN_DATA_SIZE 1 +static inline unsigned char usb_in_data_read(void) { + unsigned char r = csr_readl(0xe0004824L); + return r; +} +static inline void usb_in_data_write(unsigned char value) { + csr_writel(value, 0xe0004824L); +} +#define CSR_USB_IN_DATA_DATA_OFFSET 0 +#define CSR_USB_IN_DATA_DATA_SIZE 8 +#define CSR_USB_IN_CTRL_ADDR 0xe0004828L +#define CSR_USB_IN_CTRL_SIZE 1 +static inline unsigned char usb_in_ctrl_read(void) { + unsigned char r = csr_readl(0xe0004828L); + return r; +} +static inline void usb_in_ctrl_write(unsigned char value) { + csr_writel(value, 0xe0004828L); +} +#define CSR_USB_IN_CTRL_EPNO_OFFSET 0 +#define CSR_USB_IN_CTRL_EPNO_SIZE 4 +#define CSR_USB_IN_CTRL_RESET_OFFSET 5 +#define CSR_USB_IN_CTRL_RESET_SIZE 1 +#define CSR_USB_IN_CTRL_STALL_OFFSET 6 +#define CSR_USB_IN_CTRL_STALL_SIZE 1 +#define CSR_USB_IN_STATUS_ADDR 0xe000482cL +#define CSR_USB_IN_STATUS_SIZE 1 +static inline unsigned char usb_in_status_read(void) { + unsigned char r = csr_readl(0xe000482cL); + return r; +} +#define CSR_USB_IN_STATUS_IDLE_OFFSET 0 +#define CSR_USB_IN_STATUS_IDLE_SIZE 1 +#define CSR_USB_IN_STATUS_HAVE_OFFSET 4 +#define CSR_USB_IN_STATUS_HAVE_SIZE 1 +#define CSR_USB_IN_STATUS_PEND_OFFSET 5 +#define CSR_USB_IN_STATUS_PEND_SIZE 1 +#define CSR_USB_IN_EV_STATUS_ADDR 0xe0004830L +#define CSR_USB_IN_EV_STATUS_SIZE 1 +static inline unsigned char usb_in_ev_status_read(void) { + unsigned char r = csr_readl(0xe0004830L); + return r; +} +static inline void usb_in_ev_status_write(unsigned char value) { + csr_writel(value, 0xe0004830L); +} +#define CSR_USB_IN_EV_PENDING_ADDR 0xe0004834L +#define CSR_USB_IN_EV_PENDING_SIZE 1 +static inline unsigned char usb_in_ev_pending_read(void) { + unsigned char r = csr_readl(0xe0004834L); + return r; +} +static inline void usb_in_ev_pending_write(unsigned char value) { + csr_writel(value, 0xe0004834L); +} +#define CSR_USB_IN_EV_ENABLE_ADDR 0xe0004838L +#define CSR_USB_IN_EV_ENABLE_SIZE 1 +static inline unsigned char usb_in_ev_enable_read(void) { + unsigned char r = csr_readl(0xe0004838L); + return r; +} +static inline void usb_in_ev_enable_write(unsigned char value) { + csr_writel(value, 0xe0004838L); +} +#define CSR_USB_OUT_DATA_ADDR 0xe000483cL +#define CSR_USB_OUT_DATA_SIZE 1 +static inline unsigned char usb_out_data_read(void) { + unsigned char r = csr_readl(0xe000483cL); + return r; +} +#define CSR_USB_OUT_DATA_DATA_OFFSET 0 +#define CSR_USB_OUT_DATA_DATA_SIZE 8 +#define CSR_USB_OUT_CTRL_ADDR 0xe0004840L +#define CSR_USB_OUT_CTRL_SIZE 1 +static inline unsigned char usb_out_ctrl_read(void) { + unsigned char r = csr_readl(0xe0004840L); + return r; +} +static inline void usb_out_ctrl_write(unsigned char value) { + csr_writel(value, 0xe0004840L); +} +#define CSR_USB_OUT_CTRL_EPNO_OFFSET 0 +#define CSR_USB_OUT_CTRL_EPNO_SIZE 4 +#define CSR_USB_OUT_CTRL_ENABLE_OFFSET 4 +#define CSR_USB_OUT_CTRL_ENABLE_SIZE 1 +#define CSR_USB_OUT_CTRL_RESET_OFFSET 5 +#define CSR_USB_OUT_CTRL_RESET_SIZE 1 +#define CSR_USB_OUT_CTRL_STALL_OFFSET 6 +#define CSR_USB_OUT_CTRL_STALL_SIZE 1 +#define CSR_USB_OUT_STATUS_ADDR 0xe0004844L +#define CSR_USB_OUT_STATUS_SIZE 1 +static inline unsigned char usb_out_status_read(void) { + unsigned char r = csr_readl(0xe0004844L); + return r; +} +#define CSR_USB_OUT_STATUS_EPNO_OFFSET 0 +#define CSR_USB_OUT_STATUS_EPNO_SIZE 4 +#define CSR_USB_OUT_STATUS_HAVE_OFFSET 4 +#define CSR_USB_OUT_STATUS_HAVE_SIZE 1 +#define CSR_USB_OUT_STATUS_PEND_OFFSET 5 +#define CSR_USB_OUT_STATUS_PEND_SIZE 1 +#define CSR_USB_OUT_EV_STATUS_ADDR 0xe0004848L +#define CSR_USB_OUT_EV_STATUS_SIZE 1 +static inline unsigned char usb_out_ev_status_read(void) { + unsigned char r = csr_readl(0xe0004848L); + return r; +} +static inline void usb_out_ev_status_write(unsigned char value) { + csr_writel(value, 0xe0004848L); +} +#define CSR_USB_OUT_EV_PENDING_ADDR 0xe000484cL +#define CSR_USB_OUT_EV_PENDING_SIZE 1 +static inline unsigned char usb_out_ev_pending_read(void) { + unsigned char r = csr_readl(0xe000484cL); + return r; +} +static inline void usb_out_ev_pending_write(unsigned char value) { + csr_writel(value, 0xe000484cL); +} +#define CSR_USB_OUT_EV_ENABLE_ADDR 0xe0004850L +#define CSR_USB_OUT_EV_ENABLE_SIZE 1 +static inline unsigned char usb_out_ev_enable_read(void) { + unsigned char r = csr_readl(0xe0004850L); + return r; +} +static inline void usb_out_ev_enable_write(unsigned char value) { + csr_writel(value, 0xe0004850L); +} +#define CSR_USB_OUT_ENABLE_STATUS_ADDR 0xe0004854L +#define CSR_USB_OUT_ENABLE_STATUS_SIZE 1 +static inline unsigned char usb_out_enable_status_read(void) { + unsigned char r = csr_readl(0xe0004854L); + return r; +} +#define CSR_USB_OUT_STALL_STATUS_ADDR 0xe0004858L +#define CSR_USB_OUT_STALL_STATUS_SIZE 1 +static inline unsigned char usb_out_stall_status_read(void) { + unsigned char r = csr_readl(0xe0004858L); + return r; +} + +/* version */ +#define CSR_VERSION_BASE 0xe0007000L +#define CSR_VERSION_MAJOR_ADDR 0xe0007000L +#define CSR_VERSION_MAJOR_SIZE 1 +static inline unsigned char version_major_read(void) { + unsigned char r = csr_readl(0xe0007000L); + return r; +} +#define CSR_VERSION_MINOR_ADDR 0xe0007004L +#define CSR_VERSION_MINOR_SIZE 1 +static inline unsigned char version_minor_read(void) { + unsigned char r = csr_readl(0xe0007004L); + return r; +} +#define CSR_VERSION_REVISION_ADDR 0xe0007008L +#define CSR_VERSION_REVISION_SIZE 1 +static inline unsigned char version_revision_read(void) { + unsigned char r = csr_readl(0xe0007008L); + return r; +} +#define CSR_VERSION_GITREV_ADDR 0xe000700cL +#define CSR_VERSION_GITREV_SIZE 4 +static inline unsigned int version_gitrev_read(void) { + unsigned int r = csr_readl(0xe000700cL); + r <<= 8; + r |= csr_readl(0xe0007010L); + r <<= 8; + r |= csr_readl(0xe0007014L); + r <<= 8; + r |= csr_readl(0xe0007018L); + return r; +} +#define CSR_VERSION_GITEXTRA_ADDR 0xe000701cL +#define CSR_VERSION_GITEXTRA_SIZE 2 +static inline unsigned short int version_gitextra_read(void) { + unsigned short int r = csr_readl(0xe000701cL); + r <<= 8; + r |= csr_readl(0xe0007020L); + return r; +} +#define CSR_VERSION_DIRTY_ADDR 0xe0007024L +#define CSR_VERSION_DIRTY_SIZE 1 +static inline unsigned char version_dirty_read(void) { + unsigned char r = csr_readl(0xe0007024L); + return r; +} +#define CSR_VERSION_DIRTY_DIRTY_OFFSET 0 +#define CSR_VERSION_DIRTY_DIRTY_SIZE 1 +#define CSR_VERSION_MODEL_ADDR 0xe0007028L +#define CSR_VERSION_MODEL_SIZE 1 +static inline unsigned char version_model_read(void) { + unsigned char r = csr_readl(0xe0007028L); + return r; +} +#define CSR_VERSION_MODEL_MODEL_OFFSET 0 +#define CSR_VERSION_MODEL_MODEL_SIZE 8 +#define CSR_VERSION_SEED_ADDR 0xe000702cL +#define CSR_VERSION_SEED_SIZE 4 +static inline unsigned int version_seed_read(void) { + unsigned int r = csr_readl(0xe000702cL); + r <<= 8; + r |= csr_readl(0xe0007030L); + r <<= 8; + r |= csr_readl(0xe0007034L); + r <<= 8; + r |= csr_readl(0xe0007038L); + return r; +} + +#endif diff --git a/ports/litex/boards/fomu/fomu-spi.ld b/ports/litex/boards/fomu/fomu-spi.ld new file mode 100644 index 0000000000000..161ba607b14a8 --- /dev/null +++ b/ports/litex/boards/fomu/fomu-spi.ld @@ -0,0 +1,82 @@ +/* + GNU linker script for Fomu +*/ + +ENTRY(_start) + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x20040000, LENGTH = 0x100000 /* entire flash, 1 MiB */ + RAM (xrw) : ORIGIN = 0x10000000, LENGTH = 0x00020000 /* 128 KiB */ +} + +/* top end of the stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); + +/* define output sections */ +SECTIONS +{ + /* This is the initialized data section + The program executes knowing that the data is in the RAM + but the loader puts the initial values in the FLASH (inidata). + It is one task of the startup to copy the initial values from FLASH to RAM. */ + .data : AT ( _sidata ) + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM */ + + *(.itcm.*) /* Instruction Tightly Coupled Memory */ + *(.dtcm_data.*) /* Data Tightly Coupled Memory */ + *(.ramtext) /* .text* sections (code) */ + *(.ramtext*) /* .text* sections (code) */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.sdata) /* .data sections */ + *(.sdata*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */ + } >RAM + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + KEEP(*(.text.start)) /* isr vector table */ + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.srodata) /* .rodata sections (constants, strings, etc.) */ + *(.srodata*) /* .rodata* sections (constants, strings, etc.) */ + + . = ALIGN(4); + _etext = .; /* define a global symbol at end of code */ + _sidata = _etext; /* This is used by the startup in order to initialize the .data secion */ + } >FLASH + + /* Uninitialized data section */ + .bss : + { + . = ALIGN(4); + _sbss = .; /* define a global symbol at bss start; used by startup code */ + *(.bss) + *(.bss*) + *(.dtcm_bss.*) /* Data Tightly Coupled Memory */ + *(.sbss) + *(.sbss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end; used by startup code */ + } >RAM + + + /* this is to define the start of the heap, and make sure we have a minimum size */ + .heap : + { + . = ALIGN(4); + _heap_start = .; /* define a global symbol at heap start */ + } >RAM +} diff --git a/ports/litex/boards/fomu/generated/soc.h b/ports/litex/boards/fomu/generated/soc.h new file mode 100644 index 0000000000000..91b2f1a310a33 --- /dev/null +++ b/ports/litex/boards/fomu/generated/soc.h @@ -0,0 +1,58 @@ +//-------------------------------------------------------------------------------- +// Auto-generated by Migen (f4fcd10) & LiteX (de205d4a) on 2019-11-25 15:17:59 +//-------------------------------------------------------------------------------- +#ifndef __GENERATED_SOC_H +#define __GENERATED_SOC_H +#define CONFIG_BITSTREAM_SYNC_HEADER1 2123999870 +static inline int config_bitstream_sync_header1_read(void) { + return 2123999870; +} +#define CONFIG_BITSTREAM_SYNC_HEADER2 2125109630 +static inline int config_bitstream_sync_header2_read(void) { + return 2125109630; +} +#define CONFIG_CLOCK_FREQUENCY 12000000 +static inline int config_clock_frequency_read(void) { + return 12000000; +} +#define CONFIG_CPU_RESET_ADDR 0 +static inline int config_cpu_reset_addr_read(void) { + return 0; +} +#define CONFIG_CPU_TYPE "VEXRISCV" +static inline const char * config_cpu_type_read(void) { + return "VEXRISCV"; +} +#define CONFIG_CPU_TYPE_VEXRISCV +#define CONFIG_CPU_VARIANT "MIN" +static inline const char * config_cpu_variant_read(void) { + return "MIN"; +} +#define CONFIG_CPU_VARIANT_MIN +#define CONFIG_CSR_ALIGNMENT 32 +static inline int config_csr_alignment_read(void) { + return 32; +} +#define CONFIG_CSR_DATA_WIDTH 8 +static inline int config_csr_data_width_read(void) { + return 8; +} +#define CONFIG_FOMU_REV "HACKER" +static inline const char * config_fomu_rev_read(void) { + return "HACKER"; +} +#define CONFIG_FOMU_REV_HACKER +#define CONFIG_SHADOW_BASE 2147483648 +static inline int config_shadow_base_read(void) { + return 2147483648; +} +#define TIMER0_INTERRUPT 2 +static inline int timer0_interrupt_read(void) { + return 2; +} +#define USB_INTERRUPT 3 +static inline int usb_interrupt_read(void) { + return 3; +} + +#endif diff --git a/ports/litex/boards/fomu/mpconfigboard.h b/ports/litex/boards/fomu/mpconfigboard.h new file mode 100644 index 0000000000000..127301eee2b0c --- /dev/null +++ b/ports/litex/boards/fomu/mpconfigboard.h @@ -0,0 +1,37 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2019 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +//Micropython setup + +#define MICROPY_HW_BOARD_NAME "Fomu" +#define MICROPY_HW_MCU_NAME "VexRiscv" + +#define FLASH_SIZE (0x100000) +#define FLASH_PAGE_SIZE (0x1000) +#define FLASH_PARTITION_OFFSET_BYTES (1024*1024) + +#define AUTORESET_DELAY_MS 500 +#define BOARD_FLASH_SIZE (FLASH_SIZE) diff --git a/ports/litex/boards/fomu/mpconfigboard.mk b/ports/litex/boards/fomu/mpconfigboard.mk new file mode 100644 index 0000000000000..4787803ccdd56 --- /dev/null +++ b/ports/litex/boards/fomu/mpconfigboard.mk @@ -0,0 +1,20 @@ +USB_VID = 0x1209 +USB_PID = 0x5BF0 +USB_PRODUCT = "Fomu" +USB_MANUFACTURER = "Foosn" +USB_DEVICES = "CDC,MSC,AUDIO,HID" + +INTERNAL_FLASH_FILESYSTEM = 1 +LONGINT_IMPL = MPZ + +# The default queue depth of 16 overflows on release builds, +# so increase it to 32. +CFLAGS += -DCFG_TUD_TASK_QUEUE_SZ=32 + +# Fomu only implements rv32i +CFLAGS += -march=rv32i -mabi=ilp32 +LDFLAGS += -march=rv32i -mabi=ilp32 + +CIRCUITPY_NEOPIXEL_WRITE = 1 +CIRCUITPY_DIGITALIO = 1 +CIRCUITPY_MICROCONTROLLER = 1 diff --git a/ports/litex/boards/fomu/pins.c b/ports/litex/boards/fomu/pins.c new file mode 100644 index 0000000000000..6be495c3319ad --- /dev/null +++ b/ports/litex/boards/fomu/pins.c @@ -0,0 +1,9 @@ +#include "shared-bindings/board/__init__.h" + +STATIC const mp_rom_map_elem_t board_global_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR_TOUCH1), MP_ROM_PTR(&pin_TOUCH1) }, + { MP_ROM_QSTR(MP_QSTR_TOUCH2), MP_ROM_PTR(&pin_TOUCH2) }, + { MP_ROM_QSTR(MP_QSTR_TOUCH3), MP_ROM_PTR(&pin_TOUCH3) }, + { MP_ROM_QSTR(MP_QSTR_TOUCH4), MP_ROM_PTR(&pin_TOUCH4) }, +}; +MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table); diff --git a/ports/litex/boards/fomu/profiling.gdb.txt b/ports/litex/boards/fomu/profiling.gdb.txt new file mode 100644 index 0000000000000..28faf45b73d39 --- /dev/null +++ b/ports/litex/boards/fomu/profiling.gdb.txt @@ -0,0 +1,16 @@ +set pagination 0 +set logging file profile.txt +set logging overwrite + +server define poor_profile +set $total = $arg0 +set $i = 0 + set logging on + while($i<$total) + set $i = $i + 1 + cont + p $pc + bt + end + set logging off +end diff --git a/ports/litex/common-hal/digitalio/DigitalInOut.c b/ports/litex/common-hal/digitalio/DigitalInOut.c new file mode 100644 index 0000000000000..574d0de567431 --- /dev/null +++ b/ports/litex/common-hal/digitalio/DigitalInOut.c @@ -0,0 +1,119 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries + * Copyright (c) 2019 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "shared-bindings/digitalio/DigitalInOut.h" +#include "py/runtime.h" +#include "supervisor/shared/translate.h" + +#include "csr.h" + +void common_hal_digitalio_digitalinout_never_reset( + digitalio_digitalinout_obj_t *self) { + (void)self; +} + +digitalinout_result_t common_hal_digitalio_digitalinout_construct( + digitalio_digitalinout_obj_t *self, const mcu_pin_obj_t *pin) { + + // claim_pin(pin); + self->pin = pin; + + return DIGITALINOUT_OK; +} + +bool common_hal_digitalio_digitalinout_deinited(digitalio_digitalinout_obj_t *self) { + return self->pin == mp_const_none; +} + +void common_hal_digitalio_digitalinout_deinit(digitalio_digitalinout_obj_t *self) { + if (common_hal_digitalio_digitalinout_deinited(self)) { + return; + } + + // reset_pin_number(0, self->pin->number); + self->pin = mp_const_none; +} + +void common_hal_digitalio_digitalinout_switch_to_input( + digitalio_digitalinout_obj_t *self, digitalio_pull_t pull) { + (void)pull; + touch_oe_write(touch_oe_read() & ~(1 << self->pin->number)); +} + +void common_hal_digitalio_digitalinout_switch_to_output( + digitalio_digitalinout_obj_t *self, bool value, + digitalio_drive_mode_t drive_mode) { + (void)drive_mode; + common_hal_digitalio_digitalinout_set_value(self, value); + touch_oe_write(touch_oe_read() | (1 << self->pin->number)); +} + +digitalio_direction_t common_hal_digitalio_digitalinout_get_direction( + digitalio_digitalinout_obj_t *self) { + + return (touch_oe_read() & (1 << self->pin->number)) + ? DIRECTION_OUTPUT : DIRECTION_INPUT; +} + +void common_hal_digitalio_digitalinout_set_value( + digitalio_digitalinout_obj_t *self, bool value) { + if (value) + touch_o_write(touch_o_read() | (1 << self->pin->number)); + else + touch_o_write(touch_o_read() & ~(1 << self->pin->number)); +} + +bool common_hal_digitalio_digitalinout_get_value( + digitalio_digitalinout_obj_t *self) { + return !!(touch_i_read() & (1 << self->pin->number)); +} + +void common_hal_digitalio_digitalinout_set_drive_mode( + digitalio_digitalinout_obj_t *self, + digitalio_drive_mode_t drive_mode) { + (void)self; + (void)drive_mode; +} + +digitalio_drive_mode_t common_hal_digitalio_digitalinout_get_drive_mode( + digitalio_digitalinout_obj_t *self) { + if (common_hal_digitalio_digitalinout_get_direction(self) == DIRECTION_OUTPUT) + return DRIVE_MODE_PUSH_PULL; + else + return DRIVE_MODE_OPEN_DRAIN; +} + +void common_hal_digitalio_digitalinout_set_pull( + digitalio_digitalinout_obj_t *self, digitalio_pull_t pull) { + (void)self; + (void)pull; +} + +digitalio_pull_t common_hal_digitalio_digitalinout_get_pull( + digitalio_digitalinout_obj_t *self) { + return PULL_NONE; +} diff --git a/ports/litex/common-hal/digitalio/DigitalInOut.h b/ports/litex/common-hal/digitalio/DigitalInOut.h new file mode 100644 index 0000000000000..3c5bdafaf2c47 --- /dev/null +++ b/ports/litex/common-hal/digitalio/DigitalInOut.h @@ -0,0 +1,38 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries + * Copyright (c) 2019 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MICROPY_INCLUDED_FOMU_COMMON_HAL_DIGITALIO_DIGITALINOUT_H +#define MICROPY_INCLUDED_FOMU_COMMON_HAL_DIGITALIO_DIGITALINOUT_H + +#include "common-hal/microcontroller/Pin.h" + +typedef struct { + mp_obj_base_t base; + const mcu_pin_obj_t *pin; +} digitalio_digitalinout_obj_t; + +#endif // MICROPY_INCLUDED_FOMU_COMMON_HAL_DIGITALIO_DIGITALINOUT_H diff --git a/ports/litex/common-hal/digitalio/__init__.c b/ports/litex/common-hal/digitalio/__init__.c new file mode 100644 index 0000000000000..20fad459593ac --- /dev/null +++ b/ports/litex/common-hal/digitalio/__init__.c @@ -0,0 +1 @@ +// No digitalio module functions. diff --git a/ports/litex/common-hal/microcontroller/Pin.c b/ports/litex/common-hal/microcontroller/Pin.c new file mode 100644 index 0000000000000..632468f6d062d --- /dev/null +++ b/ports/litex/common-hal/microcontroller/Pin.c @@ -0,0 +1,56 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Scott Shawcroft for Adafruit Industries + * Copyright (c) 2019 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "shared-bindings/microcontroller/Pin.h" + +#include "py/mphal.h" + +STATIC uint8_t claimed_pins[1]; + +// Mark pin as free and return it to a quiescent state. +void reset_pin_number(uint8_t pin_port, uint8_t pin_number) { + if (pin_port == 0x0F) { + return; + } + + // Clear claimed bit. + claimed_pins[pin_port] &= ~(1<number; +} + +bool pin_number_is_free(uint8_t pin_port, uint8_t pin_number) { + return !(claimed_pins[pin_port] & 1<number); +} diff --git a/ports/litex/common-hal/microcontroller/Pin.h b/ports/litex/common-hal/microcontroller/Pin.h new file mode 100644 index 0000000000000..186e120a28aca --- /dev/null +++ b/ports/litex/common-hal/microcontroller/Pin.h @@ -0,0 +1,59 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Scott Shawcroft + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MICROPY_INCLUDED_FOMU_COMMON_HAL_MICROCONTROLLER_PIN_H +#define MICROPY_INCLUDED_FOMU_COMMON_HAL_MICROCONTROLLER_PIN_H + +#include "py/mphal.h" + + +typedef struct { + mp_obj_base_t base; + uint8_t number; +} mcu_pin_obj_t; + +#define PIN(p_number) \ +{ \ + { &mcu_pin_type }, \ + .number = p_number \ +} + +extern const mcu_pin_obj_t pin_TOUCH1; +extern const mcu_pin_obj_t pin_TOUCH2; +extern const mcu_pin_obj_t pin_TOUCH3; +extern const mcu_pin_obj_t pin_TOUCH4; + +void reset_all_pins(void); +// reset_pin_number takes the pin number instead of the pointer so that objects don't +// need to store a full pointer. +void reset_pin_number(uint8_t pin_port, uint8_t pin_number); +void claim_pin(const mcu_pin_obj_t* pin); +bool pin_number_is_free(uint8_t pin_port, uint8_t pin_number); +void never_reset_pin_number(uint8_t pin_port, uint8_t pin_number); +// GPIO_TypeDef * pin_port(uint8_t pin_port); +uint16_t pin_mask(uint8_t pin_number); + +#endif // MICROPY_INCLUDED_FOMU_COMMON_HAL_MICROCONTROLLER_PIN_H diff --git a/ports/litex/common-hal/microcontroller/Processor.c b/ports/litex/common-hal/microcontroller/Processor.c new file mode 100644 index 0000000000000..9d2b05aadeab0 --- /dev/null +++ b/ports/litex/common-hal/microcontroller/Processor.c @@ -0,0 +1,64 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Dan Halbert for Adafruit Industries + * Copyright (c) 2019 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include "common-hal/microcontroller/Processor.h" +#include "py/runtime.h" +#include "supervisor/shared/translate.h" + +#include "csr.h" +#include "generated/soc.h" + +float common_hal_mcu_processor_get_temperature(void) { + return NAN; +} + +float common_hal_mcu_processor_get_voltage(void) { + return NAN; +} + +uint32_t common_hal_mcu_processor_get_frequency(void) { + return CONFIG_CLOCK_FREQUENCY; +} + +void common_hal_mcu_processor_get_uid(uint8_t raw_id[]) { + raw_id[0] = csr_readl(CSR_VERSION_MAJOR_ADDR); + raw_id[1] = csr_readl(CSR_VERSION_MINOR_ADDR); + raw_id[2] = csr_readl(CSR_VERSION_REVISION_ADDR); + raw_id[3] = csr_readl(CSR_VERSION_GITREV_ADDR + 0); + raw_id[4] = csr_readl(CSR_VERSION_GITREV_ADDR + 4); + raw_id[5] = csr_readl(CSR_VERSION_GITREV_ADDR + 8); + raw_id[6] = csr_readl(CSR_VERSION_GITREV_ADDR + 12); + raw_id[7] = csr_readl(CSR_VERSION_GITEXTRA_ADDR + 0); + raw_id[8] = csr_readl(CSR_VERSION_GITEXTRA_ADDR + 4); + raw_id[9] = csr_readl(CSR_VERSION_DIRTY_ADDR); + raw_id[10] = csr_readl(CSR_VERSION_MODEL_ADDR); + raw_id[11] = csr_readl(CSR_VERSION_SEED_ADDR + 0); + raw_id[12] = csr_readl(CSR_VERSION_SEED_ADDR + 4); + raw_id[13] = csr_readl(CSR_VERSION_SEED_ADDR + 8); + raw_id[14] = csr_readl(CSR_VERSION_SEED_ADDR + 12); +} diff --git a/ports/litex/common-hal/microcontroller/Processor.h b/ports/litex/common-hal/microcontroller/Processor.h new file mode 100644 index 0000000000000..a2ea261c8f892 --- /dev/null +++ b/ports/litex/common-hal/microcontroller/Processor.h @@ -0,0 +1,39 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Dan Halbert for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MICROPY_INCLUDED_LITEX_COMMON_HAL_MICROCONTROLLER_PROCESSOR_H +#define MICROPY_INCLUDED_LITEX_COMMON_HAL_MICROCONTROLLER_PROCESSOR_H + +#define COMMON_HAL_MCU_PROCESSOR_UID_LENGTH 15 + +#include "py/obj.h" + +typedef struct { + mp_obj_base_t base; + // Stores no state currently. +} mcu_processor_obj_t; + +#endif // MICROPY_INCLUDED_LITEX_COMMON_HAL_MICROCONTROLLER_PROCESSOR_H diff --git a/ports/litex/common-hal/microcontroller/__init__.c b/ports/litex/common-hal/microcontroller/__init__.c new file mode 100644 index 0000000000000..3c91661144b81 --- /dev/null +++ b/ports/litex/common-hal/microcontroller/__init__.c @@ -0,0 +1,111 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Scott Shawcroft for Adafruit Industries + * Copyright (c) 2019 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/mphal.h" +#include "py/obj.h" +#include "py/runtime.h" + +#include "common-hal/microcontroller/Pin.h" +#include "common-hal/microcontroller/Processor.h" + +#include "shared-bindings/microcontroller/__init__.h" +#include "shared-bindings/microcontroller/Pin.h" +#include "shared-bindings/microcontroller/Processor.h" + +#include "supervisor/filesystem.h" +#include "supervisor/shared/safe_mode.h" + +#include "csr.h" +#include "irq.h" + +void common_hal_mcu_delay_us(uint32_t delay) { + // if (__get_PRIMASK() == 0x00000000) { + // //by default use ticks_ms + // uint32_t start = get_us(); + // while (get_us()-start < delay) { + // __asm__ __volatile__("nop"); + // } + // } else { + // //when SysTick is disabled, approximate with busy loop + // const uint32_t ucount = HAL_RCC_GetSysClockFreq() / 1000000 * delay / LOOP_TICKS; + // for (uint32_t count = 0; ++count <= ucount;) { + // } + // } +} + +volatile uint32_t nesting_count = 0; + +void common_hal_mcu_disable_interrupts(void) { + irq_setie(0); + // __DMB(); + nesting_count++; +} + +void common_hal_mcu_enable_interrupts(void) { + if (nesting_count == 0) { + // This is very very bad because it means there was mismatched disable/enables so we + // "HardFault". + asm("ebreak"); + } + nesting_count--; + if (nesting_count > 0) { + return; + } + irq_setie(1); +} + +void common_hal_mcu_on_next_reset(mcu_runmode_t runmode) { + if(runmode == RUNMODE_SAFE_MODE) + safe_mode_on_next_reset(PROGRAMMATIC_SAFE_MODE); +} + +void common_hal_mcu_reset(void) { + filesystem_flush(); //TODO: implement as part of flash improvements + // NVIC_SystemReset(); + while(1); +} + +// The singleton microcontroller.Processor object, bound to microcontroller.cpu +// It currently only has properties, and no state. +const mcu_processor_obj_t common_hal_mcu_processor_obj = { + .base = { + .type = &mcu_processor_type, + }, +}; + +const mcu_pin_obj_t pin_TOUCH1 = PIN(0); +const mcu_pin_obj_t pin_TOUCH2 = PIN(1); +const mcu_pin_obj_t pin_TOUCH3 = PIN(2); +const mcu_pin_obj_t pin_TOUCH4 = PIN(3); + +STATIC const mp_rom_map_elem_t mcu_pin_globals_table[] = { + { MP_ROM_QSTR(MP_QSTR_TOUCH1), MP_ROM_PTR(&pin_TOUCH1) }, + { MP_ROM_QSTR(MP_QSTR_TOUCH2), MP_ROM_PTR(&pin_TOUCH2) }, + { MP_ROM_QSTR(MP_QSTR_TOUCH3), MP_ROM_PTR(&pin_TOUCH3) }, + { MP_ROM_QSTR(MP_QSTR_TOUCH4), MP_ROM_PTR(&pin_TOUCH4) }, +}; +MP_DEFINE_CONST_DICT(mcu_pin_globals, mcu_pin_globals_table); diff --git a/ports/litex/common-hal/neopixel_write/__init__.c b/ports/litex/common-hal/neopixel_write/__init__.c new file mode 100644 index 0000000000000..29fd318d401e7 --- /dev/null +++ b/ports/litex/common-hal/neopixel_write/__init__.c @@ -0,0 +1,93 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2018 hathach for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/mphal.h" +#include "shared-bindings/neopixel_write/__init__.h" +#include "csr.h" + +// ICE40 LED Driver hard macro. +// See http://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/IK/ICE40LEDDriverUsageGuide.ashx?document_id=50668 +enum led_registers { + LEDDCR0 = 8, + LEDDBR = 9, + LEDDONR = 10, + LEDDOFR = 11, + LEDDBCRR = 5, + LEDDBCFR = 6, + LEDDPWRR = 1, + LEDDPWRG = 2, + LEDDPWRB = 3, +}; + +// Control register definitions +#define LEDDCR0_LEDDEN (1 << 7) +#define LEDDCR0_FR250 (1 << 6) +#define LEDDCR0_OUTPOL (1 << 5) +#define LEDDCR0_OUTSKEW (1 << 4) +#define LEDDCR0_QUICKSTOP (1 << 3) +#define LEDDCR0_PWM_MODE (1 << 2) +#define LEDDCR0_BRMSBEXT (1 << 0) + +// Write a value into the LEDDA_IP register. +static void ledda_write(uint8_t value, uint8_t addr) { + rgb_addr_write(addr); + rgb_dat_write(value); +} + +static int ledda_init_done; + +static void ledda_init(void) { + if (ledda_init_done) + return; + + // Enable the driver + rgb_ctrl_write((1 << CSR_RGB_CTRL_EXE_OFFSET) | (1 << CSR_RGB_CTRL_CURREN_OFFSET) | (1 << CSR_RGB_CTRL_RGBLEDEN_OFFSET)); + + ledda_write(LEDDCR0_LEDDEN | LEDDCR0_FR250 | LEDDCR0_QUICKSTOP, LEDDCR0); + + // Set clock register to 12 MHz / 64 kHz - 1 + ledda_write((12000000/64000)-1, LEDDBR); + + // Ensure LED "breathe" effect is diabled + ledda_write(0, LEDDBCRR); + ledda_write(0, LEDDBCFR); + + // Also disable the LED blink time + ledda_write(0, LEDDONR); + ledda_write(0, LEDDOFR); + + ledda_init_done = 1; +} + +void common_hal_neopixel_write (const digitalio_digitalinout_obj_t* digitalinout, uint8_t *pixels, uint32_t numBytes) { + (void)digitalinout; + (void)numBytes; + ledda_init(); + + ledda_write(pixels[0], LEDDPWRR); // Red + ledda_write(pixels[1], LEDDPWRG); // Green + ledda_write(pixels[2], LEDDPWRB); // Blue +} diff --git a/ports/litex/common-hal/supervisor/Runtime.c b/ports/litex/common-hal/supervisor/Runtime.c new file mode 100644 index 0000000000000..feab6987d8b8c --- /dev/null +++ b/ports/litex/common-hal/supervisor/Runtime.c @@ -0,0 +1,38 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2018 Michael Schroeder + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include "shared-bindings/supervisor/Runtime.h" +#include "supervisor/serial.h" + +bool common_hal_get_serial_connected(void) { + return (bool) serial_connected(); +} + +bool common_hal_get_serial_bytes_available(void) { + return (bool) serial_bytes_available(); +} + diff --git a/ports/litex/common-hal/supervisor/Runtime.h b/ports/litex/common-hal/supervisor/Runtime.h new file mode 100644 index 0000000000000..d1fe246211bd5 --- /dev/null +++ b/ports/litex/common-hal/supervisor/Runtime.h @@ -0,0 +1,37 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2018 Michael Schroeder + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MICROPY_INCLUDED_LITEX_COMMON_HAL_SUPERVISOR_RUNTIME_H +#define MICROPY_INCLUDED_LITEX_COMMON_HAL_SUPERVISOR_RUNTIME_H + +#include "py/obj.h" + +typedef struct { + mp_obj_base_t base; + // Stores no state currently. +} super_runtime_obj_t; + +#endif // MICROPY_INCLUDED_LITEX_COMMON_HAL_SUPERVISOR_RUNTIME_H diff --git a/ports/litex/common-hal/supervisor/__init__.c b/ports/litex/common-hal/supervisor/__init__.c new file mode 100644 index 0000000000000..ac88556b45da4 --- /dev/null +++ b/ports/litex/common-hal/supervisor/__init__.c @@ -0,0 +1,40 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2018 Michael Schroeder + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + + +#include "py/obj.h" + +#include "shared-bindings/supervisor/__init__.h" +#include "shared-bindings/supervisor/Runtime.h" + + +// The singleton supervisor.Runtime object, bound to supervisor.runtime +// It currently only has properties, and no state. +const super_runtime_obj_t common_hal_supervisor_runtime_obj = { + .base = { + .type = &supervisor_runtime_type, + }, +}; \ No newline at end of file diff --git a/ports/litex/common-hal/time/__init__.c b/ports/litex/common-hal/time/__init__.c new file mode 100644 index 0000000000000..c85077868aa30 --- /dev/null +++ b/ports/litex/common-hal/time/__init__.c @@ -0,0 +1,45 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/mphal.h" + +#include "tick.h" + +uint64_t common_hal_time_monotonic(void) { + return supervisor_ticks_ms64(); +} + +uint64_t common_hal_time_monotonic_ns(void) { + uint64_t ms; + uint32_t us_until_ms; + current_tick(&ms, &us_until_ms); + // us counts down. + return 1000 * (ms * 1000 + (1000 - us_until_ms)); +} + +void common_hal_time_delay_ms(uint32_t delay) { + mp_hal_delay_ms(delay); +} diff --git a/ports/litex/crt0-vexriscv.S b/ports/litex/crt0-vexriscv.S new file mode 100644 index 0000000000000..0419acf8511d9 --- /dev/null +++ b/ports/litex/crt0-vexriscv.S @@ -0,0 +1,94 @@ +.global main +.global isr + +.section .text.start +.global _start + +_start: + j crt_init + # This sentinal ensures that this program is loaded + # to RAM when loaded using dfu-util. + #.word 0x17ab0f23 + #.word 0x10001000 + +.section .ramtext +.global trap_entry +.align 4 +trap_entry: + sw x1, - 1*4(sp) + sw x5, - 2*4(sp) + sw x6, - 3*4(sp) + sw x7, - 4*4(sp) + sw x10, - 5*4(sp) + sw x11, - 6*4(sp) + sw x12, - 7*4(sp) + sw x13, - 8*4(sp) + sw x14, - 9*4(sp) + sw x15, -10*4(sp) + sw x16, -11*4(sp) + sw x17, -12*4(sp) + sw x28, -13*4(sp) + sw x29, -14*4(sp) + sw x30, -15*4(sp) + sw x31, -16*4(sp) + addi sp,sp,-16*4 + call isr + lw x1 , 15*4(sp) + lw x5, 14*4(sp) + lw x6, 13*4(sp) + lw x7, 12*4(sp) + lw x10, 11*4(sp) + lw x11, 10*4(sp) + lw x12, 9*4(sp) + lw x13, 8*4(sp) + lw x14, 7*4(sp) + lw x15, 6*4(sp) + lw x16, 5*4(sp) + lw x17, 4*4(sp) + lw x28, 3*4(sp) + lw x29, 2*4(sp) + lw x30, 1*4(sp) + lw x31, 0*4(sp) + addi sp,sp,16*4 + mret + +.text + +crt_init: + # # Flush the caches + # .word 16399 + # .word 19 + # .word 19 + # .word 19 + la sp, _estack - 4 + la a0, trap_entry + csrw mtvec, a0 + +bss_init: + la a0, _sbss + la a1, _ebss +bss_loop: + beq a0,a1,bss_done + sw zero,0(a0) + add a0,a0,4 + j bss_loop +bss_done: + + /* Load DATA */ + la t0, _sidata + la t1, _sdata + la t2, _edata +3: + lw t3, 0(t0) + sw t3, 0(t1) + /* _edata is aligned to 16 bytes. Use word-xfers. */ + addi t0, t0, 4 + addi t1, t1, 4 + bltu t1, t2, 3b + + li a0, 0x880 //880 enable timer + external interrupt sources (until mstatus.MIE is set, they will never trigger an interrupt) + csrw mie,a0 + + call main +infinite_loop: + j infinite_loop diff --git a/ports/litex/fatfs_port.c b/ports/litex/fatfs_port.c new file mode 100644 index 0000000000000..13ac21fb1bcca --- /dev/null +++ b/ports/litex/fatfs_port.c @@ -0,0 +1,33 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/runtime.h" +#include "lib/oofatfs/ff.h" + +DWORD get_fattime(void) { + // TODO: Implement this function. For now, fake it. + return ((2016 - 1980) << 25) | ((12) << 21) | ((4) << 16) | ((00) << 11) | ((18) << 5) | (23 / 2); +} diff --git a/ports/litex/hw/common.h b/ports/litex/hw/common.h new file mode 100644 index 0000000000000..6a97ca2e93f0a --- /dev/null +++ b/ports/litex/hw/common.h @@ -0,0 +1,33 @@ +#ifndef _HW_COMMON_H_ +#define _HW_COMMON_H_ +#include +static inline void csr_writeb(uint8_t value, uint32_t addr) +{ + *((volatile uint8_t *)addr) = value; +} + +static inline uint8_t csr_readb(uint32_t addr) +{ + return *(volatile uint8_t *)addr; +} + +static inline void csr_writew(uint16_t value, uint32_t addr) +{ + *((volatile uint16_t *)addr) = value; +} + +static inline uint16_t csr_readw(uint32_t addr) +{ + return *(volatile uint16_t *)addr; +} + +static inline void csr_writel(uint32_t value, uint32_t addr) +{ + *((volatile uint32_t *)addr) = value; +} + +static inline uint32_t csr_readl(uint32_t addr) +{ + return *(volatile uint32_t *)addr; +} +#endif /* _HW_COMMON_H_ */ \ No newline at end of file diff --git a/ports/litex/irq.h b/ports/litex/irq.h new file mode 100644 index 0000000000000..a8221890719a9 --- /dev/null +++ b/ports/litex/irq.h @@ -0,0 +1,71 @@ +#ifndef __IRQ_H +#define __IRQ_H + +#ifdef __cplusplus +extern "C" { +#endif + + +#define CSR_MSTATUS_MIE 0x8 + +#define CSR_IRQ_MASK 0xBC0 +#define CSR_IRQ_PENDING 0xFC0 + +#define CSR_DCACHE_INFO 0xCC0 + +#define csrr(reg) ({ unsigned long __tmp; \ + asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define csrw(reg, val) ({ \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ + else \ + asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) + +#define csrs(reg, bit) ({ \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrs x0, " #reg ", %0" :: "i"(bit)); \ + else \ + asm volatile ("csrrs x0, " #reg ", %0" :: "r"(bit)); }) + +#define csrc(reg, bit) ({ \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrc x0, " #reg ", %0" :: "i"(bit)); \ + else \ + asm volatile ("csrrc x0, " #reg ", %0" :: "r"(bit)); }) + +static inline unsigned int irq_getie(void) +{ + return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0; +} + +static inline void irq_setie(unsigned int ie) +{ + if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE); +} + +static inline unsigned int irq_getmask(void) +{ + unsigned int mask; + asm volatile ("csrr %0, %1" : "=r"(mask) : "i"(CSR_IRQ_MASK)); + return mask; +} + +static inline void irq_setmask(unsigned int mask) +{ + asm volatile ("csrw %0, %1" :: "i"(CSR_IRQ_MASK), "r"(mask)); +} + +static inline unsigned int irq_pending(void) +{ + unsigned int pending; + asm volatile ("csrr %0, %1" : "=r"(pending) : "i"(CSR_IRQ_PENDING)); + return pending; +} + +#ifdef __cplusplus +} +#endif + +#endif /* __IRQ_H */ \ No newline at end of file diff --git a/ports/litex/mpconfigport.h b/ports/litex/mpconfigport.h new file mode 100644 index 0000000000000..cfa3eb5c74592 --- /dev/null +++ b/ports/litex/mpconfigport.h @@ -0,0 +1,43 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2015 Glenn Ruben Bakke + * Copyright (c) 2019 Dan Halbert for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef FPGA_MPCONFIGPORT_H__ +#define FPGA_MPCONFIGPORT_H__ + +#define MICROPY_PY_UJSON (0) +#define CIRCUITPY_INTERNAL_NVM_SIZE (0) +#define MICROPY_NLR_THUMB (0) + +#include "py/circuitpy_mpconfig.h" + +#define MICROPY_PORT_ROOT_POINTERS \ + CIRCUITPY_COMMON_ROOT_POINTERS +#define MICROPY_NLR_SETJMP (1) +#define CIRCUITPY_DEFAULT_STACK_SIZE 0x6000 + + +#endif // __INCLUDED_FPGA_MPCONFIGPORT_H diff --git a/ports/litex/mpconfigport.mk b/ports/litex/mpconfigport.mk new file mode 100644 index 0000000000000..47e2b1abc8f21 --- /dev/null +++ b/ports/litex/mpconfigport.mk @@ -0,0 +1,31 @@ +# Define an equivalent for MICROPY_LONGINT_IMPL, to pass to $(MPY-TOOL) in py/mkrules.mk +# $(MPY-TOOL) needs to know what kind of longint to use (if any) to freeze long integers. +# This should correspond to the MICROPY_LONGINT_IMPL definition in mpconfigport.h. +MPY_TOOL_LONGINT_IMPL = -mlongint-impl=mpz + +# Internal math library is substantially smaller than toolchain one +INTERNAL_LIBM = 1 + +# Chip supplied serial number, in bytes +USB_SERIAL_NUMBER_LENGTH = 30 + +# Longints can be implemented as mpz, as longlong, or not +LONGINT_IMPL = MPZ + +#Reduced feature set for early port +CIRCUITPY_MINIMAL_BUILD = 1 + +# CIRCUITPY_BOARD = 1 +# CIRCUITPY_DIGITALIO = 1 +# CIRCUITPY_ANALOGIO = 1 +# CIRCUITPY_MICROCONTROLLER = 1 +# CIRCUITPY_BUSIO = 1 +# CIRCUITPY_PULSEIO = 1 +# CIRCUITPY_OS = 1 +# CIRCUITPY_STORAGE = 1 +# CIRCUITPY_RANDOM = 1 +CIRCUITPY_USB_HID = 1 +CIRCUITPY_USB_MIDI = 1 + +#ifeq ($(MCU_SUB_VARIANT), stm32f412zx) +#endif diff --git a/ports/litex/mphalport.c b/ports/litex/mphalport.c new file mode 100644 index 0000000000000..005a65aac4ac6 --- /dev/null +++ b/ports/litex/mphalport.c @@ -0,0 +1,81 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2015 Glenn Ruben Bakke + * Copyright (c) 2018 Artur Pacholec + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include + +#include "py/mphal.h" +#include "py/mpstate.h" +#include "py/gc.h" + +#include "csr.h" +#include "generated/soc.h" + +#include "irq.h" + +#ifdef CFG_TUSB_MCU + void hal_dcd_isr(uint8_t rhport); +#endif + +/*------------------------------------------------------------------*/ +/* delay + *------------------------------------------------------------------*/ +void mp_hal_delay_ms(mp_uint_t delay) { + uint64_t start_tick = supervisor_ticks_ms64(); + uint64_t duration = 0; + while (duration < delay) { + #ifdef MICROPY_VM_HOOK_LOOP + MICROPY_VM_HOOK_LOOP + #endif + // Check to see if we've been CTRL-Ced by autoreload or the user. + if(MP_STATE_VM(mp_pending_exception) == MP_OBJ_FROM_PTR(&MP_STATE_VM(mp_kbd_exception)) || + MP_STATE_VM(mp_pending_exception) == MP_OBJ_FROM_PTR(&MP_STATE_VM(mp_reload_exception))) { + break; + } + duration = (supervisor_ticks_ms64() - start_tick); + // TODO(tannewt): Go to sleep for a little while while we wait. + } +} + +extern void SysTick_Handler(void); + +__attribute__((section(".ramtext"))) +void isr(void) { + uint8_t irqs = irq_pending() & irq_getmask(); + +#ifdef CFG_TUSB_MCU + if (irqs & (1 << USB_INTERRUPT)) + hal_dcd_isr(0); +#endif + if (irqs & (1 << TIMER0_INTERRUPT)) + SysTick_Handler(); +} + +mp_uint_t cpu_get_regs_and_sp(mp_uint_t *regs) { + unsigned long __tmp; + asm volatile ("mv %0, x2" :"=r"(__tmp)); + return __tmp; +} diff --git a/ports/litex/mphalport.h b/ports/litex/mphalport.h new file mode 100644 index 0000000000000..540575c5879ee --- /dev/null +++ b/ports/litex/mphalport.h @@ -0,0 +1,42 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2015 Glenn Ruben Bakke + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef __FOMU_HAL +#define __FOMU_HAL + +#include +#include + +#include "lib/utils/interrupt_char.h" +#include "py/mpconfig.h" +#include "supervisor/shared/tick.h" + +#define mp_hal_ticks_ms() ((mp_uint_t) supervisor_ticks_ms32()) +//#define mp_hal_delay_us(us) NRFX_DELAY_US((uint32_t) (us)) + +bool mp_hal_stdin_any(void); + +#endif diff --git a/ports/litex/qstrdefsport.h b/ports/litex/qstrdefsport.h new file mode 100644 index 0000000000000..3ba897069bf73 --- /dev/null +++ b/ports/litex/qstrdefsport.h @@ -0,0 +1 @@ +// qstrs specific to this port diff --git a/ports/litex/supervisor/internal_flash.c b/ports/litex/supervisor/internal_flash.c new file mode 100644 index 0000000000000..93aeda8cbddb3 --- /dev/null +++ b/ports/litex/supervisor/internal_flash.c @@ -0,0 +1,350 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * Copyright (c) 2019 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#include "supervisor/internal_flash.h" + +#include +#include +#include + +#include "extmod/vfs.h" +#include "extmod/vfs_fat.h" +#include "py/mphal.h" +#include "py/obj.h" +#include "py/runtime.h" +#include "lib/oofatfs/ff.h" + +#include "supervisor/usb.h" + +#include "csr.h" +#include "irq.h" + +enum pin { + PIN_MOSI = 0, + PIN_CLK = 1, + PIN_CS = 2, + PIN_MISO_EN = 3, + PIN_MISO = 4, // Value is ignored +}; + +#define NO_CACHE 0xffffffff + +static uint8_t _flash_cache[FLASH_PAGE_SIZE] __attribute__((aligned(4))); +static uint32_t _flash_page_addr = NO_CACHE; +static bool _flash_cache_dirty; +// ------------------------------------------------------------------------- +// When performing SPI operations, the flash cannot be accessed. Since we +// normally execute directly from SPI, this can cause problems. +// To work around this, we execute from RAM. This is accomplished by marking +// functions as being in the section ".ramtext". +// When building under GCC with -O0 or -Od, the `inline` attribute is ignored. +// Therefore, we must re-implement these functions here and explicitly mark +// them as being in `.ramtext`, even though they really ought to be inlined. +__attribute__((section(".ramtext"))) +static inline void spi_writel(uint32_t value, uint32_t addr) +{ + *((volatile uint32_t *)addr) = value; +} + +__attribute__((section(".ramtext"))) +static inline uint32_t spi_readl(uint32_t addr) +{ + return *(volatile uint32_t *)addr; +} + +__attribute__((section(".ramtext"))) +static inline void bb_spi_write(unsigned char value) { + spi_writel(value, CSR_LXSPI_BITBANG_ADDR); +} + +__attribute__((section(".ramtext"))) +static inline uint32_t bb_read(void) { + return spi_readl(CSR_LXSPI_MISO_ADDR); +} + +__attribute__((section(".ramtext"))) +static inline void bb_spi_en(unsigned int en) { + spi_writel(en, CSR_LXSPI_BITBANG_EN_ADDR); +} + +__attribute__((section(".ramtext"))) +static inline void bb_spi_irq_setie(unsigned int ie) +{ + if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE); +} + +__attribute__((section(".ramtext"))) +static inline void bb_spi_begin(void) { + bb_spi_write((0 << PIN_CLK) | (0 << PIN_CS)); +} + +__attribute__((section(".ramtext"))) +static inline void bb_spi_end(void) { + bb_spi_write((0 << PIN_CLK) | (1 << PIN_CS)); +} + +__attribute__((section(".ramtext"))) +static void spi_single_tx(uint8_t out) { + int bit; + + for (bit = 7; bit >= 0; bit--) { + if (out & (1 << bit)) { + bb_spi_write((0 << PIN_CLK) | (1 << PIN_MOSI)); + bb_spi_write((1 << PIN_CLK) | (1 << PIN_MOSI)); + bb_spi_write((0 << PIN_CLK) | (1 << PIN_MOSI)); + } else { + bb_spi_write((0 << PIN_CLK) | (0 << PIN_MOSI)); + bb_spi_write((1 << PIN_CLK) | (0 << PIN_MOSI)); + bb_spi_write((0 << PIN_CLK) | (0 << PIN_MOSI)); + } + } +} + +__attribute__((section(".ramtext"))) +static uint8_t spi_single_rx(void) { + int bit = 0; + uint8_t in = 0; + + bb_spi_write((1 << PIN_MISO_EN) | (0 << PIN_CLK)); + + while (bit++ < 8) { + bb_spi_write((1 << PIN_MISO_EN) | (1 << PIN_CLK)); + in = (in << 1) | bb_read(); + bb_spi_write((1 << PIN_MISO_EN) | (0 << PIN_CLK)); + } + + return in; +} + +__attribute__((section(".ramtext"))) +static int bb_spi_beginErase4(uint32_t erase_addr) { + // Enable Write-Enable Latch (WEL) + bb_spi_begin(); + spi_single_tx(0x06); + bb_spi_end(); + + bb_spi_begin(); + spi_single_tx(0x20); + spi_single_tx(erase_addr >> 16); + spi_single_tx(erase_addr >> 8); + spi_single_tx(erase_addr >> 0); + bb_spi_end(); + return 0; +} + +__attribute__((section(".ramtext"))) +static int bb_spi_beginWrite(uint32_t addr, const void *v_data, unsigned int count) { + const uint8_t write_cmd = 0x02; + const uint8_t *data = v_data; + unsigned int i; + +#ifdef NDEBUG + if (v_data < (const void *)_flash_cache) { + asm("ebreak"); + } + if ((v_data+count) > (const void *)&_flash_cache[4096]) { + asm("ebreak"); + } +#endif + + // Enable Write-Enable Latch (WEL) + bb_spi_begin(); + spi_single_tx(0x06); + bb_spi_end(); + + bb_spi_begin(); + spi_single_tx(write_cmd); + spi_single_tx(addr >> 16); + spi_single_tx(addr >> 8); + spi_single_tx(addr >> 0); + for (i = 0; (i < count) && (i < 256); i++) + spi_single_tx(*data++); + bb_spi_end(); + + return 0; +} + +__attribute__((section(".ramtext"))) +static uint8_t spi_read_status(void) { + uint8_t val; + + bb_spi_begin(); + spi_single_tx(0x05); + val = spi_single_rx(); + bb_spi_end(); + return val; +} + +__attribute__((section(".ramtext"))) +static int bb_spi_is_busy(void) { + return spi_read_status() & (1 << 0); +} + +__attribute__((used)) +uint32_t page_write_log[128]; +__attribute__((used)) +uint32_t page_write_log_offset; + +__attribute__((section(".ramtext"))) +static void bb_spi_write_page(uint32_t flash_address, const uint8_t *data) { + const uint32_t flash_address_end = flash_address + FLASH_PAGE_SIZE; + + // Ensure we're within the target flash address range. + if ((flash_address - FLASH_PARTITION_OFFSET_BYTES) > FLASH_SIZE) { + asm("ebreak"); + return; + } + if (flash_address < FLASH_PARTITION_OFFSET_BYTES) { + asm("ebreak"); + return; + } + + if ((flash_address_end - FLASH_PARTITION_OFFSET_BYTES) > FLASH_SIZE) { + asm("ebreak"); + return; + } + if (flash_address_end < FLASH_PARTITION_OFFSET_BYTES) { + asm("ebreak"); + return; + } + + // Ensure we're not erasing the middle of a flash bank + if ((flash_address & 0xfff) != 0) { + asm("ebreak"); + return; + } + + page_write_log[page_write_log_offset++] = flash_address; + if (page_write_log_offset > sizeof(page_write_log)/sizeof(*page_write_log)) page_write_log_offset=0; + + while (bb_spi_is_busy()) + ; // relax + bb_spi_beginErase4(flash_address); + while (bb_spi_is_busy()) + ; // relax + while (flash_address < flash_address_end) { + bb_spi_beginWrite(flash_address, data, 256); + while (bb_spi_is_busy()) + ; // relax + flash_address += 256; + data += 256; + } +} + +static inline uint32_t lba2addr(uint32_t block) { + return (0x20000000 + FLASH_PARTITION_OFFSET_BYTES) + (block * FILESYSTEM_BLOCK_SIZE); +} + +void supervisor_flash_init(void) { +} + +uint32_t supervisor_flash_get_block_size(void) { + return FILESYSTEM_BLOCK_SIZE; +} + +uint32_t supervisor_flash_get_block_count(void) { + return FLASH_SIZE/FILESYSTEM_BLOCK_SIZE; +} + +__attribute__((section(".ramtext"))) +void supervisor_flash_flush(void) { + // Skip if data is the same, or if there is no data in the cache + if (_flash_page_addr == NO_CACHE) + return; + if (!_flash_cache_dirty) + return; + + // Disable interrupts and enable bit-bang mode on the SPI flash. + // This function is running from RAM -- otherwise enabling bitbang mode + // would crash the CPU as the program suddenly became an endless stream + // of `0xffffffff`. + bb_spi_irq_setie(0); + bb_spi_write((0 << PIN_CLK) | (1 << PIN_CS)); + bb_spi_en(1); + + bb_spi_write_page(_flash_page_addr & 0x00ffffff, (const uint8_t *)_flash_cache); + + bb_spi_en(0); + bb_spi_irq_setie(1); + + _flash_cache_dirty = false; +} + +mp_uint_t supervisor_flash_read_blocks(uint8_t *dest, uint32_t block, uint32_t num_blocks) { + // Must write out anything in cache before trying to read. + supervisor_flash_flush(); + + uint32_t src = lba2addr(block); + memcpy(dest, (uint8_t*) src, FILESYSTEM_BLOCK_SIZE*num_blocks); + + #if USB_AVAILABLE + usb_background(); + #endif + + return 0; +} + +mp_uint_t supervisor_flash_write_blocks(const uint8_t *src, uint32_t lba, uint32_t num_blocks) { + while (num_blocks) { + uint32_t const addr = lba2addr(lba); + uint32_t const page_addr = addr & ~(FLASH_PAGE_SIZE - 1); + + uint32_t count = 8 - (lba % 8); // up to page boundary + count = MIN(num_blocks, count); + + if (page_addr != _flash_page_addr) { + // Write out anything in cache before overwriting it. + supervisor_flash_flush(); + + _flash_page_addr = page_addr; + _flash_cache_dirty = false; + + // Copy the current contents of the entire page into the cache. + memcpy(_flash_cache, (void *)page_addr, FLASH_PAGE_SIZE); + } + + // Overwrite part or all of the page cache with the src data, but only if it's changed. + if (_flash_cache_dirty || memcmp(_flash_cache + (addr & (FLASH_PAGE_SIZE - 1)), src, count * FILESYSTEM_BLOCK_SIZE)) { + memcpy(_flash_cache + (addr & (FLASH_PAGE_SIZE - 1)), src, count * FILESYSTEM_BLOCK_SIZE); + _flash_cache_dirty = true; + } + + // adjust for next run + lba += count; + src += count * FILESYSTEM_BLOCK_SIZE; + num_blocks -= count; + + #if USB_AVAILABLE + usb_background(); + #endif + } + + return 0; // success +} + +void supervisor_flash_release_cache(void) { +} + diff --git a/ports/litex/supervisor/internal_flash.h b/ports/litex/supervisor/internal_flash.h new file mode 100644 index 0000000000000..41a69e2abef1a --- /dev/null +++ b/ports/litex/supervisor/internal_flash.h @@ -0,0 +1,38 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * Copyright (c) 2019 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#ifndef MICROPY_INCLUDED_LITEX_INTERNAL_FLASH_H +#define MICROPY_INCLUDED_LITEX_INTERNAL_FLASH_H + +#include +#include + +#include "py/mpconfig.h" + +#define INTERNAL_FLASH_SYSTICK_MASK (0x1ff) // 512ms +#define INTERNAL_FLASH_IDLE_TICK(tick) (((tick) & INTERNAL_FLASH_SYSTICK_MASK) == 2) + +#endif // MICROPY_INCLUDED_LITEX_INTERNAL_FLASH_H diff --git a/ports/litex/supervisor/internal_flash_root_pointers.h b/ports/litex/supervisor/internal_flash_root_pointers.h new file mode 100644 index 0000000000000..ae3e45e14c001 --- /dev/null +++ b/ports/litex/supervisor/internal_flash_root_pointers.h @@ -0,0 +1,31 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2018 Scott Shawcroft for Adafruit Industries LLC + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#ifndef MICROPY_INCLUDED_LITEX_INTERNAL_FLASH_ROOT_POINTERS_H +#define MICROPY_INCLUDED_LITEX_INTERNAL_FLASH_ROOT_POINTERS_H + +#define FLASH_ROOT_POINTERS + +#endif // MICROPY_INCLUDED_LITEX_INTERNAL_FLASH_ROOT_POINTERS_H diff --git a/ports/litex/supervisor/port.c b/ports/litex/supervisor/port.c new file mode 100644 index 0000000000000..9688c7baefa15 --- /dev/null +++ b/ports/litex/supervisor/port.c @@ -0,0 +1,85 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries + * Copyright (c) 2019 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include "supervisor/port.h" +#include "boards/board.h" +#include "tick.h" +#include "irq.h" +#include "csr.h" + +safe_mode_t port_init(void) { + irq_setmask(0); + irq_setie(1); + tick_init(); + board_init(); + return NO_SAFE_MODE; +} + +extern uint32_t _ebss; +extern uint32_t _heap_start; +extern uint32_t _estack; + +void reset_port(void) { + // reset_all_pins(); + // i2c_reset(); + // spi_reset(); + // uart_reset(); + // pwmout_reset(); +} + +void reset_to_bootloader(void) { + reboot_ctrl_write(0xac); +} + +void reset_cpu(void) { +} + +uint32_t *port_heap_get_bottom(void) { + return port_stack_get_limit(); +} + +uint32_t *port_heap_get_top(void) { + return port_stack_get_top(); +} + +uint32_t *port_stack_get_limit(void) { + return &_ebss; +} + +uint32_t *port_stack_get_top(void) { + return &_estack; +} + +// Place the word to save just after our BSS section that gets blanked. +void port_set_saved_word(uint32_t value) { + _ebss = value; +} + +uint32_t port_get_saved_word(void) { + return _ebss; +} diff --git a/ports/litex/supervisor/usb.c b/ports/litex/supervisor/usb.c new file mode 100644 index 0000000000000..182360b713179 --- /dev/null +++ b/ports/litex/supervisor/usb.c @@ -0,0 +1,36 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2018 hathach for Adafruit Industries + * Copyright (c) 2019 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + + +#include "tick.h" +#include "supervisor/usb.h" +#include "lib/utils/interrupt_char.h" +#include "lib/mp-readline/readline.h" + +void init_usb_hardware(void) { + +} diff --git a/ports/litex/tick.c b/ports/litex/tick.c new file mode 100644 index 0000000000000..8ba06044ac492 --- /dev/null +++ b/ports/litex/tick.c @@ -0,0 +1,82 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "csr.h" +#include "tick.h" +#include "irq.h" + +#include "supervisor/shared/autoreload.h" +#include "supervisor/filesystem.h" +#include "supervisor/shared/tick.h" +#include "shared-module/gamepad/__init__.h" +#include "shared-bindings/microcontroller/Processor.h" + +// Global millisecond tick count +// volatile uint64_t ticks_ms = 0; + +__attribute__((section(".ramtext"))) +void SysTick_Handler(void) { + timer0_ev_pending_write(1); + supervisor_tick(); +} + +void tick_init() { + int t; + + timer0_en_write(0); + t = CONFIG_CLOCK_FREQUENCY / 1000; // 1000 kHz tick + timer0_reload_write(t); + timer0_load_write(t); + timer0_en_write(1); + timer0_ev_enable_write(1); + timer0_ev_pending_write(1); + irq_setmask(irq_getmask() | (1 << TIMER0_INTERRUPT)); +} + +void tick_delay(uint32_t us) { + // uint32_t ticks_per_us = SystemCoreClock / 1000 / 1000; + // uint32_t us_between_ticks = SysTick->VAL / ticks_per_us; + // uint64_t start_ms = ticks_ms; + // while (us > 1000) { + // while (ticks_ms == start_ms) {} + // us -= us_between_ticks; + // start_ms = ticks_ms; + // us_between_ticks = 1000; + // } + // while (SysTick->VAL > ((us_between_ticks - us) * ticks_per_us)) {} +} + +// us counts down! +void current_tick(uint64_t* ms, uint32_t* us_until_ms) { + // uint32_t ticks_per_us = SystemCoreClock / 1000 / 1000; + // *ms = ticks_ms; + // *us_until_ms = SysTick->VAL / ticks_per_us; +} + +void wait_until(uint64_t ms, uint32_t us_until_ms) { + // uint32_t ticks_per_us = SystemCoreClock / 1000 / 1000; + // while(ticks_ms <= ms && SysTick->VAL / ticks_per_us >= us_until_ms) {} +} diff --git a/ports/litex/tick.h b/ports/litex/tick.h new file mode 100644 index 0000000000000..b4d27b8416e50 --- /dev/null +++ b/ports/litex/tick.h @@ -0,0 +1,46 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#ifndef MICROPY_INCLUDED_LITEX_TICK_H +#define MICROPY_INCLUDED_LITEX_TICK_H + +#include "py/mpconfig.h" + +#include + +extern volatile uint64_t ticks_ms; + +extern struct timer_descriptor ms_timer; + +void tick_init(void); + +void tick_delay(uint32_t us); + +void current_tick(uint64_t* ms, uint32_t* us_until_ms); +// Do not call this with interrupts disabled because it may be waiting for +// ticks_ms to increment. +void wait_until(uint64_t ms, uint32_t us_until_ms); + +#endif // MICROPY_INCLUDED_LITEX_TICK_H diff --git a/ports/mimxrt10xx/common-hal/neopixel_write/__init__.c b/ports/mimxrt10xx/common-hal/neopixel_write/__init__.c index 9ea2335021b31..3e1d343ec851e 100644 --- a/ports/mimxrt10xx/common-hal/neopixel_write/__init__.c +++ b/ports/mimxrt10xx/common-hal/neopixel_write/__init__.c @@ -32,7 +32,6 @@ #include "py/mperrno.h" #include "py/runtime.h" #include "common-hal/microcontroller/Pin.h" -#include "fsl_gpio.h" uint64_t next_start_tick_ms = 0; uint32_t next_start_tick_us = 1000; @@ -45,7 +44,7 @@ uint32_t next_start_tick_us = 1000; #pragma GCC push_options #pragma GCC optimize ("Os") -void common_hal_neopixel_write (const digitalio_digitalinout_obj_t* digitalinout, uint8_t *pixels, +void PLACE_IN_ITCM(common_hal_neopixel_write)(const digitalio_digitalinout_obj_t* digitalinout, uint8_t *pixels, uint32_t numBytes) { uint8_t *p = pixels, *end = p + numBytes, pix = *p++, mask = 0x80; uint32_t start = 0; @@ -54,14 +53,10 @@ void common_hal_neopixel_write (const digitalio_digitalinout_obj_t* digitalinout //assumes 800_000Hz frequency //Theoretical values here are 800_000 -> 1.25us, 2500000->0.4us, 1250000->0.8us //TODO: try to get dynamic weighting working again -#ifdef MIMXRT1011_SERIES - uint32_t sys_freq = CLOCK_GetCoreFreq(); -#else - uint32_t sys_freq = CLOCK_GetAhbFreq(); -#endif - uint32_t interval = sys_freq/MAGIC_800_INT; - uint32_t t0 = (sys_freq/MAGIC_800_T0H); - uint32_t t1 = (sys_freq/MAGIC_800_T1H); + const uint32_t sys_freq = SystemCoreClock; + const uint32_t interval = (sys_freq / MAGIC_800_INT); + const uint32_t t0 = (sys_freq / MAGIC_800_T0H); + const uint32_t t1 = (sys_freq / MAGIC_800_T1H); // This must be called while interrupts are on in case we're waiting for a // future ms tick. @@ -79,9 +74,9 @@ void common_hal_neopixel_write (const digitalio_digitalinout_obj_t* digitalinout for(;;) { cyc = (pix & mask) ? t1 : t0; start = DWT->CYCCNT; - GPIO_PinWrite(gpio, pin, 1); + gpio->DR |= (1U << pin); while((DWT->CYCCNT - start) < cyc); - GPIO_PinWrite(gpio, pin, 0); + gpio->DR &= ~(1U << pin); while((DWT->CYCCNT - start) < interval); if(!(mask >>= 1)) { if(p >= end) break; diff --git a/ports/nrf/boards/clue_nrf52840_express/board.c b/ports/nrf/boards/clue_nrf52840_express/board.c index 03b212f9e078d..e9f8d244e43b9 100644 --- a/ports/nrf/boards/clue_nrf52840_express/board.c +++ b/ports/nrf/boards/clue_nrf52840_express/board.c @@ -59,7 +59,9 @@ void board_init(void) { &pin_P0_13, // TFT_DC Command or data &pin_P0_12, // TFT_CS Chip select &pin_P1_03, // TFT_RST Reset - 60000000); + 60000000, // Baudrate + 0, // Polarity + 0); // Phase displayio_display_obj_t* display = &displays[0].display; display->base.type = &displayio_display_type; diff --git a/ports/nrf/boards/ohs2020_badge/board.c b/ports/nrf/boards/ohs2020_badge/board.c index 106bbd6e1665d..88c68bcb84b8d 100644 --- a/ports/nrf/boards/ohs2020_badge/board.c +++ b/ports/nrf/boards/ohs2020_badge/board.c @@ -59,7 +59,9 @@ void board_init(void) { &pin_P0_08, // TFT_DC Command or data &pin_P0_14, // TFT_CS Chip select &pin_P0_13, // TFT_RST Reset - 60000000); + 60000000, // Baudrate + 0, // Polarity + 0); // Phase displayio_display_obj_t* display = &displays[0].display; display->base.type = &displayio_display_type; diff --git a/ports/nrf/common-hal/_bleio/Connection.c b/ports/nrf/common-hal/_bleio/Connection.c index 96e8b8fbe9fb2..d4c7308fd13df 100644 --- a/ports/nrf/common-hal/_bleio/Connection.c +++ b/ports/nrf/common-hal/_bleio/Connection.c @@ -162,7 +162,8 @@ bool connection_on_ble_evt(ble_evt_t *ble_evt, void *self_in) { self->do_bond_cccds = true; self->do_bond_cccds_request_time = supervisor_ticks_ms64(); } - break; + // Return false so other handlers get this event as well. + return false; case BLE_GATTS_EVT_SYS_ATTR_MISSING: sd_ble_gatts_sys_attr_set(self->conn_handle, NULL, 0, 0); diff --git a/ports/nrf/common-hal/_bleio/PacketBuffer.c b/ports/nrf/common-hal/_bleio/PacketBuffer.c index 27dacb49384f8..6ed6d145149b3 100644 --- a/ports/nrf/common-hal/_bleio/PacketBuffer.c +++ b/ports/nrf/common-hal/_bleio/PacketBuffer.c @@ -148,6 +148,7 @@ STATIC bool packet_buffer_on_ble_server_evt(ble_evt_t *ble_evt, void *param) { // A client wrote to this server characteristic. ble_gatts_evt_write_t *evt_write = &ble_evt->evt.gatts_evt.params.write; + // Event handle must match the handle for my characteristic. if (evt_write->handle == self->characteristic->handle) { if (self->conn_handle == BLE_CONN_HANDLE_INVALID) { @@ -156,8 +157,7 @@ STATIC bool packet_buffer_on_ble_server_evt(ble_evt_t *ble_evt, void *param) { return false; } write_to_ringbuf(self, evt_write->data, evt_write->len); - } else if (evt_write->handle == self->characteristic->cccd_handle && - self->conn_handle == BLE_CONN_HANDLE_INVALID) { + } else if (evt_write->handle == self->characteristic->cccd_handle) { uint16_t cccd = *((uint16_t*) evt_write->data); if (cccd & BLE_GATT_HVX_NOTIFICATION) { self->conn_handle = conn_handle; @@ -167,6 +167,11 @@ STATIC bool packet_buffer_on_ble_server_evt(ble_evt_t *ble_evt, void *param) { } break; } + case BLE_GAP_EVT_DISCONNECTED: { + if (self->conn_handle == conn_handle) { + self->conn_handle = BLE_CONN_HANDLE_INVALID; + } + } case BLE_GATTS_EVT_HVN_TX_COMPLETE: { queue_next_write(self); } @@ -192,6 +197,8 @@ void common_hal_bleio_packet_buffer_construct( incoming = outgoing; outgoing = temp; self->conn_handle = bleio_connection_get_conn_handle(MP_OBJ_TO_PTR(self->characteristic->service->connection)); + } else { + self->conn_handle = BLE_CONN_HANDLE_INVALID; } if (incoming) { @@ -255,8 +262,7 @@ int common_hal_bleio_packet_buffer_readinto(bleio_packet_buffer_obj_t *self, uin sd_nvic_critical_region_enter(&is_nested_critical_region); if (packet_length > len) { - // TODO: raise an exception. - packet_length = len; + return len - packet_length; } ringbuf_get_n(&self->ringbuf, data, packet_length); diff --git a/ports/stm/boards/meowbit_v121/board.c b/ports/stm/boards/meowbit_v121/board.c index da87f00ec208e..9e2d99bce080f 100644 --- a/ports/stm/boards/meowbit_v121/board.c +++ b/ports/stm/boards/meowbit_v121/board.c @@ -61,7 +61,7 @@ uint8_t display_init_sequence[] = { 0x3a, 1, 0x05, // COLMOD - 16bit color 0xe0, 0x10, 0x02, 0x1c, 0x07, 0x12, 0x37, 0x32, 0x29, 0x2d, - 0x29, 0x25, 0x2B, 0x39, + 0x29, 0x25, 0x2B, 0x39, 0x00, 0x01, 0x03, 0x10, // _GMCTRP1 Gamma 0xe1, 0x10, 0x03, 0x1d, 0x07, 0x06, 0x2E, 0x2C, 0x29, 0x2D, @@ -80,7 +80,9 @@ void board_init(void) { &pin_PA08, // Command or data &pin_PB12, // Chip select &pin_PB10, // Reset - 24000000); + 24000000, // Baudrate + 0, // Polarity + 0); // Phase displayio_display_obj_t* display = &displays[0].display; display->base.type = &displayio_display_type; diff --git a/shared-bindings/_bleio/PacketBuffer.c b/shared-bindings/_bleio/PacketBuffer.c index 3ed295f017c85..9e3666044abd1 100644 --- a/shared-bindings/_bleio/PacketBuffer.c +++ b/shared-bindings/_bleio/PacketBuffer.c @@ -109,7 +109,12 @@ STATIC mp_obj_t bleio_packet_buffer_readinto(mp_obj_t self_in, mp_obj_t buffer_o mp_buffer_info_t bufinfo; mp_get_buffer_raise(buffer_obj, &bufinfo, MP_BUFFER_WRITE); - return MP_OBJ_NEW_SMALL_INT(common_hal_bleio_packet_buffer_readinto(self, bufinfo.buf, bufinfo.len)); + int size = common_hal_bleio_packet_buffer_readinto(self, bufinfo.buf, bufinfo.len); + if (size < 0) { + mp_raise_ValueError_varg(translate("Buffer too short by %d bytes"), size * -1); + } + + return MP_OBJ_NEW_SMALL_INT(size); } STATIC MP_DEFINE_CONST_FUN_OBJ_2(bleio_packet_buffer_readinto_obj, bleio_packet_buffer_readinto); diff --git a/shared-bindings/displayio/FourWire.c b/shared-bindings/displayio/FourWire.c index 2cbceec48cd06..77329578a43b8 100644 --- a/shared-bindings/displayio/FourWire.c +++ b/shared-bindings/displayio/FourWire.c @@ -46,7 +46,7 @@ //| Manage updating a display over SPI four wire protocol in the background while Python code runs. //| It doesn't handle display initialization. //| -//| .. class:: FourWire(spi_bus, *, command, chip_select, reset=None, baudrate=24000000) +//| .. class:: FourWire(spi_bus, *, command, chip_select, reset=None, baudrate=24000000, polarity=0, phase=0) //| //| Create a FourWire object associated with the given pins. //| @@ -60,15 +60,20 @@ //| :param microcontroller.Pin chip_select: Chip select pin //| :param microcontroller.Pin reset: Reset pin. When None only software reset can be used //| :param int baudrate: Maximum baudrate in Hz for the display on the bus +//| :param int polarity: the base state of the clock line (0 or 1) +//| :param int phase: the edge of the clock that data is captured. First (0) +//| or second (1). Rising or falling depends on clock polarity. //| STATIC mp_obj_t displayio_fourwire_make_new(const mp_obj_type_t *type, size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { - enum { ARG_spi_bus, ARG_command, ARG_chip_select, ARG_reset, ARG_baudrate }; + enum { ARG_spi_bus, ARG_command, ARG_chip_select, ARG_reset, ARG_baudrate, ARG_polarity, ARG_phase }; static const mp_arg_t allowed_args[] = { { MP_QSTR_spi_bus, MP_ARG_REQUIRED | MP_ARG_OBJ }, { MP_QSTR_command, MP_ARG_OBJ | MP_ARG_KW_ONLY | MP_ARG_REQUIRED }, { MP_QSTR_chip_select, MP_ARG_OBJ | MP_ARG_KW_ONLY | MP_ARG_REQUIRED }, { MP_QSTR_reset, MP_ARG_OBJ | MP_ARG_KW_ONLY, {.u_obj = mp_const_none} }, { MP_QSTR_baudrate, MP_ARG_INT | MP_ARG_KW_ONLY, {.u_int = 24000000} }, + { MP_QSTR_polarity, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} }, + { MP_QSTR_phase, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} }, }; mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; mp_arg_parse_all(n_args, pos_args, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); @@ -91,8 +96,17 @@ STATIC mp_obj_t displayio_fourwire_make_new(const mp_obj_type_t *type, size_t n_ mp_raise_RuntimeError(translate("Too many display busses")); } + uint8_t polarity = args[ARG_polarity].u_int; + if (polarity != 0 && polarity != 1) { + mp_raise_ValueError(translate("Invalid polarity")); + } + uint8_t phase = args[ARG_phase].u_int; + if (phase != 0 && phase != 1) { + mp_raise_ValueError(translate("Invalid phase")); + } + common_hal_displayio_fourwire_construct(self, - MP_OBJ_TO_PTR(spi), command, chip_select, reset, args[ARG_baudrate].u_int); + MP_OBJ_TO_PTR(spi), command, chip_select, reset, args[ARG_baudrate].u_int, polarity, phase); return self; } diff --git a/shared-bindings/displayio/FourWire.h b/shared-bindings/displayio/FourWire.h index d0935f06390d0..ac186d2c3ee76 100644 --- a/shared-bindings/displayio/FourWire.h +++ b/shared-bindings/displayio/FourWire.h @@ -38,7 +38,8 @@ extern const mp_obj_type_t displayio_fourwire_type; void common_hal_displayio_fourwire_construct(displayio_fourwire_obj_t* self, busio_spi_obj_t* spi, const mcu_pin_obj_t* command, - const mcu_pin_obj_t* chip_select, const mcu_pin_obj_t* reset, uint32_t baudrate); + const mcu_pin_obj_t* chip_select, const mcu_pin_obj_t* reset, uint32_t baudrate, + uint8_t polarity, uint8_t phase); void common_hal_displayio_fourwire_deinit(displayio_fourwire_obj_t* self); diff --git a/shared-module/displayio/FourWire.c b/shared-module/displayio/FourWire.c index 256c29642dc93..fe7234aa7a401 100644 --- a/shared-module/displayio/FourWire.c +++ b/shared-module/displayio/FourWire.c @@ -40,7 +40,8 @@ void common_hal_displayio_fourwire_construct(displayio_fourwire_obj_t* self, busio_spi_obj_t* spi, const mcu_pin_obj_t* command, - const mcu_pin_obj_t* chip_select, const mcu_pin_obj_t* reset, uint32_t baudrate) { + const mcu_pin_obj_t* chip_select, const mcu_pin_obj_t* reset, uint32_t baudrate, + uint8_t polarity, uint8_t phase) { self->bus = spi; common_hal_busio_spi_never_reset(self->bus); @@ -49,8 +50,8 @@ void common_hal_displayio_fourwire_construct(displayio_fourwire_obj_t* self, gc_never_free(self->bus); self->frequency = baudrate; - self->polarity = 0; - self->phase = 0; + self->polarity = polarity; + self->phase = phase; common_hal_digitalio_digitalinout_construct(&self->command, command); common_hal_digitalio_digitalinout_switch_to_output(&self->command, true, DRIVE_MODE_PUSH_PULL); diff --git a/supervisor/linker.h b/supervisor/linker.h index 57ae1461587ed..878268c734c4f 100755 --- a/supervisor/linker.h +++ b/supervisor/linker.h @@ -29,7 +29,7 @@ #ifndef MICROPY_INCLUDED_SUPERVISOR_LINKER_H #define MICROPY_INCLUDED_SUPERVISOR_LINKER_H -#if defined(IMXRT10XX) // || defined(STM32H7) +#if defined(IMXRT10XX) || defined(FOMU) // || defined(STM32H7) #define PLACE_IN_DTCM_DATA(name) name __attribute__((section(".dtcm_data." #name ))) #define PLACE_IN_DTCM_BSS(name) name __attribute__((section(".dtcm_bss." #name ))) #define PLACE_IN_ITCM(name) __attribute__((section(".itcm." #name ))) name diff --git a/tools/build_board_info.py b/tools/build_board_info.py index b64f734f88d7f..543224faea6f3 100644 --- a/tools/build_board_info.py +++ b/tools/build_board_info.py @@ -12,7 +12,7 @@ sys.path.append("adabot") import adabot.github_requests as github -SUPPORTED_PORTS = ["nrf", "atmel-samd", "stm", "cxd56", "mimxrt10xx"] +SUPPORTED_PORTS = ["nrf", "atmel-samd", "stm", "cxd56", "mimxrt10xx", "litex"] BIN = ('bin',) UF2 = ('uf2',) @@ -20,6 +20,8 @@ HEX = ('hex',) HEX_UF2 = ('hex', 'uf2') SPK = ('spk',) +DFU = ('dfu',) +BIN_DFU = ('bin', 'dfu') # Example: # https://downloads.circuitpython.org/bin/trinket_m0/en_US/adafruit-circuitpython-trinket_m0-en_US-5.0.0-rc.0.uf2 @@ -32,6 +34,7 @@ "stm": BIN, "cxd56": SPK, "mimxrt10xx": HEX_UF2, + "litex": DFU, } # Per board overrides diff --git a/tools/dfu.py b/tools/dfu.py old mode 100755 new mode 100644 index 54b602438b381..dd6019235bd89 --- a/tools/dfu.py +++ b/tools/dfu.py @@ -1,6 +1,7 @@ #!/usr/bin/python # Written by Antonio Galea - 2010/11/18 +# Updated for DFU 1.1 by Sean Cross - 2020/03/31 # Distributed under Gnu LGPL 3.0 # see http://www.gnu.org/licenses/lgpl-3.0.txt @@ -23,30 +24,7 @@ def parse(file,dump_images=False): print ('File: "%s"' % file) data = open(file,'rb').read() crc = compute_crc(data[:-4]) - prefix, data = consume('<5sBIB',data,'signature version size targets') - print ('%(signature)s v%(version)d, image size: %(size)d, targets: %(targets)d' % prefix) - for t in range(prefix['targets']): - tprefix, data = consume('<6sBI255s2I',data,'signature altsetting named name size elements') - tprefix['num'] = t - if tprefix['named']: - tprefix['name'] = cstring(tprefix['name']) - else: - tprefix['name'] = '' - print ('%(signature)s %(num)d, alt setting: %(altsetting)s, name: "%(name)s", size: %(size)d, elements: %(elements)d' % tprefix) - tsize = tprefix['size'] - target, data = data[:tsize], data[tsize:] - for e in range(tprefix['elements']): - eprefix, target = consume('<2I',target,'address size') - eprefix['num'] = e - print (' %(num)d, address: 0x%(address)08x, size: %(size)d' % eprefix) - esize = eprefix['size'] - image, target = target[:esize], target[esize:] - if dump_images: - out = '%s.target%d.image%d.bin' % (file,t,e) - open(out,'wb').write(image) - print (' DUMPED IMAGE TO "%s"' % out) - if len(target): - print ("target %d: PARSE ERROR" % t) + data = data[len(data)-16:] suffix = named(struct.unpack('<4H3sBI',data[:16]),'device product vendor dfu ufd len crc') print ('usb: %(vendor)04x:%(product)04x, device: 0x%(device)04x, dfu: 0x%(dfu)04x, %(ufd)s, %(len)d, 0x%(crc)08x' % suffix) if crc != suffix['crc']: @@ -55,53 +33,49 @@ def parse(file,dump_images=False): if data: print ("PARSE ERROR") -def build(file,targets,device=DEFAULT_DEVICE): - data = b'' - for t,target in enumerate(targets): - tdata = b'' - for image in target: - tdata += struct.pack('<2I',image['address'],len(image['data']))+image['data'] - tdata = struct.pack('<6sBI255s2I',b'Target',0,1, b'ST...',len(tdata),len(target)) + tdata - data += tdata - data = struct.pack('<5sBIB',b'DfuSe',1,len(data)+11,len(targets)) + data +def build(file,data,device=DEFAULT_DEVICE): + # Parse the VID and PID from the `device` argument v,d=map(lambda x: int(x,0) & 0xFFFF, device.split(':',1)) - data += struct.pack('<4H3sB',0,d,v,0x011a,b'UFD',16) + + # Generate the DFU suffix, consisting of these fields: + # Field name | Length | Description + # ================+=========+================================ + # bcdDevice | 2 | The release number of this firmware (0xffff - don't care) + # idProduct | 2 | PID of this device + # idVendor | 2 | VID of this device + # bcdDFU | 2 | Version of this DFU spec (0x01 0x00) + # ucDfuSignature | 3 | The characters 'DFU', printed in reverse order + # bLength | 1 | The length of this suffix (16 bytes) + # dwCRC | 4 | A CRC32 of the data, including this suffix + data += struct.pack('<4H3sB',0xffff,d,v,0x0100,b'UFD',16) crc = compute_crc(data) + # Append the CRC32 of the entire block data += struct.pack(' Date: Thu, 2 Apr 2020 11:47:16 -0400 Subject: [PATCH 07/17] Implement F7 Nucleo --- ports/mimxrt10xx/supervisor/port.c | 2 +- ports/stm/Makefile | 7 +- ports/stm/boards/STM32F767ZITx_FLASH.ld | 189 ++++++ ports/stm/boards/STM32F767_fs.ld | 107 +++ ports/stm/boards/nucleo_f767zi/board.c | 38 ++ .../stm/boards/nucleo_f767zi/mpconfigboard.h | 35 + .../stm/boards/nucleo_f767zi/mpconfigboard.mk | 14 + ports/stm/boards/nucleo_f767zi/pins.c | 142 ++++ .../boards/nucleo_f767zi/stm32f7xx_hal_conf.h | 445 +++++++++++++ ports/stm/boards/startup_stm32f767xx.s | 618 ++++++++++++++++++ ports/stm/common-hal/digitalio/DigitalInOut.c | 2 + ports/stm/mpconfigport.mk | 16 + ports/stm/peripherals/periph.h | 9 + ports/stm/peripherals/pins.h | 5 + .../peripherals/stm32f7/stm32f767xx/clocks.c | 66 ++ .../peripherals/stm32f7/stm32f767xx/gpio.c | 48 ++ .../peripherals/stm32f7/stm32f767xx/periph.c | 248 +++++++ .../peripherals/stm32f7/stm32f767xx/periph.h | 55 ++ .../peripherals/stm32f7/stm32f767xx/pins.c | 200 ++++++ .../peripherals/stm32f7/stm32f767xx/pins.h | 199 ++++++ ports/stm/supervisor/internal_flash.c | 56 +- ports/stm/supervisor/internal_flash.h | 6 + ports/stm/supervisor/usb.c | 5 +- ports/stm/system_stm32f7xx.c | 247 +++++++ ports/stm/tools/parse_af_csv.py | 2 +- ports/stm/tools/pins.csv | 137 ++++ ports/stm/tools/stm32f767_af.csv | 168 +++++ 27 files changed, 3038 insertions(+), 28 deletions(-) create mode 100644 ports/stm/boards/STM32F767ZITx_FLASH.ld create mode 100644 ports/stm/boards/STM32F767_fs.ld create mode 100644 ports/stm/boards/nucleo_f767zi/board.c create mode 100644 ports/stm/boards/nucleo_f767zi/mpconfigboard.h create mode 100644 ports/stm/boards/nucleo_f767zi/mpconfigboard.mk create mode 100644 ports/stm/boards/nucleo_f767zi/pins.c create mode 100644 ports/stm/boards/nucleo_f767zi/stm32f7xx_hal_conf.h create mode 100644 ports/stm/boards/startup_stm32f767xx.s create mode 100644 ports/stm/peripherals/stm32f7/stm32f767xx/clocks.c create mode 100644 ports/stm/peripherals/stm32f7/stm32f767xx/gpio.c create mode 100644 ports/stm/peripherals/stm32f7/stm32f767xx/periph.c create mode 100644 ports/stm/peripherals/stm32f7/stm32f767xx/periph.h create mode 100644 ports/stm/peripherals/stm32f7/stm32f767xx/pins.c create mode 100644 ports/stm/peripherals/stm32f7/stm32f767xx/pins.h create mode 100644 ports/stm/system_stm32f7xx.c create mode 100644 ports/stm/tools/pins.csv create mode 100644 ports/stm/tools/stm32f767_af.csv diff --git a/ports/mimxrt10xx/supervisor/port.c b/ports/mimxrt10xx/supervisor/port.c index b311e89206511..7ba7a77011b0e 100644 --- a/ports/mimxrt10xx/supervisor/port.c +++ b/ports/mimxrt10xx/supervisor/port.c @@ -154,7 +154,7 @@ __attribute__((used, naked)) void Reset_Handler(void) { /* Disable MPU */ ARM_MPU_Disable(); - // Copy all of the code to run from ITCM. Do this while the MPU is disabled because we write + // Copy all of the itcm code to run from ITCM. Do this while the MPU is disabled because we write // protect it. for (uint32_t i = 0; i < ((size_t) &_ld_itcm_size) / 4; i++) { (&_ld_itcm_destination)[i] = (&_ld_itcm_flash_copy)[i]; diff --git a/ports/stm/Makefile b/ports/stm/Makefile index a654feac01f5e..9b90079381eec 100755 --- a/ports/stm/Makefile +++ b/ports/stm/Makefile @@ -96,11 +96,8 @@ C_DEFS = -D$(MCU_PACKAGE) -DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER -D$(MCU_VARIANT) CFLAGS += $(INC) -Werror -Wall -std=gnu11 -nostdlib $(BASE_CFLAGS) $(C_DEFS) $(CFLAGS_MOD) $(COPT) # Undo some warnings. -# STM32 apparently also uses undefined preprocessor variables quite casually, -# so we can't do warning checks for these. -CFLAGS += -Wno-undef -# STM32 might do casts that increase alignment requirements. -CFLAGS += -Wno-cast-align +# STM32 HAL uses undefined preprocessor variables, shadowed variables, casts that change alignment reqs +CFLAGS += -Wno-undef -Wno-shadow -Wno-cast-align CFLAGS += -mthumb -mabi=aapcs-linux diff --git a/ports/stm/boards/STM32F767ZITx_FLASH.ld b/ports/stm/boards/STM32F767ZITx_FLASH.ld new file mode 100644 index 0000000000000..78a794402d2d6 --- /dev/null +++ b/ports/stm/boards/STM32F767ZITx_FLASH.ld @@ -0,0 +1,189 @@ +/* +****************************************************************************** +** + +** File : LinkerScript.ld +** +** Author : Auto-generated by System Workbench for STM32 +** +** Abstract : Linker script for STM32F767ZITx series +** 2048Kbytes FLASH and 512Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed “as is,” without any warranty +** of any kind. +** +***************************************************************************** +** @attention +** +**

© COPYRIGHT(c) 2019 STMicroelectronics

+** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** 1. Redistributions of source code must retain the above copyright notice, +** this list of conditions and the following disclaimer. +** 2. Redistributions in binary form must reproduce the above copyright notice, +** this list of conditions and the following disclaimer in the documentation +** and/or other materials provided with the distribution. +** 3. Neither the name of STMicroelectronics nor the names of its contributors +** may be used to endorse or promote products derived from this software +** without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20080000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 512K +FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 2048K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/ports/stm/boards/STM32F767_fs.ld b/ports/stm/boards/STM32F767_fs.ld new file mode 100644 index 0000000000000..f0fb2d323d702 --- /dev/null +++ b/ports/stm/boards/STM32F767_fs.ld @@ -0,0 +1,107 @@ +/* + GNU linker script for STM32F405 via Micropython +*/ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 2048K /* entire flash */ + FLASH_ISR (rx) : ORIGIN = 0x08000000, LENGTH = 32K /* sector 0 */ + FLASH_FS (rx) : ORIGIN = 0x08008000, LENGTH = 96K /* sectors 1,2,3 are 32K */ + FLASH_TEXT (rx) : ORIGIN = 0x08010000, LENGTH = 1920K /* sector 4 is 128K, sectors 5,6,7 are 256K */ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 512K +} + +/* produce a link error if there is not this amount of RAM for these sections */ +_minimum_stack_size = 2K; +_minimum_heap_size = 16K; + +/* Define tho top end of the stack. The stack is full descending so begins just + above last byte of RAM. Note that EABI requires the stack to be 8-byte + aligned for a call. */ +_estack = ORIGIN(RAM) + LENGTH(RAM); + +/* RAM extents for the garbage collector */ +_ram_start = ORIGIN(RAM); +_ram_end = ORIGIN(RAM) + LENGTH(RAM); + +ENTRY(Reset_Handler) + +/* define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + + /* This first flash block is 16K annd the isr vectors only take up + about 400 bytes. Micropython pads this with files, but this didn't + work with the size of Circuitpython's ff object. */ + + . = ALIGN(4); + } >FLASH_ISR + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text*) /* .text* sections (code) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + /* *(.glue_7) */ /* glue arm to thumb code */ + /* *(.glue_7t) */ /* glue thumb to arm code */ + + . = ALIGN(4); + _etext = .; /* define a global symbol at end of code */ + } >FLASH_TEXT + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* This is the initialized data section + The program executes knowing that the data is in the RAM + but the loader puts the initial values in the FLASH (inidata). + It is one task of the startup to copy the initial values from FLASH to RAM. */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */ + } >RAM AT> FLASH_TEXT + + /* Uninitialized data section */ + .bss : + { + . = ALIGN(4); + _sbss = .; /* define a global symbol at bss start; used by startup code */ + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end; used by startup code and GC */ + } >RAM + + /* this is to define the start of the heap, and make sure we have a minimum size */ + .heap : + { + . = ALIGN(4); + . = . + _minimum_heap_size; + . = ALIGN(4); + } >RAM + + /* this just checks there is enough RAM for the stack */ + .stack : + { + . = ALIGN(4); + . = . + _minimum_stack_size; + . = ALIGN(4); + } >RAM + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/ports/stm/boards/nucleo_f767zi/board.c b/ports/stm/boards/nucleo_f767zi/board.c new file mode 100644 index 0000000000000..4421970eefe4d --- /dev/null +++ b/ports/stm/boards/nucleo_f767zi/board.c @@ -0,0 +1,38 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "boards/board.h" + +void board_init(void) { +} + +bool board_requests_safe_mode(void) { + return false; +} + +void reset_board(void) { + +} diff --git a/ports/stm/boards/nucleo_f767zi/mpconfigboard.h b/ports/stm/boards/nucleo_f767zi/mpconfigboard.h new file mode 100644 index 0000000000000..b481a2835b9a5 --- /dev/null +++ b/ports/stm/boards/nucleo_f767zi/mpconfigboard.h @@ -0,0 +1,35 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +//Micropython setup + +#define MICROPY_HW_BOARD_NAME "NUCLEO STM32F767" +#define MICROPY_HW_MCU_NAME "STM32F767" + +#define FLASH_SIZE (0x200000) +#define FLASH_PAGE_SIZE (0x4000) + +#define BOARD_OSC_DIV (8) diff --git a/ports/stm/boards/nucleo_f767zi/mpconfigboard.mk b/ports/stm/boards/nucleo_f767zi/mpconfigboard.mk new file mode 100644 index 0000000000000..11c2215196d5d --- /dev/null +++ b/ports/stm/boards/nucleo_f767zi/mpconfigboard.mk @@ -0,0 +1,14 @@ +USB_VID = 0x239A #REPLACE +USB_PID = 0x808A #REPLACE +USB_PRODUCT = "Nucleo F767ZI - CPy" +USB_MANUFACTURER = "STMicroelectronics" +USB_DEVICES = "CDC,MSC" + +INTERNAL_FLASH_FILESYSTEM = 1 + +MCU_SERIES = F7 +MCU_VARIANT = STM32F767xx +MCU_PACKAGE = LQFP144 + +LD_FILE = boards/STM32F767_fs.ld + diff --git a/ports/stm/boards/nucleo_f767zi/pins.c b/ports/stm/boards/nucleo_f767zi/pins.c new file mode 100644 index 0000000000000..9ecc38f01f2ad --- /dev/null +++ b/ports/stm/boards/nucleo_f767zi/pins.c @@ -0,0 +1,142 @@ +#include "shared-bindings/board/__init__.h" + +STATIC const mp_rom_map_elem_t board_module_globals_table[] = { +{ MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_PA03) }, +{ MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_PC00) }, +{ MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_PC03) }, +{ MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_PF03) }, +{ MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_PF05) }, +{ MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_PF10) }, +{ MP_ROM_QSTR(MP_QSTR_A6), MP_ROM_PTR(&pin_PB01) }, +{ MP_ROM_QSTR(MP_QSTR_A7), MP_ROM_PTR(&pin_PC02) }, +{ MP_ROM_QSTR(MP_QSTR_A8), MP_ROM_PTR(&pin_PF04) }, +{ MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_PG09) }, +{ MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_PG14) }, +{ MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_PF15) }, +{ MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_PE13) }, +{ MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_PF14) }, +{ MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_PE11) }, +{ MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_PE09) }, +{ MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_PF13) }, +{ MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_PF12) }, +{ MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_PD15) }, +{ MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PD14) }, +{ MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PA07) }, +{ MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PA06) }, +{ MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA05) }, +{ MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_PB09) }, +{ MP_ROM_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_PB08) }, +{ MP_ROM_QSTR(MP_QSTR_D16), MP_ROM_PTR(&pin_PC06) }, +{ MP_ROM_QSTR(MP_QSTR_D17), MP_ROM_PTR(&pin_PB15) }, +{ MP_ROM_QSTR(MP_QSTR_D18), MP_ROM_PTR(&pin_PB13) }, +{ MP_ROM_QSTR(MP_QSTR_D19), MP_ROM_PTR(&pin_PB12) }, +{ MP_ROM_QSTR(MP_QSTR_D20), MP_ROM_PTR(&pin_PA15) }, +{ MP_ROM_QSTR(MP_QSTR_D21), MP_ROM_PTR(&pin_PC07) }, +{ MP_ROM_QSTR(MP_QSTR_D22), MP_ROM_PTR(&pin_PB05) }, +{ MP_ROM_QSTR(MP_QSTR_D23), MP_ROM_PTR(&pin_PB03) }, +{ MP_ROM_QSTR(MP_QSTR_D24), MP_ROM_PTR(&pin_PA04) }, +{ MP_ROM_QSTR(MP_QSTR_D25), MP_ROM_PTR(&pin_PB04) }, +{ MP_ROM_QSTR(MP_QSTR_D26), MP_ROM_PTR(&pin_PB06) }, +{ MP_ROM_QSTR(MP_QSTR_D27), MP_ROM_PTR(&pin_PB02) }, +{ MP_ROM_QSTR(MP_QSTR_D28), MP_ROM_PTR(&pin_PD13) }, +{ MP_ROM_QSTR(MP_QSTR_D29), MP_ROM_PTR(&pin_PD12) }, +{ MP_ROM_QSTR(MP_QSTR_D30), MP_ROM_PTR(&pin_PD11) }, +{ MP_ROM_QSTR(MP_QSTR_D31), MP_ROM_PTR(&pin_PE02) }, +{ MP_ROM_QSTR(MP_QSTR_D32), MP_ROM_PTR(&pin_PA00) }, +{ MP_ROM_QSTR(MP_QSTR_D33), MP_ROM_PTR(&pin_PB00) }, +{ MP_ROM_QSTR(MP_QSTR_D34), MP_ROM_PTR(&pin_PE00) }, +{ MP_ROM_QSTR(MP_QSTR_D35), MP_ROM_PTR(&pin_PB11) }, +{ MP_ROM_QSTR(MP_QSTR_D36), MP_ROM_PTR(&pin_PB10) }, +{ MP_ROM_QSTR(MP_QSTR_D37), MP_ROM_PTR(&pin_PE15) }, +{ MP_ROM_QSTR(MP_QSTR_D38), MP_ROM_PTR(&pin_PE14) }, +{ MP_ROM_QSTR(MP_QSTR_D39), MP_ROM_PTR(&pin_PE12) }, +{ MP_ROM_QSTR(MP_QSTR_D40), MP_ROM_PTR(&pin_PE10) }, +{ MP_ROM_QSTR(MP_QSTR_D41), MP_ROM_PTR(&pin_PE07) }, +{ MP_ROM_QSTR(MP_QSTR_D42), MP_ROM_PTR(&pin_PE08) }, +{ MP_ROM_QSTR(MP_QSTR_D43), MP_ROM_PTR(&pin_PC08) }, +{ MP_ROM_QSTR(MP_QSTR_D44), MP_ROM_PTR(&pin_PC09) }, +{ MP_ROM_QSTR(MP_QSTR_D45), MP_ROM_PTR(&pin_PC10) }, +{ MP_ROM_QSTR(MP_QSTR_D46), MP_ROM_PTR(&pin_PC11) }, +{ MP_ROM_QSTR(MP_QSTR_D47), MP_ROM_PTR(&pin_PC12) }, +{ MP_ROM_QSTR(MP_QSTR_D48), MP_ROM_PTR(&pin_PD02) }, +{ MP_ROM_QSTR(MP_QSTR_D49), MP_ROM_PTR(&pin_PG02) }, +{ MP_ROM_QSTR(MP_QSTR_D50), MP_ROM_PTR(&pin_PG03) }, +{ MP_ROM_QSTR(MP_QSTR_D51), MP_ROM_PTR(&pin_PD07) }, +{ MP_ROM_QSTR(MP_QSTR_D52), MP_ROM_PTR(&pin_PD06) }, +{ MP_ROM_QSTR(MP_QSTR_D53), MP_ROM_PTR(&pin_PD05) }, +{ MP_ROM_QSTR(MP_QSTR_D54), MP_ROM_PTR(&pin_PD04) }, +{ MP_ROM_QSTR(MP_QSTR_D55), MP_ROM_PTR(&pin_PD03) }, +{ MP_ROM_QSTR(MP_QSTR_D56), MP_ROM_PTR(&pin_PE02) }, +{ MP_ROM_QSTR(MP_QSTR_D57), MP_ROM_PTR(&pin_PE04) }, +{ MP_ROM_QSTR(MP_QSTR_D58), MP_ROM_PTR(&pin_PE05) }, +{ MP_ROM_QSTR(MP_QSTR_D59), MP_ROM_PTR(&pin_PE06) }, +{ MP_ROM_QSTR(MP_QSTR_D60), MP_ROM_PTR(&pin_PE03) }, +{ MP_ROM_QSTR(MP_QSTR_D61), MP_ROM_PTR(&pin_PF08) }, +{ MP_ROM_QSTR(MP_QSTR_D62), MP_ROM_PTR(&pin_PF07) }, +{ MP_ROM_QSTR(MP_QSTR_D63), MP_ROM_PTR(&pin_PF09) }, +{ MP_ROM_QSTR(MP_QSTR_D64), MP_ROM_PTR(&pin_PG01) }, +{ MP_ROM_QSTR(MP_QSTR_D65), MP_ROM_PTR(&pin_PG00) }, +{ MP_ROM_QSTR(MP_QSTR_D66), MP_ROM_PTR(&pin_PD01) }, +{ MP_ROM_QSTR(MP_QSTR_D67), MP_ROM_PTR(&pin_PD00) }, +{ MP_ROM_QSTR(MP_QSTR_D68), MP_ROM_PTR(&pin_PF00) }, +{ MP_ROM_QSTR(MP_QSTR_D69), MP_ROM_PTR(&pin_PF01) }, +{ MP_ROM_QSTR(MP_QSTR_D70), MP_ROM_PTR(&pin_PF02) }, +{ MP_ROM_QSTR(MP_QSTR_D71), MP_ROM_PTR(&pin_PA07) }, +{ MP_ROM_QSTR(MP_QSTR_DAC1), MP_ROM_PTR(&pin_PA04) }, +{ MP_ROM_QSTR(MP_QSTR_DAC2), MP_ROM_PTR(&pin_PA05) }, +{ MP_ROM_QSTR(MP_QSTR_LED1), MP_ROM_PTR(&pin_PB00) }, +{ MP_ROM_QSTR(MP_QSTR_LED2), MP_ROM_PTR(&pin_PB07) }, +{ MP_ROM_QSTR(MP_QSTR_LED3), MP_ROM_PTR(&pin_PB14) }, +{ MP_ROM_QSTR(MP_QSTR_SW), MP_ROM_PTR(&pin_PC13) }, +{ MP_ROM_QSTR(MP_QSTR_SD_D0), MP_ROM_PTR(&pin_PC08) }, +{ MP_ROM_QSTR(MP_QSTR_SD_D1), MP_ROM_PTR(&pin_PC09) }, +{ MP_ROM_QSTR(MP_QSTR_SD_D2), MP_ROM_PTR(&pin_PC10) }, +{ MP_ROM_QSTR(MP_QSTR_SD_D3), MP_ROM_PTR(&pin_PC11) }, +{ MP_ROM_QSTR(MP_QSTR_SD_CMD), MP_ROM_PTR(&pin_PD02) }, +{ MP_ROM_QSTR(MP_QSTR_SD_CK), MP_ROM_PTR(&pin_PC12) }, +{ MP_ROM_QSTR(MP_QSTR_SD_SW), MP_ROM_PTR(&pin_PG02) }, +{ MP_ROM_QSTR(MP_QSTR_OTG_FS_POWER), MP_ROM_PTR(&pin_PG06) }, +{ MP_ROM_QSTR(MP_QSTR_OTG_FS_OVER_CURRENT), MP_ROM_PTR(&pin_PG07) }, +{ MP_ROM_QSTR(MP_QSTR_USB_VBUS), MP_ROM_PTR(&pin_PA09) }, +{ MP_ROM_QSTR(MP_QSTR_USB_ID), MP_ROM_PTR(&pin_PA10) }, +{ MP_ROM_QSTR(MP_QSTR_USB_DM), MP_ROM_PTR(&pin_PA11) }, +{ MP_ROM_QSTR(MP_QSTR_USB_DP), MP_ROM_PTR(&pin_PA12) }, +{ MP_ROM_QSTR(MP_QSTR_UART2_TX), MP_ROM_PTR(&pin_PD05) }, +{ MP_ROM_QSTR(MP_QSTR_UART2_RX), MP_ROM_PTR(&pin_PD06) }, +{ MP_ROM_QSTR(MP_QSTR_UART2_RTS), MP_ROM_PTR(&pin_PD04) }, +{ MP_ROM_QSTR(MP_QSTR_UART2_CTS), MP_ROM_PTR(&pin_PD03) }, +{ MP_ROM_QSTR(MP_QSTR_VCP_TX), MP_ROM_PTR(&pin_PD08) }, +{ MP_ROM_QSTR(MP_QSTR_VCP_RX), MP_ROM_PTR(&pin_PD09) }, +{ MP_ROM_QSTR(MP_QSTR_UART3_TX), MP_ROM_PTR(&pin_PD08) }, +{ MP_ROM_QSTR(MP_QSTR_UART3_RX), MP_ROM_PTR(&pin_PD09) }, +{ MP_ROM_QSTR(MP_QSTR_UART5_TX), MP_ROM_PTR(&pin_PB06) }, +{ MP_ROM_QSTR(MP_QSTR_UART5_RX), MP_ROM_PTR(&pin_PB12) }, +{ MP_ROM_QSTR(MP_QSTR_UART6_TX), MP_ROM_PTR(&pin_PC06) }, +{ MP_ROM_QSTR(MP_QSTR_UART6_RX), MP_ROM_PTR(&pin_PC07) }, +{ MP_ROM_QSTR(MP_QSTR_UART7_TX), MP_ROM_PTR(&pin_PF07) }, +{ MP_ROM_QSTR(MP_QSTR_UART7_RX), MP_ROM_PTR(&pin_PF06) }, +{ MP_ROM_QSTR(MP_QSTR_UART8_TX), MP_ROM_PTR(&pin_PE01) }, +{ MP_ROM_QSTR(MP_QSTR_UART8_RX), MP_ROM_PTR(&pin_PE00) }, +{ MP_ROM_QSTR(MP_QSTR_SPI3_NSS), MP_ROM_PTR(&pin_PA04) }, +{ MP_ROM_QSTR(MP_QSTR_SPI3_SCK), MP_ROM_PTR(&pin_PB03) }, +{ MP_ROM_QSTR(MP_QSTR_SPI3_MISO), MP_ROM_PTR(&pin_PB04) }, +{ MP_ROM_QSTR(MP_QSTR_SPI3_MOSI), MP_ROM_PTR(&pin_PB05) }, +{ MP_ROM_QSTR(MP_QSTR_I2C1_SDA), MP_ROM_PTR(&pin_PB09) }, +{ MP_ROM_QSTR(MP_QSTR_I2C1_SCL), MP_ROM_PTR(&pin_PB08) }, +{ MP_ROM_QSTR(MP_QSTR_I2C2_SDA), MP_ROM_PTR(&pin_PF00) }, +{ MP_ROM_QSTR(MP_QSTR_I2C2_SCL), MP_ROM_PTR(&pin_PF01) }, +{ MP_ROM_QSTR(MP_QSTR_I2C4_SCL), MP_ROM_PTR(&pin_PF14) }, +{ MP_ROM_QSTR(MP_QSTR_I2C4_SDA), MP_ROM_PTR(&pin_PF15) }, +{ MP_ROM_QSTR(MP_QSTR_ETH_MDC), MP_ROM_PTR(&pin_PC01) }, +{ MP_ROM_QSTR(MP_QSTR_ETH_MDIO), MP_ROM_PTR(&pin_PA02) }, +{ MP_ROM_QSTR(MP_QSTR_ETH_RMII_REF_CLK), MP_ROM_PTR(&pin_PA01) }, +{ MP_ROM_QSTR(MP_QSTR_ETH_RMII_CRS_DV), MP_ROM_PTR(&pin_PA07) }, +{ MP_ROM_QSTR(MP_QSTR_ETH_RMII_RXD0), MP_ROM_PTR(&pin_PC04) }, +{ MP_ROM_QSTR(MP_QSTR_ETH_RMII_RXD1), MP_ROM_PTR(&pin_PC05) }, +{ MP_ROM_QSTR(MP_QSTR_ETH_RMII_TX_EN), MP_ROM_PTR(&pin_PG11) }, +{ MP_ROM_QSTR(MP_QSTR_ETH_RMII_TXD0), MP_ROM_PTR(&pin_PG13) }, +{ MP_ROM_QSTR(MP_QSTR_ETH_RMII_TXD1), MP_ROM_PTR(&pin_PB13) }, +{ MP_ROM_QSTR(MP_QSTR_SWDIO), MP_ROM_PTR(&pin_PA13) }, +{ MP_ROM_QSTR(MP_QSTR_SWDCLK), MP_ROM_PTR(&pin_PA14) } +}; +MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table); diff --git a/ports/stm/boards/nucleo_f767zi/stm32f7xx_hal_conf.h b/ports/stm/boards/nucleo_f767zi/stm32f7xx_hal_conf.h new file mode 100644 index 0000000000000..84699bd784db7 --- /dev/null +++ b/ports/stm/boards/nucleo_f767zi/stm32f7xx_hal_conf.h @@ -0,0 +1,445 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_conf_template.h + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32f7xx_hal_conf.h. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_CONF_H +#define __STM32F7xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED + + #define HAL_ADC_MODULE_ENABLED +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_CAN_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +#define HAL_DAC_MODULE_ENABLED +/* #define HAL_DCMI_MODULE_ENABLED */ +/* #define HAL_DMA2D_MODULE_ENABLED */ +#define HAL_ETH_MODULE_ENABLED +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_SRAM_MODULE_ENABLED */ +/* #define HAL_SDRAM_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +/* #define HAL_LTDC_MODULE_ENABLED */ +/* #define HAL_QSPI_MODULE_ENABLED */ +/* #define HAL_RNG_MODULE_ENABLED */ +/* #define HAL_RTC_MODULE_ENABLED */ +/* #define HAL_SAI_MODULE_ENABLED */ +/* #define HAL_SD_MODULE_ENABLED */ +/* #define HAL_MMC_MODULE_ENABLED */ +/* #define HAL_SPDIFRX_MODULE_ENABLED */ +#define HAL_SPI_MODULE_ENABLED +#define HAL_TIM_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +#define HAL_PCD_MODULE_ENABLED +/* #define HAL_HCD_MODULE_ENABLED */ +/* #define HAL_DFSDM_MODULE_ENABLED */ +/* #define HAL_DSI_MODULE_ENABLED */ +/* #define HAL_JPEG_MODULE_ENABLED */ +/* #define HAL_MDIOS_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +/* #define HAL_EXTI_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 0U +#define ART_ACCLERATOR_ENABLE 0U /* To enable instruction cache and prefetch */ + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Ethernet peripheral configuration ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 2U +#define MAC_ADDR1 0U +#define MAC_ADDR2 0U +#define MAC_ADDR3 0U +#define MAC_ADDR4 0U +#define MAC_ADDR5 0U + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ + +/* LAN8742A_PHY_ADDRESS Address*/ +#define LAN8742A_PHY_ADDRESS 0 +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY ((uint32_t)0x000000FFU) +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU) + +#define PHY_READ_TO ((uint32_t)0x0000FFFFU) +#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU) + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x00U) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x01U) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ +#define PHY_SR ((uint16_t)0x1FU) /*!< PHY status register Offset */ + +#define PHY_SPEED_STATUS ((uint16_t)0x0004U) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0010U) /*!< PHY Duplex mask */ + +#define PHY_ISFR ((uint16_t)0x001DU) /*!< PHY Interrupt Source Flag register Offset */ +#define PHY_ISFR_INT4 ((uint16_t)0x000BU) /*!< PHY Link down inturrupt */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f7xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32f7xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f7xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f7xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f7xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f7xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f7xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32f7xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f7xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32f7xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32f7xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f7xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32f7xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32f7xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f7xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32f7xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32f7xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32f7xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32f7xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32f7xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f7xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f7xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f7xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32f7xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32f7xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f7xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32f7xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32f7xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f7xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32f7xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32f7xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32f7xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32f7xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f7xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f7xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f7xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f7xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f7xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f7xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f7xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f7xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32f7xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32f7xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32f7xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_JPEG_MODULE_ENABLED + #include "stm32f7xx_hal_jpeg.h" +#endif /* HAL_JPEG_MODULE_ENABLED */ + +#ifdef HAL_MDIOS_MODULE_ENABLED + #include "stm32f7xx_hal_mdios.h" +#endif /* HAL_MDIOS_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32f7xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_CONF_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/ports/stm/boards/startup_stm32f767xx.s b/ports/stm/boards/startup_stm32f767xx.s new file mode 100644 index 0000000000000..84309d4dadc64 --- /dev/null +++ b/ports/stm/boards/startup_stm32f767xx.s @@ -0,0 +1,618 @@ +/** + ****************************************************************************** + * @file startup_stm32f767xx.s + * @author MCD Application Team + * @brief STM32F767xx Devices vector table for GCC based toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M7 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m7 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system initialization function.*/ + bl SystemInit +/* Call static constructors */ +/* bl __libc_init_array */ +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M7. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FMC_IRQHandler /* FMC */ + .word SDMMC1_IRQHandler /* SDMMC1 */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word 0 /* Reserved */ + .word RNG_IRQHandler /* RNG */ + .word FPU_IRQHandler /* FPU */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word SPI6_IRQHandler /* SPI6 */ + .word SAI1_IRQHandler /* SAI1 */ + .word LTDC_IRQHandler /* LTDC */ + .word LTDC_ER_IRQHandler /* LTDC error */ + .word DMA2D_IRQHandler /* DMA2D */ + .word SAI2_IRQHandler /* SAI2 */ + .word QUADSPI_IRQHandler /* QUADSPI */ + .word LPTIM1_IRQHandler /* LPTIM1 */ + .word CEC_IRQHandler /* HDMI_CEC */ + .word I2C4_EV_IRQHandler /* I2C4 Event */ + .word I2C4_ER_IRQHandler /* I2C4 Error */ + .word SPDIF_RX_IRQHandler /* SPDIF_RX */ + .word 0 /* Reserved */ + .word DFSDM1_FLT0_IRQHandler /* DFSDM1 Filter 0 global Interrupt */ + .word DFSDM1_FLT1_IRQHandler /* DFSDM1 Filter 1 global Interrupt */ + .word DFSDM1_FLT2_IRQHandler /* DFSDM1 Filter 2 global Interrupt */ + .word DFSDM1_FLT3_IRQHandler /* DFSDM1 Filter 3 global Interrupt */ + .word SDMMC2_IRQHandler /* SDMMC2 */ + .word CAN3_TX_IRQHandler /* CAN3 TX */ + .word CAN3_RX0_IRQHandler /* CAN3 RX0 */ + .word CAN3_RX1_IRQHandler /* CAN3 RX1 */ + .word CAN3_SCE_IRQHandler /* CAN3 SCE */ + .word JPEG_IRQHandler /* JPEG */ + .word MDIOS_IRQHandler /* MDIOS */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak LTDC_IRQHandler + .thumb_set LTDC_IRQHandler,Default_Handler + + .weak LTDC_ER_IRQHandler + .thumb_set LTDC_ER_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set DMA2D_IRQHandler,Default_Handler + + .weak SAI2_IRQHandler + .thumb_set SAI2_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak I2C4_EV_IRQHandler + .thumb_set I2C4_EV_IRQHandler,Default_Handler + + .weak I2C4_ER_IRQHandler + .thumb_set I2C4_ER_IRQHandler,Default_Handler + + .weak SPDIF_RX_IRQHandler + .thumb_set SPDIF_RX_IRQHandler,Default_Handler + + .weak DFSDM1_FLT0_IRQHandler + .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler + + .weak DFSDM1_FLT1_IRQHandler + .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler + + .weak DFSDM1_FLT2_IRQHandler + .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler + + .weak DFSDM1_FLT3_IRQHandler + .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler + + .weak SDMMC2_IRQHandler + .thumb_set SDMMC2_IRQHandler,Default_Handler + + .weak CAN3_TX_IRQHandler + .thumb_set CAN3_TX_IRQHandler,Default_Handler + + .weak CAN3_RX0_IRQHandler + .thumb_set CAN3_RX0_IRQHandler,Default_Handler + + .weak CAN3_RX1_IRQHandler + .thumb_set CAN3_RX1_IRQHandler,Default_Handler + + .weak CAN3_SCE_IRQHandler + .thumb_set CAN3_SCE_IRQHandler,Default_Handler + + .weak JPEG_IRQHandler + .thumb_set JPEG_IRQHandler,Default_Handler + + .weak MDIOS_IRQHandler + .thumb_set MDIOS_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/ports/stm/common-hal/digitalio/DigitalInOut.c b/ports/stm/common-hal/digitalio/DigitalInOut.c index 40e13ca3ba538..82a8a72e4fa58 100644 --- a/ports/stm/common-hal/digitalio/DigitalInOut.c +++ b/ports/stm/common-hal/digitalio/DigitalInOut.c @@ -32,6 +32,8 @@ //TODO: rework this module to use HAL only #ifdef STM32H743xx #include "stm32h7xx_ll_gpio.h" +#elif STM32F767xx +#include "stm32f7xx_ll_gpio.h" #else #include "stm32f4xx_ll_gpio.h" #endif diff --git a/ports/stm/mpconfigport.mk b/ports/stm/mpconfigport.mk index 0342fc7639b4f..e1e983e39fa02 100644 --- a/ports/stm/mpconfigport.mk +++ b/ports/stm/mpconfigport.mk @@ -88,3 +88,19 @@ ifeq ($(MCU_SERIES), H7) CIRCUITPY_NEOPIXEL_WRITE = 0 CIRCUITPY_DISPLAYIO = 0 endif + +ifeq ($(MCU_SERIES), F7) + CIRCUITPY_BOARD = 1 + CIRCUITPY_DIGITALIO = 1 + CIRCUITPY_ANALOGIO = 0 + CIRCUITPY_MICROCONTROLLER = 1 + CIRCUITPY_BUSIO = 0 + CIRCUITPY_PULSEIO = 0 + CIRCUITPY_OS = 0 + CIRCUITPY_STORAGE = 0 + CIRCUITPY_RANDOM = 0 + CIRCUITPY_USB_HID = 0 + CIRCUITPY_USB_MIDI = 0 + CIRCUITPY_NEOPIXEL_WRITE = 0 + CIRCUITPY_DISPLAYIO = 0 +endif diff --git a/ports/stm/peripherals/periph.h b/ports/stm/peripherals/periph.h index 394ab25b119eb..209d35ee95cbf 100644 --- a/ports/stm/peripherals/periph.h +++ b/ports/stm/peripherals/periph.h @@ -105,6 +105,15 @@ typedef struct { #include "stm32f4/stm32f407xx/periph.h" #endif +// F7 Series + +#ifdef STM32F767xx +#define HAS_DAC 0 +#define HAS_TRNG 0 +#define HAS_BASIC_TIM 0 +#include "stm32f7/stm32f767xx/periph.h" +#endif + // H7 Series // Single Core diff --git a/ports/stm/peripherals/pins.h b/ports/stm/peripherals/pins.h index c6f1ec322bbe9..628e09695aa5c 100644 --- a/ports/stm/peripherals/pins.h +++ b/ports/stm/peripherals/pins.h @@ -92,6 +92,11 @@ extern const mp_obj_type_t mcu_pin_type; #include "stm32f4/stm32f407xx/pins.h" #endif +// F7 Series +#ifdef STM32F767xx +#include "stm32f7/stm32f767xx/pins.h" +#endif + // H7 Series #ifdef STM32H743xx #include "stm32h7/stm32h743xx/pins.h" diff --git a/ports/stm/peripherals/stm32f7/stm32f767xx/clocks.c b/ports/stm/peripherals/stm32f7/stm32f767xx/clocks.c new file mode 100644 index 0000000000000..15f1188706d9e --- /dev/null +++ b/ports/stm/peripherals/stm32f7/stm32f767xx/clocks.c @@ -0,0 +1,66 @@ + +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/mpconfig.h" + +void stm32_peripherals_clocks_init(void) { + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + + /* Enable Power Control clock */ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* The voltage scaling allows optimizing the power consumption when the device is + clocked below the maximum system frequency, to update the voltage scaling value + regarding system frequency refer to product datasheet. */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /* Enable HSE Oscillator and activate PLL with HSE as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000; + RCC_OscInitStruct.PLL.PLLN = 432; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 9; + RCC_OscInitStruct.PLL.PLLR = 7; + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + /* Activate the OverDrive to reach the 216 MHz Frequency */ + HAL_PWREx_EnableOverDrive(); + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7); + +} diff --git a/ports/stm/peripherals/stm32f7/stm32f767xx/gpio.c b/ports/stm/peripherals/stm32f7/stm32f767xx/gpio.c new file mode 100644 index 0000000000000..d51ff53c1f0df --- /dev/null +++ b/ports/stm/peripherals/stm32f7/stm32f767xx/gpio.c @@ -0,0 +1,48 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "gpio.h" +#include "common-hal/microcontroller/Pin.h" + +void stm32_peripherals_gpio_init(void) { + //Enable all GPIO for now + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + + //Never reset pins + never_reset_pin_number(2,14); //PC14 OSC32_IN + never_reset_pin_number(2,15); //PC15 OSC32_OUT + never_reset_pin_number(0,13); //PA13 SWDIO + never_reset_pin_number(0,14); //PA14 SWCLK +} + + diff --git a/ports/stm/peripherals/stm32f7/stm32f767xx/periph.c b/ports/stm/peripherals/stm32f7/stm32f767xx/periph.c new file mode 100644 index 0000000000000..07d226db30f82 --- /dev/null +++ b/ports/stm/peripherals/stm32f7/stm32f767xx/periph.c @@ -0,0 +1,248 @@ + /* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/obj.h" +#include "py/mphal.h" +#include "peripherals/pins.h" +#include "peripherals/periph.h" + +// I2C + +I2C_TypeDef * mcu_i2c_banks[4] = {I2C1, I2C2, I2C3, I2C4}; + +const mcu_periph_obj_t mcu_i2c_sda_list[12] = { + PERIPH(1, 4, &pin_PB07), + PERIPH(4, 11, &pin_PB07), + PERIPH(4, 1, &pin_PB09), + PERIPH(1, 4, &pin_PB09), + PERIPH(2, 4, &pin_PB11), + PERIPH(3, 4, &pin_PC09), + PERIPH(4, 4, &pin_PD13), + PERIPH(2, 4, &pin_PF00), + PERIPH(4, 4, &pin_PF15), + PERIPH(2, 4, &pin_PH05), + PERIPH(3, 4, &pin_PH08), + PERIPH(4, 4, &pin_PH12), +}; +const mcu_periph_obj_t mcu_i2c_scl_list[12] = { + PERIPH(3, 4, &pin_PA08), + PERIPH(1, 4, &pin_PB06), + PERIPH(4, 11, &pin_PB06), + PERIPH(4, 1, &pin_PB08), + PERIPH(1, 4, &pin_PB08), + PERIPH(2, 4, &pin_PB10), + PERIPH(4, 4, &pin_PD12), + PERIPH(2, 4, &pin_PF01), + PERIPH(4, 4, &pin_PF14), + PERIPH(2, 4, &pin_PH04), + PERIPH(3, 4, &pin_PH07), + PERIPH(4, 4, &pin_PH11), +}; + +//SPI + +SPI_TypeDef * mcu_spi_banks[6] = {SPI1, SPI2, SPI3, SPI4, SPI5, SPI6}; + +const mcu_periph_obj_t mcu_spi_sck_list[18] = { + PERIPH(1, 5, &pin_PA05), + PERIPH(6, 8, &pin_PA05), + PERIPH(2, 5, &pin_PA09), + PERIPH(2, 5, &pin_PA12), + PERIPH(1, 5, &pin_PB03), + PERIPH(3, 6, &pin_PB03), + PERIPH(6, 8, &pin_PB03), + PERIPH(2, 5, &pin_PB10), + PERIPH(2, 5, &pin_PB13), + PERIPH(3, 6, &pin_PC10), + PERIPH(2, 5, &pin_PD03), + PERIPH(4, 5, &pin_PE02), + PERIPH(4, 5, &pin_PE12), + PERIPH(5, 5, &pin_PF07), + PERIPH(1, 5, &pin_PG11), + PERIPH(6, 5, &pin_PG13), + PERIPH(5, 5, &pin_PH06), + PERIPH(2, 5, &pin_PI01), +}; +const mcu_periph_obj_t mcu_spi_mosi_list[18] = { + PERIPH(1, 5, &pin_PA07), + PERIPH(6, 8, &pin_PA07), + PERIPH(3, 7, &pin_PB02), + PERIPH(1, 5, &pin_PB05), + PERIPH(3, 6, &pin_PB05), + PERIPH(6, 8, &pin_PB05), + PERIPH(2, 5, &pin_PB15), + PERIPH(2, 5, &pin_PC01), + PERIPH(2, 5, &pin_PC03), + PERIPH(3, 6, &pin_PC12), + PERIPH(3, 5, &pin_PD06), + PERIPH(1, 5, &pin_PD07), + PERIPH(4, 5, &pin_PE06), + PERIPH(4, 5, &pin_PE14), + PERIPH(5, 5, &pin_PF09), + PERIPH(5, 5, &pin_PF11), + PERIPH(6, 5, &pin_PG14), + PERIPH(2, 5, &pin_PI03), +}; +const mcu_periph_obj_t mcu_spi_miso_list[15] = { + PERIPH(1, 5, &pin_PA06), + PERIPH(6, 8, &pin_PA06), + PERIPH(1, 5, &pin_PB04), + PERIPH(3, 6, &pin_PB04), + PERIPH(6, 8, &pin_PB04), + PERIPH(2, 5, &pin_PB14), + PERIPH(2, 5, &pin_PC02), + PERIPH(3, 6, &pin_PC11), + PERIPH(4, 5, &pin_PE05), + PERIPH(4, 5, &pin_PE13), + PERIPH(5, 5, &pin_PF08), + PERIPH(1, 5, &pin_PG09), + PERIPH(6, 5, &pin_PG12), + PERIPH(5, 5, &pin_PH07), + PERIPH(2, 5, &pin_PI02), +}; + +//UART + +USART_TypeDef * mcu_uart_banks[MAX_UART] = {USART1, USART2, USART3, UART4, UART5, USART6, UART7, UART8}; +bool mcu_uart_has_usart[MAX_UART] = {true, true, true, true, true, true, true, true}; + +const mcu_periph_obj_t mcu_uart_tx_list[24] = { + PERIPH(4, 8, &pin_PA00), + PERIPH(2, 7, &pin_PA02), + PERIPH(1, 7, &pin_PA09), + PERIPH(4, 6, &pin_PA12), + PERIPH(7, 12, &pin_PA15), + PERIPH(7, 12, &pin_PB04), + PERIPH(5, 1, &pin_PB06), + PERIPH(1, 7, &pin_PB06), + PERIPH(5, 7, &pin_PB09), + PERIPH(3, 7, &pin_PB10), + PERIPH(5, 8, &pin_PB13), + PERIPH(1, 4, &pin_PB14), + PERIPH(6, 8, &pin_PC06), + PERIPH(3, 7, &pin_PC10), + PERIPH(4, 8, &pin_PC10), + PERIPH(5, 8, &pin_PC12), + PERIPH(4, 8, &pin_PD01), + PERIPH(2, 7, &pin_PD05), + PERIPH(3, 7, &pin_PD08), + PERIPH(8, 8, &pin_PE01), + PERIPH(7, 8, &pin_PE08), + PERIPH(7, 8, &pin_PF07), + PERIPH(6, 8, &pin_PG14), + PERIPH(4, 8, &pin_PH13), +}; +const mcu_periph_obj_t mcu_uart_rx_list[25] = { + PERIPH(4, 8, &pin_PA01), + PERIPH(2, 7, &pin_PA03), + PERIPH(7, 12, &pin_PA08), + PERIPH(1, 7, &pin_PA10), + PERIPH(4, 6, &pin_PA11), + PERIPH(7, 12, &pin_PB03), + PERIPH(5, 1, &pin_PB05), + PERIPH(1, 7, &pin_PB07), + PERIPH(5, 7, &pin_PB08), + PERIPH(3, 7, &pin_PB11), + PERIPH(5, 8, &pin_PB12), + PERIPH(1, 4, &pin_PB15), + PERIPH(6, 8, &pin_PC07), + PERIPH(3, 7, &pin_PC11), + PERIPH(4, 8, &pin_PC11), + PERIPH(4, 8, &pin_PD00), + PERIPH(5, 8, &pin_PD02), + PERIPH(2, 7, &pin_PD06), + PERIPH(3, 7, &pin_PD09), + PERIPH(8, 8, &pin_PE00), + PERIPH(7, 8, &pin_PE07), + PERIPH(7, 8, &pin_PF06), + PERIPH(6, 8, &pin_PG09), + PERIPH(4, 8, &pin_PH14), + PERIPH(4, 8, &pin_PI09), +}; + +//Timers +//TIM6 and TIM7 are basic timers that are only used by DAC, and don't have pins +//TODO: H7 has more timers than this, but are they tied to pins? +TIM_TypeDef * mcu_tim_banks[14] = {TIM1, TIM2, TIM3, TIM4, TIM5, NULL, NULL, TIM8, NULL, NULL, + NULL, TIM12, TIM13, TIM14}; + +const mcu_tim_pin_obj_t mcu_tim_pin_list[55] = { + TIM(2, 1, 1, &pin_PA00), + TIM(5, 2, 1, &pin_PA00), + TIM(2, 1, 2, &pin_PA01), + TIM(5, 2, 2, &pin_PA01), + TIM(2, 1, 3, &pin_PA02), + TIM(5, 2, 3, &pin_PA02), + TIM(9, 3, 1, &pin_PA02), + TIM(2, 1, 4, &pin_PA03), + TIM(5, 2, 4, &pin_PA03), + TIM(9, 3, 2, &pin_PA03), + TIM(2, 1, 1, &pin_PA05), + TIM(3, 2, 1, &pin_PA06), + TIM(3, 2, 2, &pin_PA07), + TIM(1, 1, 1, &pin_PA08), + TIM(1, 1, 2, &pin_PA09), + TIM(1, 1, 3, &pin_PA10), + TIM(1, 1, 4, &pin_PA11), + TIM(2, 1, 1, &pin_PA15), + TIM(3, 2, 3, &pin_PB00), + TIM(3, 2, 4, &pin_PB01), + TIM(2, 1, 2, &pin_PB03), + TIM(3, 2, 1, &pin_PB04), + TIM(3, 2, 2, &pin_PB05), + TIM(4, 2, 1, &pin_PB06), + TIM(4, 2, 2, &pin_PB07), + TIM(4, 2, 3, &pin_PB08), + TIM(4, 2, 4, &pin_PB09), + TIM(2, 1, 3, &pin_PB10), + TIM(2, 1, 4, &pin_PB11), + TIM(3, 2, 1, &pin_PC06), + TIM(8, 3, 1, &pin_PC06), + TIM(3, 2, 2, &pin_PC07), + TIM(8, 3, 2, &pin_PC07), + TIM(3, 2, 3, &pin_PC08), + TIM(8, 3, 3, &pin_PC08), + TIM(3, 2, 4, &pin_PC09), + TIM(8, 3, 4, &pin_PC09), + TIM(4, 2, 1, &pin_PD12), + TIM(4, 2, 2, &pin_PD13), + TIM(4, 2, 3, &pin_PD14), + TIM(4, 2, 4, &pin_PD15), + TIM(9, 3, 1, &pin_PE05), + TIM(9, 3, 2, &pin_PE06), + TIM(1, 1, 1, &pin_PE09), + TIM(1, 1, 2, &pin_PE11), + TIM(1, 1, 3, &pin_PE13), + TIM(1, 1, 4, &pin_PE14), + TIM(5, 2, 1, &pin_PH10), + TIM(5, 2, 2, &pin_PH11), + TIM(5, 2, 3, &pin_PH12), + TIM(5, 2, 4, &pin_PI00), + TIM(8, 3, 4, &pin_PI02), + TIM(8, 3, 1, &pin_PI05), + TIM(8, 3, 2, &pin_PI06), + TIM(8, 3, 3, &pin_PI07), +}; diff --git a/ports/stm/peripherals/stm32f7/stm32f767xx/periph.h b/ports/stm/peripherals/stm32f7/stm32f767xx/periph.h new file mode 100644 index 0000000000000..f1878ee2e674e --- /dev/null +++ b/ports/stm/peripherals/stm32f7/stm32f767xx/periph.h @@ -0,0 +1,55 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F767XX_PERIPH_H +#define MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F767XX_PERIPH_H + +//I2C +extern I2C_TypeDef * mcu_i2c_banks[4]; + +const mcu_periph_obj_t mcu_i2c_sda_list[12]; +const mcu_periph_obj_t mcu_i2c_scl_list[12]; + +//SPI +extern SPI_TypeDef * mcu_spi_banks[6]; + +const mcu_periph_obj_t mcu_spi_sck_list[18]; +const mcu_periph_obj_t mcu_spi_mosi_list[18]; +const mcu_periph_obj_t mcu_spi_miso_list[15]; + +//UART +extern USART_TypeDef * mcu_uart_banks[MAX_UART]; +extern bool mcu_uart_has_usart[MAX_UART]; + +const mcu_periph_obj_t mcu_uart_tx_list[24]; +const mcu_periph_obj_t mcu_uart_rx_list[25]; + +//Timers +#define TIM_BANK_ARRAY_LEN 14 +#define TIM_PIN_ARRAY_LEN 55 +TIM_TypeDef * mcu_tim_banks[TIM_BANK_ARRAY_LEN]; + +#endif // MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F767XX_PERIPH_H \ No newline at end of file diff --git a/ports/stm/peripherals/stm32f7/stm32f767xx/pins.c b/ports/stm/peripherals/stm32f7/stm32f767xx/pins.c new file mode 100644 index 0000000000000..870545f994b2a --- /dev/null +++ b/ports/stm/peripherals/stm32f7/stm32f767xx/pins.c @@ -0,0 +1,200 @@ + /* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/obj.h" +#include "py/mphal.h" +#include "peripherals/pins.h" + +// Todo: some pins do have ADCs, but the module isn't set up yet. + +const mcu_pin_obj_t pin_PA00 = PIN(0, 0, NO_ADC); +const mcu_pin_obj_t pin_PA01 = PIN(0, 1, NO_ADC); +const mcu_pin_obj_t pin_PA02 = PIN(0, 2, NO_ADC); +const mcu_pin_obj_t pin_PA03 = PIN(0, 3, NO_ADC); +const mcu_pin_obj_t pin_PA04 = PIN(0, 4, NO_ADC); +const mcu_pin_obj_t pin_PA05 = PIN(0, 5, NO_ADC); +const mcu_pin_obj_t pin_PA06 = PIN(0, 6, NO_ADC); +const mcu_pin_obj_t pin_PA07 = PIN(0, 7, NO_ADC); +const mcu_pin_obj_t pin_PA08 = PIN(0, 8, NO_ADC); +const mcu_pin_obj_t pin_PA09 = PIN(0, 9, NO_ADC); +const mcu_pin_obj_t pin_PA10 = PIN(0, 10, NO_ADC); +const mcu_pin_obj_t pin_PA11 = PIN(0, 11, NO_ADC); +const mcu_pin_obj_t pin_PA12 = PIN(0, 12, NO_ADC); +const mcu_pin_obj_t pin_PA13 = PIN(0, 13, NO_ADC); +const mcu_pin_obj_t pin_PA14 = PIN(0, 14, NO_ADC); +const mcu_pin_obj_t pin_PA15 = PIN(0, 15, NO_ADC); +const mcu_pin_obj_t pin_PB00 = PIN(1, 0, NO_ADC); +const mcu_pin_obj_t pin_PB01 = PIN(1, 1, NO_ADC); +const mcu_pin_obj_t pin_PB02 = PIN(1, 2, NO_ADC); +const mcu_pin_obj_t pin_PB03 = PIN(1, 3, NO_ADC); +const mcu_pin_obj_t pin_PB04 = PIN(1, 4, NO_ADC); +const mcu_pin_obj_t pin_PB05 = PIN(1, 5, NO_ADC); +const mcu_pin_obj_t pin_PB06 = PIN(1, 6, NO_ADC); +const mcu_pin_obj_t pin_PB07 = PIN(1, 7, NO_ADC); +const mcu_pin_obj_t pin_PB08 = PIN(1, 8, NO_ADC); +const mcu_pin_obj_t pin_PB09 = PIN(1, 9, NO_ADC); +const mcu_pin_obj_t pin_PB10 = PIN(1, 10, NO_ADC); +const mcu_pin_obj_t pin_PB11 = PIN(1, 11, NO_ADC); +const mcu_pin_obj_t pin_PB12 = PIN(1, 12, NO_ADC); +const mcu_pin_obj_t pin_PB13 = PIN(1, 13, NO_ADC); +const mcu_pin_obj_t pin_PB14 = PIN(1, 14, NO_ADC); +const mcu_pin_obj_t pin_PB15 = PIN(1, 15, NO_ADC); +const mcu_pin_obj_t pin_PC00 = PIN(2, 0, NO_ADC); +const mcu_pin_obj_t pin_PC01 = PIN(2, 1, NO_ADC); +const mcu_pin_obj_t pin_PC02 = PIN(2, 2, NO_ADC); +const mcu_pin_obj_t pin_PC03 = PIN(2, 3, NO_ADC); +const mcu_pin_obj_t pin_PC04 = PIN(2, 4, NO_ADC); +const mcu_pin_obj_t pin_PC05 = PIN(2, 5, NO_ADC); +const mcu_pin_obj_t pin_PC06 = PIN(2, 6, NO_ADC); +const mcu_pin_obj_t pin_PC07 = PIN(2, 7, NO_ADC); +const mcu_pin_obj_t pin_PC08 = PIN(2, 8, NO_ADC); +const mcu_pin_obj_t pin_PC09 = PIN(2, 9, NO_ADC); +const mcu_pin_obj_t pin_PC10 = PIN(2, 10, NO_ADC); +const mcu_pin_obj_t pin_PC11 = PIN(2, 11, NO_ADC); +const mcu_pin_obj_t pin_PC12 = PIN(2, 12, NO_ADC); +const mcu_pin_obj_t pin_PC13 = PIN(2, 13, NO_ADC); +const mcu_pin_obj_t pin_PC14 = PIN(2, 14, NO_ADC); +const mcu_pin_obj_t pin_PC15 = PIN(2, 15, NO_ADC); +const mcu_pin_obj_t pin_PD00 = PIN(3, 0, NO_ADC); +const mcu_pin_obj_t pin_PD01 = PIN(3, 1, NO_ADC); +const mcu_pin_obj_t pin_PD02 = PIN(3, 2, NO_ADC); +const mcu_pin_obj_t pin_PD03 = PIN(3, 3, NO_ADC); +const mcu_pin_obj_t pin_PD04 = PIN(3, 4, NO_ADC); +const mcu_pin_obj_t pin_PD05 = PIN(3, 5, NO_ADC); +const mcu_pin_obj_t pin_PD06 = PIN(3, 6, NO_ADC); +const mcu_pin_obj_t pin_PD07 = PIN(3, 7, NO_ADC); +const mcu_pin_obj_t pin_PD08 = PIN(3, 8, NO_ADC); +const mcu_pin_obj_t pin_PD09 = PIN(3, 9, NO_ADC); +const mcu_pin_obj_t pin_PD10 = PIN(3, 10, NO_ADC); +const mcu_pin_obj_t pin_PD11 = PIN(3, 11, NO_ADC); +const mcu_pin_obj_t pin_PD12 = PIN(3, 12, NO_ADC); +const mcu_pin_obj_t pin_PD13 = PIN(3, 13, NO_ADC); +const mcu_pin_obj_t pin_PD14 = PIN(3, 14, NO_ADC); +const mcu_pin_obj_t pin_PD15 = PIN(3, 15, NO_ADC); +const mcu_pin_obj_t pin_PE00 = PIN(4, 0, NO_ADC); +const mcu_pin_obj_t pin_PE01 = PIN(4, 1, NO_ADC); +const mcu_pin_obj_t pin_PE02 = PIN(4, 2, NO_ADC); +const mcu_pin_obj_t pin_PE03 = PIN(4, 3, NO_ADC); +const mcu_pin_obj_t pin_PE04 = PIN(4, 4, NO_ADC); +const mcu_pin_obj_t pin_PE05 = PIN(4, 5, NO_ADC); +const mcu_pin_obj_t pin_PE06 = PIN(4, 6, NO_ADC); +const mcu_pin_obj_t pin_PE07 = PIN(4, 7, NO_ADC); +const mcu_pin_obj_t pin_PE08 = PIN(4, 8, NO_ADC); +const mcu_pin_obj_t pin_PE09 = PIN(4, 9, NO_ADC); +const mcu_pin_obj_t pin_PE10 = PIN(4, 10, NO_ADC); +const mcu_pin_obj_t pin_PE11 = PIN(4, 11, NO_ADC); +const mcu_pin_obj_t pin_PE12 = PIN(4, 12, NO_ADC); +const mcu_pin_obj_t pin_PE13 = PIN(4, 13, NO_ADC); +const mcu_pin_obj_t pin_PE14 = PIN(4, 14, NO_ADC); +const mcu_pin_obj_t pin_PE15 = PIN(4, 15, NO_ADC); +const mcu_pin_obj_t pin_PF00 = PIN(5, 0, NO_ADC); +const mcu_pin_obj_t pin_PF01 = PIN(5, 1, NO_ADC); +const mcu_pin_obj_t pin_PF02 = PIN(5, 2, NO_ADC); +const mcu_pin_obj_t pin_PF03 = PIN(5, 3, NO_ADC); +const mcu_pin_obj_t pin_PF04 = PIN(5, 4, NO_ADC); +const mcu_pin_obj_t pin_PF05 = PIN(5, 5, NO_ADC); +const mcu_pin_obj_t pin_PF06 = PIN(5, 6, NO_ADC); +const mcu_pin_obj_t pin_PF07 = PIN(5, 7, NO_ADC); +const mcu_pin_obj_t pin_PF08 = PIN(5, 8, NO_ADC); +const mcu_pin_obj_t pin_PF09 = PIN(5, 9, NO_ADC); +const mcu_pin_obj_t pin_PF10 = PIN(5, 10, NO_ADC); +const mcu_pin_obj_t pin_PF11 = PIN(5, 11, NO_ADC); +const mcu_pin_obj_t pin_PF12 = PIN(5, 12, NO_ADC); +const mcu_pin_obj_t pin_PF13 = PIN(5, 13, NO_ADC); +const mcu_pin_obj_t pin_PF14 = PIN(5, 14, NO_ADC); +const mcu_pin_obj_t pin_PF15 = PIN(5, 15, NO_ADC); +const mcu_pin_obj_t pin_PG00 = PIN(6, 0, NO_ADC); +const mcu_pin_obj_t pin_PG01 = PIN(6, 1, NO_ADC); +const mcu_pin_obj_t pin_PG02 = PIN(6, 2, NO_ADC); +const mcu_pin_obj_t pin_PG03 = PIN(6, 3, NO_ADC); +const mcu_pin_obj_t pin_PG04 = PIN(6, 4, NO_ADC); +const mcu_pin_obj_t pin_PG05 = PIN(6, 5, NO_ADC); +const mcu_pin_obj_t pin_PG06 = PIN(6, 6, NO_ADC); +const mcu_pin_obj_t pin_PG07 = PIN(6, 7, NO_ADC); +const mcu_pin_obj_t pin_PG08 = PIN(6, 8, NO_ADC); +const mcu_pin_obj_t pin_PG09 = PIN(6, 9, NO_ADC); +const mcu_pin_obj_t pin_PG10 = PIN(6, 10, NO_ADC); +const mcu_pin_obj_t pin_PG11 = PIN(6, 11, NO_ADC); +const mcu_pin_obj_t pin_PG12 = PIN(6, 12, NO_ADC); +const mcu_pin_obj_t pin_PG13 = PIN(6, 13, NO_ADC); +const mcu_pin_obj_t pin_PG14 = PIN(6, 14, NO_ADC); +const mcu_pin_obj_t pin_PG15 = PIN(6, 15, NO_ADC); +const mcu_pin_obj_t pin_PH00 = PIN(7, 0, NO_ADC); +const mcu_pin_obj_t pin_PH01 = PIN(7, 1, NO_ADC); +const mcu_pin_obj_t pin_PH02 = PIN(7, 2, NO_ADC); +const mcu_pin_obj_t pin_PH03 = PIN(7, 3, NO_ADC); +const mcu_pin_obj_t pin_PH04 = PIN(7, 4, NO_ADC); +const mcu_pin_obj_t pin_PH05 = PIN(7, 5, NO_ADC); +const mcu_pin_obj_t pin_PH06 = PIN(7, 6, NO_ADC); +const mcu_pin_obj_t pin_PH07 = PIN(7, 7, NO_ADC); +const mcu_pin_obj_t pin_PH08 = PIN(7, 8, NO_ADC); +const mcu_pin_obj_t pin_PH09 = PIN(7, 9, NO_ADC); +const mcu_pin_obj_t pin_PH10 = PIN(7, 10, NO_ADC); +const mcu_pin_obj_t pin_PH11 = PIN(7, 11, NO_ADC); +const mcu_pin_obj_t pin_PH12 = PIN(7, 12, NO_ADC); +const mcu_pin_obj_t pin_PH13 = PIN(7, 13, NO_ADC); +const mcu_pin_obj_t pin_PH14 = PIN(7, 14, NO_ADC); +const mcu_pin_obj_t pin_PH15 = PIN(7, 15, NO_ADC); +const mcu_pin_obj_t pin_PI00 = PIN(8, 0, NO_ADC); +const mcu_pin_obj_t pin_PI01 = PIN(8, 1, NO_ADC); +const mcu_pin_obj_t pin_PI02 = PIN(8, 2, NO_ADC); +const mcu_pin_obj_t pin_PI03 = PIN(8, 3, NO_ADC); +const mcu_pin_obj_t pin_PI04 = PIN(8, 4, NO_ADC); +const mcu_pin_obj_t pin_PI05 = PIN(8, 5, NO_ADC); +const mcu_pin_obj_t pin_PI06 = PIN(8, 6, NO_ADC); +const mcu_pin_obj_t pin_PI07 = PIN(8, 7, NO_ADC); +const mcu_pin_obj_t pin_PI08 = PIN(8, 8, NO_ADC); +const mcu_pin_obj_t pin_PI09 = PIN(8, 9, NO_ADC); +const mcu_pin_obj_t pin_PI10 = PIN(8, 10, NO_ADC); +const mcu_pin_obj_t pin_PI11 = PIN(8, 11, NO_ADC); +const mcu_pin_obj_t pin_PI12 = PIN(8, 12, NO_ADC); +const mcu_pin_obj_t pin_PI13 = PIN(8, 13, NO_ADC); +const mcu_pin_obj_t pin_PI14 = PIN(8, 14, NO_ADC); +const mcu_pin_obj_t pin_PI15 = PIN(8, 15, NO_ADC); +const mcu_pin_obj_t pin_PJ00 = PIN(9, 0, NO_ADC); +const mcu_pin_obj_t pin_PJ01 = PIN(9, 1, NO_ADC); +const mcu_pin_obj_t pin_PJ02 = PIN(9, 2, NO_ADC); +const mcu_pin_obj_t pin_PJ03 = PIN(9, 3, NO_ADC); +const mcu_pin_obj_t pin_PJ04 = PIN(9, 4, NO_ADC); +const mcu_pin_obj_t pin_PJ05 = PIN(9, 5, NO_ADC); +const mcu_pin_obj_t pin_PJ06 = PIN(9, 6, NO_ADC); +const mcu_pin_obj_t pin_PJ07 = PIN(9, 7, NO_ADC); +const mcu_pin_obj_t pin_PJ08 = PIN(9, 8, NO_ADC); +const mcu_pin_obj_t pin_PJ09 = PIN(9, 9, NO_ADC); +const mcu_pin_obj_t pin_PJ10 = PIN(9, 10, NO_ADC); +const mcu_pin_obj_t pin_PJ11 = PIN(9, 11, NO_ADC); +const mcu_pin_obj_t pin_PJ12 = PIN(9, 12, NO_ADC); +const mcu_pin_obj_t pin_PJ13 = PIN(9, 13, NO_ADC); +const mcu_pin_obj_t pin_PJ14 = PIN(9, 14, NO_ADC); +const mcu_pin_obj_t pin_PJ15 = PIN(9, 15, NO_ADC); +const mcu_pin_obj_t pin_PK00 = PIN(10, 0, NO_ADC); +const mcu_pin_obj_t pin_PK01 = PIN(10, 1, NO_ADC); +const mcu_pin_obj_t pin_PK02 = PIN(10, 2, NO_ADC); +const mcu_pin_obj_t pin_PK03 = PIN(10, 3, NO_ADC); +const mcu_pin_obj_t pin_PK04 = PIN(10, 4, NO_ADC); +const mcu_pin_obj_t pin_PK05 = PIN(10, 5, NO_ADC); +const mcu_pin_obj_t pin_PK06 = PIN(10, 6, NO_ADC); +const mcu_pin_obj_t pin_PK07 = PIN(10, 7, NO_ADC); diff --git a/ports/stm/peripherals/stm32f7/stm32f767xx/pins.h b/ports/stm/peripherals/stm32f7/stm32f767xx/pins.h new file mode 100644 index 0000000000000..e0f2bb0566cb5 --- /dev/null +++ b/ports/stm/peripherals/stm32f7/stm32f767xx/pins.h @@ -0,0 +1,199 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Lucian Copeland for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F767XX_PINS_H +#define MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F767XX_PINS_H + +extern const mcu_pin_obj_t pin_PA00; +extern const mcu_pin_obj_t pin_PA01; +extern const mcu_pin_obj_t pin_PA02; +extern const mcu_pin_obj_t pin_PA03; +extern const mcu_pin_obj_t pin_PA04; +extern const mcu_pin_obj_t pin_PA05; +extern const mcu_pin_obj_t pin_PA06; +extern const mcu_pin_obj_t pin_PA07; +extern const mcu_pin_obj_t pin_PA08; +extern const mcu_pin_obj_t pin_PA09; +extern const mcu_pin_obj_t pin_PA10; +extern const mcu_pin_obj_t pin_PA11; +extern const mcu_pin_obj_t pin_PA12; +extern const mcu_pin_obj_t pin_PA13; +extern const mcu_pin_obj_t pin_PA14; +extern const mcu_pin_obj_t pin_PA15; +extern const mcu_pin_obj_t pin_PB00; +extern const mcu_pin_obj_t pin_PB01; +extern const mcu_pin_obj_t pin_PB02; +extern const mcu_pin_obj_t pin_PB03; +extern const mcu_pin_obj_t pin_PB04; +extern const mcu_pin_obj_t pin_PB05; +extern const mcu_pin_obj_t pin_PB06; +extern const mcu_pin_obj_t pin_PB07; +extern const mcu_pin_obj_t pin_PB08; +extern const mcu_pin_obj_t pin_PB09; +extern const mcu_pin_obj_t pin_PB10; +extern const mcu_pin_obj_t pin_PB11; +extern const mcu_pin_obj_t pin_PB12; +extern const mcu_pin_obj_t pin_PB13; +extern const mcu_pin_obj_t pin_PB14; +extern const mcu_pin_obj_t pin_PB15; +extern const mcu_pin_obj_t pin_PC00; +extern const mcu_pin_obj_t pin_PC01; +extern const mcu_pin_obj_t pin_PC02; +extern const mcu_pin_obj_t pin_PC03; +extern const mcu_pin_obj_t pin_PC04; +extern const mcu_pin_obj_t pin_PC05; +extern const mcu_pin_obj_t pin_PC06; +extern const mcu_pin_obj_t pin_PC07; +extern const mcu_pin_obj_t pin_PC08; +extern const mcu_pin_obj_t pin_PC09; +extern const mcu_pin_obj_t pin_PC10; +extern const mcu_pin_obj_t pin_PC11; +extern const mcu_pin_obj_t pin_PC12; +extern const mcu_pin_obj_t pin_PC13; +extern const mcu_pin_obj_t pin_PC14; +extern const mcu_pin_obj_t pin_PC15; +extern const mcu_pin_obj_t pin_PD00; +extern const mcu_pin_obj_t pin_PD01; +extern const mcu_pin_obj_t pin_PD02; +extern const mcu_pin_obj_t pin_PD03; +extern const mcu_pin_obj_t pin_PD04; +extern const mcu_pin_obj_t pin_PD05; +extern const mcu_pin_obj_t pin_PD06; +extern const mcu_pin_obj_t pin_PD07; +extern const mcu_pin_obj_t pin_PD08; +extern const mcu_pin_obj_t pin_PD09; +extern const mcu_pin_obj_t pin_PD10; +extern const mcu_pin_obj_t pin_PD11; +extern const mcu_pin_obj_t pin_PD12; +extern const mcu_pin_obj_t pin_PD13; +extern const mcu_pin_obj_t pin_PD14; +extern const mcu_pin_obj_t pin_PD15; +extern const mcu_pin_obj_t pin_PE00; +extern const mcu_pin_obj_t pin_PE01; +extern const mcu_pin_obj_t pin_PE02; +extern const mcu_pin_obj_t pin_PE03; +extern const mcu_pin_obj_t pin_PE04; +extern const mcu_pin_obj_t pin_PE05; +extern const mcu_pin_obj_t pin_PE06; +extern const mcu_pin_obj_t pin_PE07; +extern const mcu_pin_obj_t pin_PE08; +extern const mcu_pin_obj_t pin_PE09; +extern const mcu_pin_obj_t pin_PE10; +extern const mcu_pin_obj_t pin_PE11; +extern const mcu_pin_obj_t pin_PE12; +extern const mcu_pin_obj_t pin_PE13; +extern const mcu_pin_obj_t pin_PE14; +extern const mcu_pin_obj_t pin_PE15; +extern const mcu_pin_obj_t pin_PF00; +extern const mcu_pin_obj_t pin_PF01; +extern const mcu_pin_obj_t pin_PF02; +extern const mcu_pin_obj_t pin_PF03; +extern const mcu_pin_obj_t pin_PF04; +extern const mcu_pin_obj_t pin_PF05; +extern const mcu_pin_obj_t pin_PF06; +extern const mcu_pin_obj_t pin_PF07; +extern const mcu_pin_obj_t pin_PF08; +extern const mcu_pin_obj_t pin_PF09; +extern const mcu_pin_obj_t pin_PF10; +extern const mcu_pin_obj_t pin_PF11; +extern const mcu_pin_obj_t pin_PF12; +extern const mcu_pin_obj_t pin_PF13; +extern const mcu_pin_obj_t pin_PF14; +extern const mcu_pin_obj_t pin_PF15; +extern const mcu_pin_obj_t pin_PG00; +extern const mcu_pin_obj_t pin_PG01; +extern const mcu_pin_obj_t pin_PG02; +extern const mcu_pin_obj_t pin_PG03; +extern const mcu_pin_obj_t pin_PG04; +extern const mcu_pin_obj_t pin_PG05; +extern const mcu_pin_obj_t pin_PG06; +extern const mcu_pin_obj_t pin_PG07; +extern const mcu_pin_obj_t pin_PG08; +extern const mcu_pin_obj_t pin_PG09; +extern const mcu_pin_obj_t pin_PG10; +extern const mcu_pin_obj_t pin_PG11; +extern const mcu_pin_obj_t pin_PG12; +extern const mcu_pin_obj_t pin_PG13; +extern const mcu_pin_obj_t pin_PG14; +extern const mcu_pin_obj_t pin_PG15; +extern const mcu_pin_obj_t pin_PH00; +extern const mcu_pin_obj_t pin_PH01; +extern const mcu_pin_obj_t pin_PH02; +extern const mcu_pin_obj_t pin_PH03; +extern const mcu_pin_obj_t pin_PH04; +extern const mcu_pin_obj_t pin_PH05; +extern const mcu_pin_obj_t pin_PH06; +extern const mcu_pin_obj_t pin_PH07; +extern const mcu_pin_obj_t pin_PH08; +extern const mcu_pin_obj_t pin_PH09; +extern const mcu_pin_obj_t pin_PH10; +extern const mcu_pin_obj_t pin_PH11; +extern const mcu_pin_obj_t pin_PH12; +extern const mcu_pin_obj_t pin_PH13; +extern const mcu_pin_obj_t pin_PH14; +extern const mcu_pin_obj_t pin_PH15; +extern const mcu_pin_obj_t pin_PI00; +extern const mcu_pin_obj_t pin_PI01; +extern const mcu_pin_obj_t pin_PI02; +extern const mcu_pin_obj_t pin_PI03; +extern const mcu_pin_obj_t pin_PI04; +extern const mcu_pin_obj_t pin_PI05; +extern const mcu_pin_obj_t pin_PI06; +extern const mcu_pin_obj_t pin_PI07; +extern const mcu_pin_obj_t pin_PI08; +extern const mcu_pin_obj_t pin_PI09; +extern const mcu_pin_obj_t pin_PI10; +extern const mcu_pin_obj_t pin_PI11; +extern const mcu_pin_obj_t pin_PI12; +extern const mcu_pin_obj_t pin_PI13; +extern const mcu_pin_obj_t pin_PI14; +extern const mcu_pin_obj_t pin_PI15; +extern const mcu_pin_obj_t pin_PJ00; +extern const mcu_pin_obj_t pin_PJ01; +extern const mcu_pin_obj_t pin_PJ02; +extern const mcu_pin_obj_t pin_PJ03; +extern const mcu_pin_obj_t pin_PJ04; +extern const mcu_pin_obj_t pin_PJ05; +extern const mcu_pin_obj_t pin_PJ06; +extern const mcu_pin_obj_t pin_PJ07; +extern const mcu_pin_obj_t pin_PJ08; +extern const mcu_pin_obj_t pin_PJ09; +extern const mcu_pin_obj_t pin_PJ10; +extern const mcu_pin_obj_t pin_PJ11; +extern const mcu_pin_obj_t pin_PJ12; +extern const mcu_pin_obj_t pin_PJ13; +extern const mcu_pin_obj_t pin_PJ14; +extern const mcu_pin_obj_t pin_PJ15; +extern const mcu_pin_obj_t pin_PK00; +extern const mcu_pin_obj_t pin_PK01; +extern const mcu_pin_obj_t pin_PK02; +extern const mcu_pin_obj_t pin_PK03; +extern const mcu_pin_obj_t pin_PK04; +extern const mcu_pin_obj_t pin_PK05; +extern const mcu_pin_obj_t pin_PK06; +extern const mcu_pin_obj_t pin_PK07; + +#endif // MICROPY_INCLUDED_STM32_PERIPHERALS_STM32F767XX_PINS_H diff --git a/ports/stm/supervisor/internal_flash.c b/ports/stm/supervisor/internal_flash.c index 5bd6e8758e9a4..7d394d187a651 100644 --- a/ports/stm/supervisor/internal_flash.c +++ b/ports/stm/supervisor/internal_flash.c @@ -49,27 +49,47 @@ typedef struct { #if defined(STM32F4) -STATIC const flash_layout_t flash_layout[] = { - { 0x08000000, 0x04000, 4 }, - { 0x08010000, 0x10000, 1 }, - { 0x08020000, 0x20000, 3 }, - #if defined(FLASH_SECTOR_8) - { 0x08080000, 0x20000, 4 }, - #endif - #if defined(FLASH_SECTOR_12) - { 0x08100000, 0x04000, 4 }, - { 0x08110000, 0x10000, 1 }, - { 0x08120000, 0x20000, 7 }, + STATIC const flash_layout_t flash_layout[] = { + { 0x08000000, 0x04000, 4 }, + { 0x08010000, 0x10000, 1 }, + { 0x08020000, 0x20000, 3 }, + #if defined(FLASH_SECTOR_8) + { 0x08080000, 0x20000, 4 }, + #endif + #if defined(FLASH_SECTOR_12) + { 0x08100000, 0x04000, 4 }, + { 0x08110000, 0x10000, 1 }, + { 0x08120000, 0x20000, 7 }, + #endif + }; + STATIC uint8_t _flash_cache[0x4000] __attribute__((aligned(4))); + +#elif defined(STM32F7) + + // FLASH_FLAG_PGSERR (Programming Sequence Error) was renamed to + // FLASH_FLAG_ERSERR (Erasing Sequence Error) in STM32F7 + #define FLASH_FLAG_PGSERR FLASH_FLAG_ERSERR + #if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F732xx) || defined(STM32F733xx) + static const flash_layout_t flash_layout[] = { + { 0x08000000, 0x04000, 4 }, + { 0x08010000, 0x10000, 1 }, + { 0x08020000, 0x20000, 3 }, + }; + STATIC uint8_t _flash_cache[0x4000] __attribute__((aligned(4))); + #else + static const flash_layout_t flash_layout[] = { + { 0x08000000, 0x08000, 4 }, + { 0x08020000, 0x20000, 1 }, + { 0x08040000, 0x40000, 3 }, + }; + STATIC uint8_t _flash_cache[0x8000] __attribute__((aligned(4))); #endif -}; -STATIC uint8_t _flash_cache[0x4000] __attribute__((aligned(4))); - #elif defined(STM32H7) -STATIC const flash_layout_t flash_layout[] = { - { 0x08000000, 0x20000, 16 }, -}; -STATIC uint8_t _flash_cache[0x20000] __attribute__((aligned(4))); + STATIC const flash_layout_t flash_layout[] = { + { 0x08000000, 0x20000, 16 }, + }; + STATIC uint8_t _flash_cache[0x20000] __attribute__((aligned(4))); #else #error Unsupported processor diff --git a/ports/stm/supervisor/internal_flash.h b/ports/stm/supervisor/internal_flash.h index 665b194c5fabf..e54cd92311e8a 100644 --- a/ports/stm/supervisor/internal_flash.h +++ b/ports/stm/supervisor/internal_flash.h @@ -66,6 +66,12 @@ #define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08004000 #endif +#ifdef STM32F767xx +#define STM32_FLASH_SIZE 0x200000 //2MB +#define INTERNAL_FLASH_FILESYSTEM_SIZE 0x18000 //96KiB +#define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08008000 +#endif + #ifdef STM32H743xx #define STM32_FLASH_SIZE 0x200000 //2MB #define INTERNAL_FLASH_FILESYSTEM_SIZE 0x20000 //128KiB diff --git a/ports/stm/supervisor/usb.c b/ports/stm/supervisor/usb.c index 997bf413f8fa3..501550aed7791 100644 --- a/ports/stm/supervisor/usb.c +++ b/ports/stm/supervisor/usb.c @@ -80,7 +80,7 @@ void init_usb_hardware(void) { GPIO_InitStruct.Pull = GPIO_NOPULL; #if defined(STM32H7) GPIO_InitStruct.Alternate = GPIO_AF10_OTG1_FS; - #elif defined(STM32F4) + #elif defined(STM32F4) || defined(STM32F7) GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; #else #error Unsupported processor @@ -105,7 +105,7 @@ void init_usb_hardware(void) { GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; #if defined(STM32H7) GPIO_InitStruct.Alternate = GPIO_AF10_OTG1_FS; - #elif defined(STM32F4) + #elif defined(STM32F4) || defined(STM32F7) GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; #else #error Unsupported processor @@ -128,7 +128,6 @@ void init_usb_hardware(void) { __HAL_RCC_USB2_OTG_FS_CLK_ENABLE(); #else /* Peripheral clock enable */ - __HAL_RCC_USB_OTG_FS_CLK_DISABLE(); __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); #endif diff --git a/ports/stm/system_stm32f7xx.c b/ports/stm/system_stm32f7xx.c new file mode 100644 index 0000000000000..184fefb36c210 --- /dev/null +++ b/ports/stm/system_stm32f7xx.c @@ -0,0 +1,247 @@ +/** + ****************************************************************************** + * @file system_stm32f7xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f7xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f7xx_system + * @{ + */ + +/** @addtogroup STM32F7xx_System_Private_Includes + * @{ + */ + +#include "stm32f7xx.h" + +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Variables + * @{ + */ + + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 16000000; + const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ +#endif + + /* Configure the Vector Table location add offset address ------------------*/ +#if !(BOARD_VTOR_DEFER) //only set VTOR if the bootloader hasn't already + #ifdef VECT_TAB_SRAM + SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ + #else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ + #endif +#endif + +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/ports/stm/tools/parse_af_csv.py b/ports/stm/tools/parse_af_csv.py index 56baf8c7654ce..b257a450c20e9 100644 --- a/ports/stm/tools/parse_af_csv.py +++ b/ports/stm/tools/parse_af_csv.py @@ -102,7 +102,7 @@ def evaluate_tim(inper, inlist, altfn, pin): for i in range(len(todo)): ins = (todo[i][0]).lower() + '_' + (todo[i][1]).lower() + '_' # const mcu_i2c_sda_obj_t mcu_i2c_sda_list[4] = { - print("const mcu_" + ins + "obj_t mcu_" + ins + "list[" + str(len(outlist[i])) + "] = {") + print("const mcu_periph_obj_t mcu_" + ins + "list[" + str(len(outlist[i])) + "] = {") for row in outlist[i]: print(" PERIPH(" + row[0] + ", " + str(row[1]) + ", &pin_" + row[2] + "),") print("};") diff --git a/ports/stm/tools/pins.csv b/ports/stm/tools/pins.csv new file mode 100644 index 0000000000000..e447b76b05b06 --- /dev/null +++ b/ports/stm/tools/pins.csv @@ -0,0 +1,137 @@ +A0,PA3 +A1,PC0 +A2,PC3 +A3,PF3 +A4,PF5 +A5,PF10 +A6,PB1 +A7,PC2 +A8,PF4 +D0,PG9 +D1,PG14 +D2,PF15 +D3,PE13 +D4,PF14 +D5,PE11 +D6,PE9 +D7,PF13 +D8,PF12 +D9,PD15 +D10,PD14 +D11,PA7 +D12,PA6 +D13,PA5 +D14,PB9 +D15,PB8 +D16,PC6 +D17,PB15 +D18,PB13 +D19,PB12 +D20,PA15 +D21,PC7 +D22,PB5 +D23,PB3 +D24,PA4 +D25,PB4 +D26,PB6 +D27,PB2 +D28,PD13 +D29,PD12 +D30,PD11 +D31,PE2 +D32,PA0 +D33,PB0 +D34,PE0 +D35,PB11 +D36,PB10 +D37,PE15 +D38,PE14 +D39,PE12 +D40,PE10 +D41,PE7 +D42,PE8 +D43,PC8 +D44,PC9 +D45,PC10 +D46,PC11 +D47,PC12 +D48,PD2 +D49,PG2 +D50,PG3 +D51,PD7 +D52,PD6 +D53,PD5 +D54,PD4 +D55,PD3 +D56,PE2 +D57,PE4 +D58,PE5 +D59,PE6 +D60,PE3 +D61,PF8 +D62,PF7 +D63,PF9 +D64,PG1 +D65,PG0 +D66,PD1 +D67,PD0 +D68,PF0 +D69,PF1 +D70,PF2 +D71,PA7 +DAC1,PA4 +DAC2,PA5 +LED1,PB0 +LED2,PB7 +LED3,PB14 +SW,PC13 +SD_D0,PC8 +SD_D1,PC9 +SD_D2,PC10 +SD_D3,PC11 +SD_CMD,PD2 +SD_CK,PC12 +SD_SW,PG2 +OTG_FS_POWER,PG6 +OTG_FS_OVER_CURRENT,PG7 +USB_VBUS,PA9 +USB_ID,PA10 +USB_DM,PA11 +USB_DP,PA12 +UART2_TX,PD5 +UART2_RX,PD6 +UART2_RTS,PD4 +UART2_CTS,PD3 +VCP_TX,PD8 +VCP_RX,PD9 +UART3_TX,PD8 +UART3_RX,PD9 +UART5_TX,PB6 +UART5_RX,PB12 +UART6_TX,PC6 +UART6_RX,PC7 +UART7_TX,PF7 +UART7_RX,PF6 +UART8_TX,PE1 +UART8_RX,PE0 +SPI3_NSS,PA4 +SPI3_SCK,PB3 +SPI3_MISO,PB4 +SPI3_MOSI,PB5 +I2C1_SDA,PB9 +I2C1_SCL,PB8 +I2C2_SDA,PF0 +I2C2_SCL,PF1 +I2C4_SCL,PF14 +I2C4_SDA,PF15 +ETH_MDC,PC1 +ETH_MDIO,PA2 +ETH_RMII_REF_CLK,PA1 +ETH_RMII_CRS_DV,PA7 +ETH_RMII_RXD0,PC4 +ETH_RMII_RXD1,PC5 +ETH_RMII_TX_EN,PG11 +ETH_RMII_TXD0,PG13 +ETH_RMII_TXD1,PB13 +SWDIO,PA13 +SWDCLK,PA14 diff --git a/ports/stm/tools/stm32f767_af.csv b/ports/stm/tools/stm32f767_af.csv new file mode 100644 index 0000000000000..86f10b6dc8cf2 --- /dev/null +++ b/ports/stm/tools/stm32f767_af.csv @@ -0,0 +1,168 @@ +PortA,PA0,,TIM2_CH1/TIM2_ETR,TIM5_CH1,TIM8_ETR,,,,USART2_CTS,UART4_TX,,SAI2_SD_B,ETH_MII_CRS,,,,EVENTOUT,ADC123_IN0 +PortA,PA1,,TIM2_CH2,TIM5_CH2,,,,,USART2_RTS,UART4_RX,QUADSPI_BK1_IO3,SAI2_MCK_B,ETH_MII_RX_CLK/ETH_RMII_REF_CLK,,,LCD_R2,EVENTOUT,ADC123_IN1 +PortA,PA2,,TIM2_CH3,TIM5_CH3,TIM9_CH1,,,,USART2_TX,SAI2_SCK_B,,,ETH_MDIO,MDIOS_MDIO,,LCD_R1,EVENTOUT,ADC123_IN2 +PortA,PA3,,TIM2_CH4,TIM5_CH4,TIM9_CH2,,,,USART2_RX,,LCD_B2,OTG_HS_ULPI_D0,ETH_MII_COL,,,LCD_B5,EVENTOUT,ADC123_IN3 +PortA,PA4,,,,,,SPI1_NSS/I2S1_WS,SPI3_NSS/I2S3_WS,USART2_CK,SPI6_NSS,,,,OTG_HS_SOF,DCMI_HSYNC,LCD_VSYNC,EVENTOUT,ADC12_IN4 +PortA,PA5,,TIM2_CH1/TIM2_ETR,,TIM8_CH1N,,SPI1_SCK/I2S1_CK,,,SPI6_SCK,,OTG_HS_ULPI_CK,,,,LCD_R4,EVENTOUT,ADC12_IN5 +PortA,PA6,,TIM1_BKIN,TIM3_CH1,TIM8_BKIN,,SPI1_MISO,,,SPI6_MISO,TIM13_CH1,,,MDIOS_MDC,DCMI_PIXCLK,LCD_G2,EVENTOUT,ADC12_IN6 +PortA,PA7,,TIM1_CH1N,TIM3_CH2,TIM8_CH1N,,SPI1_MOSI/I2S1_SD,,,SPI6_MOSI,TIM14_CH1,,ETH_MII_RX_DV/ETH_RMII_CRS_DV,FMC_SDNWE,,,EVENTOUT,ADC12_IN7 +PortA,PA8,MCO1,TIM1_CH1,,TIM8_BKIN2,I2C3_SCL,,,USART1_CK,,,OTG_FS_SOF,CAN3_RX,UART7_RX,LCD_B3,LCD_R6,EVENTOUT, +PortA,PA9,,TIM1_CH2,,,I2C3_SMBA,SPI2_SCK/I2S2_CK,,USART1_TX,,,,,,DCMI_D0,LCD_R5,EVENTOUT, +PortA,PA10,,TIM1_CH3,,,,,,USART1_RX,,LCD_B4,OTG_FS_ID,,MDIOS_MDIO,DCMI_D1,LCD_B1,EVENTOUT, +PortA,PA11,,TIM1_CH4,,,,SPI2_NSS/I2S2_WS,UART4_RX,USART1_CTS,,CAN1_RX,OTG_FS_DM,,,,LCD_R4,EVENTOUT, +PortA,PA12,,TIM1_ETR,,,,SPI2_SCK/I2S2_CK,UART4_TX,USART1_RTS,SAI2_FS_B,CAN1_TX,OTG_FS_DP,,,,LCD_R5,EVENTOUT, +PortA,PA13,JTMS/SWDIO,,,,,,,,,,,,,,,EVENTOUT, +PortA,PA14,JTCK/SWCLK,,,,,,,,,,,,,,,EVENTOUT, +PortA,PA15,JTDI,TIM2_CH1/TIM2_ETR,,,HDMI_CEC,SPI1_NSS/I2S1_WS,SPI3_NSS/I2S3_WS,SPI6_NSS,UART4_RTS,,,CAN3_TX,UART7_TX,,,EVENTOUT, +PortB,PB0,,TIM1_CH2N,TIM3_CH3,TIM8_CH2N,,,DFSDM1_CKOUT,,UART4_CTS,LCD_R3,OTG_HS_ULPI_D1,ETH_MII_RXD2,,,LCD_G1,EVENTOUT,ADC12_IN8 +PortB,PB1,,TIM1_CH3N,TIM3_CH4,TIM8_CH3N,,,DFSDM1_DATAIN1,,,LCD_R6,OTG_HS_ULPI_D2,ETH_MII_RXD3,,,LCD_G0,EVENTOUT,ADC12_IN9 +PortB,PB2,,,,,,,SAI1_SD_A,SPI3_MOSI/I2S3_SD,,QUADSPI_CLK,DFSDM1_CKIN1,,,,,EVENTOUT, +PortB,PB3,JTDO/TRACESWO,TIM2_CH2,,,,SPI1_SCK/I2S1_CK,SPI3_SCK/I2S3_CK,,SPI6_SCK,,SDMMC2_D2,CAN3_RX,UART7_RX,,,EVENTOUT, +PortB,PB4,NJTRST,,TIM3_CH1,,,SPI1_MISO,SPI3_MISO,SPI2_NSS/I2S2_WS,SPI6_MISO,,SDMMC2_D3,CAN3_TX,UART7_TX,,,EVENTOUT, +PortB,PB5,,UART5_RX,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI/I2S1_SD,SPI3_MOSI/I2S3_SD,,SPI6_MOSI,CAN2_RX,OTG_HS_ULPI_D7,ETH_PPS_OUT,FMC_SDCKE1,DCMI_D10,LCD_G7,EVENTOUT, +PortB,PB6,,UART5_TX,TIM4_CH1,HDMI_CEC,I2C1_SCL,,DFSDM1_DATAIN5,USART1_TX,,CAN2_TX,QUADSPI_BK1_NCS,I2C4_SCL,FMC_SDNE1,DCMI_D5,,EVENTOUT, +PortB,PB7,,,TIM4_CH2,,I2C1_SDA,,DFSDM1_CKIN5,USART1_RX,,,,I2C4_SDA,FMC_NL,DCMI_VSYNC,,EVENTOUT, +PortB,PB8,,I2C4_SCL,TIM4_CH3,TIM10_CH1,I2C1_SCL,,DFSDM1_CKIN7,UART5_RX,,CAN1_RX,SDMMC2_D4,ETH_MII_TXD3,SDMMC1_D4,DCMI_D6,LCD_B6,EVENTOUT, +PortB,PB9,,I2C4_SDA,TIM4_CH4,TIM11_CH1,I2C1_SDA,SPI2_NSS/I2S2_WS,DFSDM1_DATAIN7,UART5_TX,,CAN1_TX,SDMMC2_D5,I2C4_SMBA,SDMMC1_D5,DCMI_D7,LCD_B7,EVENTOUT, +PortB,PB10,,TIM2_CH3,,,I2C2_SCL,SPI2_SCK/I2S2_CK,DFSDM1_DATAIN7,USART3_TX,,QUADSPI_BK1_NCS,OTG_HS_ULPI_D3,ETH_MII_RX_ER,,,LCD_G4,EVENTOUT, +PortB,PB11,,TIM2_CH4,,,I2C2_SDA,,DFSDM1_CKIN7,USART3_RX,,,OTG_HS_ULPI_D4,ETH_MII_TX_EN/ETH_RMII_TX_EN,,DSI_TE,LCD_G5,EVENTOUT, +PortB,PB12,,TIM1_BKIN,,,I2C2_SMBA,SPI2_NSS/I2S2_WS,DFSDM1_DATAIN1,USART3_CK,UART5_RX,CAN2_RX,OTG_HS_ULPI_D5,ETH_MII_TXD0/ETH_RMII_TXD0,OTG_HS_ID,,,EVENTOUT, +PortB,PB13,,TIM1_CH1N,,,,SPI2_SCK/I2S2_CK,DFSDM1_CKIN1,USART3_CTS,UART5_TX,CAN2_TX,OTG_HS_ULPI_D6,ETH_MII_TXD1/ETH_RMII_TXD1,,,,EVENTOUT, +PortB,PB14,,TIM1_CH2N,,TIM8_CH2N,USART1_TX,SPI2_MISO,DFSDM1_DATAIN2,USART3_RTS,UART4_RTS,TIM12_CH1,SDMMC2_D0,,OTG_HS_DM,,,EVENTOUT, +PortB,PB15,RTC_REFIN,TIM1_CH3N,,TIM8_CH3N,USART1_RX,SPI2_MOSI/I2S2_SD,DFSDM1_CKIN2,,UART4_CTS,TIM12_CH2,SDMMC2_D1,,OTG_HS_DP,,,EVENTOUT, +PortC,PC0,,,,DFSDM1_CKIN0,,,DFSDM1_DATAIN4,,SAI2_FS_B,,OTG_HS_ULPI_STP,,FMC_SDNWE,,LCD_R5,EVENTOUT,ADC123_IN10 +PortC,PC1,TRACED0,,,DFSDM1_DATAIN0,,SPI2_MOSI/I2S2_SD,SAI1_SD_A,,,,DFSDM1_CKIN4,ETH_MDC,MDIOS_MDC,,,EVENTOUT,ADC123_IN11 +PortC,PC2,,,,DFSDM1_CKIN1,,SPI2_MISO,DFSDM1_CKOUT,,,,OTG_HS_ULPI_DIR,ETH_MII_TXD2,FMC_SDNE0,,,EVENTOUT,ADC123_IN12 +PortC,PC3,,,,DFSDM1_DATAIN1,,SPI2_MOSI/I2S2_SD,,,,,OTG_HS_ULPI_NXT,ETH_MII_TX_CLK,FMC_SDCKE0,,,EVENTOUT,ADC123_IN13 +PortC,PC4,,,,DFSDM1_CKIN2,,I2S1_MCK,,,SPDIFRX_IN2,,,ETH_MII_RXD0/ETH_RMII_RXD0,FMC_SDNE0,,,EVENTOUT,ADC12_IN14 +PortC,PC5,,,,DFSDM1_DATAIN2,,,,,SPDIFRX_IN3,,,ETH_MII_RXD1/ETH_RMII_RXD1,FMC_SDCKE0,,,EVENTOUT,ADC12_IN15 +PortC,PC6,,,TIM3_CH1,TIM8_CH1,,I2S2_MCK,,DFSDM1_CKIN3,USART6_TX,FMC_NWAIT,SDMMC2_D6,,SDMMC1_D6,DCMI_D0,LCD_HSYNC,EVENTOUT, +PortC,PC7,,,TIM3_CH2,TIM8_CH2,,,I2S3_MCK,DFSDM1_DATAIN3,USART6_RX,FMC_NE1,SDMMC2_D7,,SDMMC1_D7,DCMI_D1,LCD_G6,EVENTOUT, +PortC,PC8,TRACED1,,TIM3_CH3,TIM8_CH3,,,,UART5_RTS,USART6_CK,FMC_NE2/FMC_NCE,,,SDMMC1_D0,DCMI_D2,,EVENTOUT, +PortC,PC9,MCO2,,TIM3_CH4,TIM8_CH4,I2C3_SDA,I2S_CKIN,,UART5_CTS,,QUADSPI_BK1_IO0,LCD_G3,,SDMMC1_D1,DCMI_D3,LCD_B2,EVENTOUT, +PortC,PC10,,,,DFSDM1_CKIN5,,,SPI3_SCK/I2S3_CK,USART3_TX,UART4_TX,QUADSPI_BK1_IO1,,,SDMMC1_D2,DCMI_D8,LCD_R2,EVENTOUT, +PortC,PC11,,,,DFSDM1_DATAIN5,,,SPI3_MISO,USART3_RX,UART4_RX,QUADSPI_BK2_NCS,,,SDMMC1_D3,DCMI_D4,,EVENTOUT, +PortC,PC12,TRACED3,,,,,,SPI3_MOSI/I2S3_SD,USART3_CK,UART5_TX,,,,SDMMC1_CK,DCMI_D9,,EVENTOUT, +PortC,PC13,,,,,,,,,,,,,,,,EVENTOUT, +PortC,PC14,,,,,,,,,,,,,,,,EVENTOUT, +PortC,PC15,,,,,,,,,,,,,,,,EVENTOUT, +PortD,PD0,,,,DFSDM1_CKIN6,,,DFSDM1_DATAIN7,,UART4_RX,CAN1_RX,,,FMC_D2,,,EVENTOUT, +PortD,PD1,,,,DFSDM1_DATAIN6,,,DFSDM1_CKIN7,,UART4_TX,CAN1_TX,,,FMC_D3,,,EVENTOUT, +PortD,PD2,TRACED2,,TIM3_ETR,,,,,,UART5_RX,,,,SDMMC1_CMD,DCMI_D11,,EVENTOUT, +PortD,PD3,,,,DFSDM1_CKOUT,,SPI2_SCK/I2S2_CK,DFSDM1_DATAIN0,USART2_CTS,,,,,FMC_CLK,DCMI_D5,LCD_G7,EVENTOUT, +PortD,PD4,,,,,,,DFSDM1_CKIN0,USART2_RTS,,,,,FMC_NOE,,,EVENTOUT, +PortD,PD5,,,,,,,,USART2_TX,,,,,FMC_NWE,,,EVENTOUT, +PortD,PD6,,,,DFSDM1_CKIN4,,SPI3_MOSI/I2S3_SD,SAI1_SD_A,USART2_RX,,,DFSDM1_DATAIN1,SDMMC2_CK,FMC_NWAIT,DCMI_D10,LCD_B2,EVENTOUT, +PortD,PD7,,,,DFSDM1_DATAIN4,,SPI1_MOSI/I2S1_SD,DFSDM1_CKIN1,USART2_CK,SPDIFRX_IN0,,,SDMMC2_CMD,FMC_NE1,,,EVENTOUT, +PortD,PD8,,,,DFSDM1_CKIN3,,,,USART3_TX,SPDIFRX_IN1,,,,FMC_D13,,,EVENTOUT, +PortD,PD9,,,,DFSDM1_DATAIN3,,,,USART3_RX,,,,,FMC_D14,,,EVENTOUT, +PortD,PD10,,,,DFSDM1_CKOUT,,,,USART3_CK,,,,,FMC_D15,,LCD_B3,EVENTOUT, +PortD,PD11,,,,,I2C4_SMBA,,,USART3_CTS,,QUADSPI_BK1_IO0,SAI2_SD_A,,FMC_A16/FMC_CLE,,,EVENTOUT, +PortD,PD12,,,TIM4_CH1,LPTIM1_IN1,I2C4_SCL,,,USART3_RTS,,QUADSPI_BK1_IO1,SAI2_FS_A,,FMC_A17/FMC_ALE,,,EVENTOUT, +PortD,PD13,,,TIM4_CH2,LPTIM1_OUT,I2C4_SDA,,,,,QUADSPI_BK1_IO3,SAI2_SCK_A,,FMC_A18,,,EVENTOUT, +PortD,PD14,,,TIM4_CH3,,,,,,UART8_CTS,,,,FMC_D0,,,EVENTOUT, +PortD,PD15,,,TIM4_CH4,,,,,,UART8_RTS,,,,FMC_D1,,,EVENTOUT, +PortE,PE0,,,TIM4_ETR,LPTIM1_ETR,,,,,UART8_RX,,SAI2_MCK_A,,FMC_NBL0,DCMI_D2,,EVENTOUT, +PortE,PE1,,,,LPTIM1_IN2,,,,,UART8_TX,,,,FMC_NBL1,DCMI_D3,,EVENTOUT, +PortE,PE2,TRACECLK,,,,,SPI4_SCK,SAI1_MCLK_A,,,QUADSPI_BK1_IO2,,ETH_MII_TXD3,FMC_A23,,,EVENTOUT, +PortE,PE3,TRACED0,,,,,,SAI1_SD_B,,,,,,FMC_A19,,,EVENTOUT, +PortE,PE4,TRACED1,,,,,SPI4_NSS,SAI1_FS_A,,,,DFSDM1_DATAIN3,,FMC_A20,DCMI_D4,LCD_B0,EVENTOUT, +PortE,PE5,TRACED2,,,TIM9_CH1,,SPI4_MISO,SAI1_SCK_A,,,,DFSDM1_CKIN3,,FMC_A21,DCMI_D6,LCD_G0,EVENTOUT, +PortE,PE6,TRACED3,TIM1_BKIN2,,TIM9_CH2,,SPI4_MOSI,SAI1_SD_A,,,,SAI2_MCK_B,,FMC_A22,DCMI_D7,LCD_G1,EVENTOUT, +PortE,PE7,,TIM1_ETR,,,,,DFSDM1_DATAIN2,,UART7_RX,,QUADSPI_BK2_IO0,,FMC_D4,,,EVENTOUT, +PortE,PE8,,TIM1_CH1N,,,,,DFSDM1_CKIN2,,UART7_TX,,QUADSPI_BK2_IO1,,FMC_D5,,,EVENTOUT, +PortE,PE9,,TIM1_CH1,,,,,DFSDM1_CKOUT,,UART7_RTS,,QUADSPI_BK2_IO2,,FMC_D6,,,EVENTOUT, +PortE,PE10,,TIM1_CH2N,,,,,DFSDM1_DATAIN4,,UART7_CTS,,QUADSPI_BK2_IO3,,FMC_D7,,,EVENTOUT, +PortE,PE11,,TIM1_CH2,,,,SPI4_NSS,DFSDM1_CKIN4,,,,SAI2_SD_B,,FMC_D8,,LCD_G3,EVENTOUT, +PortE,PE12,,TIM1_CH3N,,,,SPI4_SCK,DFSDM1_DATAIN5,,,,SAI2_SCK_B,,FMC_D9,,LCD_B4,EVENTOUT, +PortE,PE13,,TIM1_CH3,,,,SPI4_MISO,DFSDM1_CKIN5,,,,SAI2_FS_B,,FMC_D10,,LCD_DE,EVENTOUT, +PortE,PE14,,TIM1_CH4,,,,SPI4_MOSI,,,,,SAI2_MCK_B,,FMC_D11,,LCD_CLK,EVENTOUT, +PortE,PE15,,TIM1_BKIN,,,,,,,,,,,FMC_D12,,LCD_R7,EVENTOUT, +PortF,PF0,,,,,I2C2_SDA,,,,,,,,FMC_A0,,,EVENTOUT, +PortF,PF1,,,,,I2C2_SCL,,,,,,,,FMC_A1,,,EVENTOUT, +PortF,PF2,,,,,I2C2_SMBA,,,,,,,,FMC_A2,,,EVENTOUT, +PortF,PF3,,,,,,,,,,,,,FMC_A3,,,EVENTOUT,ADC3_IN9 +PortF,PF4,,,,,,,,,,,,,FMC_A4,,,EVENTOUT,ADC3_IN14 +PortF,PF5,,,,,,,,,,,,,FMC_A5,,,EVENTOUT,ADC3_IN15 +PortF,PF6,,,,TIM10_CH1,,SPI5_NSS,SAI1_SD_B,,UART7_RX,QUADSPI_BK1_IO3,,,,,,EVENTOUT,ADC3_IN4 +PortF,PF7,,,,TIM11_CH1,,SPI5_SCK,SAI1_MCLK_B,,UART7_TX,QUADSPI_BK1_IO2,,,,,,EVENTOUT,ADC3_IN5 +PortF,PF8,,,,,,SPI5_MISO,SAI1_SCK_B,,UART7_RTS,TIM13_CH1,QUADSPI_BK1_IO0,,,,,EVENTOUT,ADC3_IN6 +PortF,PF9,,,,,,SPI5_MOSI,SAI1_FS_B,,UART7_CTS,TIM14_CH1,QUADSPI_BK1_IO1,,,,,EVENTOUT,ADC3_IN7 +PortF,PF10,,,,,,,,,,QUADSPI_CLK,,,,DCMI_D11,LCD_DE,EVENTOUT,ADC3_IN8 +PortF,PF11,,,,,,SPI5_MOSI,,,,,SAI2_SD_B,,FMC_SDNRAS,DCMI_D12,,EVENTOUT, +PortF,PF12,,,,,,,,,,,,,FMC_A6,,,EVENTOUT, +PortF,PF13,,,,,I2C4_SMBA,,DFSDM1_DATAIN6,,,,,,FMC_A7,,,EVENTOUT, +PortF,PF14,,,,,I2C4_SCL,,DFSDM1_CKIN6,,,,,,FMC_A8,,,EVENTOUT, +PortF,PF15,,,,,I2C4_SDA,,,,,,,,FMC_A9,,,EVENTOUT, +PortG,PG0,,,,,,,,,,,,,FMC_A10,,,EVENTOUT, +PortG,PG1,,,,,,,,,,,,,FMC_A11,,,EVENTOUT, +PortG,PG2,,,,,,,,,,,,,FMC_A12,,,EVENTOUT, +PortG,PG3,,,,,,,,,,,,,FMC_A13,,,EVENTOUT, +PortG,PG4,,,,,,,,,,,,,FMC_A14/FMC_BA0,,,EVENTOUT, +PortG,PG5,,,,,,,,,,,,,FMC_A15/FMC_BA1,,,EVENTOUT, +PortG,PG6,,,,,,,,,,,,,FMC_NE3,DCMI_D12,LCD_R7,EVENTOUT, +PortG,PG7,,,,,,,SAI1_MCLK_A,,USART6_CK,,,,FMC_INT,DCMI_D13,LCD_CLK,EVENTOUT, +PortG,PG8,,,,,,SPI6_NSS,,SPDIFRX_IN2,USART6_RTS,,,ETH_PPS_OUT,FMC_SDCLK,,LCD_G7,EVENTOUT, +PortG,PG9,,,,,,SPI1_MISO,,SPDIFRX_IN3,USART6_RX,QUADSPI_BK2_IO2,SAI2_FS_B,SDMMC2_D0,FMC_NE2/FMC_NCE,DCMI_VSYNC,,EVENTOUT, +PortG,PG10,,,,,,SPI1_NSS/I2S1_WS,,,,LCD_G3,SAI2_SD_B,SDMMC2_D1,FMC_NE3,DCMI_D2,LCD_B2,EVENTOUT, +PortG,PG11,,,,,,SPI1_SCK/I2S1_CK,,SPDIFRX_IN0,,,SDMMC2_D2,ETH_MII_TX_EN/ETH_RMII_TX_EN,,DCMI_D3,LCD_B3,EVENTOUT, +PortG,PG12,,,,LPTIM1_IN1,,SPI6_MISO,,SPDIFRX_IN1,USART6_RTS,LCD_B4,,SDMMC2_D3,FMC_NE4,,LCD_B1,EVENTOUT, +PortG,PG13,TRACED0,,,LPTIM1_OUT,,SPI6_SCK,,,USART6_CTS,,,ETH_MII_TXD0/ETH_RMII_TXD0,FMC_A24,,LCD_R0,EVENTOUT, +PortG,PG14,TRACED1,,,LPTIM1_ETR,,SPI6_MOSI,,,USART6_TX,QUADSPI_BK2_IO3,,ETH_MII_TXD1/ETH_RMII_TXD1,FMC_A25,,LCD_B0,EVENTOUT, +PortG,PG15,,,,,,,,,USART6_CTS,,,,FMC_SDNCAS,DCMI_D13,,EVENTOUT, +PortH,PH0,,,,,,,,,,,,,,,,EVENTOUT, +PortH,PH1,,,,,,,,,,,,,,,,EVENTOUT, +PortH,PH2,,,,LPTIM1_IN2,,,,,,QUADSPI_BK2_IO0,SAI2_SCK_B,ETH_MII_CRS,FMC_SDCKE0,,LCD_R0,EVENTOUT, +PortH,PH3,,,,,,,,,,QUADSPI_BK2_IO1,SAI2_MCK_B,ETH_MII_COL,FMC_SDNE0,,LCD_R1,EVENTOUT, +PortH,PH4,,,,,I2C2_SCL,,,,,LCD_G5,OTG_HS_ULPI_NXT,,,,LCD_G4,EVENTOUT, +PortH,PH5,,,,,I2C2_SDA,SPI5_NSS,,,,,,,FMC_SDNWE,,,EVENTOUT, +PortH,PH6,,,,,I2C2_SMBA,SPI5_SCK,,,,TIM12_CH1,,ETH_MII_RXD2,FMC_SDNE1,DCMI_D8,,EVENTOUT, +PortH,PH7,,,,,I2C3_SCL,SPI5_MISO,,,,,,ETH_MII_RXD3,FMC_SDCKE1,DCMI_D9,,EVENTOUT, +PortH,PH8,,,,,I2C3_SDA,,,,,,,,FMC_D16,DCMI_HSYNC,LCD_R2,EVENTOUT, +PortH,PH9,,,,,I2C3_SMBA,,,,,TIM12_CH2,,,FMC_D17,DCMI_D0,LCD_R3,EVENTOUT, +PortH,PH10,,,TIM5_CH1,,I2C4_SMBA,,,,,,,,FMC_D18,DCMI_D1,LCD_R4,EVENTOUT, +PortH,PH11,,,TIM5_CH2,,I2C4_SCL,,,,,,,,FMC_D19,DCMI_D2,LCD_R5,EVENTOUT, +PortH,PH12,,,TIM5_CH3,,I2C4_SDA,,,,,,,,FMC_D20,DCMI_D3,LCD_R6,EVENTOUT, +PortH,PH13,,,,TIM8_CH1N,,,,,UART4_TX,CAN1_TX,,,FMC_D21,,LCD_G2,EVENTOUT, +PortH,PH14,,,,TIM8_CH2N,,,,,UART4_RX,CAN1_RX,,,FMC_D22,DCMI_D4,LCD_G3,EVENTOUT, +PortH,PH15,,,,TIM8_CH3N,,,,,,,,,FMC_D23,DCMI_D11,LCD_G4,EVENTOUT, +PortI,PI0,,,TIM5_CH4,,,SPI2_NSS/I2S2_WS,,,,,,,FMC_D24,DCMI_D13,LCD_G5,EVENTOUT, +PortI,PI1,,,,TIM8_BKIN2,,SPI2_SCK/I2S2_CK,,,,,,,FMC_D25,DCMI_D8,LCD_G6,EVENTOUT, +PortI,PI2,,,,TIM8_CH4,,SPI2_MISO,,,,,,,FMC_D26,DCMI_D9,LCD_G7,EVENTOUT, +PortI,PI3,,,,TIM8_ETR,,SPI2_MOSI/I2S2_SD,,,,,,,FMC_D27,DCMI_D10,,EVENTOUT, +PortI,PI4,,,,TIM8_BKIN,,,,,,,SAI2_MCK_A,,FMC_NBL2,DCMI_D5,LCD_B4,EVENTOUT, +PortI,PI5,,,,TIM8_CH1,,,,,,,SAI2_SCK_A,,FMC_NBL3,DCMI_VSYNC,LCD_B5,EVENTOUT, +PortI,PI6,,,,TIM8_CH2,,,,,,,SAI2_SD_A,,FMC_D28,DCMI_D6,LCD_B6,EVENTOUT, +PortI,PI7,,,,TIM8_CH3,,,,,,,SAI2_FS_A,,FMC_D29,DCMI_D7,LCD_B7,EVENTOUT, +PortI,PI8,,,,,,,,,,,,,,,,EVENTOUT, +PortI,PI9,,,,,,,,,UART4_RX,CAN1_RX,,,FMC_D30,,LCD_VSYNC,EVENTOUT, +PortI,PI10,,,,,,,,,,,,ETH_MII_RX_ER,FMC_D31,,LCD_HSYNC,EVENTOUT, +PortI,PI11,,,,,,,,,,LCD_G6,OTG_HS_ULPI_DIR,,,,,EVENTOUT, +PortI,PI12,,,,,,,,,,,,,,,LCD_HSYNC,EVENTOUT, +PortI,PI13,,,,,,,,,,,,,,,LCD_VSYNC,EVENTOUT, +PortI,PI14,,,,,,,,,,,,,,,LCD_CLK,EVENTOUT, +PortI,PI15,,,,,,,,,,LCD_G2,,,,,LCD_R0,EVENTOUT, +PortJ,PJ0,,,,,,,,,,LCD_R7,,,,,LCD_R1,EVENTOUT, +PortJ,PJ1,,,,,,,,,,,,,,,LCD_R2,EVENTOUT, +PortJ,PJ2,,,,,,,,,,,,,,DSI_TE,LCD_R3,EVENTOUT, +PortJ,PJ3,,,,,,,,,,,,,,,LCD_R4,EVENTOUT, +PortJ,PJ4,,,,,,,,,,,,,,,LCD_R5,EVENTOUT, +PortJ,PJ5,,,,,,,,,,,,,,,LCD_R6,EVENTOUT, +PortJ,PJ6,,,,,,,,,,,,,,,LCD_R7,EVENTOUT, +PortJ,PJ7,,,,,,,,,,,,,,,LCD_G0,EVENTOUT, +PortJ,PJ8,,,,,,,,,,,,,,,LCD_G1,EVENTOUT, +PortJ,PJ9,,,,,,,,,,,,,,,LCD_G2,EVENTOUT, +PortJ,PJ10,,,,,,,,,,,,,,,LCD_G3,EVENTOUT, +PortJ,PJ11,,,,,,,,,,,,,,,LCD_G4,EVENTOUT, +PortJ,PJ12,,,,,,,,,,LCD_G3,,,,,LCD_B0,EVENTOUT, +PortJ,PJ13,,,,,,,,,,LCD_G4,,,,,LCD_B1,EVENTOUT, +PortJ,PJ14,,,,,,,,,,,,,,,LCD_B2,EVENTOUT, +PortJ,PJ15,,,,,,,,,,,,,,,LCD_B3,EVENTOUT, +PortK,PK0,,,,,,,,,,,,,,,LCD_G5,EVENTOUT, +PortK,PK1,,,,,,,,,,,,,,,LCD_G6,EVENTOUT, +PortK,PK2,,,,,,,,,,,,,,,LCD_G7,EVENTOUT, +PortK,PK3,,,,,,,,,,,,,,,LCD_B4,EVENTOUT, +PortK,PK4,,,,,,,,,,,,,,,LCD_B5,EVENTOUT, +PortK,PK5,,,,,,,,,,,,,,,LCD_B6,EVENTOUT, +PortK,PK6,,,,,,,,,,,,,,,LCD_B7,EVENTOUT, +PortK,PK7,,,,,,,,,,,,,,,LCD_DE,EVENTOUT, From 9761672d42c489af215a8873ddfa71b62434623c Mon Sep 17 00:00:00 2001 From: Lucian Copeland Date: Thu, 2 Apr 2020 16:15:12 -0400 Subject: [PATCH 08/17] Linker file restructure, TCM and MPU additions --- ports/stm/Makefile | 17 +- ports/stm/boards/STM32F401xd_fs.ld | 83 +------- ports/stm/boards/STM32F401xe_boot.ld | 82 +------- ports/stm/boards/STM32F401xe_fs.ld | 81 -------- ports/stm/boards/STM32F405_boot.ld | 80 -------- ports/stm/boards/STM32F405_default.ld | 82 +------- ports/stm/boards/STM32F405_fs.ld | 82 +------- ports/stm/boards/STM32F407_fs.ld | 82 +------- ports/stm/boards/STM32F411_fs.ld | 27 +++ ports/stm/boards/STM32F411_nvm.ld | 27 +++ ports/stm/boards/STM32F412_fs.ld | 27 +++ ports/stm/boards/STM32F767ZITx_FLASH.ld | 189 ------------------ ports/stm/boards/STM32F767_fs.ld | 82 +------- ports/stm/boards/STM32H743_fs.ld | 179 +---------------- ...M32F412ZGTx_FLASH.ld => common_default.ld} | 46 ++--- .../{STM32F411VETx_FLASH.ld => common_nvm.ld} | 56 +++--- ...M32F411VETx_nvm_FLASH.ld => common_tcm.ld} | 101 ++++++---- .../stm/boards/espruino_pico/mpconfigboard.mk | 1 + .../stm/boards/espruino_wifi/mpconfigboard.mk | 3 +- .../mpconfigboard.mk | 1 + .../stm/boards/meowbit_v121/mpconfigboard.mk | 1 + .../stm/boards/nucleo_f767zi/mpconfigboard.mk | 1 + .../boards/nucleo_h743zi_2/mpconfigboard.mk | 1 + ports/stm/boards/pyb_nano_v2/mpconfigboard.mk | 3 +- ports/stm/boards/pyboard_v11/mpconfigboard.mk | 1 + .../stm32f411ce_blackpill/mpconfigboard.mk | 3 +- .../stm32f411ve_discovery/mpconfigboard.mk | 3 +- .../stm32f412zg_discovery/mpconfigboard.mk | 3 +- .../boards/stm32f4_discovery/mpconfigboard.mk | 1 + ports/stm/boards/thunderpack/mpconfigboard.mk | 11 +- ports/stm/mpconfigport.h | 7 +- ports/stm/packages/LQFP100_f4.c | 2 +- ports/stm/packages/LQFP64.c | 2 +- ports/stm/supervisor/port.c | 168 +++++++++++++++- supervisor/linker.h | 2 +- supervisor/shared/stack.c | 2 +- 36 files changed, 406 insertions(+), 1133 deletions(-) create mode 100644 ports/stm/boards/STM32F411_fs.ld create mode 100644 ports/stm/boards/STM32F411_nvm.ld create mode 100644 ports/stm/boards/STM32F412_fs.ld delete mode 100644 ports/stm/boards/STM32F767ZITx_FLASH.ld rename ports/stm/boards/{STM32F412ZGTx_FLASH.ld => common_default.ld} (68%) rename ports/stm/boards/{STM32F411VETx_FLASH.ld => common_nvm.ld} (69%) rename ports/stm/boards/{STM32F411VETx_nvm_FLASH.ld => common_tcm.ld} (62%) diff --git a/ports/stm/Makefile b/ports/stm/Makefile index 9b90079381eec..ec15e4f7f6dd9 100755 --- a/ports/stm/Makefile +++ b/ports/stm/Makefile @@ -93,7 +93,8 @@ endif # MCU Series is defined by the HAL package and doesn't need to be specified here C_DEFS = -D$(MCU_PACKAGE) -DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER -D$(MCU_VARIANT) -CFLAGS += $(INC) -Werror -Wall -std=gnu11 -nostdlib $(BASE_CFLAGS) $(C_DEFS) $(CFLAGS_MOD) $(COPT) +CFLAGS += $(INC) -Werror -Wall -std=gnu11 $(BASE_CFLAGS) $(C_DEFS) $(CFLAGS_MOD) $(COPT) +# Removed -nostdlib since it conflicts with stm32 startup files # Undo some warnings. # STM32 HAL uses undefined preprocessor variables, shadowed variables, casts that change alignment reqs @@ -107,6 +108,7 @@ MCU_FLAGS_F7 = -mcpu=cortex-m7 MCU_FLAGS_H7 = -mcpu=cortex-m7 CFLAGS += $(MCU_FLAGS_$(MCU_SERIES)) +# Select HAL file for distribution via mpconfigport CFLAGS += -DSTM32_HAL_H='' # Floating point settings @@ -132,7 +134,7 @@ ifndef BOOTLOADER_OFFSET BOOTLOADER_OFFSET := 0x8000000 endif -LDFLAGS = $(CFLAGS) -fshort-enums -Wl,-nostdlib -Wl,-T,$(LD_FILE) -Wl,-Map=$@.map -Wl,-cref -Wl,-gc-sections -specs=nano.specs +LDFLAGS = $(CFLAGS) -fshort-enums -Wl,-nostdlib -Wl,-T,$(LD_FILE) -Wl,-T,$(LD_COMMON) -Wl,-Map=$@.map -Wl,-cref -Wl,-gc-sections -specs=nano.specs LIBS := -lgcc -lc LDFLAGS += -mthumb $(MCU_FLAGS_$(MCU_SERIES)) @@ -143,7 +145,13 @@ LIBS += -lm endif # TinyUSB defines -CFLAGS += -DCFG_TUSB_MCU=OPT_MCU_STM32$(MCU_SERIES) -DCFG_TUD_CDC_RX_BUFSIZE=1024 -DCFG_TUD_CDC_TX_BUFSIZE=1024 -DCFG_TUD_MSC_BUFSIZE=4096 -DCFG_TUD_MIDI_RX_BUFSIZE=128 -DCFG_TUD_MIDI_TX_BUFSIZE=128 +CFLAGS += \ + -DCFG_TUSB_MCU=OPT_MCU_STM32$(MCU_SERIES) \ + -DCFG_TUD_CDC_RX_BUFSIZE=1024 \ + -DCFG_TUD_CDC_TX_BUFSIZE=1024 \ + -DCFG_TUD_MSC_BUFSIZE=4096 \ + -DCFG_TUD_MIDI_RX_BUFSIZE=128 \ + -DCFG_TUD_MIDI_TX_BUFSIZE=128 SRC_STM32 = $(addprefix $(HAL_DIR)/Src/stm32$(MCU_SERIES_LOWER)xx_,\ hal_adc.c \ @@ -218,7 +226,7 @@ endif SRC_S = \ supervisor/cpu.s \ - boards/startup_$(MCU_VARIANT_LOWER).s + st_driver/CMSIS/Device/ST/STM32$(MCU_SERIES)xx/Source/Templates/gcc/startup_$(MCU_VARIANT_LOWER).s SRC_COMMON_HAL_EXPANDED = $(addprefix shared-bindings/, $(SRC_COMMON_HAL)) \ $(addprefix shared-bindings/, $(SRC_BINDINGS_ENUMS)) \ @@ -241,6 +249,7 @@ OBJ += $(addprefix $(BUILD)/, $(SRC_SHARED_MODULE_EXPANDED:.c=.o)) ifeq ($(INTERNAL_LIBM),1) OBJ += $(addprefix $(BUILD)/, $(SRC_LIBM:.c=.o)) endif +#OBJ += $(addprefix $(BUILD)/, $(SRC_O)) OBJ += $(addprefix $(BUILD)/, $(SRC_S:.s=.o)) OBJ += $(addprefix $(BUILD)/, $(SRC_MOD:.c=.o)) diff --git a/ports/stm/boards/STM32F401xd_fs.ld b/ports/stm/boards/STM32F401xd_fs.ld index c42dfcca8c976..826e1d4043526 100644 --- a/ports/stm/boards/STM32F401xd_fs.ld +++ b/ports/stm/boards/STM32F401xd_fs.ld @@ -1,5 +1,5 @@ /* - GNU linker script for STM32F401 with bootloader (such as the Meowbit) + GNU linker script for STM32F401 with filesystem */ /* Specify the memory areas */ @@ -24,84 +24,3 @@ _estack = ORIGIN(RAM) + LENGTH(RAM); /* RAM extents for the garbage collector */ _ram_start = ORIGIN(RAM); _ram_end = ORIGIN(RAM) + LENGTH(RAM); - -ENTRY(Reset_Handler) - -/* define output sections */ -SECTIONS -{ - /* The startup code goes first into FLASH */ - .isr_vector : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - - /* This first flash block is 16K annd the isr vectors only take up - about 400 bytes. Micropython pads this with files, but this didn't - work with the size of Circuitpython's ff object. */ - - . = ALIGN(4); - } >FLASH_ISR - - /* The program code and other data goes into FLASH */ - .text : - { - . = ALIGN(4); - *(.text*) /* .text* sections (code) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - /* *(.glue_7) */ /* glue arm to thumb code */ - /* *(.glue_7t) */ /* glue thumb to arm code */ - - . = ALIGN(4); - _etext = .; /* define a global symbol at end of code */ - } >FLASH_TEXT - - /* used by the startup to initialize data */ - _sidata = LOADADDR(.data); - - /* This is the initialized data section - The program executes knowing that the data is in the RAM - but the loader puts the initial values in the FLASH (inidata). - It is one task of the startup to copy the initial values from FLASH to RAM. */ - .data : - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM */ - *(.data*) /* .data* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */ - } >RAM AT> FLASH_TEXT - - /* Uninitialized data section */ - .bss : - { - . = ALIGN(4); - _sbss = .; /* define a global symbol at bss start; used by startup code */ - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end; used by startup code and GC */ - } >RAM - - /* this is to define the start of the heap, and make sure we have a minimum size */ - .heap : - { - . = ALIGN(4); - . = . + _minimum_heap_size; - . = ALIGN(4); - } >RAM - - /* this just checks there is enough RAM for the stack */ - .stack : - { - . = ALIGN(4); - . = . + _minimum_stack_size; - . = ALIGN(4); - } >RAM - - .ARM.attributes 0 : { *(.ARM.attributes) } -} - - diff --git a/ports/stm/boards/STM32F401xe_boot.ld b/ports/stm/boards/STM32F401xe_boot.ld index 125d785fc228d..17dac2f1a6aed 100644 --- a/ports/stm/boards/STM32F401xe_boot.ld +++ b/ports/stm/boards/STM32F401xe_boot.ld @@ -1,5 +1,5 @@ /* - GNU linker script for STM32F401 with bootloader (such as the Meowbit) + GNU linker script for STM32F401 with bootloader (such as the Meowbit). No internal fs. */ /* Specify the memory areas */ @@ -24,83 +24,3 @@ _estack = ORIGIN(RAM) + LENGTH(RAM); _ram_start = ORIGIN(RAM); _ram_end = ORIGIN(RAM) + LENGTH(RAM); -ENTRY(Reset_Handler) - -/* define output sections */ -SECTIONS -{ - /* The startup code goes first into FLASH */ - .isr_vector : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - - /* This first flash block is 16K annd the isr vectors only take up - about 400 bytes. Micropython pads this with files, but this didn't - work with the size of Circuitpython's ff object. */ - - . = ALIGN(4); - } >FLASH_ISR - - /* The program code and other data goes into FLASH */ - .text : - { - . = ALIGN(4); - *(.text*) /* .text* sections (code) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - /* *(.glue_7) */ /* glue arm to thumb code */ - /* *(.glue_7t) */ /* glue thumb to arm code */ - - . = ALIGN(4); - _etext = .; /* define a global symbol at end of code */ - } >FLASH_TEXT - - /* used by the startup to initialize data */ - _sidata = LOADADDR(.data); - - /* This is the initialized data section - The program executes knowing that the data is in the RAM - but the loader puts the initial values in the FLASH (inidata). - It is one task of the startup to copy the initial values from FLASH to RAM. */ - .data : - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM */ - *(.data*) /* .data* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */ - } >RAM AT> FLASH_TEXT - - /* Uninitialized data section */ - .bss : - { - . = ALIGN(4); - _sbss = .; /* define a global symbol at bss start; used by startup code */ - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end; used by startup code and GC */ - } >RAM - - /* this is to define the start of the heap, and make sure we have a minimum size */ - .heap : - { - . = ALIGN(4); - . = . + _minimum_heap_size; - . = ALIGN(4); - } >RAM - - /* this just checks there is enough RAM for the stack */ - .stack : - { - . = ALIGN(4); - . = . + _minimum_stack_size; - . = ALIGN(4); - } >RAM - - .ARM.attributes 0 : { *(.ARM.attributes) } -} - - diff --git a/ports/stm/boards/STM32F401xe_fs.ld b/ports/stm/boards/STM32F401xe_fs.ld index fd30e16228dd0..f0136943adac5 100644 --- a/ports/stm/boards/STM32F401xe_fs.ld +++ b/ports/stm/boards/STM32F401xe_fs.ld @@ -24,84 +24,3 @@ _estack = ORIGIN(RAM) + LENGTH(RAM); /* RAM extents for the garbage collector */ _ram_start = ORIGIN(RAM); _ram_end = ORIGIN(RAM) + LENGTH(RAM); - -ENTRY(Reset_Handler) - -/* define output sections */ -SECTIONS -{ - /* The startup code goes first into FLASH */ - .isr_vector : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - - /* This first flash block is 16K annd the isr vectors only take up - about 400 bytes. Micropython pads this with files, but this didn't - work with the size of Circuitpython's ff object. */ - - . = ALIGN(4); - } >FLASH_ISR - - /* The program code and other data goes into FLASH */ - .text : - { - . = ALIGN(4); - *(.text*) /* .text* sections (code) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - /* *(.glue_7) */ /* glue arm to thumb code */ - /* *(.glue_7t) */ /* glue thumb to arm code */ - - . = ALIGN(4); - _etext = .; /* define a global symbol at end of code */ - } >FLASH_TEXT - - /* used by the startup to initialize data */ - _sidata = LOADADDR(.data); - - /* This is the initialized data section - The program executes knowing that the data is in the RAM - but the loader puts the initial values in the FLASH (inidata). - It is one task of the startup to copy the initial values from FLASH to RAM. */ - .data : - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM */ - *(.data*) /* .data* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */ - } >RAM AT> FLASH_TEXT - - /* Uninitialized data section */ - .bss : - { - . = ALIGN(4); - _sbss = .; /* define a global symbol at bss start; used by startup code */ - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end; used by startup code and GC */ - } >RAM - - /* this is to define the start of the heap, and make sure we have a minimum size */ - .heap : - { - . = ALIGN(4); - . = . + _minimum_heap_size; - . = ALIGN(4); - } >RAM - - /* this just checks there is enough RAM for the stack */ - .stack : - { - . = ALIGN(4); - . = . + _minimum_stack_size; - . = ALIGN(4); - } >RAM - - .ARM.attributes 0 : { *(.ARM.attributes) } -} - - diff --git a/ports/stm/boards/STM32F405_boot.ld b/ports/stm/boards/STM32F405_boot.ld index 64da3b6520e4a..7e611be9d8e62 100644 --- a/ports/stm/boards/STM32F405_boot.ld +++ b/ports/stm/boards/STM32F405_boot.ld @@ -1,6 +1,5 @@ /* GNU linker script for STM32F405 with bootloader - Based on Micropython */ /* Specify the memory areas */ @@ -26,82 +25,3 @@ _estack = ORIGIN(RAM) + LENGTH(RAM); _ram_start = ORIGIN(RAM); _ram_end = ORIGIN(RAM) + LENGTH(RAM); -ENTRY(Reset_Handler) - -/* define output sections */ -SECTIONS -{ - /* The startup code goes first into FLASH */ - .isr_vector : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - - /* This first flash block is 16K annd the isr vectors only take up - about 400 bytes. Micropython pads this with files, but this didn't - work with the size of Circuitpython's ff object. */ - - . = ALIGN(4); - } >FLASH_ISR - - /* The program code and other data goes into FLASH */ - .text : - { - . = ALIGN(4); - *(.text*) /* .text* sections (code) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - /* *(.glue_7) */ /* glue arm to thumb code */ - /* *(.glue_7t) */ /* glue thumb to arm code */ - - . = ALIGN(4); - _etext = .; /* define a global symbol at end of code */ - } >FLASH_TEXT - - /* used by the startup to initialize data */ - _sidata = LOADADDR(.data); - - /* This is the initialized data section - The program executes knowing that the data is in the RAM - but the loader puts the initial values in the FLASH (inidata). - It is one task of the startup to copy the initial values from FLASH to RAM. */ - .data : - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM */ - *(.data*) /* .data* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */ - } >RAM AT> FLASH_TEXT - - /* Uninitialized data section */ - .bss : - { - . = ALIGN(4); - _sbss = .; /* define a global symbol at bss start; used by startup code */ - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end; used by startup code and GC */ - } >RAM - - /* this is to define the start of the heap, and make sure we have a minimum size */ - .heap : - { - . = ALIGN(4); - . = . + _minimum_heap_size; - . = ALIGN(4); - } >RAM - - /* this just checks there is enough RAM for the stack */ - .stack : - { - . = ALIGN(4); - . = . + _minimum_stack_size; - . = ALIGN(4); - } >RAM - - .ARM.attributes 0 : { *(.ARM.attributes) } -} - diff --git a/ports/stm/boards/STM32F405_default.ld b/ports/stm/boards/STM32F405_default.ld index c2b8c843ee448..6b497356dd2d1 100644 --- a/ports/stm/boards/STM32F405_default.ld +++ b/ports/stm/boards/STM32F405_default.ld @@ -1,5 +1,5 @@ /* - GNU linker script for STM32F405 via Micropython + GNU linker script for STM32F405, no filesystem */ /* Specify the memory areas */ @@ -25,83 +25,3 @@ _estack = ORIGIN(RAM) + LENGTH(RAM); _ram_start = ORIGIN(RAM); _ram_end = ORIGIN(RAM) + LENGTH(RAM); -ENTRY(Reset_Handler) - -/* define output sections */ -SECTIONS -{ - /* The startup code goes first into FLASH */ - .isr_vector : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - - /* This first flash block is 16K annd the isr vectors only take up - about 400 bytes. Micropython pads this with files, but this didn't - work with the size of Circuitpython's ff object. */ - - . = ALIGN(4); - } >FLASH_ISR - - /* The program code and other data goes into FLASH */ - .text : - { - . = ALIGN(4); - *(.text*) /* .text* sections (code) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - /* *(.glue_7) */ /* glue arm to thumb code */ - /* *(.glue_7t) */ /* glue thumb to arm code */ - - . = ALIGN(4); - _etext = .; /* define a global symbol at end of code */ - } >FLASH_TEXT - - /* used by the startup to initialize data */ - _sidata = LOADADDR(.data); - - /* This is the initialized data section - The program executes knowing that the data is in the RAM - but the loader puts the initial values in the FLASH (inidata). - It is one task of the startup to copy the initial values from FLASH to RAM. */ - .data : - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM */ - *(.data*) /* .data* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */ - } >RAM AT> FLASH_TEXT - - /* Uninitialized data section */ - .bss : - { - . = ALIGN(4); - _sbss = .; /* define a global symbol at bss start; used by startup code */ - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end; used by startup code and GC */ - } >RAM - - /* this is to define the start of the heap, and make sure we have a minimum size */ - .heap : - { - . = ALIGN(4); - . = . + _minimum_heap_size; - . = ALIGN(4); - } >RAM - - /* this just checks there is enough RAM for the stack */ - .stack : - { - . = ALIGN(4); - . = . + _minimum_stack_size; - . = ALIGN(4); - } >RAM - - .ARM.attributes 0 : { *(.ARM.attributes) } -} - - diff --git a/ports/stm/boards/STM32F405_fs.ld b/ports/stm/boards/STM32F405_fs.ld index 7f7c917846662..72ee49633cff2 100644 --- a/ports/stm/boards/STM32F405_fs.ld +++ b/ports/stm/boards/STM32F405_fs.ld @@ -1,5 +1,5 @@ /* - GNU linker script for STM32F405 via Micropython + GNU linker script for STM32F405 with filesystem */ /* Specify the memory areas */ @@ -26,83 +26,3 @@ _estack = ORIGIN(RAM) + LENGTH(RAM); _ram_start = ORIGIN(RAM); _ram_end = ORIGIN(RAM) + LENGTH(RAM); -ENTRY(Reset_Handler) - -/* define output sections */ -SECTIONS -{ - /* The startup code goes first into FLASH */ - .isr_vector : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - - /* This first flash block is 16K annd the isr vectors only take up - about 400 bytes. Micropython pads this with files, but this didn't - work with the size of Circuitpython's ff object. */ - - . = ALIGN(4); - } >FLASH_ISR - - /* The program code and other data goes into FLASH */ - .text : - { - . = ALIGN(4); - *(.text*) /* .text* sections (code) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - /* *(.glue_7) */ /* glue arm to thumb code */ - /* *(.glue_7t) */ /* glue thumb to arm code */ - - . = ALIGN(4); - _etext = .; /* define a global symbol at end of code */ - } >FLASH_TEXT - - /* used by the startup to initialize data */ - _sidata = LOADADDR(.data); - - /* This is the initialized data section - The program executes knowing that the data is in the RAM - but the loader puts the initial values in the FLASH (inidata). - It is one task of the startup to copy the initial values from FLASH to RAM. */ - .data : - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM */ - *(.data*) /* .data* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */ - } >RAM AT> FLASH_TEXT - - /* Uninitialized data section */ - .bss : - { - . = ALIGN(4); - _sbss = .; /* define a global symbol at bss start; used by startup code */ - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end; used by startup code and GC */ - } >RAM - - /* this is to define the start of the heap, and make sure we have a minimum size */ - .heap : - { - . = ALIGN(4); - . = . + _minimum_heap_size; - . = ALIGN(4); - } >RAM - - /* this just checks there is enough RAM for the stack */ - .stack : - { - . = ALIGN(4); - . = . + _minimum_stack_size; - . = ALIGN(4); - } >RAM - - .ARM.attributes 0 : { *(.ARM.attributes) } -} - - diff --git a/ports/stm/boards/STM32F407_fs.ld b/ports/stm/boards/STM32F407_fs.ld index 7f7c917846662..d08cb8972c0a5 100644 --- a/ports/stm/boards/STM32F407_fs.ld +++ b/ports/stm/boards/STM32F407_fs.ld @@ -1,5 +1,5 @@ /* - GNU linker script for STM32F405 via Micropython + GNU linker script for STM32F407 with filesystem */ /* Specify the memory areas */ @@ -26,83 +26,3 @@ _estack = ORIGIN(RAM) + LENGTH(RAM); _ram_start = ORIGIN(RAM); _ram_end = ORIGIN(RAM) + LENGTH(RAM); -ENTRY(Reset_Handler) - -/* define output sections */ -SECTIONS -{ - /* The startup code goes first into FLASH */ - .isr_vector : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - - /* This first flash block is 16K annd the isr vectors only take up - about 400 bytes. Micropython pads this with files, but this didn't - work with the size of Circuitpython's ff object. */ - - . = ALIGN(4); - } >FLASH_ISR - - /* The program code and other data goes into FLASH */ - .text : - { - . = ALIGN(4); - *(.text*) /* .text* sections (code) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - /* *(.glue_7) */ /* glue arm to thumb code */ - /* *(.glue_7t) */ /* glue thumb to arm code */ - - . = ALIGN(4); - _etext = .; /* define a global symbol at end of code */ - } >FLASH_TEXT - - /* used by the startup to initialize data */ - _sidata = LOADADDR(.data); - - /* This is the initialized data section - The program executes knowing that the data is in the RAM - but the loader puts the initial values in the FLASH (inidata). - It is one task of the startup to copy the initial values from FLASH to RAM. */ - .data : - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM */ - *(.data*) /* .data* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */ - } >RAM AT> FLASH_TEXT - - /* Uninitialized data section */ - .bss : - { - . = ALIGN(4); - _sbss = .; /* define a global symbol at bss start; used by startup code */ - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end; used by startup code and GC */ - } >RAM - - /* this is to define the start of the heap, and make sure we have a minimum size */ - .heap : - { - . = ALIGN(4); - . = . + _minimum_heap_size; - . = ALIGN(4); - } >RAM - - /* this just checks there is enough RAM for the stack */ - .stack : - { - . = ALIGN(4); - . = . + _minimum_stack_size; - . = ALIGN(4); - } >RAM - - .ARM.attributes 0 : { *(.ARM.attributes) } -} - - diff --git a/ports/stm/boards/STM32F411_fs.ld b/ports/stm/boards/STM32F411_fs.ld new file mode 100644 index 0000000000000..28667214e02d9 --- /dev/null +++ b/ports/stm/boards/STM32F411_fs.ld @@ -0,0 +1,27 @@ +/* + GNU linker script for STM32F411 with filesystem +*/ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K /* entire flash */ + FLASH_ISR (rx) : ORIGIN = 0x08000000, LENGTH = 16K /* sector 0 */ + FLASH_FS (rx) : ORIGIN = 0x08004000, LENGTH = 48K /* sectors 1,2,3 are 16K */ + FLASH_TEXT (rx) : ORIGIN = 0x08010000, LENGTH = 448K /* sector 4 is 64K, sectors 5,6,7 are 128K */ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K +} + +/* produce a link error if there is not this amount of RAM for these sections */ +_minimum_stack_size = 2K; +_minimum_heap_size = 16K; + +/* Define tho top end of the stack. The stack is full descending so begins just + above last byte of RAM. Note that EABI requires the stack to be 8-byte + aligned for a call. */ +_estack = ORIGIN(RAM) + LENGTH(RAM); + +/* RAM extents for the garbage collector */ +_ram_start = ORIGIN(RAM); +_ram_end = ORIGIN(RAM) + LENGTH(RAM); + diff --git a/ports/stm/boards/STM32F411_nvm.ld b/ports/stm/boards/STM32F411_nvm.ld new file mode 100644 index 0000000000000..bb37c081b3a4e --- /dev/null +++ b/ports/stm/boards/STM32F411_nvm.ld @@ -0,0 +1,27 @@ +/* + GNU linker script for STM32F411 with nvm +*/ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K /* entire flash */ + FLASH_ISR (rx) : ORIGIN = 0x08000000, LENGTH = 16K /* sector 0 */ + FLASH_FS (rx) : ORIGIN = 0x08004000, LENGTH = 32K /* sectors 1,2 are 16K */ + FLASH_NVM (rwx) : ORIGIN = 0x0800C000, LENGTH = 16K /* sector 3 is 16K */ + FLASH_TEXT (rx) : ORIGIN = 0x08010000, LENGTH = 448K /* sector 4 is 64K, sectors 5,6,7 are 128K */ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K +} + +/* produce a link error if there is not this amount of RAM for these sections */ +_minimum_stack_size = 2K; +_minimum_heap_size = 16K; + +/* Define the top end of the stack. The stack is full descending so begins just + above last byte of RAM. Note that EABI requires the stack to be 8-byte + aligned for a call. */ +_estack = ORIGIN(RAM) + LENGTH(RAM); + +/* RAM extents for the garbage collector */ +_ram_start = ORIGIN(RAM); +_ram_end = ORIGIN(RAM) + LENGTH(RAM); diff --git a/ports/stm/boards/STM32F412_fs.ld b/ports/stm/boards/STM32F412_fs.ld new file mode 100644 index 0000000000000..5985b209e4124 --- /dev/null +++ b/ports/stm/boards/STM32F412_fs.ld @@ -0,0 +1,27 @@ +/* + GNU linker script for STM32F412 with filesystem, tcm +*/ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K /* entire flash */ + FLASH_ISR (rx) : ORIGIN = 0x08000000, LENGTH = 16K /* sector 0 */ + FLASH_FS (rx) : ORIGIN = 0x08004000, LENGTH = 48K /* sectors 1,2,3 are 16K */ + FLASH_TEXT (rx) : ORIGIN = 0x08010000, LENGTH = 960K /* sector 4 is 64K, sectors 5,6,7 are 128K */ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 256K +} + +/* produce a link error if there is not this amount of RAM for these sections */ +_minimum_stack_size = 2K; +_minimum_heap_size = 16K; + +/* Define tho top end of the stack. The stack is full descending so begins just + above last byte of RAM. Note that EABI requires the stack to be 8-byte + aligned for a call. */ +_estack = ORIGIN(RAM) + LENGTH(RAM); + +/* RAM extents for the garbage collector */ +_ram_start = ORIGIN(RAM); +_ram_end = ORIGIN(RAM) + LENGTH(RAM); + diff --git a/ports/stm/boards/STM32F767ZITx_FLASH.ld b/ports/stm/boards/STM32F767ZITx_FLASH.ld deleted file mode 100644 index 78a794402d2d6..0000000000000 --- a/ports/stm/boards/STM32F767ZITx_FLASH.ld +++ /dev/null @@ -1,189 +0,0 @@ -/* -****************************************************************************** -** - -** File : LinkerScript.ld -** -** Author : Auto-generated by System Workbench for STM32 -** -** Abstract : Linker script for STM32F767ZITx series -** 2048Kbytes FLASH and 512Kbytes RAM -** -** Set heap size, stack size and stack location according -** to application requirements. -** -** Set memory bank area and size if external memory is used. -** -** Target : STMicroelectronics STM32 -** -** Distribution: The file is distributed “as is,” without any warranty -** of any kind. -** -***************************************************************************** -** @attention -** -**

© COPYRIGHT(c) 2019 STMicroelectronics

-** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** 1. Redistributions of source code must retain the above copyright notice, -** this list of conditions and the following disclaimer. -** 2. Redistributions in binary form must reproduce the above copyright notice, -** this list of conditions and the following disclaimer in the documentation -** and/or other materials provided with the distribution. -** 3. Neither the name of STMicroelectronics nor the names of its contributors -** may be used to endorse or promote products derived from this software -** without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -***************************************************************************** -*/ - -/* Entry Point */ -ENTRY(Reset_Handler) - -/* Highest address of the user mode stack */ -_estack = 0x20080000; /* end of RAM */ -/* Generate a link error if heap and stack don't fit into RAM */ -_Min_Heap_Size = 0x200; /* required amount of heap */ -_Min_Stack_Size = 0x400; /* required amount of stack */ - -/* Specify the memory areas */ -MEMORY -{ -RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 512K -FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 2048K -} - -/* Define output sections */ -SECTIONS -{ - /* The startup code goes first into FLASH */ - .isr_vector : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } >FLASH - - /* The program code and other data goes into FLASH */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - - KEEP (*(.init)) - KEEP (*(.fini)) - - . = ALIGN(4); - _etext = .; /* define a global symbols at end of code */ - } >FLASH - - /* Constant data goes into FLASH */ - .rodata : - { - . = ALIGN(4); - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - . = ALIGN(4); - } >FLASH - - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } >FLASH - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } >FLASH - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } >FLASH - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } >FLASH - - /* used by the startup to initialize data */ - _sidata = LOADADDR(.data); - - /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end */ - } >RAM AT> FLASH - - - /* Uninitialized data section */ - . = ALIGN(4); - .bss : - { - /* This is used by the startup in order to initialize the .bss secion */ - _sbss = .; /* define a global symbol at bss start */ - __bss_start__ = _sbss; - *(.bss) - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end */ - __bss_end__ = _ebss; - } >RAM - - /* User_heap_stack section, used to check that there is enough RAM left */ - ._user_heap_stack : - { - . = ALIGN(8); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - . = . + _Min_Heap_Size; - . = . + _Min_Stack_Size; - . = ALIGN(8); - } >RAM - - - - /* Remove information from the standard libraries */ - /DISCARD/ : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - - .ARM.attributes 0 : { *(.ARM.attributes) } -} - - diff --git a/ports/stm/boards/STM32F767_fs.ld b/ports/stm/boards/STM32F767_fs.ld index f0fb2d323d702..40f7d740ae2d2 100644 --- a/ports/stm/boards/STM32F767_fs.ld +++ b/ports/stm/boards/STM32F767_fs.ld @@ -1,5 +1,5 @@ /* - GNU linker script for STM32F405 via Micropython + GNU linker script for STM32F767 with filesystem */ /* Specify the memory areas */ @@ -25,83 +25,3 @@ _estack = ORIGIN(RAM) + LENGTH(RAM); _ram_start = ORIGIN(RAM); _ram_end = ORIGIN(RAM) + LENGTH(RAM); -ENTRY(Reset_Handler) - -/* define output sections */ -SECTIONS -{ - /* The startup code goes first into FLASH */ - .isr_vector : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - - /* This first flash block is 16K annd the isr vectors only take up - about 400 bytes. Micropython pads this with files, but this didn't - work with the size of Circuitpython's ff object. */ - - . = ALIGN(4); - } >FLASH_ISR - - /* The program code and other data goes into FLASH */ - .text : - { - . = ALIGN(4); - *(.text*) /* .text* sections (code) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - /* *(.glue_7) */ /* glue arm to thumb code */ - /* *(.glue_7t) */ /* glue thumb to arm code */ - - . = ALIGN(4); - _etext = .; /* define a global symbol at end of code */ - } >FLASH_TEXT - - /* used by the startup to initialize data */ - _sidata = LOADADDR(.data); - - /* This is the initialized data section - The program executes knowing that the data is in the RAM - but the loader puts the initial values in the FLASH (inidata). - It is one task of the startup to copy the initial values from FLASH to RAM. */ - .data : - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM */ - *(.data*) /* .data* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */ - } >RAM AT> FLASH_TEXT - - /* Uninitialized data section */ - .bss : - { - . = ALIGN(4); - _sbss = .; /* define a global symbol at bss start; used by startup code */ - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end; used by startup code and GC */ - } >RAM - - /* this is to define the start of the heap, and make sure we have a minimum size */ - .heap : - { - . = ALIGN(4); - . = . + _minimum_heap_size; - . = ALIGN(4); - } >RAM - - /* this just checks there is enough RAM for the stack */ - .stack : - { - . = ALIGN(4); - . = . + _minimum_stack_size; - . = ALIGN(4); - } >RAM - - .ARM.attributes 0 : { *(.ARM.attributes) } -} - - diff --git a/ports/stm/boards/STM32H743_fs.ld b/ports/stm/boards/STM32H743_fs.ld index fdeab9a3d0f9c..28cc12b4aa282 100644 --- a/ports/stm/boards/STM32H743_fs.ld +++ b/ports/stm/boards/STM32H743_fs.ld @@ -1,59 +1,11 @@ /* -****************************************************************************** -** - -** File : LinkerScript.ld -** -** Author : Auto-generated by System Workbench for STM32 -** -** Abstract : Linker script for STM32H743ZITx series -** 2048Kbytes FLASH and 1056Kbytes RAM -** -** Set heap size, stack size and stack location according -** to application requirements. -** -** Set memory bank area and size if external memory is used. -** -** Target : STMicroelectronics STM32 -** -** Distribution: The file is distributed “as is,” without any warranty -** of any kind. -** -***************************************************************************** -** @attention -** -**

© COPYRIGHT(c) 2019 STMicroelectronics

-** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** 1. Redistributions of source code must retain the above copyright notice, -** this list of conditions and the following disclaimer. -** 2. Redistributions in binary form must reproduce the above copyright notice, -** this list of conditions and the following disclaimer in the documentation -** and/or other materials provided with the distribution. -** 3. Neither the name of STMicroelectronics nor the names of its contributors -** may be used to endorse or promote products derived from this software -** without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -***************************************************************************** + GNU linker script for STM32H743 with filesystem, tcm */ /* Entry Point */ ENTRY(Reset_Handler) -/* Highest address of the user mode stack */ -_estack = 0x20020000; /* end of RAM */ +_ld_default_stack_size = 24K; /* Specify the memory areas */ MEMORY @@ -79,134 +31,9 @@ _minimum_heap_size = 16K; /* Define tho top end of the stack. The stack is full descending so begins just above last byte of RAM. Note that EABI requires the stack to be 8-byte aligned for a call. */ -_estack = ORIGIN(RAM) + LENGTH(RAM); +_estack = ORIGIN(DTCM) + LENGTH(DTCM); /* RAM extents for the garbage collector */ _ram_start = ORIGIN(RAM); _ram_end = ORIGIN(RAM) + LENGTH(RAM); -ENTRY(Reset_Handler) - -/* define output sections */ -SECTIONS -{ - /* The startup code goes first into FLASH */ - .isr_vector : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - - /* This first flash block is 16K annd the isr vectors only take up - about 400 bytes. Micropython pads this with files, but this didn't - work with the size of Circuitpython's ff object. */ - - . = ALIGN(4); - } >FLASH_ISR - - /* The program code and other data goes into FLASH */ - .text : - { - . = ALIGN(4); - *(.text*) /* .text* sections (code) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - /* *(.glue_7) */ /* glue arm to thumb code */ - /* *(.glue_7t) */ /* glue thumb to arm code */ - - . = ALIGN(4); - _etext = .; /* define a global symbol at end of code */ - } >FLASH_TEXT - - /* used by the startup to initialize data */ - _sidata = LOADADDR(.data); - - /* This is the initialized data section - The program executes knowing that the data is in the RAM - but the loader puts the initial values in the FLASH (inidata). - It is one task of the startup to copy the initial values from FLASH to RAM. */ - .data : - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM */ - *(.data*) /* .data* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */ - } >RAM AT> FLASH_TEXT - - /* Uninitialized data section */ - .bss : - { - . = ALIGN(4); - _sbss = .; /* define a global symbol at bss start; used by startup code */ - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end; used by startup code and GC */ - } >RAM - - /* this is to define the start of the heap, and make sure we have a minimum size */ - .heap : - { - . = ALIGN(4); - . = . + _minimum_heap_size; - . = ALIGN(4); - } >RAM - - /* this just checks there is enough RAM for the stack */ - .stack : - { - . = ALIGN(4); - . = . + _minimum_stack_size; - . = ALIGN(4); - } >RAM - - /* itcm stuff doesn't work, results in arcane hard crashes - .itcm : - { - . = ALIGN(4); - - *(.itcm.*) - - . = ALIGN(4); - } > ITCM AT> FLASH_TEXT - _ld_itcm_destination = ADDR(.itcm); - _ld_itcm_flash_copy = LOADADDR(.itcm); - _ld_itcm_size = SIZEOF(.itcm); - - .dtcm_data : - { - . = ALIGN(4); - - *(.dtcm_data.*) - - . = ALIGN(4); - } > DTCM AT> FLASH_TEXT - _ld_dtcm_data_destination = ADDR(.dtcm_data); - _ld_dtcm_data_flash_copy = LOADADDR(.dtcm_data); - _ld_dtcm_data_size = SIZEOF(.dtcm_data); - - .dtcm_bss : - { - . = ALIGN(4); - - *(.dtcm_bss.*) - - . = ALIGN(4); - } > DTCM AT> DTCM - _ld_dtcm_bss_start = ADDR(.dtcm_bss); - _ld_dtcm_bss_size = SIZEOF(.dtcm_bss); - - .stack : - { - . = ALIGN(8); - _ld_stack_bottom = .; - . += _ld_default_stack_size; - } > DTCM - _ld_stack_top = ORIGIN(DTCM) + LENGTH(DTCM); - */ - - .ARM.attributes 0 : { *(.ARM.attributes) } -} - - diff --git a/ports/stm/boards/STM32F412ZGTx_FLASH.ld b/ports/stm/boards/common_default.ld similarity index 68% rename from ports/stm/boards/STM32F412ZGTx_FLASH.ld rename to ports/stm/boards/common_default.ld index e0586709e6cd1..41fe4dfb6736a 100644 --- a/ports/stm/boards/STM32F412ZGTx_FLASH.ld +++ b/ports/stm/boards/common_default.ld @@ -1,34 +1,20 @@ -/* - GNU linker script for STM32F412 -*/ - -/* Specify the memory areas */ -MEMORY -{ - FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K /* entire flash */ - FLASH_ISR (rx) : ORIGIN = 0x08000000, LENGTH = 16K /* sector 0 */ - FLASH_FS (rx) : ORIGIN = 0x08004000, LENGTH = 48K /* sectors 1,2,3 are 16K */ - FLASH_TEXT (rx) : ORIGIN = 0x08010000, LENGTH = 960K /* sector 4 is 64K, sectors 5,6,7 are 128K */ - RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 256K -} - -/* produce a link error if there is not this amount of RAM for these sections */ -_minimum_stack_size = 2K; -_minimum_heap_size = 16K; +/* Memory layout for default case. -/* Define tho top end of the stack. The stack is full descending so begins just - above last byte of RAM. Note that EABI requires the stack to be 8-byte - aligned for a call. */ -_estack = ORIGIN(RAM) + LENGTH(RAM); + FLASH_ISR .isr_vector + FLASH_TEXT .text + FLASH_TEXT .data + FLASH_FS // ignored for fs use -/* RAM extents for the garbage collector */ -_ram_start = ORIGIN(RAM); -_ram_end = ORIGIN(RAM) + LENGTH(RAM); -_heap_start = _ebss; /* heap starts just after statically allocated memory */ -_heap_end = 0x20020000; /* tunable */ + RAM .data + RAM .bss + RAM .heap + RAM .stack +*/ ENTRY(Reset_Handler) +_ld_default_stack_size = _minimum_stack_size; + /* define output sections */ SECTIONS { @@ -51,6 +37,8 @@ SECTIONS . = ALIGN(4); *(.text*) /* .text* sections (code) */ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + /* *(.glue_7) */ /* glue arm to thumb code */ + /* *(.glue_7t) */ /* glue thumb to arm code */ . = ALIGN(4); _etext = .; /* define a global symbol at end of code */ @@ -89,17 +77,23 @@ SECTIONS .heap : { . = ALIGN(4); + _ld_heap_start = .; . = . + _minimum_heap_size; . = ALIGN(4); } >RAM + _ld_heap_end = ORIGIN(RAM) + LENGTH(RAM); /* this just checks there is enough RAM for the stack */ .stack : { . = ALIGN(4); + _ld_stack_bottom = .; . = . + _minimum_stack_size; . = ALIGN(4); } >RAM + _ld_stack_top = ORIGIN(RAM) + LENGTH(RAM); + .ARM.attributes 0 : { *(.ARM.attributes) } } + diff --git a/ports/stm/boards/STM32F411VETx_FLASH.ld b/ports/stm/boards/common_nvm.ld similarity index 69% rename from ports/stm/boards/STM32F411VETx_FLASH.ld rename to ports/stm/boards/common_nvm.ld index ac1ba32408618..cee71d19446ef 100644 --- a/ports/stm/boards/STM32F411VETx_FLASH.ld +++ b/ports/stm/boards/common_nvm.ld @@ -1,34 +1,22 @@ -/* - GNU linker script for STM32F411 via Micropython +/* Memory layout for case with dedicated nvm sector (inefficient) +TODO: rewrite nvm module, remove this file entirely + + FLASH_ISR .isr_vector + FLASH_TEXT .text + FLASH_TEXT .data + FLASH_NVM .nvm_data + FLASH_FS // ignored for fs use + + RAM .data + RAM .bss + RAM .heap + RAM .stack */ -/* Specify the memory areas */ -MEMORY -{ - FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K /* entire flash */ - FLASH_ISR (rx) : ORIGIN = 0x08000000, LENGTH = 16K /* sector 0 */ - FLASH_FS (rx) : ORIGIN = 0x08004000, LENGTH = 48K /* sectors 1,2,3 are 16K */ - FLASH_TEXT (rx) : ORIGIN = 0x08010000, LENGTH = 448K /* sector 4 is 64K, sectors 5,6,7 are 128K */ - RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K -} - -/* produce a link error if there is not this amount of RAM for these sections */ -_minimum_stack_size = 2K; -_minimum_heap_size = 16K; - -/* Define tho top end of the stack. The stack is full descending so begins just - above last byte of RAM. Note that EABI requires the stack to be 8-byte - aligned for a call. */ -_estack = ORIGIN(RAM) + LENGTH(RAM); - -/* RAM extents for the garbage collector */ -_ram_start = ORIGIN(RAM); -_ram_end = ORIGIN(RAM) + LENGTH(RAM); -_heap_start = _ebss; /* heap starts just after statically allocated memory */ -_heap_end = 0x2001c000; /* tunable */ - ENTRY(Reset_Handler) +_ld_default_stack_size = _minimum_stack_size; + /* define output sections */ SECTIONS { @@ -45,6 +33,14 @@ SECTIONS . = ALIGN(4); } >FLASH_ISR + /* Non-volitile memory */ + .nvm_data : + { + . = ALIGN(4); + KEEP(*(.nvm_data)) + . = ALIGN(4); + } >FLASH_NVM + /* The program code and other data goes into FLASH */ .text : { @@ -91,19 +87,23 @@ SECTIONS .heap : { . = ALIGN(4); + _ld_heap_start = .; . = . + _minimum_heap_size; . = ALIGN(4); } >RAM + _ld_heap_end = ORIGIN(RAM) + LENGTH(RAM); /* this just checks there is enough RAM for the stack */ .stack : { . = ALIGN(4); + _ld_stack_bottom = .; . = . + _minimum_stack_size; . = ALIGN(4); } >RAM + _ld_stack_top = ORIGIN(RAM) + LENGTH(RAM); + .ARM.attributes 0 : { *(.ARM.attributes) } } - diff --git a/ports/stm/boards/STM32F411VETx_nvm_FLASH.ld b/ports/stm/boards/common_tcm.ld similarity index 62% rename from ports/stm/boards/STM32F411VETx_nvm_FLASH.ld rename to ports/stm/boards/common_tcm.ld index 8382cb7818647..0aab4c7f9eedc 100644 --- a/ports/stm/boards/STM32F411VETx_nvm_FLASH.ld +++ b/ports/stm/boards/common_tcm.ld @@ -1,32 +1,19 @@ -/* - GNU linker script for STM32F411 via Micropython -*/ - -/* Specify the memory areas */ -MEMORY -{ - FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K /* entire flash */ - FLASH_ISR (rx) : ORIGIN = 0x08000000, LENGTH = 16K /* sector 0 */ - FLASH_FS (rx) : ORIGIN = 0x08004000, LENGTH = 32K /* sectors 1,2 are 16K */ - FLASH_NVM (rwx) : ORIGIN = 0x0800C000, LENGTH = 16K /* sector 3 is 16K */ - FLASH_TEXT (rx) : ORIGIN = 0x08010000, LENGTH = 448K /* sector 4 is 64K, sectors 5,6,7 are 128K */ - RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K -} +/* Memory layout for cases with itcm and dtcm -/* produce a link error if there is not this amount of RAM for these sections */ -_minimum_stack_size = 2K; -_minimum_heap_size = 16K; + FLASH_ISR .isr_vector + FLASH_TEXT .text + FLASH_TEXT .data + FLASH_FS // ignored for fs use -/* Define the top end of the stack. The stack is full descending so begins just - above last byte of RAM. Note that EABI requires the stack to be 8-byte - aligned for a call. */ -_estack = ORIGIN(RAM) + LENGTH(RAM); + RAM .data + RAM .bss + RAM .heap -/* RAM extents for the garbage collector */ -_ram_start = ORIGIN(RAM); -_ram_end = ORIGIN(RAM) + LENGTH(RAM); -_heap_start = _ebss; /* heap starts just after statically allocated memory */ -_heap_end = 0x2001c000; /* tunable */ + ITCM .itcm + DTCM .dtcm_data + DTCM .dtcm_bss + DTCM .stack +*/ ENTRY(Reset_Handler) @@ -46,14 +33,6 @@ SECTIONS . = ALIGN(4); } >FLASH_ISR - /* Non-volitile memory */ - .nvm_data : - { - . = ALIGN(4); - KEEP(*(.nvm_data)) - . = ALIGN(4); - } >FLASH_NVM - /* The program code and other data goes into FLASH */ .text : { @@ -83,6 +62,9 @@ SECTIONS . = ALIGN(4); _edata = .; /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */ } >RAM AT> FLASH_TEXT + _ld_d1_ram_data_destination = ADDR(.data); + _ld_d1_ram_data_flash_copy = LOADADDR(.data); + _ld_d1_ram_data_size = SIZEOF(.data); /* Uninitialized data section */ .bss : @@ -95,6 +77,10 @@ SECTIONS . = ALIGN(4); _ebss = .; /* define a global symbol at bss end; used by startup code and GC */ } >RAM + _ld_d1_ram_bss_start = ADDR(.bss); + _ld_d1_ram_bss_size = SIZEOF(.bss); + _ld_heap_start = _ld_d1_ram_bss_start + _ld_d1_ram_bss_size; + _ld_heap_end = ORIGIN(RAM) + LENGTH(RAM); /* this is to define the start of the heap, and make sure we have a minimum size */ .heap : @@ -104,15 +90,50 @@ SECTIONS . = ALIGN(4); } >RAM - /* this just checks there is enough RAM for the stack */ - .stack : + /* itcm stuff */ + .itcm : { . = ALIGN(4); - . = . + _minimum_stack_size; + + *(.itcm.*) + . = ALIGN(4); - } >RAM + } > ITCM AT> FLASH_TEXT + _ld_itcm_destination = ADDR(.itcm); + _ld_itcm_flash_copy = LOADADDR(.itcm); + _ld_itcm_size = SIZEOF(.itcm); - .ARM.attributes 0 : { *(.ARM.attributes) } -} + .dtcm_data : + { + . = ALIGN(4); + + *(.dtcm_data.*) + + . = ALIGN(4); + } > DTCM AT> FLASH_TEXT + _ld_dtcm_data_destination = ADDR(.dtcm_data); + _ld_dtcm_data_flash_copy = LOADADDR(.dtcm_data); + _ld_dtcm_data_size = SIZEOF(.dtcm_data); + + .dtcm_bss : + { + . = ALIGN(4); + *(.dtcm_bss.*) + . = ALIGN(4); + } > DTCM AT> DTCM + _ld_dtcm_bss_start = ADDR(.dtcm_bss); + _ld_dtcm_bss_size = SIZEOF(.dtcm_bss); + + .stack : + { + . = ALIGN(8); + _ld_stack_bottom = .; + . += _ld_default_stack_size; + } > DTCM + _ld_stack_top = ORIGIN(DTCM) + LENGTH(DTCM); + + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/ports/stm/boards/espruino_pico/mpconfigboard.mk b/ports/stm/boards/espruino_pico/mpconfigboard.mk index 01264d512b9f8..b7937dd04c89a 100644 --- a/ports/stm/boards/espruino_pico/mpconfigboard.mk +++ b/ports/stm/boards/espruino_pico/mpconfigboard.mk @@ -10,5 +10,6 @@ MCU_SERIES = F4 MCU_VARIANT = STM32F401xE MCU_PACKAGE = UFQFPN48 +LD_COMMON = boards/common_default.ld LD_FILE = boards/STM32F401xd_fs.ld # use for internal flash diff --git a/ports/stm/boards/espruino_wifi/mpconfigboard.mk b/ports/stm/boards/espruino_wifi/mpconfigboard.mk index b4b394443989e..70d0ea2bdf5bc 100644 --- a/ports/stm/boards/espruino_wifi/mpconfigboard.mk +++ b/ports/stm/boards/espruino_wifi/mpconfigboard.mk @@ -10,5 +10,6 @@ MCU_SERIES = F4 MCU_VARIANT = STM32F411xE MCU_PACKAGE = UFQFPN48 -LD_FILE = boards/STM32F411VETx_FLASH.ld +LD_COMMON = boards/common_default.ld +LD_FILE = boards/STM32F411_fs.ld diff --git a/ports/stm/boards/feather_stm32f405_express/mpconfigboard.mk b/ports/stm/boards/feather_stm32f405_express/mpconfigboard.mk index 351adf1b8cd38..85ed18f4f63f3 100644 --- a/ports/stm/boards/feather_stm32f405_express/mpconfigboard.mk +++ b/ports/stm/boards/feather_stm32f405_express/mpconfigboard.mk @@ -12,6 +12,7 @@ MCU_SERIES = F4 MCU_VARIANT = STM32F405xx MCU_PACKAGE = LQFP64 +LD_COMMON = boards/common_default.ld LD_DEFAULT = boards/STM32F405_default.ld LD_BOOT = boards/STM32F405_boot.ld # UF2 boot option UF2_OFFSET = 0x8010000 diff --git a/ports/stm/boards/meowbit_v121/mpconfigboard.mk b/ports/stm/boards/meowbit_v121/mpconfigboard.mk index 0a725d75ba724..cd8d3b548e3de 100644 --- a/ports/stm/boards/meowbit_v121/mpconfigboard.mk +++ b/ports/stm/boards/meowbit_v121/mpconfigboard.mk @@ -15,6 +15,7 @@ MCU_SERIES = F4 MCU_VARIANT = STM32F401xE MCU_PACKAGE = LQFP64 +LD_COMMON = boards/common_default.ld LD_FILE = boards/STM32F401xe_boot.ld # LD_FILE = boards/STM32F401xe_fs.ld # use for internal flash diff --git a/ports/stm/boards/nucleo_f767zi/mpconfigboard.mk b/ports/stm/boards/nucleo_f767zi/mpconfigboard.mk index 11c2215196d5d..cac4a273eb0a0 100644 --- a/ports/stm/boards/nucleo_f767zi/mpconfigboard.mk +++ b/ports/stm/boards/nucleo_f767zi/mpconfigboard.mk @@ -10,5 +10,6 @@ MCU_SERIES = F7 MCU_VARIANT = STM32F767xx MCU_PACKAGE = LQFP144 +LD_COMMON = boards/common_default.ld LD_FILE = boards/STM32F767_fs.ld diff --git a/ports/stm/boards/nucleo_h743zi_2/mpconfigboard.mk b/ports/stm/boards/nucleo_h743zi_2/mpconfigboard.mk index 0f003d5fe3e0b..dd7f05f290b89 100644 --- a/ports/stm/boards/nucleo_h743zi_2/mpconfigboard.mk +++ b/ports/stm/boards/nucleo_h743zi_2/mpconfigboard.mk @@ -10,5 +10,6 @@ MCU_SERIES = H7 MCU_VARIANT = STM32H743xx MCU_PACKAGE = LQFP144 +LD_COMMON = boards/common_tcm.ld LD_FILE = boards/STM32H743_fs.ld diff --git a/ports/stm/boards/pyb_nano_v2/mpconfigboard.mk b/ports/stm/boards/pyb_nano_v2/mpconfigboard.mk index e9f1d0369ef06..0a06852fb8649 100644 --- a/ports/stm/boards/pyb_nano_v2/mpconfigboard.mk +++ b/ports/stm/boards/pyb_nano_v2/mpconfigboard.mk @@ -12,5 +12,6 @@ MCU_SERIES = F4 MCU_VARIANT = STM32F411xE MCU_PACKAGE = UFQFPN48 -LD_FILE = boards/STM32F411VETx_FLASH.ld +LD_COMMON = boards/common_default.ld +LD_FILE = boards/STM32F411_fs.ld diff --git a/ports/stm/boards/pyboard_v11/mpconfigboard.mk b/ports/stm/boards/pyboard_v11/mpconfigboard.mk index ab2ce86a983ad..9d8b0f3f27733 100644 --- a/ports/stm/boards/pyboard_v11/mpconfigboard.mk +++ b/ports/stm/boards/pyboard_v11/mpconfigboard.mk @@ -10,5 +10,6 @@ MCU_SERIES = F4 MCU_VARIANT = STM32F405xx MCU_PACKAGE = LQFP64 +LD_COMMON = boards/common_default.ld LD_FILE = boards/STM32F405_fs.ld diff --git a/ports/stm/boards/stm32f411ce_blackpill/mpconfigboard.mk b/ports/stm/boards/stm32f411ce_blackpill/mpconfigboard.mk index bf2dd55965682..62887c0289a42 100644 --- a/ports/stm/boards/stm32f411ce_blackpill/mpconfigboard.mk +++ b/ports/stm/boards/stm32f411ce_blackpill/mpconfigboard.mk @@ -15,5 +15,6 @@ MCU_SERIES = F4 MCU_VARIANT = STM32F411xE MCU_PACKAGE = UFQFPN48 -LD_FILE = boards/STM32F411VETx_FLASH.ld +LD_COMMON = boards/common_default.ld +LD_FILE = boards/STM32F411_fs.ld diff --git a/ports/stm/boards/stm32f411ve_discovery/mpconfigboard.mk b/ports/stm/boards/stm32f411ve_discovery/mpconfigboard.mk index da24fe3f0acfe..761602acdfdb0 100644 --- a/ports/stm/boards/stm32f411ve_discovery/mpconfigboard.mk +++ b/ports/stm/boards/stm32f411ve_discovery/mpconfigboard.mk @@ -10,5 +10,6 @@ MCU_SERIES = F4 MCU_VARIANT = STM32F411xE MCU_PACKAGE = LQFP100_f4 -LD_FILE = boards/STM32F411VETx_FLASH.ld +LD_COMMON = boards/common_default.ld +LD_FILE = boards/STM32F411_fs.ld diff --git a/ports/stm/boards/stm32f412zg_discovery/mpconfigboard.mk b/ports/stm/boards/stm32f412zg_discovery/mpconfigboard.mk index d227803de7331..09e7bda85da79 100644 --- a/ports/stm/boards/stm32f412zg_discovery/mpconfigboard.mk +++ b/ports/stm/boards/stm32f412zg_discovery/mpconfigboard.mk @@ -15,6 +15,7 @@ MCU_SERIES = F4 MCU_VARIANT = STM32F412Zx MCU_PACKAGE = LQFP144 -LD_FILE = boards/STM32F412ZGTx_FLASH.ld +LD_COMMON = boards/common_default.ld +LD_FILE = boards/STM32F412_fs.ld diff --git a/ports/stm/boards/stm32f4_discovery/mpconfigboard.mk b/ports/stm/boards/stm32f4_discovery/mpconfigboard.mk index c8c424c0c493d..57a65f75aee81 100644 --- a/ports/stm/boards/stm32f4_discovery/mpconfigboard.mk +++ b/ports/stm/boards/stm32f4_discovery/mpconfigboard.mk @@ -10,5 +10,6 @@ MCU_SERIES = F4 MCU_VARIANT = STM32F407xx MCU_PACKAGE = LQFP100_f4 +LD_COMMON = boards/common_default.ld LD_FILE = boards/STM32F407_fs.ld diff --git a/ports/stm/boards/thunderpack/mpconfigboard.mk b/ports/stm/boards/thunderpack/mpconfigboard.mk index 6fcaae6ab0ac9..40b0e92506b1c 100644 --- a/ports/stm/boards/thunderpack/mpconfigboard.mk +++ b/ports/stm/boards/thunderpack/mpconfigboard.mk @@ -9,12 +9,9 @@ LONGINT_IMPL = NONE CIRCUITPY_NVM = 1 -MCU_SERIES = m4 -MCU_VARIANT = stm32f4 -MCU_SUB_VARIANT = stm32f411xe +MCU_SERIES = F4 +MCU_VARIANT = STM32F411xE MCU_PACKAGE = 48 -CMSIS_MCU = STM32F411xE -LD_FILE = boards/STM32F411VETx_nvm_FLASH.ld -STARTUP_FILE = startup_stm32f411xe.s - +LD_FILE = boards/common_nvm.ld +LD_FILE = boards/STM32F411_nvm.ld diff --git a/ports/stm/mpconfigport.h b/ports/stm/mpconfigport.h index 297c7338ed777..65b0611241ec3 100644 --- a/ports/stm/mpconfigport.h +++ b/ports/stm/mpconfigport.h @@ -28,14 +28,19 @@ #ifndef STM32_MPCONFIGPORT_H__ #define STM32_MPCONFIGPORT_H__ +#include + #define MICROPY_PY_COLLECTIONS_ORDEREDDICT (1) #define MICROPY_PY_FUNCTION_ATTRS (1) #define MICROPY_PY_IO (1) #define MICROPY_PY_REVERSE_SPECIAL_METHODS (1) #define MICROPY_PY_UJSON (1) +extern uint8_t _ld_default_stack_size; + // 24kiB stack -#define CIRCUITPY_DEFAULT_STACK_SIZE 0x6000 +// #define CIRCUITPY_DEFAULT_STACK_SIZE 0x6000 +#define CIRCUITPY_DEFAULT_STACK_SIZE ((uint32_t) &_ld_default_stack_size) #include "py/circuitpy_mpconfig.h" diff --git a/ports/stm/packages/LQFP100_f4.c b/ports/stm/packages/LQFP100_f4.c index a2219ccc087ec..5bc0a5158ebc9 100644 --- a/ports/stm/packages/LQFP100_f4.c +++ b/ports/stm/packages/LQFP100_f4.c @@ -53,7 +53,7 @@ STATIC const mp_rom_map_elem_t mcu_pin_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_PE14), MP_ROM_PTR(&pin_PE14) }, { MP_ROM_QSTR(MP_QSTR_PE15), MP_ROM_PTR(&pin_PE15) }, { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) }, -#if MCU_LINE == FOUNDATION || MCU_LINE == ADVANCED +#if defined(STM32F405xx) || defined(STM32F412Zx) || defined(STM32F407xx) || defined(STM32F767xx) { MP_ROM_QSTR(MP_QSTR_PB11), MP_ROM_PTR(&pin_PB11) }, #endif //or VCAP1 -----------------------------------*/ // VCAP1 or VSS -----------------------------------*/ diff --git a/ports/stm/packages/LQFP64.c b/ports/stm/packages/LQFP64.c index 02dcfa00ca931..e6a492bc33e31 100644 --- a/ports/stm/packages/LQFP64.c +++ b/ports/stm/packages/LQFP64.c @@ -35,7 +35,7 @@ STATIC const mp_rom_map_elem_t mcu_pin_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) }, { MP_ROM_QSTR(MP_QSTR_PB02), MP_ROM_PTR(&pin_PB02) }, { MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) }, -#if MCU_LINE == FOUNDATION || MCU_LINE == ADVANCED +#if defined(STM32F405xx) || defined(STM32F412Zx) || defined(STM32F407xx) || defined(STM32F767xx) { MP_ROM_QSTR(MP_QSTR_PB11), MP_ROM_PTR(&pin_PB11) }, #endif //or VCAP1 -----------------------------------*/ // VCAP1 or VSS -----------------------------------*/ diff --git a/ports/stm/supervisor/port.c b/ports/stm/supervisor/port.c index fa377e74a9b1f..16796d9ce3a21 100644 --- a/ports/stm/supervisor/port.c +++ b/ports/stm/supervisor/port.c @@ -44,6 +44,131 @@ #include "clocks.h" #include "gpio.h" +//only enable the Reset Handler overwrite for the H7 for now +#if defined(STM32H7) + +// Device memories must be accessed in order. +#define DEVICE 2 +// Normal memory can have accesses reorder and prefetched. +#define NORMAL 0 +// Prevents instruction access. +#define NO_EXECUTION 1 +#define EXECUTION 0 +// Shareable if the memory system manages coherency. +#define NOT_SHAREABLE 0 +#define SHAREABLE 1 +#define NOT_CACHEABLE 0 +#define CACHEABLE 1 +#define NOT_BUFFERABLE 0 +#define BUFFERABLE 1 +#define NO_SUBREGIONS 0 + +extern uint32_t _ld_stack_top; + +extern uint32_t _ld_d1_ram_bss_start; +extern uint32_t _ld_d1_ram_bss_size; +extern uint32_t _ld_d1_ram_data_destination; +extern uint32_t _ld_d1_ram_data_size; +extern uint32_t _ld_d1_ram_data_flash_copy; +extern uint32_t _ld_dtcm_bss_start; +extern uint32_t _ld_dtcm_bss_size; +extern uint32_t _ld_dtcm_data_destination; +extern uint32_t _ld_dtcm_data_size; +extern uint32_t _ld_dtcm_data_flash_copy; +extern uint32_t _ld_itcm_destination; +extern uint32_t _ld_itcm_size; +extern uint32_t _ld_itcm_flash_copy; + +extern void main(void); +extern void SystemInit(void); + +// This replaces the Reset_Handler in startup_*.S and SystemInit in system_*.c. +__attribute__((used, naked)) void Reset_Handler(void) { + __disable_irq(); + __set_MSP((uint32_t) &_ld_stack_top); + + // TODO: Is any of this commented stuff actually required? + + /* Disable I cache and D cache */ + // SCB_DisableICache(); + // SCB_DisableDCache(); // this causes an instant hardfault if used + + // #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + // SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */ + // #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + + // /* Disable Systick which might be enabled by bootrom */ + // if (SysTick->CTRL & SysTick_CTRL_ENABLE_Msk) + // { + // SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + // } + + /* Disable MPU */ + ARM_MPU_Disable(); + + // Copy all of the itcm code to run from ITCM. Do this while the MPU is disabled because we write + // protect it. + for (uint32_t i = 0; i < ((size_t) &_ld_itcm_size) / 4; i++) { + (&_ld_itcm_destination)[i] = (&_ld_itcm_flash_copy)[i]; + } + + // The first number in RBAR is the region number. When searching for a policy, the region with + // the highest number wins. If none match, then the default policy set at enable applies. + // TODO: what is the default policy? Where is that set? + + // TODO: do I need to subdivide this up? + // Mark all the flash the same until instructed otherwise. + MPU->RBAR = ARM_MPU_RBAR(11, 0x08000000U); + MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_FULL, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, NO_SUBREGIONS, ARM_MPU_REGION_SIZE_2MB); + + // This the ITCM. Set it to read-only because we've loaded everything already and it's easy to + // accidentally write the wrong value to 0x00000000 (aka NULL). + MPU->RBAR = ARM_MPU_RBAR(12, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_RO, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, NO_SUBREGIONS, ARM_MPU_REGION_SIZE_128KB); + + // This the DTCM. + MPU->RBAR = ARM_MPU_RBAR(14, 0x20000000U); + MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_FULL, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, NO_SUBREGIONS, ARM_MPU_REGION_SIZE_128KB); + + // This is AXI SRAM (D1). + MPU->RBAR = ARM_MPU_RBAR(15, 0x24000000U); + MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_FULL, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, NO_SUBREGIONS, ARM_MPU_REGION_SIZE_512KB); + + // TODO: what is the mask here doing? + /* Enable MPU */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + // We're done mucking with memory so enable I cache and D cache + // SCB_EnableDCache(); + // SCB_EnableICache(); + + // Copy all of the data to run from DTCM. + for (uint32_t i = 0; i < ((size_t) &_ld_dtcm_data_size) / 4; i++) { + (&_ld_dtcm_data_destination)[i] = (&_ld_dtcm_data_flash_copy)[i]; + } + + // Clear DTCM bss. + for (uint32_t i = 0; i < ((size_t) &_ld_dtcm_bss_size) / 4; i++) { + (&_ld_dtcm_bss_start)[i] = 0; + } + + // Copy all of the data to run from D1 RAM. + for (uint32_t i = 0; i < ((size_t) &_ld_d1_ram_data_size) / 4; i++) { + (&_ld_d1_ram_data_destination)[i] = (&_ld_d1_ram_data_flash_copy)[i]; + } + + // Clear D1 RAM bss. + for (uint32_t i = 0; i < ((size_t) &_ld_d1_ram_bss_size) / 4; i++) { + (&_ld_d1_ram_bss_start)[i] = 0; + } + + SystemInit(); + __enable_irq(); + main(); +} + +#endif //end H7 specific code + safe_mode_t port_init(void) { HAL_Init(); __HAL_RCC_SYSCFG_CLK_ENABLE(); @@ -63,6 +188,7 @@ safe_mode_t port_init(void) { void reset_port(void) { reset_all_pins(); + // TODO: it'd be nice if this was more automatic #if defined(STM32F4) i2c_reset(); spi_reset(); @@ -81,22 +207,25 @@ void reset_cpu(void) { NVIC_SystemReset(); } +extern uint32_t _ld_heap_start, _ld_heap_end, _ld_stack_top, _ld_stack_bottom; + uint32_t *port_heap_get_bottom(void) { - return port_stack_get_limit(); + return &_ld_heap_start; } uint32_t *port_heap_get_top(void) { - return port_stack_get_top(); + return &_ld_heap_end; } uint32_t *port_stack_get_limit(void) { - return &_ebss; + return &_ld_stack_bottom; } uint32_t *port_stack_get_top(void) { - return &_estack; + return &_ld_stack_top; } +// TODO: what even are these extern uint32_t _ebss; // Place the word to save just after our BSS section that gets blanked. void port_set_saved_word(uint32_t value) { @@ -107,7 +236,36 @@ uint32_t port_get_saved_word(void) { return _ebss; } -void HardFault_Handler(void) { +__attribute__((used)) void MemManage_Handler(void) +{ + __ASM volatile ("bkpt"); + reset_into_safe_mode(MEM_MANAGE); + while (true) { + asm("nop;"); + } +} + +__attribute__((used)) void BusFault_Handler(void) +{ + __ASM volatile ("bkpt"); + reset_into_safe_mode(MEM_MANAGE); + while (true) { + asm("nop;"); + } +} + +__attribute__((used)) void UsageFault_Handler(void) +{ + __ASM volatile ("bkpt"); + reset_into_safe_mode(MEM_MANAGE); + while (true) { + asm("nop;"); + } +} + +__attribute__((used)) void HardFault_Handler(void) +{ + __ASM volatile ("bkpt"); reset_into_safe_mode(HARD_CRASH); while (true) { asm("nop;"); diff --git a/supervisor/linker.h b/supervisor/linker.h index 878268c734c4f..74b2dd5a6d21d 100755 --- a/supervisor/linker.h +++ b/supervisor/linker.h @@ -29,7 +29,7 @@ #ifndef MICROPY_INCLUDED_SUPERVISOR_LINKER_H #define MICROPY_INCLUDED_SUPERVISOR_LINKER_H -#if defined(IMXRT10XX) || defined(FOMU) // || defined(STM32H7) +#if defined(IMXRT10XX) || defined(FOMU) || defined(STM32H7) #define PLACE_IN_DTCM_DATA(name) name __attribute__((section(".dtcm_data." #name ))) #define PLACE_IN_DTCM_BSS(name) name __attribute__((section(".dtcm_bss." #name ))) #define PLACE_IN_ITCM(name) __attribute__((section(".itcm." #name ))) name diff --git a/supervisor/shared/stack.c b/supervisor/shared/stack.c index 2b7b1c03a48d9..2a7daf4658d78 100755 --- a/supervisor/shared/stack.c +++ b/supervisor/shared/stack.c @@ -46,7 +46,7 @@ void allocate_stack(void) { mp_uint_t c_size = (uint32_t) port_stack_get_top() - sp; - if (port_stack_get_top() != port_heap_get_top()) { + if (port_stack_get_top() != port_heap_get_top()) { //Why is this here? Doesn't apply to some chips. return; } From 92a0621e5956fee84591859ffa58c04be8e46158 Mon Sep 17 00:00:00 2001 From: Lucian Copeland Date: Mon, 6 Apr 2020 19:13:55 -0400 Subject: [PATCH 09/17] Add busio support, cleanup --- .github/workflows/build.yml | 1 + ports/stm/Makefile | 16 +- ports/stm/boards/STM32H743ZITx_FLASH.ld | 193 ----- ports/stm/boards/nucleo_h743zi_2/pins.c | 2 +- ports/stm/boards/startup_stm32f401xe.s | 448 ----------- ports/stm/boards/startup_stm32f405xx.s | 516 ------------ ports/stm/boards/startup_stm32f407xx.s | 516 ------------ ports/stm/boards/startup_stm32f411xe.s | 452 ----------- ports/stm/boards/startup_stm32f412zx.s | 524 ------------ ports/stm/boards/startup_stm32f767xx.s | 618 --------------- ports/stm/boards/startup_stm32h743xx.s | 748 ------------------ ports/stm/{ => boards}/system_stm32f4xx.c | 0 ports/stm/{ => boards}/system_stm32f7xx.c | 0 ports/stm/{ => boards}/system_stm32h7xx.c | 0 ports/stm/boards/thunderpack/mpconfigboard.mk | 2 +- ports/stm/common-hal/busio/I2C.c | 45 +- ports/stm/common-hal/busio/SPI.c | 49 +- ports/stm/common-hal/busio/UART.c | 13 + ports/stm/common-hal/digitalio/DigitalInOut.c | 9 +- ports/stm/fatfs_port.c | 2 +- ports/stm/mpconfigport.h | 18 + ports/stm/mpconfigport.mk | 4 +- .../peripherals/stm32f4/stm32f407xx/gpio.c | 2 +- .../peripherals/stm32f4/stm32f412zx/gpio.c | 1 - .../peripherals/stm32f7/stm32f767xx/clocks.c | 2 +- .../peripherals/stm32h7/stm32h743xx/clocks.c | 72 +- ports/stm/supervisor/internal_flash.h | 3 +- ports/stm/supervisor/port.c | 13 +- 28 files changed, 175 insertions(+), 4094 deletions(-) delete mode 100644 ports/stm/boards/STM32H743ZITx_FLASH.ld delete mode 100644 ports/stm/boards/startup_stm32f401xe.s delete mode 100644 ports/stm/boards/startup_stm32f405xx.s delete mode 100644 ports/stm/boards/startup_stm32f407xx.s delete mode 100644 ports/stm/boards/startup_stm32f411xe.s delete mode 100644 ports/stm/boards/startup_stm32f412zx.s delete mode 100644 ports/stm/boards/startup_stm32f767xx.s delete mode 100644 ports/stm/boards/startup_stm32h743xx.s rename ports/stm/{ => boards}/system_stm32f4xx.c (100%) rename ports/stm/{ => boards}/system_stm32f7xx.c (100%) rename ports/stm/{ => boards}/system_stm32h7xx.c (100%) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 847cdf0249755..8f9d03d0080db 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -189,6 +189,7 @@ jobs: - "mini_sam_m4" - "monster_m4sk" - "ndgarage_ndbit6" + - "nucleo_f767zi" - "nucleo_h743zi_2" - "ohs2020_badge" - "openbook_m4" diff --git a/ports/stm/Makefile b/ports/stm/Makefile index ec15e4f7f6dd9..355fd1d026b1d 100755 --- a/ports/stm/Makefile +++ b/ports/stm/Makefile @@ -25,11 +25,11 @@ # Select the board to build for. ifeq ($(BOARD),) - $(error You must provide a BOARD parameter) +$(error You must provide a BOARD parameter) else - ifeq ($(wildcard boards/$(BOARD)/.),) - $(error Invalid BOARD specified) - endif +ifeq ($(wildcard boards/$(BOARD)/.),) +$(error Invalid BOARD specified) +endif endif # If the build directory is not given, make it reflect the board name. @@ -193,7 +193,13 @@ SRC_STM32 = $(addprefix $(HAL_DIR)/Src/stm32$(MCU_SERIES_LOWER)xx_,\ ll_exti.c \ ) -SRC_STM32 += system_stm32$(MCU_SERIES_LOWER)xx.c +# Need this to avoid UART linker problems. TODO: rewrite to use registered callbacks. +# Does not exist for F4 and lower +ifeq ($(MCU_VARIANT),$(filter $(MCU_VARIANT),STM32F765xx STM32F767xx STM32F769xx STM32H743xx)) + SRC_STM32 += $(HAL_DIR)/Src/stm32$(MCU_SERIES_LOWER)xx_hal_uart_ex.c +endif + +SRC_STM32 += boards/system_stm32$(MCU_SERIES_LOWER)xx.c SRC_C += \ background.c \ diff --git a/ports/stm/boards/STM32H743ZITx_FLASH.ld b/ports/stm/boards/STM32H743ZITx_FLASH.ld deleted file mode 100644 index 38b1fe4eaae9b..0000000000000 --- a/ports/stm/boards/STM32H743ZITx_FLASH.ld +++ /dev/null @@ -1,193 +0,0 @@ -/* -****************************************************************************** -** - -** File : LinkerScript.ld -** -** Author : Auto-generated by System Workbench for STM32 -** -** Abstract : Linker script for STM32H743ZITx series -** 2048Kbytes FLASH and 1056Kbytes RAM -** -** Set heap size, stack size and stack location according -** to application requirements. -** -** Set memory bank area and size if external memory is used. -** -** Target : STMicroelectronics STM32 -** -** Distribution: The file is distributed “as is,” without any warranty -** of any kind. -** -***************************************************************************** -** @attention -** -**

© COPYRIGHT(c) 2019 STMicroelectronics

-** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** 1. Redistributions of source code must retain the above copyright notice, -** this list of conditions and the following disclaimer. -** 2. Redistributions in binary form must reproduce the above copyright notice, -** this list of conditions and the following disclaimer in the documentation -** and/or other materials provided with the distribution. -** 3. Neither the name of STMicroelectronics nor the names of its contributors -** may be used to endorse or promote products derived from this software -** without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -***************************************************************************** -*/ - -/* Entry Point */ -ENTRY(Reset_Handler) - -/* Highest address of the user mode stack */ -_estack = 0x20020000; /* end of RAM */ -/* Generate a link error if heap and stack don't fit into RAM */ -_Min_Heap_Size = 0x200; /* required amount of heap */ -_Min_Stack_Size = 0x400; /* required amount of stack */ - -/* Specify the memory areas */ -MEMORY -{ -DTCMRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K -RAM_D1 (xrw) : ORIGIN = 0x24000000, LENGTH = 512K -RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K -RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K -ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K -FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 2048K -} - -/* Define output sections */ -SECTIONS -{ - /* The startup code goes first into FLASH */ - .isr_vector : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } >FLASH - - /* The program code and other data goes into FLASH */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - - KEEP (*(.init)) - KEEP (*(.fini)) - - . = ALIGN(4); - _etext = .; /* define a global symbols at end of code */ - } >FLASH - - /* Constant data goes into FLASH */ - .rodata : - { - . = ALIGN(4); - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - . = ALIGN(4); - } >FLASH - - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } >FLASH - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } >FLASH - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } >FLASH - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } >FLASH - - /* used by the startup to initialize data */ - _sidata = LOADADDR(.data); - - /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end */ - } >DTCMRAM AT> FLASH - - - /* Uninitialized data section */ - . = ALIGN(4); - .bss : - { - /* This is used by the startup in order to initialize the .bss secion */ - _sbss = .; /* define a global symbol at bss start */ - __bss_start__ = _sbss; - *(.bss) - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end */ - __bss_end__ = _ebss; - } >DTCMRAM - - /* User_heap_stack section, used to check that there is enough RAM left */ - ._user_heap_stack : - { - . = ALIGN(8); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - . = . + _Min_Heap_Size; - . = . + _Min_Stack_Size; - . = ALIGN(8); - } >DTCMRAM - - - - /* Remove information from the standard libraries */ - /DISCARD/ : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - - .ARM.attributes 0 : { *(.ARM.attributes) } -} - - diff --git a/ports/stm/boards/nucleo_h743zi_2/pins.c b/ports/stm/boards/nucleo_h743zi_2/pins.c index dc2db9e184ee1..3ba172df17add 100644 --- a/ports/stm/boards/nucleo_h743zi_2/pins.c +++ b/ports/stm/boards/nucleo_h743zi_2/pins.c @@ -23,7 +23,7 @@ STATIC const mp_rom_map_elem_t board_module_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_PD14) }, { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_PB05) }, { MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_PA06) }, - { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA07) }, + { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_PA05) }, { MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_PB09) }, { MP_ROM_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_PB08) }, { MP_ROM_QSTR(MP_QSTR_D16), MP_ROM_PTR(&pin_PC06) }, diff --git a/ports/stm/boards/startup_stm32f401xe.s b/ports/stm/boards/startup_stm32f401xe.s deleted file mode 100644 index 815ac17197b53..0000000000000 --- a/ports/stm/boards/startup_stm32f401xe.s +++ /dev/null @@ -1,448 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f401xe.s - * @author MCD Application Team - * @brief STM32F401xExx Devices vector table for GCC based toolchains. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M4 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m4 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss -/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr sp, =_estack /* set stack pointer */ - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call static constructors */ - /* bl __libc_init_array */ -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - - /* External Interrupts */ - .word WWDG_IRQHandler /* Window WatchDog */ - .word PVD_IRQHandler /* PVD through EXTI Line detection */ - .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ - .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_IRQHandler /* RCC */ - .word EXTI0_IRQHandler /* EXTI Line0 */ - .word EXTI1_IRQHandler /* EXTI Line1 */ - .word EXTI2_IRQHandler /* EXTI Line2 */ - .word EXTI3_IRQHandler /* EXTI Line3 */ - .word EXTI4_IRQHandler /* EXTI Line4 */ - .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ - .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ - .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ - .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ - .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ - .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ - .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ - .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word EXTI9_5_IRQHandler /* External Line[9:5]s */ - .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ - .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ - .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word TIM2_IRQHandler /* TIM2 */ - .word TIM3_IRQHandler /* TIM3 */ - .word TIM4_IRQHandler /* TIM4 */ - .word I2C1_EV_IRQHandler /* I2C1 Event */ - .word I2C1_ER_IRQHandler /* I2C1 Error */ - .word I2C2_EV_IRQHandler /* I2C2 Event */ - .word I2C2_ER_IRQHandler /* I2C2 Error */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word 0 /* Reserved */ - .word EXTI15_10_IRQHandler /* External Line[15:10]s */ - .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ - .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ - .word 0 /* Reserved */ - .word SDIO_IRQHandler /* SDIO */ - .word TIM5_IRQHandler /* TIM5 */ - .word SPI3_IRQHandler /* SPI3 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ - .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ - .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ - .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ - .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word OTG_FS_IRQHandler /* USB OTG FS */ - .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ - .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ - .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ - .word USART6_IRQHandler /* USART6 */ - .word I2C3_EV_IRQHandler /* I2C3 event */ - .word I2C3_ER_IRQHandler /* I2C3 error */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word FPU_IRQHandler /* FPU */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word SPI4_IRQHandler /* SPI4 */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMP_STAMP_IRQHandler - .thumb_set TAMP_STAMP_IRQHandler,Default_Handler - - .weak RTC_WKUP_IRQHandler - .thumb_set RTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Stream0_IRQHandler - .thumb_set DMA1_Stream0_IRQHandler,Default_Handler - - .weak DMA1_Stream1_IRQHandler - .thumb_set DMA1_Stream1_IRQHandler,Default_Handler - - .weak DMA1_Stream2_IRQHandler - .thumb_set DMA1_Stream2_IRQHandler,Default_Handler - - .weak DMA1_Stream3_IRQHandler - .thumb_set DMA1_Stream3_IRQHandler,Default_Handler - - .weak DMA1_Stream4_IRQHandler - .thumb_set DMA1_Stream4_IRQHandler,Default_Handler - - .weak DMA1_Stream5_IRQHandler - .thumb_set DMA1_Stream5_IRQHandler,Default_Handler - - .weak DMA1_Stream6_IRQHandler - .thumb_set DMA1_Stream6_IRQHandler,Default_Handler - - .weak ADC_IRQHandler - .thumb_set ADC_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_TIM9_IRQHandler - .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler - - .weak TIM1_UP_TIM10_IRQHandler - .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_TIM11_IRQHandler - .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler - - .weak OTG_FS_WKUP_IRQHandler - .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler - - .weak DMA1_Stream7_IRQHandler - .thumb_set DMA1_Stream7_IRQHandler,Default_Handler - - .weak SDIO_IRQHandler - .thumb_set SDIO_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak DMA2_Stream0_IRQHandler - .thumb_set DMA2_Stream0_IRQHandler,Default_Handler - - .weak DMA2_Stream1_IRQHandler - .thumb_set DMA2_Stream1_IRQHandler,Default_Handler - - .weak DMA2_Stream2_IRQHandler - .thumb_set DMA2_Stream2_IRQHandler,Default_Handler - - .weak DMA2_Stream3_IRQHandler - .thumb_set DMA2_Stream3_IRQHandler,Default_Handler - - .weak DMA2_Stream4_IRQHandler - .thumb_set DMA2_Stream4_IRQHandler,Default_Handler - - .weak OTG_FS_IRQHandler - .thumb_set OTG_FS_IRQHandler,Default_Handler - - .weak DMA2_Stream5_IRQHandler - .thumb_set DMA2_Stream5_IRQHandler,Default_Handler - - .weak DMA2_Stream6_IRQHandler - .thumb_set DMA2_Stream6_IRQHandler,Default_Handler - - .weak DMA2_Stream7_IRQHandler - .thumb_set DMA2_Stream7_IRQHandler,Default_Handler - - .weak USART6_IRQHandler - .thumb_set USART6_IRQHandler,Default_Handler - - .weak I2C3_EV_IRQHandler - .thumb_set I2C3_EV_IRQHandler,Default_Handler - - .weak I2C3_ER_IRQHandler - .thumb_set I2C3_ER_IRQHandler,Default_Handler - - .weak FPU_IRQHandler - .thumb_set FPU_IRQHandler,Default_Handler - - .weak SPI4_IRQHandler - .thumb_set SPI4_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/ports/stm/boards/startup_stm32f405xx.s b/ports/stm/boards/startup_stm32f405xx.s deleted file mode 100644 index 6b77655ca1b31..0000000000000 --- a/ports/stm/boards/startup_stm32f405xx.s +++ /dev/null @@ -1,516 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f405xx.s - * @author MCD Application Team - * @brief STM32F405xx Devices vector table for GCC based toolchains. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M4 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m4 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss -/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr sp, =_estack /* set stack pointer */ - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call static constructors */ -/* bl __libc_init_array */ -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - - -g_pfnVectors: - .word _estack - .word Reset_Handler - - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - - /* External Interrupts */ - .word WWDG_IRQHandler /* Window WatchDog */ - .word PVD_IRQHandler /* PVD through EXTI Line detection */ - .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ - .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_IRQHandler /* RCC */ - .word EXTI0_IRQHandler /* EXTI Line0 */ - .word EXTI1_IRQHandler /* EXTI Line1 */ - .word EXTI2_IRQHandler /* EXTI Line2 */ - .word EXTI3_IRQHandler /* EXTI Line3 */ - .word EXTI4_IRQHandler /* EXTI Line4 */ - .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ - .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ - .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ - .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ - .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ - .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ - .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ - .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ - .word CAN1_TX_IRQHandler /* CAN1 TX */ - .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ - .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ - .word CAN1_SCE_IRQHandler /* CAN1 SCE */ - .word EXTI9_5_IRQHandler /* External Line[9:5]s */ - .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ - .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ - .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word TIM2_IRQHandler /* TIM2 */ - .word TIM3_IRQHandler /* TIM3 */ - .word TIM4_IRQHandler /* TIM4 */ - .word I2C1_EV_IRQHandler /* I2C1 Event */ - .word I2C1_ER_IRQHandler /* I2C1 Error */ - .word I2C2_EV_IRQHandler /* I2C2 Event */ - .word I2C2_ER_IRQHandler /* I2C2 Error */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word USART3_IRQHandler /* USART3 */ - .word EXTI15_10_IRQHandler /* External Line[15:10]s */ - .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ - .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ - .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ - .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ - .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ - .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ - .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ - .word FSMC_IRQHandler /* FSMC */ - .word SDIO_IRQHandler /* SDIO */ - .word TIM5_IRQHandler /* TIM5 */ - .word SPI3_IRQHandler /* SPI3 */ - .word UART4_IRQHandler /* UART4 */ - .word UART5_IRQHandler /* UART5 */ - .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ - .word TIM7_IRQHandler /* TIM7 */ - .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ - .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ - .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ - .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ - .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word CAN2_TX_IRQHandler /* CAN2 TX */ - .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ - .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ - .word CAN2_SCE_IRQHandler /* CAN2 SCE */ - .word OTG_FS_IRQHandler /* USB OTG FS */ - .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ - .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ - .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ - .word USART6_IRQHandler /* USART6 */ - .word I2C3_EV_IRQHandler /* I2C3 event */ - .word I2C3_ER_IRQHandler /* I2C3 error */ - .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ - .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ - .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ - .word OTG_HS_IRQHandler /* USB OTG HS */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word HASH_RNG_IRQHandler /* Hash and Rng */ - .word FPU_IRQHandler /* FPU */ - - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMP_STAMP_IRQHandler - .thumb_set TAMP_STAMP_IRQHandler,Default_Handler - - .weak RTC_WKUP_IRQHandler - .thumb_set RTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Stream0_IRQHandler - .thumb_set DMA1_Stream0_IRQHandler,Default_Handler - - .weak DMA1_Stream1_IRQHandler - .thumb_set DMA1_Stream1_IRQHandler,Default_Handler - - .weak DMA1_Stream2_IRQHandler - .thumb_set DMA1_Stream2_IRQHandler,Default_Handler - - .weak DMA1_Stream3_IRQHandler - .thumb_set DMA1_Stream3_IRQHandler,Default_Handler - - .weak DMA1_Stream4_IRQHandler - .thumb_set DMA1_Stream4_IRQHandler,Default_Handler - - .weak DMA1_Stream5_IRQHandler - .thumb_set DMA1_Stream5_IRQHandler,Default_Handler - - .weak DMA1_Stream6_IRQHandler - .thumb_set DMA1_Stream6_IRQHandler,Default_Handler - - .weak ADC_IRQHandler - .thumb_set ADC_IRQHandler,Default_Handler - - .weak CAN1_TX_IRQHandler - .thumb_set CAN1_TX_IRQHandler,Default_Handler - - .weak CAN1_RX0_IRQHandler - .thumb_set CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SCE_IRQHandler - .thumb_set CAN1_SCE_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_TIM9_IRQHandler - .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler - - .weak TIM1_UP_TIM10_IRQHandler - .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_TIM11_IRQHandler - .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler - - .weak OTG_FS_WKUP_IRQHandler - .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler - - .weak TIM8_BRK_TIM12_IRQHandler - .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler - - .weak TIM8_UP_TIM13_IRQHandler - .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler - - .weak TIM8_TRG_COM_TIM14_IRQHandler - .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler - - .weak TIM8_CC_IRQHandler - .thumb_set TIM8_CC_IRQHandler,Default_Handler - - .weak DMA1_Stream7_IRQHandler - .thumb_set DMA1_Stream7_IRQHandler,Default_Handler - - .weak FSMC_IRQHandler - .thumb_set FSMC_IRQHandler,Default_Handler - - .weak SDIO_IRQHandler - .thumb_set SDIO_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak UART4_IRQHandler - .thumb_set UART4_IRQHandler,Default_Handler - - .weak UART5_IRQHandler - .thumb_set UART5_IRQHandler,Default_Handler - - .weak TIM6_DAC_IRQHandler - .thumb_set TIM6_DAC_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - - .weak DMA2_Stream0_IRQHandler - .thumb_set DMA2_Stream0_IRQHandler,Default_Handler - - .weak DMA2_Stream1_IRQHandler - .thumb_set DMA2_Stream1_IRQHandler,Default_Handler - - .weak DMA2_Stream2_IRQHandler - .thumb_set DMA2_Stream2_IRQHandler,Default_Handler - - .weak DMA2_Stream3_IRQHandler - .thumb_set DMA2_Stream3_IRQHandler,Default_Handler - - .weak DMA2_Stream4_IRQHandler - .thumb_set DMA2_Stream4_IRQHandler,Default_Handler - - .weak CAN2_TX_IRQHandler - .thumb_set CAN2_TX_IRQHandler,Default_Handler - - .weak CAN2_RX0_IRQHandler - .thumb_set CAN2_RX0_IRQHandler,Default_Handler - - .weak CAN2_RX1_IRQHandler - .thumb_set CAN2_RX1_IRQHandler,Default_Handler - - .weak CAN2_SCE_IRQHandler - .thumb_set CAN2_SCE_IRQHandler,Default_Handler - - .weak OTG_FS_IRQHandler - .thumb_set OTG_FS_IRQHandler,Default_Handler - - .weak DMA2_Stream5_IRQHandler - .thumb_set DMA2_Stream5_IRQHandler,Default_Handler - - .weak DMA2_Stream6_IRQHandler - .thumb_set DMA2_Stream6_IRQHandler,Default_Handler - - .weak DMA2_Stream7_IRQHandler - .thumb_set DMA2_Stream7_IRQHandler,Default_Handler - - .weak USART6_IRQHandler - .thumb_set USART6_IRQHandler,Default_Handler - - .weak I2C3_EV_IRQHandler - .thumb_set I2C3_EV_IRQHandler,Default_Handler - - .weak I2C3_ER_IRQHandler - .thumb_set I2C3_ER_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_OUT_IRQHandler - .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_IN_IRQHandler - .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler - - .weak OTG_HS_WKUP_IRQHandler - .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler - - .weak OTG_HS_IRQHandler - .thumb_set OTG_HS_IRQHandler,Default_Handler - - .weak HASH_RNG_IRQHandler - .thumb_set HASH_RNG_IRQHandler,Default_Handler - - .weak FPU_IRQHandler - .thumb_set FPU_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - - diff --git a/ports/stm/boards/startup_stm32f407xx.s b/ports/stm/boards/startup_stm32f407xx.s deleted file mode 100644 index 6b77655ca1b31..0000000000000 --- a/ports/stm/boards/startup_stm32f407xx.s +++ /dev/null @@ -1,516 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f405xx.s - * @author MCD Application Team - * @brief STM32F405xx Devices vector table for GCC based toolchains. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M4 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m4 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss -/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr sp, =_estack /* set stack pointer */ - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call static constructors */ -/* bl __libc_init_array */ -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - - -g_pfnVectors: - .word _estack - .word Reset_Handler - - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - - /* External Interrupts */ - .word WWDG_IRQHandler /* Window WatchDog */ - .word PVD_IRQHandler /* PVD through EXTI Line detection */ - .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ - .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_IRQHandler /* RCC */ - .word EXTI0_IRQHandler /* EXTI Line0 */ - .word EXTI1_IRQHandler /* EXTI Line1 */ - .word EXTI2_IRQHandler /* EXTI Line2 */ - .word EXTI3_IRQHandler /* EXTI Line3 */ - .word EXTI4_IRQHandler /* EXTI Line4 */ - .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ - .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ - .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ - .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ - .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ - .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ - .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ - .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ - .word CAN1_TX_IRQHandler /* CAN1 TX */ - .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ - .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ - .word CAN1_SCE_IRQHandler /* CAN1 SCE */ - .word EXTI9_5_IRQHandler /* External Line[9:5]s */ - .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ - .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ - .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word TIM2_IRQHandler /* TIM2 */ - .word TIM3_IRQHandler /* TIM3 */ - .word TIM4_IRQHandler /* TIM4 */ - .word I2C1_EV_IRQHandler /* I2C1 Event */ - .word I2C1_ER_IRQHandler /* I2C1 Error */ - .word I2C2_EV_IRQHandler /* I2C2 Event */ - .word I2C2_ER_IRQHandler /* I2C2 Error */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word USART3_IRQHandler /* USART3 */ - .word EXTI15_10_IRQHandler /* External Line[15:10]s */ - .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ - .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ - .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ - .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ - .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ - .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ - .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ - .word FSMC_IRQHandler /* FSMC */ - .word SDIO_IRQHandler /* SDIO */ - .word TIM5_IRQHandler /* TIM5 */ - .word SPI3_IRQHandler /* SPI3 */ - .word UART4_IRQHandler /* UART4 */ - .word UART5_IRQHandler /* UART5 */ - .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ - .word TIM7_IRQHandler /* TIM7 */ - .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ - .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ - .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ - .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ - .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word CAN2_TX_IRQHandler /* CAN2 TX */ - .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ - .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ - .word CAN2_SCE_IRQHandler /* CAN2 SCE */ - .word OTG_FS_IRQHandler /* USB OTG FS */ - .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ - .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ - .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ - .word USART6_IRQHandler /* USART6 */ - .word I2C3_EV_IRQHandler /* I2C3 event */ - .word I2C3_ER_IRQHandler /* I2C3 error */ - .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ - .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ - .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ - .word OTG_HS_IRQHandler /* USB OTG HS */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word HASH_RNG_IRQHandler /* Hash and Rng */ - .word FPU_IRQHandler /* FPU */ - - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMP_STAMP_IRQHandler - .thumb_set TAMP_STAMP_IRQHandler,Default_Handler - - .weak RTC_WKUP_IRQHandler - .thumb_set RTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Stream0_IRQHandler - .thumb_set DMA1_Stream0_IRQHandler,Default_Handler - - .weak DMA1_Stream1_IRQHandler - .thumb_set DMA1_Stream1_IRQHandler,Default_Handler - - .weak DMA1_Stream2_IRQHandler - .thumb_set DMA1_Stream2_IRQHandler,Default_Handler - - .weak DMA1_Stream3_IRQHandler - .thumb_set DMA1_Stream3_IRQHandler,Default_Handler - - .weak DMA1_Stream4_IRQHandler - .thumb_set DMA1_Stream4_IRQHandler,Default_Handler - - .weak DMA1_Stream5_IRQHandler - .thumb_set DMA1_Stream5_IRQHandler,Default_Handler - - .weak DMA1_Stream6_IRQHandler - .thumb_set DMA1_Stream6_IRQHandler,Default_Handler - - .weak ADC_IRQHandler - .thumb_set ADC_IRQHandler,Default_Handler - - .weak CAN1_TX_IRQHandler - .thumb_set CAN1_TX_IRQHandler,Default_Handler - - .weak CAN1_RX0_IRQHandler - .thumb_set CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SCE_IRQHandler - .thumb_set CAN1_SCE_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_TIM9_IRQHandler - .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler - - .weak TIM1_UP_TIM10_IRQHandler - .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_TIM11_IRQHandler - .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler - - .weak OTG_FS_WKUP_IRQHandler - .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler - - .weak TIM8_BRK_TIM12_IRQHandler - .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler - - .weak TIM8_UP_TIM13_IRQHandler - .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler - - .weak TIM8_TRG_COM_TIM14_IRQHandler - .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler - - .weak TIM8_CC_IRQHandler - .thumb_set TIM8_CC_IRQHandler,Default_Handler - - .weak DMA1_Stream7_IRQHandler - .thumb_set DMA1_Stream7_IRQHandler,Default_Handler - - .weak FSMC_IRQHandler - .thumb_set FSMC_IRQHandler,Default_Handler - - .weak SDIO_IRQHandler - .thumb_set SDIO_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak UART4_IRQHandler - .thumb_set UART4_IRQHandler,Default_Handler - - .weak UART5_IRQHandler - .thumb_set UART5_IRQHandler,Default_Handler - - .weak TIM6_DAC_IRQHandler - .thumb_set TIM6_DAC_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - - .weak DMA2_Stream0_IRQHandler - .thumb_set DMA2_Stream0_IRQHandler,Default_Handler - - .weak DMA2_Stream1_IRQHandler - .thumb_set DMA2_Stream1_IRQHandler,Default_Handler - - .weak DMA2_Stream2_IRQHandler - .thumb_set DMA2_Stream2_IRQHandler,Default_Handler - - .weak DMA2_Stream3_IRQHandler - .thumb_set DMA2_Stream3_IRQHandler,Default_Handler - - .weak DMA2_Stream4_IRQHandler - .thumb_set DMA2_Stream4_IRQHandler,Default_Handler - - .weak CAN2_TX_IRQHandler - .thumb_set CAN2_TX_IRQHandler,Default_Handler - - .weak CAN2_RX0_IRQHandler - .thumb_set CAN2_RX0_IRQHandler,Default_Handler - - .weak CAN2_RX1_IRQHandler - .thumb_set CAN2_RX1_IRQHandler,Default_Handler - - .weak CAN2_SCE_IRQHandler - .thumb_set CAN2_SCE_IRQHandler,Default_Handler - - .weak OTG_FS_IRQHandler - .thumb_set OTG_FS_IRQHandler,Default_Handler - - .weak DMA2_Stream5_IRQHandler - .thumb_set DMA2_Stream5_IRQHandler,Default_Handler - - .weak DMA2_Stream6_IRQHandler - .thumb_set DMA2_Stream6_IRQHandler,Default_Handler - - .weak DMA2_Stream7_IRQHandler - .thumb_set DMA2_Stream7_IRQHandler,Default_Handler - - .weak USART6_IRQHandler - .thumb_set USART6_IRQHandler,Default_Handler - - .weak I2C3_EV_IRQHandler - .thumb_set I2C3_EV_IRQHandler,Default_Handler - - .weak I2C3_ER_IRQHandler - .thumb_set I2C3_ER_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_OUT_IRQHandler - .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_IN_IRQHandler - .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler - - .weak OTG_HS_WKUP_IRQHandler - .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler - - .weak OTG_HS_IRQHandler - .thumb_set OTG_HS_IRQHandler,Default_Handler - - .weak HASH_RNG_IRQHandler - .thumb_set HASH_RNG_IRQHandler,Default_Handler - - .weak FPU_IRQHandler - .thumb_set FPU_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - - diff --git a/ports/stm/boards/startup_stm32f411xe.s b/ports/stm/boards/startup_stm32f411xe.s deleted file mode 100644 index 3aac640cb2f8e..0000000000000 --- a/ports/stm/boards/startup_stm32f411xe.s +++ /dev/null @@ -1,452 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f411xe.s - * @author MCD Application Team - * @brief STM32F411xExx Devices vector table for GCC based toolchains. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M4 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m4 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss -/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr sp, =_estack /* set stack pointer */ - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call static constructors */ -/* bl __libc_init_array */ -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - - /* External Interrupts */ - .word WWDG_IRQHandler /* Window WatchDog */ - .word PVD_IRQHandler /* PVD through EXTI Line detection */ - .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ - .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_IRQHandler /* RCC */ - .word EXTI0_IRQHandler /* EXTI Line0 */ - .word EXTI1_IRQHandler /* EXTI Line1 */ - .word EXTI2_IRQHandler /* EXTI Line2 */ - .word EXTI3_IRQHandler /* EXTI Line3 */ - .word EXTI4_IRQHandler /* EXTI Line4 */ - .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ - .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ - .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ - .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ - .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ - .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ - .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ - .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word EXTI9_5_IRQHandler /* External Line[9:5]s */ - .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ - .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ - .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word TIM2_IRQHandler /* TIM2 */ - .word TIM3_IRQHandler /* TIM3 */ - .word TIM4_IRQHandler /* TIM4 */ - .word I2C1_EV_IRQHandler /* I2C1 Event */ - .word I2C1_ER_IRQHandler /* I2C1 Error */ - .word I2C2_EV_IRQHandler /* I2C2 Event */ - .word I2C2_ER_IRQHandler /* I2C2 Error */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word 0 /* Reserved */ - .word EXTI15_10_IRQHandler /* External Line[15:10]s */ - .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ - .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ - .word 0 /* Reserved */ - .word SDIO_IRQHandler /* SDIO */ - .word TIM5_IRQHandler /* TIM5 */ - .word SPI3_IRQHandler /* SPI3 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ - .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ - .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ - .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ - .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word OTG_FS_IRQHandler /* USB OTG FS */ - .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ - .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ - .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ - .word USART6_IRQHandler /* USART6 */ - .word I2C3_EV_IRQHandler /* I2C3 event */ - .word I2C3_ER_IRQHandler /* I2C3 error */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word FPU_IRQHandler /* FPU */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word SPI4_IRQHandler /* SPI4 */ - .word SPI5_IRQHandler /* SPI5 */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMP_STAMP_IRQHandler - .thumb_set TAMP_STAMP_IRQHandler,Default_Handler - - .weak RTC_WKUP_IRQHandler - .thumb_set RTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Stream0_IRQHandler - .thumb_set DMA1_Stream0_IRQHandler,Default_Handler - - .weak DMA1_Stream1_IRQHandler - .thumb_set DMA1_Stream1_IRQHandler,Default_Handler - - .weak DMA1_Stream2_IRQHandler - .thumb_set DMA1_Stream2_IRQHandler,Default_Handler - - .weak DMA1_Stream3_IRQHandler - .thumb_set DMA1_Stream3_IRQHandler,Default_Handler - - .weak DMA1_Stream4_IRQHandler - .thumb_set DMA1_Stream4_IRQHandler,Default_Handler - - .weak DMA1_Stream5_IRQHandler - .thumb_set DMA1_Stream5_IRQHandler,Default_Handler - - .weak DMA1_Stream6_IRQHandler - .thumb_set DMA1_Stream6_IRQHandler,Default_Handler - - .weak ADC_IRQHandler - .thumb_set ADC_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_TIM9_IRQHandler - .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler - - .weak TIM1_UP_TIM10_IRQHandler - .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_TIM11_IRQHandler - .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler - - .weak OTG_FS_WKUP_IRQHandler - .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler - - .weak DMA1_Stream7_IRQHandler - .thumb_set DMA1_Stream7_IRQHandler,Default_Handler - - .weak SDIO_IRQHandler - .thumb_set SDIO_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak DMA2_Stream0_IRQHandler - .thumb_set DMA2_Stream0_IRQHandler,Default_Handler - - .weak DMA2_Stream1_IRQHandler - .thumb_set DMA2_Stream1_IRQHandler,Default_Handler - - .weak DMA2_Stream2_IRQHandler - .thumb_set DMA2_Stream2_IRQHandler,Default_Handler - - .weak DMA2_Stream3_IRQHandler - .thumb_set DMA2_Stream3_IRQHandler,Default_Handler - - .weak DMA2_Stream4_IRQHandler - .thumb_set DMA2_Stream4_IRQHandler,Default_Handler - - .weak OTG_FS_IRQHandler - .thumb_set OTG_FS_IRQHandler,Default_Handler - - .weak DMA2_Stream5_IRQHandler - .thumb_set DMA2_Stream5_IRQHandler,Default_Handler - - .weak DMA2_Stream6_IRQHandler - .thumb_set DMA2_Stream6_IRQHandler,Default_Handler - - .weak DMA2_Stream7_IRQHandler - .thumb_set DMA2_Stream7_IRQHandler,Default_Handler - - .weak USART6_IRQHandler - .thumb_set USART6_IRQHandler,Default_Handler - - .weak I2C3_EV_IRQHandler - .thumb_set I2C3_EV_IRQHandler,Default_Handler - - .weak I2C3_ER_IRQHandler - .thumb_set I2C3_ER_IRQHandler,Default_Handler - - .weak FPU_IRQHandler - .thumb_set FPU_IRQHandler,Default_Handler - - .weak SPI4_IRQHandler - .thumb_set SPI4_IRQHandler,Default_Handler - - .weak SPI5_IRQHandler - .thumb_set SPI5_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/ports/stm/boards/startup_stm32f412zx.s b/ports/stm/boards/startup_stm32f412zx.s deleted file mode 100644 index 8012207957fea..0000000000000 --- a/ports/stm/boards/startup_stm32f412zx.s +++ /dev/null @@ -1,524 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f412zx.s - * @author MCD Application Team - * @brief STM32F412Zx Devices vector table for GCC based toolchains. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M4 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m4 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss -/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr sp, =_estack /* set stack pointer */ - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call static constructors */ -/* bl __libc_init_array */ -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - - /* External Interrupts */ - .word WWDG_IRQHandler /* Window WatchDog */ - .word PVD_IRQHandler /* PVD through EXTI Line detection */ - .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ - .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_IRQHandler /* RCC */ - .word EXTI0_IRQHandler /* EXTI Line0 */ - .word EXTI1_IRQHandler /* EXTI Line1 */ - .word EXTI2_IRQHandler /* EXTI Line2 */ - .word EXTI3_IRQHandler /* EXTI Line3 */ - .word EXTI4_IRQHandler /* EXTI Line4 */ - .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ - .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ - .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ - .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ - .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ - .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ - .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ - .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ - .word CAN1_TX_IRQHandler /* CAN1 TX */ - .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ - .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ - .word CAN1_SCE_IRQHandler /* CAN1 SCE */ - .word EXTI9_5_IRQHandler /* External Line[9:5]s */ - .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ - .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ - .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word TIM2_IRQHandler /* TIM2 */ - .word TIM3_IRQHandler /* TIM3 */ - .word TIM4_IRQHandler /* TIM4 */ - .word I2C1_EV_IRQHandler /* I2C1 Event */ - .word I2C1_ER_IRQHandler /* I2C1 Error */ - .word I2C2_EV_IRQHandler /* I2C2 Event */ - .word I2C2_ER_IRQHandler /* I2C2 Error */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word USART3_IRQHandler /* USART3 */ - .word EXTI15_10_IRQHandler /* External Line[15:10]s */ - .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ - .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ - .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ - .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ - .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ - .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ - .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ - .word 0 /* Reserved */ - .word SDIO_IRQHandler /* SDIO */ - .word TIM5_IRQHandler /* TIM5 */ - .word SPI3_IRQHandler /* SPI3 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word TIM6_IRQHandler /* TIM6 */ - .word TIM7_IRQHandler /* TIM7 */ - .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ - .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ - .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ - .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ - .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ - .word DFSDM1_FLT0_IRQHandler /* DFSDM1 Filter0 */ - .word DFSDM1_FLT1_IRQHandler /* DFSDM1 Filter1 */ - .word CAN2_TX_IRQHandler /* CAN2 TX */ - .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ - .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ - .word CAN2_SCE_IRQHandler /* CAN2 SCE */ - .word OTG_FS_IRQHandler /* USB OTG FS */ - .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ - .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ - .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ - .word USART6_IRQHandler /* USART6 */ - .word I2C3_EV_IRQHandler /* I2C3 event */ - .word I2C3_ER_IRQHandler /* I2C3 error */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word RNG_IRQHandler /* RNG */ - .word FPU_IRQHandler /* FPU */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word SPI4_IRQHandler /* SPI4 */ - .word SPI5_IRQHandler /* SPI5 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word QUADSPI_IRQHandler /* QuadSPI */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word FMPI2C1_EV_IRQHandler /* FMPI2C1 Event */ - .word FMPI2C1_ER_IRQHandler /* FMPI2C1 Error */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMP_STAMP_IRQHandler - .thumb_set TAMP_STAMP_IRQHandler,Default_Handler - - .weak RTC_WKUP_IRQHandler - .thumb_set RTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Stream0_IRQHandler - .thumb_set DMA1_Stream0_IRQHandler,Default_Handler - - .weak DMA1_Stream1_IRQHandler - .thumb_set DMA1_Stream1_IRQHandler,Default_Handler - - .weak DMA1_Stream2_IRQHandler - .thumb_set DMA1_Stream2_IRQHandler,Default_Handler - - .weak DMA1_Stream3_IRQHandler - .thumb_set DMA1_Stream3_IRQHandler,Default_Handler - - .weak DMA1_Stream4_IRQHandler - .thumb_set DMA1_Stream4_IRQHandler,Default_Handler - - .weak DMA1_Stream5_IRQHandler - .thumb_set DMA1_Stream5_IRQHandler,Default_Handler - - .weak DMA1_Stream6_IRQHandler - .thumb_set DMA1_Stream6_IRQHandler,Default_Handler - - .weak ADC_IRQHandler - .thumb_set ADC_IRQHandler,Default_Handler - - .weak CAN1_TX_IRQHandler - .thumb_set CAN1_TX_IRQHandler,Default_Handler - - .weak CAN1_RX0_IRQHandler - .thumb_set CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SCE_IRQHandler - .thumb_set CAN1_SCE_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_TIM9_IRQHandler - .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler - - .weak TIM1_UP_TIM10_IRQHandler - .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_TIM11_IRQHandler - .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler - - .weak OTG_FS_WKUP_IRQHandler - .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler - - .weak TIM8_BRK_TIM12_IRQHandler - .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler - - .weak TIM8_UP_TIM13_IRQHandler - .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler - - .weak TIM8_TRG_COM_TIM14_IRQHandler - .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler - - .weak TIM8_CC_IRQHandler - .thumb_set TIM8_CC_IRQHandler,Default_Handler - - .weak DMA1_Stream7_IRQHandler - .thumb_set DMA1_Stream7_IRQHandler,Default_Handler - - .weak SDIO_IRQHandler - .thumb_set SDIO_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak TIM6_IRQHandler - .thumb_set TIM6_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - - .weak DMA2_Stream0_IRQHandler - .thumb_set DMA2_Stream0_IRQHandler,Default_Handler - - .weak DMA2_Stream1_IRQHandler - .thumb_set DMA2_Stream1_IRQHandler,Default_Handler - - .weak DMA2_Stream2_IRQHandler - .thumb_set DMA2_Stream2_IRQHandler,Default_Handler - - .weak DMA2_Stream3_IRQHandler - .thumb_set DMA2_Stream3_IRQHandler,Default_Handler - - .weak DMA2_Stream4_IRQHandler - .thumb_set DMA2_Stream4_IRQHandler,Default_Handler - - .weak DFSDM1_FLT0_IRQHandler - .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler - - .weak DFSDM1_FLT1_IRQHandler - .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler - - .weak CAN2_TX_IRQHandler - .thumb_set CAN2_TX_IRQHandler,Default_Handler - - .weak CAN2_RX0_IRQHandler - .thumb_set CAN2_RX0_IRQHandler,Default_Handler - - .weak CAN2_RX1_IRQHandler - .thumb_set CAN2_RX1_IRQHandler,Default_Handler - - .weak CAN2_SCE_IRQHandler - .thumb_set CAN2_SCE_IRQHandler,Default_Handler - - .weak OTG_FS_IRQHandler - .thumb_set OTG_FS_IRQHandler,Default_Handler - - .weak DMA2_Stream5_IRQHandler - .thumb_set DMA2_Stream5_IRQHandler,Default_Handler - - .weak DMA2_Stream6_IRQHandler - .thumb_set DMA2_Stream6_IRQHandler,Default_Handler - - .weak DMA2_Stream7_IRQHandler - .thumb_set DMA2_Stream7_IRQHandler,Default_Handler - - .weak USART6_IRQHandler - .thumb_set USART6_IRQHandler,Default_Handler - - .weak I2C3_EV_IRQHandler - .thumb_set I2C3_EV_IRQHandler,Default_Handler - - .weak I2C3_ER_IRQHandler - .thumb_set I2C3_ER_IRQHandler,Default_Handler - - .weak RNG_IRQHandler - .thumb_set RNG_IRQHandler,Default_Handler - - .weak FPU_IRQHandler - .thumb_set FPU_IRQHandler,Default_Handler - - .weak SPI4_IRQHandler - .thumb_set SPI4_IRQHandler,Default_Handler - - .weak SPI5_IRQHandler - .thumb_set SPI5_IRQHandler,Default_Handler - - .weak QUADSPI_IRQHandler - .thumb_set QUADSPI_IRQHandler,Default_Handler - - .weak FMPI2C1_EV_IRQHandler - .thumb_set FMPI2C1_EV_IRQHandler,Default_Handler - - .weak FMPI2C1_ER_IRQHandler - .thumb_set FMPI2C1_ER_IRQHandler,Default_Handler -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/ports/stm/boards/startup_stm32f767xx.s b/ports/stm/boards/startup_stm32f767xx.s deleted file mode 100644 index 84309d4dadc64..0000000000000 --- a/ports/stm/boards/startup_stm32f767xx.s +++ /dev/null @@ -1,618 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f767xx.s - * @author MCD Application Team - * @brief STM32F767xx Devices vector table for GCC based toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M7 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m7 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss -/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr sp, =_estack /* set stack pointer */ - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss - -/* Call the clock system initialization function.*/ - bl SystemInit -/* Call static constructors */ -/* bl __libc_init_array */ -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M7. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - - /* External Interrupts */ - .word WWDG_IRQHandler /* Window WatchDog */ - .word PVD_IRQHandler /* PVD through EXTI Line detection */ - .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ - .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_IRQHandler /* RCC */ - .word EXTI0_IRQHandler /* EXTI Line0 */ - .word EXTI1_IRQHandler /* EXTI Line1 */ - .word EXTI2_IRQHandler /* EXTI Line2 */ - .word EXTI3_IRQHandler /* EXTI Line3 */ - .word EXTI4_IRQHandler /* EXTI Line4 */ - .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ - .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ - .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ - .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ - .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ - .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ - .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ - .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ - .word CAN1_TX_IRQHandler /* CAN1 TX */ - .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ - .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ - .word CAN1_SCE_IRQHandler /* CAN1 SCE */ - .word EXTI9_5_IRQHandler /* External Line[9:5]s */ - .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ - .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ - .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word TIM2_IRQHandler /* TIM2 */ - .word TIM3_IRQHandler /* TIM3 */ - .word TIM4_IRQHandler /* TIM4 */ - .word I2C1_EV_IRQHandler /* I2C1 Event */ - .word I2C1_ER_IRQHandler /* I2C1 Error */ - .word I2C2_EV_IRQHandler /* I2C2 Event */ - .word I2C2_ER_IRQHandler /* I2C2 Error */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word USART3_IRQHandler /* USART3 */ - .word EXTI15_10_IRQHandler /* External Line[15:10]s */ - .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ - .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ - .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ - .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ - .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ - .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ - .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ - .word FMC_IRQHandler /* FMC */ - .word SDMMC1_IRQHandler /* SDMMC1 */ - .word TIM5_IRQHandler /* TIM5 */ - .word SPI3_IRQHandler /* SPI3 */ - .word UART4_IRQHandler /* UART4 */ - .word UART5_IRQHandler /* UART5 */ - .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ - .word TIM7_IRQHandler /* TIM7 */ - .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ - .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ - .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ - .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ - .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ - .word ETH_IRQHandler /* Ethernet */ - .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ - .word CAN2_TX_IRQHandler /* CAN2 TX */ - .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ - .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ - .word CAN2_SCE_IRQHandler /* CAN2 SCE */ - .word OTG_FS_IRQHandler /* USB OTG FS */ - .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ - .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ - .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ - .word USART6_IRQHandler /* USART6 */ - .word I2C3_EV_IRQHandler /* I2C3 event */ - .word I2C3_ER_IRQHandler /* I2C3 error */ - .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ - .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ - .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ - .word OTG_HS_IRQHandler /* USB OTG HS */ - .word DCMI_IRQHandler /* DCMI */ - .word 0 /* Reserved */ - .word RNG_IRQHandler /* RNG */ - .word FPU_IRQHandler /* FPU */ - .word UART7_IRQHandler /* UART7 */ - .word UART8_IRQHandler /* UART8 */ - .word SPI4_IRQHandler /* SPI4 */ - .word SPI5_IRQHandler /* SPI5 */ - .word SPI6_IRQHandler /* SPI6 */ - .word SAI1_IRQHandler /* SAI1 */ - .word LTDC_IRQHandler /* LTDC */ - .word LTDC_ER_IRQHandler /* LTDC error */ - .word DMA2D_IRQHandler /* DMA2D */ - .word SAI2_IRQHandler /* SAI2 */ - .word QUADSPI_IRQHandler /* QUADSPI */ - .word LPTIM1_IRQHandler /* LPTIM1 */ - .word CEC_IRQHandler /* HDMI_CEC */ - .word I2C4_EV_IRQHandler /* I2C4 Event */ - .word I2C4_ER_IRQHandler /* I2C4 Error */ - .word SPDIF_RX_IRQHandler /* SPDIF_RX */ - .word 0 /* Reserved */ - .word DFSDM1_FLT0_IRQHandler /* DFSDM1 Filter 0 global Interrupt */ - .word DFSDM1_FLT1_IRQHandler /* DFSDM1 Filter 1 global Interrupt */ - .word DFSDM1_FLT2_IRQHandler /* DFSDM1 Filter 2 global Interrupt */ - .word DFSDM1_FLT3_IRQHandler /* DFSDM1 Filter 3 global Interrupt */ - .word SDMMC2_IRQHandler /* SDMMC2 */ - .word CAN3_TX_IRQHandler /* CAN3 TX */ - .word CAN3_RX0_IRQHandler /* CAN3 RX0 */ - .word CAN3_RX1_IRQHandler /* CAN3 RX1 */ - .word CAN3_SCE_IRQHandler /* CAN3 SCE */ - .word JPEG_IRQHandler /* JPEG */ - .word MDIOS_IRQHandler /* MDIOS */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMP_STAMP_IRQHandler - .thumb_set TAMP_STAMP_IRQHandler,Default_Handler - - .weak RTC_WKUP_IRQHandler - .thumb_set RTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Stream0_IRQHandler - .thumb_set DMA1_Stream0_IRQHandler,Default_Handler - - .weak DMA1_Stream1_IRQHandler - .thumb_set DMA1_Stream1_IRQHandler,Default_Handler - - .weak DMA1_Stream2_IRQHandler - .thumb_set DMA1_Stream2_IRQHandler,Default_Handler - - .weak DMA1_Stream3_IRQHandler - .thumb_set DMA1_Stream3_IRQHandler,Default_Handler - - .weak DMA1_Stream4_IRQHandler - .thumb_set DMA1_Stream4_IRQHandler,Default_Handler - - .weak DMA1_Stream5_IRQHandler - .thumb_set DMA1_Stream5_IRQHandler,Default_Handler - - .weak DMA1_Stream6_IRQHandler - .thumb_set DMA1_Stream6_IRQHandler,Default_Handler - - .weak ADC_IRQHandler - .thumb_set ADC_IRQHandler,Default_Handler - - .weak CAN1_TX_IRQHandler - .thumb_set CAN1_TX_IRQHandler,Default_Handler - - .weak CAN1_RX0_IRQHandler - .thumb_set CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SCE_IRQHandler - .thumb_set CAN1_SCE_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_TIM9_IRQHandler - .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler - - .weak TIM1_UP_TIM10_IRQHandler - .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_TIM11_IRQHandler - .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler - - .weak OTG_FS_WKUP_IRQHandler - .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler - - .weak TIM8_BRK_TIM12_IRQHandler - .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler - - .weak TIM8_UP_TIM13_IRQHandler - .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler - - .weak TIM8_TRG_COM_TIM14_IRQHandler - .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler - - .weak TIM8_CC_IRQHandler - .thumb_set TIM8_CC_IRQHandler,Default_Handler - - .weak DMA1_Stream7_IRQHandler - .thumb_set DMA1_Stream7_IRQHandler,Default_Handler - - .weak FMC_IRQHandler - .thumb_set FMC_IRQHandler,Default_Handler - - .weak SDMMC1_IRQHandler - .thumb_set SDMMC1_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak UART4_IRQHandler - .thumb_set UART4_IRQHandler,Default_Handler - - .weak UART5_IRQHandler - .thumb_set UART5_IRQHandler,Default_Handler - - .weak TIM6_DAC_IRQHandler - .thumb_set TIM6_DAC_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - - .weak DMA2_Stream0_IRQHandler - .thumb_set DMA2_Stream0_IRQHandler,Default_Handler - - .weak DMA2_Stream1_IRQHandler - .thumb_set DMA2_Stream1_IRQHandler,Default_Handler - - .weak DMA2_Stream2_IRQHandler - .thumb_set DMA2_Stream2_IRQHandler,Default_Handler - - .weak DMA2_Stream3_IRQHandler - .thumb_set DMA2_Stream3_IRQHandler,Default_Handler - - .weak DMA2_Stream4_IRQHandler - .thumb_set DMA2_Stream4_IRQHandler,Default_Handler - - .weak DMA2_Stream4_IRQHandler - .thumb_set DMA2_Stream4_IRQHandler,Default_Handler - - .weak ETH_IRQHandler - .thumb_set ETH_IRQHandler,Default_Handler - - .weak ETH_WKUP_IRQHandler - .thumb_set ETH_WKUP_IRQHandler,Default_Handler - - .weak CAN2_TX_IRQHandler - .thumb_set CAN2_TX_IRQHandler,Default_Handler - - .weak CAN2_RX0_IRQHandler - .thumb_set CAN2_RX0_IRQHandler,Default_Handler - - .weak CAN2_RX1_IRQHandler - .thumb_set CAN2_RX1_IRQHandler,Default_Handler - - .weak CAN2_SCE_IRQHandler - .thumb_set CAN2_SCE_IRQHandler,Default_Handler - - .weak OTG_FS_IRQHandler - .thumb_set OTG_FS_IRQHandler,Default_Handler - - .weak DMA2_Stream5_IRQHandler - .thumb_set DMA2_Stream5_IRQHandler,Default_Handler - - .weak DMA2_Stream6_IRQHandler - .thumb_set DMA2_Stream6_IRQHandler,Default_Handler - - .weak DMA2_Stream7_IRQHandler - .thumb_set DMA2_Stream7_IRQHandler,Default_Handler - - .weak USART6_IRQHandler - .thumb_set USART6_IRQHandler,Default_Handler - - .weak I2C3_EV_IRQHandler - .thumb_set I2C3_EV_IRQHandler,Default_Handler - - .weak I2C3_ER_IRQHandler - .thumb_set I2C3_ER_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_OUT_IRQHandler - .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_IN_IRQHandler - .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler - - .weak OTG_HS_WKUP_IRQHandler - .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler - - .weak OTG_HS_IRQHandler - .thumb_set OTG_HS_IRQHandler,Default_Handler - - .weak DCMI_IRQHandler - .thumb_set DCMI_IRQHandler,Default_Handler - - .weak RNG_IRQHandler - .thumb_set RNG_IRQHandler,Default_Handler - - .weak FPU_IRQHandler - .thumb_set FPU_IRQHandler,Default_Handler - - .weak UART7_IRQHandler - .thumb_set UART7_IRQHandler,Default_Handler - - .weak UART8_IRQHandler - .thumb_set UART8_IRQHandler,Default_Handler - - .weak SPI4_IRQHandler - .thumb_set SPI4_IRQHandler,Default_Handler - - .weak SPI5_IRQHandler - .thumb_set SPI5_IRQHandler,Default_Handler - - .weak SPI6_IRQHandler - .thumb_set SPI6_IRQHandler,Default_Handler - - .weak SAI1_IRQHandler - .thumb_set SAI1_IRQHandler,Default_Handler - - .weak LTDC_IRQHandler - .thumb_set LTDC_IRQHandler,Default_Handler - - .weak LTDC_ER_IRQHandler - .thumb_set LTDC_ER_IRQHandler,Default_Handler - - .weak DMA2D_IRQHandler - .thumb_set DMA2D_IRQHandler,Default_Handler - - .weak SAI2_IRQHandler - .thumb_set SAI2_IRQHandler,Default_Handler - - .weak QUADSPI_IRQHandler - .thumb_set QUADSPI_IRQHandler,Default_Handler - - .weak LPTIM1_IRQHandler - .thumb_set LPTIM1_IRQHandler,Default_Handler - - .weak CEC_IRQHandler - .thumb_set CEC_IRQHandler,Default_Handler - - .weak I2C4_EV_IRQHandler - .thumb_set I2C4_EV_IRQHandler,Default_Handler - - .weak I2C4_ER_IRQHandler - .thumb_set I2C4_ER_IRQHandler,Default_Handler - - .weak SPDIF_RX_IRQHandler - .thumb_set SPDIF_RX_IRQHandler,Default_Handler - - .weak DFSDM1_FLT0_IRQHandler - .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler - - .weak DFSDM1_FLT1_IRQHandler - .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler - - .weak DFSDM1_FLT2_IRQHandler - .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler - - .weak DFSDM1_FLT3_IRQHandler - .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler - - .weak SDMMC2_IRQHandler - .thumb_set SDMMC2_IRQHandler,Default_Handler - - .weak CAN3_TX_IRQHandler - .thumb_set CAN3_TX_IRQHandler,Default_Handler - - .weak CAN3_RX0_IRQHandler - .thumb_set CAN3_RX0_IRQHandler,Default_Handler - - .weak CAN3_RX1_IRQHandler - .thumb_set CAN3_RX1_IRQHandler,Default_Handler - - .weak CAN3_SCE_IRQHandler - .thumb_set CAN3_SCE_IRQHandler,Default_Handler - - .weak JPEG_IRQHandler - .thumb_set JPEG_IRQHandler,Default_Handler - - .weak MDIOS_IRQHandler - .thumb_set MDIOS_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/ports/stm/boards/startup_stm32h743xx.s b/ports/stm/boards/startup_stm32h743xx.s deleted file mode 100644 index 357f7a7bab039..0000000000000 --- a/ports/stm/boards/startup_stm32h743xx.s +++ /dev/null @@ -1,748 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32h743xx.s - * @author MCD Application Team - * @brief STM32H743xx Devices vector table for GCC based toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m7 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss -/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr sp, =_estack /* set stack pointer */ - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call static constructors */ -/* bl __libc_init_array */ -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - - /* External Interrupts */ - .word WWDG_IRQHandler /* Window WatchDog */ - .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */ - .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ - .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_IRQHandler /* RCC */ - .word EXTI0_IRQHandler /* EXTI Line0 */ - .word EXTI1_IRQHandler /* EXTI Line1 */ - .word EXTI2_IRQHandler /* EXTI Line2 */ - .word EXTI3_IRQHandler /* EXTI Line3 */ - .word EXTI4_IRQHandler /* EXTI Line4 */ - .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ - .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ - .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ - .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ - .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ - .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ - .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ - .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ - .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */ - .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */ - .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */ - .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */ - .word EXTI9_5_IRQHandler /* External Line[9:5]s */ - .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */ - .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */ - .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word TIM2_IRQHandler /* TIM2 */ - .word TIM3_IRQHandler /* TIM3 */ - .word TIM4_IRQHandler /* TIM4 */ - .word I2C1_EV_IRQHandler /* I2C1 Event */ - .word I2C1_ER_IRQHandler /* I2C1 Error */ - .word I2C2_EV_IRQHandler /* I2C2 Event */ - .word I2C2_ER_IRQHandler /* I2C2 Error */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word USART3_IRQHandler /* USART3 */ - .word EXTI15_10_IRQHandler /* External Line[15:10]s */ - .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ - .word 0 /* Reserved */ - .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ - .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ - .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ - .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ - .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ - .word FMC_IRQHandler /* FMC */ - .word SDMMC1_IRQHandler /* SDMMC1 */ - .word TIM5_IRQHandler /* TIM5 */ - .word SPI3_IRQHandler /* SPI3 */ - .word UART4_IRQHandler /* UART4 */ - .word UART5_IRQHandler /* UART5 */ - .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ - .word TIM7_IRQHandler /* TIM7 */ - .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ - .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ - .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ - .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ - .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ - .word ETH_IRQHandler /* Ethernet */ - .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ - .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ - .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ - .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ - .word USART6_IRQHandler /* USART6 */ - .word I2C3_EV_IRQHandler /* I2C3 event */ - .word I2C3_ER_IRQHandler /* I2C3 error */ - .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ - .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ - .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ - .word OTG_HS_IRQHandler /* USB OTG HS */ - .word DCMI_IRQHandler /* DCMI */ - .word 0 /* Reserved */ - .word RNG_IRQHandler /* Rng */ - .word FPU_IRQHandler /* FPU */ - .word UART7_IRQHandler /* UART7 */ - .word UART8_IRQHandler /* UART8 */ - .word SPI4_IRQHandler /* SPI4 */ - .word SPI5_IRQHandler /* SPI5 */ - .word SPI6_IRQHandler /* SPI6 */ - .word SAI1_IRQHandler /* SAI1 */ - .word LTDC_IRQHandler /* LTDC */ - .word LTDC_ER_IRQHandler /* LTDC error */ - .word DMA2D_IRQHandler /* DMA2D */ - .word SAI2_IRQHandler /* SAI2 */ - .word QUADSPI_IRQHandler /* QUADSPI */ - .word LPTIM1_IRQHandler /* LPTIM1 */ - .word CEC_IRQHandler /* HDMI_CEC */ - .word I2C4_EV_IRQHandler /* I2C4 Event */ - .word I2C4_ER_IRQHandler /* I2C4 Error */ - .word SPDIF_RX_IRQHandler /* SPDIF_RX */ - .word OTG_FS_EP1_OUT_IRQHandler /* USB OTG FS End Point 1 Out */ - .word OTG_FS_EP1_IN_IRQHandler /* USB OTG FS End Point 1 In */ - .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI */ - .word OTG_FS_IRQHandler /* USB OTG FS */ - .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */ - .word HRTIM1_Master_IRQHandler /* HRTIM Master Timer global Interrupt */ - .word HRTIM1_TIMA_IRQHandler /* HRTIM Timer A global Interrupt */ - .word HRTIM1_TIMB_IRQHandler /* HRTIM Timer B global Interrupt */ - .word HRTIM1_TIMC_IRQHandler /* HRTIM Timer C global Interrupt */ - .word HRTIM1_TIMD_IRQHandler /* HRTIM Timer D global Interrupt */ - .word HRTIM1_TIME_IRQHandler /* HRTIM Timer E global Interrupt */ - .word HRTIM1_FLT_IRQHandler /* HRTIM Fault global Interrupt */ - .word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */ - .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */ - .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */ - .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */ - .word SAI3_IRQHandler /* SAI3 global Interrupt */ - .word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */ - .word TIM15_IRQHandler /* TIM15 global Interrupt */ - .word TIM16_IRQHandler /* TIM16 global Interrupt */ - .word TIM17_IRQHandler /* TIM17 global Interrupt */ - .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */ - .word MDIOS_IRQHandler /* MDIOS global Interrupt */ - .word JPEG_IRQHandler /* JPEG global Interrupt */ - .word MDMA_IRQHandler /* MDMA global Interrupt */ - .word 0 /* Reserved */ - .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */ - .word HSEM1_IRQHandler /* HSEM1 global Interrupt */ - .word 0 /* Reserved */ - .word ADC3_IRQHandler /* ADC3 global Interrupt */ - .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */ - .word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */ - .word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */ - .word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */ - .word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */ - .word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */ - .word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */ - .word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */ - .word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */ - .word COMP1_IRQHandler /* COMP1 global Interrupt */ - .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */ - .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */ - .word LPTIM4_IRQHandler /* LP TIM4 global interrupt */ - .word LPTIM5_IRQHandler /* LP TIM5 global interrupt */ - .word LPUART1_IRQHandler /* LP UART1 interrupt */ - .word 0 /* Reserved */ - .word CRS_IRQHandler /* Clock Recovery Global Interrupt */ - .word ECC_IRQHandler /* ECC diagnostic Global Interrupt */ - .word SAI4_IRQHandler /* SAI4 global interrupt */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_AVD_IRQHandler - .thumb_set PVD_AVD_IRQHandler,Default_Handler - - .weak TAMP_STAMP_IRQHandler - .thumb_set TAMP_STAMP_IRQHandler,Default_Handler - - .weak RTC_WKUP_IRQHandler - .thumb_set RTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Stream0_IRQHandler - .thumb_set DMA1_Stream0_IRQHandler,Default_Handler - - .weak DMA1_Stream1_IRQHandler - .thumb_set DMA1_Stream1_IRQHandler,Default_Handler - - .weak DMA1_Stream2_IRQHandler - .thumb_set DMA1_Stream2_IRQHandler,Default_Handler - - .weak DMA1_Stream3_IRQHandler - .thumb_set DMA1_Stream3_IRQHandler,Default_Handler - - .weak DMA1_Stream4_IRQHandler - .thumb_set DMA1_Stream4_IRQHandler,Default_Handler - - .weak DMA1_Stream5_IRQHandler - .thumb_set DMA1_Stream5_IRQHandler,Default_Handler - - .weak DMA1_Stream6_IRQHandler - .thumb_set DMA1_Stream6_IRQHandler,Default_Handler - - .weak ADC_IRQHandler - .thumb_set ADC_IRQHandler,Default_Handler - - .weak FDCAN1_IT0_IRQHandler - .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler - - .weak FDCAN2_IT0_IRQHandler - .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler - - .weak FDCAN1_IT1_IRQHandler - .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler - - .weak FDCAN2_IT1_IRQHandler - .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_IRQHandler - .thumb_set TIM1_BRK_IRQHandler,Default_Handler - - .weak TIM1_UP_IRQHandler - .thumb_set TIM1_UP_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_IRQHandler - .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler - - .weak TIM8_BRK_TIM12_IRQHandler - .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler - - .weak TIM8_UP_TIM13_IRQHandler - .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler - - .weak TIM8_TRG_COM_TIM14_IRQHandler - .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler - - .weak TIM8_CC_IRQHandler - .thumb_set TIM8_CC_IRQHandler,Default_Handler - - .weak DMA1_Stream7_IRQHandler - .thumb_set DMA1_Stream7_IRQHandler,Default_Handler - - .weak FMC_IRQHandler - .thumb_set FMC_IRQHandler,Default_Handler - - .weak SDMMC1_IRQHandler - .thumb_set SDMMC1_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak UART4_IRQHandler - .thumb_set UART4_IRQHandler,Default_Handler - - .weak UART5_IRQHandler - .thumb_set UART5_IRQHandler,Default_Handler - - .weak TIM6_DAC_IRQHandler - .thumb_set TIM6_DAC_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - - .weak DMA2_Stream0_IRQHandler - .thumb_set DMA2_Stream0_IRQHandler,Default_Handler - - .weak DMA2_Stream1_IRQHandler - .thumb_set DMA2_Stream1_IRQHandler,Default_Handler - - .weak DMA2_Stream2_IRQHandler - .thumb_set DMA2_Stream2_IRQHandler,Default_Handler - - .weak DMA2_Stream3_IRQHandler - .thumb_set DMA2_Stream3_IRQHandler,Default_Handler - - .weak DMA2_Stream4_IRQHandler - .thumb_set DMA2_Stream4_IRQHandler,Default_Handler - - .weak ETH_IRQHandler - .thumb_set ETH_IRQHandler,Default_Handler - - .weak ETH_WKUP_IRQHandler - .thumb_set ETH_WKUP_IRQHandler,Default_Handler - - .weak FDCAN_CAL_IRQHandler - .thumb_set FDCAN_CAL_IRQHandler,Default_Handler - - .weak DMA2_Stream5_IRQHandler - .thumb_set DMA2_Stream5_IRQHandler,Default_Handler - - .weak DMA2_Stream6_IRQHandler - .thumb_set DMA2_Stream6_IRQHandler,Default_Handler - - .weak DMA2_Stream7_IRQHandler - .thumb_set DMA2_Stream7_IRQHandler,Default_Handler - - .weak USART6_IRQHandler - .thumb_set USART6_IRQHandler,Default_Handler - - .weak I2C3_EV_IRQHandler - .thumb_set I2C3_EV_IRQHandler,Default_Handler - - .weak I2C3_ER_IRQHandler - .thumb_set I2C3_ER_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_OUT_IRQHandler - .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_IN_IRQHandler - .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler - - .weak OTG_HS_WKUP_IRQHandler - .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler - - .weak OTG_HS_IRQHandler - .thumb_set OTG_HS_IRQHandler,Default_Handler - - .weak DCMI_IRQHandler - .thumb_set DCMI_IRQHandler,Default_Handler - - .weak RNG_IRQHandler - .thumb_set RNG_IRQHandler,Default_Handler - - .weak FPU_IRQHandler - .thumb_set FPU_IRQHandler,Default_Handler - - .weak UART7_IRQHandler - .thumb_set UART7_IRQHandler,Default_Handler - - .weak UART8_IRQHandler - .thumb_set UART8_IRQHandler,Default_Handler - - .weak SPI4_IRQHandler - .thumb_set SPI4_IRQHandler,Default_Handler - - .weak SPI5_IRQHandler - .thumb_set SPI5_IRQHandler,Default_Handler - - .weak SPI6_IRQHandler - .thumb_set SPI6_IRQHandler,Default_Handler - - .weak SAI1_IRQHandler - .thumb_set SAI1_IRQHandler,Default_Handler - - .weak LTDC_IRQHandler - .thumb_set LTDC_IRQHandler,Default_Handler - - .weak LTDC_ER_IRQHandler - .thumb_set LTDC_ER_IRQHandler,Default_Handler - - .weak DMA2D_IRQHandler - .thumb_set DMA2D_IRQHandler,Default_Handler - - .weak SAI2_IRQHandler - .thumb_set SAI2_IRQHandler,Default_Handler - - .weak QUADSPI_IRQHandler - .thumb_set QUADSPI_IRQHandler,Default_Handler - - .weak LPTIM1_IRQHandler - .thumb_set LPTIM1_IRQHandler,Default_Handler - - .weak CEC_IRQHandler - .thumb_set CEC_IRQHandler,Default_Handler - - .weak I2C4_EV_IRQHandler - .thumb_set I2C4_EV_IRQHandler,Default_Handler - - .weak I2C4_ER_IRQHandler - .thumb_set I2C4_ER_IRQHandler,Default_Handler - - .weak SPDIF_RX_IRQHandler - .thumb_set SPDIF_RX_IRQHandler,Default_Handler - - .weak OTG_FS_EP1_OUT_IRQHandler - .thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler - - .weak OTG_FS_EP1_IN_IRQHandler - .thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler - - .weak OTG_FS_WKUP_IRQHandler - .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler - - .weak OTG_FS_IRQHandler - .thumb_set OTG_FS_IRQHandler,Default_Handler - - .weak DMAMUX1_OVR_IRQHandler - .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler - - .weak HRTIM1_Master_IRQHandler - .thumb_set HRTIM1_Master_IRQHandler,Default_Handler - - .weak HRTIM1_TIMA_IRQHandler - .thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler - - .weak HRTIM1_TIMB_IRQHandler - .thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler - - .weak HRTIM1_TIMC_IRQHandler - .thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler - - .weak HRTIM1_TIMD_IRQHandler - .thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler - - .weak HRTIM1_TIME_IRQHandler - .thumb_set HRTIM1_TIME_IRQHandler,Default_Handler - - .weak HRTIM1_FLT_IRQHandler - .thumb_set HRTIM1_FLT_IRQHandler,Default_Handler - - .weak DFSDM1_FLT0_IRQHandler - .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler - - .weak DFSDM1_FLT1_IRQHandler - .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler - - .weak DFSDM1_FLT2_IRQHandler - .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler - - .weak DFSDM1_FLT3_IRQHandler - .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler - - .weak SAI3_IRQHandler - .thumb_set SAI3_IRQHandler,Default_Handler - - .weak SWPMI1_IRQHandler - .thumb_set SWPMI1_IRQHandler,Default_Handler - - .weak TIM15_IRQHandler - .thumb_set TIM15_IRQHandler,Default_Handler - - .weak TIM16_IRQHandler - .thumb_set TIM16_IRQHandler,Default_Handler - - .weak TIM17_IRQHandler - .thumb_set TIM17_IRQHandler,Default_Handler - - .weak MDIOS_WKUP_IRQHandler - .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler - - .weak MDIOS_IRQHandler - .thumb_set MDIOS_IRQHandler,Default_Handler - - .weak JPEG_IRQHandler - .thumb_set JPEG_IRQHandler,Default_Handler - - .weak MDMA_IRQHandler - .thumb_set MDMA_IRQHandler,Default_Handler - - .weak SDMMC2_IRQHandler - .thumb_set SDMMC2_IRQHandler,Default_Handler - - .weak HSEM1_IRQHandler - .thumb_set HSEM1_IRQHandler,Default_Handler - - .weak ADC3_IRQHandler - .thumb_set ADC3_IRQHandler,Default_Handler - - .weak DMAMUX2_OVR_IRQHandler - .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler - - .weak BDMA_Channel0_IRQHandler - .thumb_set BDMA_Channel0_IRQHandler,Default_Handler - - .weak BDMA_Channel1_IRQHandler - .thumb_set BDMA_Channel1_IRQHandler,Default_Handler - - .weak BDMA_Channel2_IRQHandler - .thumb_set BDMA_Channel2_IRQHandler,Default_Handler - - .weak BDMA_Channel3_IRQHandler - .thumb_set BDMA_Channel3_IRQHandler,Default_Handler - - .weak BDMA_Channel4_IRQHandler - .thumb_set BDMA_Channel4_IRQHandler,Default_Handler - - .weak BDMA_Channel5_IRQHandler - .thumb_set BDMA_Channel5_IRQHandler,Default_Handler - - .weak BDMA_Channel6_IRQHandler - .thumb_set BDMA_Channel6_IRQHandler,Default_Handler - - .weak BDMA_Channel7_IRQHandler - .thumb_set BDMA_Channel7_IRQHandler,Default_Handler - - .weak COMP1_IRQHandler - .thumb_set COMP1_IRQHandler,Default_Handler - - .weak LPTIM2_IRQHandler - .thumb_set LPTIM2_IRQHandler,Default_Handler - - .weak LPTIM3_IRQHandler - .thumb_set LPTIM3_IRQHandler,Default_Handler - - .weak LPTIM4_IRQHandler - .thumb_set LPTIM4_IRQHandler,Default_Handler - - .weak LPTIM5_IRQHandler - .thumb_set LPTIM5_IRQHandler,Default_Handler - - .weak LPUART1_IRQHandler - .thumb_set LPUART1_IRQHandler,Default_Handler - - .weak CRS_IRQHandler - .thumb_set CRS_IRQHandler,Default_Handler - - .weak ECC_IRQHandler - .thumb_set ECC_IRQHandler,Default_Handler - - .weak SAI4_IRQHandler - .thumb_set SAI4_IRQHandler,Default_Handler - - .weak WAKEUP_PIN_IRQHandler - .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/ports/stm/system_stm32f4xx.c b/ports/stm/boards/system_stm32f4xx.c similarity index 100% rename from ports/stm/system_stm32f4xx.c rename to ports/stm/boards/system_stm32f4xx.c diff --git a/ports/stm/system_stm32f7xx.c b/ports/stm/boards/system_stm32f7xx.c similarity index 100% rename from ports/stm/system_stm32f7xx.c rename to ports/stm/boards/system_stm32f7xx.c diff --git a/ports/stm/system_stm32h7xx.c b/ports/stm/boards/system_stm32h7xx.c similarity index 100% rename from ports/stm/system_stm32h7xx.c rename to ports/stm/boards/system_stm32h7xx.c diff --git a/ports/stm/boards/thunderpack/mpconfigboard.mk b/ports/stm/boards/thunderpack/mpconfigboard.mk index 40b0e92506b1c..37aded836621b 100644 --- a/ports/stm/boards/thunderpack/mpconfigboard.mk +++ b/ports/stm/boards/thunderpack/mpconfigboard.mk @@ -11,7 +11,7 @@ CIRCUITPY_NVM = 1 MCU_SERIES = F4 MCU_VARIANT = STM32F411xE -MCU_PACKAGE = 48 +MCU_PACKAGE = UFQFPN48 LD_FILE = boards/common_nvm.ld LD_FILE = boards/STM32F411_nvm.ld diff --git a/ports/stm/common-hal/busio/I2C.c b/ports/stm/common-hal/busio/I2C.c index 4daefb58bcab6..31a1278d3501a 100644 --- a/ports/stm/common-hal/busio/I2C.c +++ b/ports/stm/common-hal/busio/I2C.c @@ -34,8 +34,9 @@ #include "supervisor/shared/translate.h" #include "common-hal/microcontroller/Pin.h" -//arrays use 0 based numbering: I2C1 is stored at index 0 -#define MAX_I2C 3 +// Arrays use 0 based numbering: I2C1 is stored at index 0 +#define MAX_I2C 4 + STATIC bool reserved_i2c[MAX_I2C]; STATIC bool never_reset_i2c[MAX_I2C]; @@ -58,31 +59,37 @@ void i2c_reset(void) { void common_hal_busio_i2c_construct(busio_i2c_obj_t *self, const mcu_pin_obj_t* scl, const mcu_pin_obj_t* sda, uint32_t frequency, uint32_t timeout) { - //match pins to I2C objects + // Match pins to I2C objects I2C_TypeDef * I2Cx; uint8_t sda_len = MP_ARRAY_SIZE(mcu_i2c_sda_list); uint8_t scl_len = MP_ARRAY_SIZE(mcu_i2c_scl_list); bool i2c_taken = false; + bool search_done = false; for (uint i = 0; i < sda_len; i++) { if (mcu_i2c_sda_list[i].pin == sda) { for (uint j = 0; j < scl_len; j++) { if ((mcu_i2c_scl_list[j].pin == scl) && (mcu_i2c_scl_list[j].periph_index == mcu_i2c_sda_list[i].periph_index)) { - //keep looking if the I2C is taken, could be another SCL that works - if (reserved_i2c[mcu_i2c_scl_list[i].periph_index - 1]) { + // Keep looking if the I2C is taken, could be another SCL that works + if (reserved_i2c[mcu_i2c_scl_list[j].periph_index - 1]) { i2c_taken = true; continue; } self->scl = &mcu_i2c_scl_list[j]; self->sda = &mcu_i2c_sda_list[i]; + // Multi-level break here, or it'll pick the highest numbered peripheral (inefficient) + search_done = true; break; } } + if (search_done) { + break; + } } } - //handle typedef selection, errors + // Handle typedef selection, errors if (self->sda != NULL && self->scl != NULL ) { I2Cx = mcu_i2c_banks[self->sda->periph_index - 1]; } else { @@ -93,7 +100,7 @@ void common_hal_busio_i2c_construct(busio_i2c_obj_t *self, } } - //Start GPIO for each pin + // Start GPIO for each pin GPIO_InitTypeDef GPIO_InitStruct = {0}; GPIO_InitStruct.Pin = pin_mask(sda->number); GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; @@ -109,13 +116,19 @@ void common_hal_busio_i2c_construct(busio_i2c_obj_t *self, GPIO_InitStruct.Alternate = self->scl->altfn_index; HAL_GPIO_Init(pin_port(scl->port), &GPIO_InitStruct); - //Note: due to I2C soft reboot issue, do not relocate clock init. + // Note: due to I2C soft reboot issue, do not relocate clock init. i2c_clock_enable(1 << (self->sda->periph_index - 1)); reserved_i2c[self->sda->periph_index - 1] = true; - self->handle.Instance = I2Cx; + // Handle the HAL handle differences + #if (CPY_STM32H7 || CPY_STM32F7) + self->handle.Init.Timing = 0x40604E73; //Taken from STCube examples + #else self->handle.Init.ClockSpeed = 100000; self->handle.Init.DutyCycle = I2C_DUTYCYCLE_2; + #endif + + self->handle.Instance = I2Cx; self->handle.Init.OwnAddress1 = 0; self->handle.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; self->handle.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; @@ -206,7 +219,7 @@ uint8_t common_hal_busio_i2c_read(busio_i2c_obj_t *self, uint16_t addr, } STATIC void i2c_clock_enable(uint8_t mask) { - //Note: hard reset required due to soft reboot issue. + // Note: hard reset required due to soft reboot issue. #ifdef I2C1 if (mask & (1 << 0)) { __HAL_RCC_I2C1_CLK_ENABLE(); @@ -228,6 +241,13 @@ STATIC void i2c_clock_enable(uint8_t mask) { __HAL_RCC_I2C3_RELEASE_RESET(); } #endif + #ifdef I2C4 + if (mask & (1 << 3)) { + __HAL_RCC_I2C4_CLK_ENABLE(); + __HAL_RCC_I2C4_FORCE_RESET(); + __HAL_RCC_I2C4_RELEASE_RESET(); + } + #endif } STATIC void i2c_clock_disable(uint8_t mask) { @@ -246,4 +266,9 @@ STATIC void i2c_clock_disable(uint8_t mask) { __HAL_RCC_I2C3_CLK_DISABLE(); } #endif + #ifdef I2C4 + if (mask & (1 << 3)) { + __HAL_RCC_I2C4_CLK_DISABLE(); + } + #endif } diff --git a/ports/stm/common-hal/busio/SPI.c b/ports/stm/common-hal/busio/SPI.c index cf001556096f2..a83f8703c722b 100644 --- a/ports/stm/common-hal/busio/SPI.c +++ b/ports/stm/common-hal/busio/SPI.c @@ -40,6 +40,7 @@ //arrays use 0 based numbering: SPI1 is stored at index 0 #define MAX_SPI 6 + STATIC bool reserved_spi[MAX_SPI]; STATIC bool never_reset_spi[MAX_SPI]; @@ -48,14 +49,24 @@ STATIC void spi_clock_enable(uint8_t mask); STATIC void spi_clock_disable(uint8_t mask); STATIC uint32_t get_busclock(SPI_TypeDef * instance) { - //SPI2 and 3 are on PCLK1, if they exist. - #ifdef SPI2 - if (instance == SPI2) return HAL_RCC_GetPCLK1Freq(); - #endif - #ifdef SPI3 - if (instance == SPI3) return HAL_RCC_GetPCLK1Freq(); + #if (CPY_STM32H7) + if (instance == SPI1 || instance == SPI2 || instance == SPI3) { + return HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI123); + } else if (instance == SPI4 || instance == SPI5) { + return HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI45); + } else { + return HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI6); + } + #elif (CPY_STM32F4 || CPY_STM32F7) + //SPI2 and 3 are on PCLK1, if they exist. + #ifdef SPI2 + if (instance == SPI2) return HAL_RCC_GetPCLK1Freq(); + #endif + #ifdef SPI3 + if (instance == SPI3) return HAL_RCC_GetPCLK1Freq(); + #endif + return HAL_RCC_GetPCLK2Freq(); #endif - return HAL_RCC_GetPCLK2Freq(); } STATIC uint32_t stm32_baud_to_spi_div(uint32_t baudrate, uint16_t * prescaler, uint32_t busclock) { @@ -107,6 +118,7 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self, uint8_t mosi_len = MP_ARRAY_SIZE(mcu_spi_mosi_list); uint8_t miso_len = MP_ARRAY_SIZE(mcu_spi_miso_list); bool spi_taken = false; + bool search_done = false; //SCK is not optional. MOSI and MISO are for (uint i = 0; i < sck_len; i++) { @@ -130,11 +142,20 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self, self->sck = &mcu_spi_sck_list[i]; self->mosi = &mcu_spi_mosi_list[j]; self->miso = &mcu_spi_miso_list[k]; + + // Multi-level break to pick lowest peripheral + search_done = true; break; } } + if (search_done) { + break; + } } } + if (search_done) { + break; + } // if just MISO, reduce search } else if (miso != NULL) { for (uint j = 0; j < miso_len; j++) { @@ -149,9 +170,15 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self, self->sck = &mcu_spi_sck_list[i]; self->mosi = NULL; self->miso = &mcu_spi_miso_list[j]; + + // Multi-level break to pick lowest peripheral + search_done = true; break; } } + if (search_done) { + break; + } // if just MOSI, reduce search } else if (mosi != NULL) { for (uint j = 0; j < mosi_len; j++) { @@ -166,9 +193,15 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self, self->sck = &mcu_spi_sck_list[i]; self->mosi = &mcu_spi_mosi_list[j]; self->miso = NULL; + + // Multi-level break to pick lowest peripheral + search_done = true; break; } } + if (search_done) { + break; + } } else { //throw an error immediately mp_raise_ValueError(translate("Must provide MISO or MOSI pin")); @@ -222,7 +255,7 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self, self->handle.Instance = SPIx; self->handle.Init.Mode = SPI_MODE_MASTER; // Direction change only required for RX-only, see RefMan RM0090:884 - self->handle.Init.Direction = (self->mosi == NULL) ? SPI_CR1_RXONLY : SPI_DIRECTION_2LINES; + self->handle.Init.Direction = (self->mosi == NULL) ? SPI_DIRECTION_2LINES_RXONLY : SPI_DIRECTION_2LINES; self->handle.Init.DataSize = SPI_DATASIZE_8BIT; self->handle.Init.CLKPolarity = SPI_POLARITY_LOW; self->handle.Init.CLKPhase = SPI_PHASE_1EDGE; diff --git a/ports/stm/common-hal/busio/UART.c b/ports/stm/common-hal/busio/UART.c index df05a68cb4c3d..a5a76ef828c60 100644 --- a/ports/stm/common-hal/busio/UART.c +++ b/ports/stm/common-hal/busio/UART.c @@ -84,6 +84,7 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self, uint8_t rx_len = MP_ARRAY_SIZE(mcu_uart_rx_list); bool uart_taken = false; uint8_t periph_index = 0; //origin 0 corrected + bool search_done = false; if ((rts != NULL) || (cts != NULL) || (rs485_dir != NULL) || (rs485_invert == true)) { mp_raise_ValueError(translate("RTS/CTS/RS485 Not yet supported on this device")); @@ -106,9 +107,15 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self, //store pins if not self->tx = &mcu_uart_tx_list[i]; self->rx = &mcu_uart_rx_list[j]; + + // Multi-level break to pick lowest peripheral + search_done = true; break; } } + if (search_done) { + break; + } } } periph_index = self->tx->periph_index - 1; @@ -125,6 +132,9 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self, } //store pins if not self->rx = &mcu_uart_rx_list[i]; + + // Multi-level break to pick lowest peripheral + search_done = true; break; } } @@ -142,6 +152,9 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self, } //store pins if not self->tx = &mcu_uart_tx_list[i]; + + // Multi-level break to pick lowest peripheral + search_done = true; break; } } diff --git a/ports/stm/common-hal/digitalio/DigitalInOut.c b/ports/stm/common-hal/digitalio/DigitalInOut.c index 82a8a72e4fa58..647a46e907f18 100644 --- a/ports/stm/common-hal/digitalio/DigitalInOut.c +++ b/ports/stm/common-hal/digitalio/DigitalInOut.c @@ -29,12 +29,12 @@ #include "py/runtime.h" #include "supervisor/shared/translate.h" -//TODO: rework this module to use HAL only -#ifdef STM32H743xx +// The HAL is sparse on obtaining register information, so we use the LLs here. +#if (CPY_STM32H7) #include "stm32h7xx_ll_gpio.h" -#elif STM32F767xx +#elif (CPY_STM32F7) #include "stm32f7xx_ll_gpio.h" -#else +#elif (CPY_STM32F4) #include "stm32f4xx_ll_gpio.h" #endif @@ -152,7 +152,6 @@ void common_hal_digitalio_digitalinout_set_pull( digitalio_pull_t common_hal_digitalio_digitalinout_get_pull( digitalio_digitalinout_obj_t *self) { - switch (LL_GPIO_GetPinPull(pin_port(self->pin->port), pin_mask(self->pin->number))) { case LL_GPIO_PULL_UP: return PULL_UP; diff --git a/ports/stm/fatfs_port.c b/ports/stm/fatfs_port.c index 13ac21fb1bcca..6a17f627bd585 100644 --- a/ports/stm/fatfs_port.c +++ b/ports/stm/fatfs_port.c @@ -28,6 +28,6 @@ #include "lib/oofatfs/ff.h" DWORD get_fattime(void) { - // TODO: Implement this function. For now, fake it. + // TODO: Implement this function. For now, fake it. return ((2016 - 1980) << 25) | ((12) << 21) | ((4) << 16) | ((00) << 11) | ((18) << 5) | (23 / 2); } diff --git a/ports/stm/mpconfigport.h b/ports/stm/mpconfigport.h index 65b0611241ec3..f570d32e5ff2b 100644 --- a/ports/stm/mpconfigport.h +++ b/ports/stm/mpconfigport.h @@ -47,6 +47,24 @@ extern uint8_t _ld_default_stack_size; // The STM32 HAL file is included virtually everywhere: #include STM32_HAL_H +// These prevent you from accidentally omitting a python file that links mpconfigport +// and having a file accept a lack of chip family as an option. +#if defined(STM32F4) +#define CPY_STM32F4 1 +#define CPY_STM32F7 0 +#define CPY_STM32H7 0 +#elif defined(STM32F7) +#define CPY_STM32F4 0 +#define CPY_STM32F7 1 +#define CPY_STM32H7 0 +#elif defined(STM32H7) +#define CPY_STM32F4 0 +#define CPY_STM32F7 0 +#define CPY_STM32H7 1 +#else +#error undefined processor +#endif + // Board flags: #ifndef BOARD_OVERWRITE_SWD #define BOARD_OVERWRITE_SWD (0) diff --git a/ports/stm/mpconfigport.mk b/ports/stm/mpconfigport.mk index e1e983e39fa02..323fd7646624e 100644 --- a/ports/stm/mpconfigport.mk +++ b/ports/stm/mpconfigport.mk @@ -78,7 +78,7 @@ ifeq ($(MCU_SERIES), H7) CIRCUITPY_DIGITALIO = 1 CIRCUITPY_ANALOGIO = 0 CIRCUITPY_MICROCONTROLLER = 1 - CIRCUITPY_BUSIO = 0 + CIRCUITPY_BUSIO = 1 CIRCUITPY_PULSEIO = 0 CIRCUITPY_OS = 0 CIRCUITPY_STORAGE = 0 @@ -94,7 +94,7 @@ ifeq ($(MCU_SERIES), F7) CIRCUITPY_DIGITALIO = 1 CIRCUITPY_ANALOGIO = 0 CIRCUITPY_MICROCONTROLLER = 1 - CIRCUITPY_BUSIO = 0 + CIRCUITPY_BUSIO = 1 CIRCUITPY_PULSEIO = 0 CIRCUITPY_OS = 0 CIRCUITPY_STORAGE = 0 diff --git a/ports/stm/peripherals/stm32f4/stm32f407xx/gpio.c b/ports/stm/peripherals/stm32f4/stm32f407xx/gpio.c index dfdd61fde4364..a5f4eae78ce3d 100644 --- a/ports/stm/peripherals/stm32f4/stm32f407xx/gpio.c +++ b/ports/stm/peripherals/stm32f4/stm32f407xx/gpio.c @@ -27,7 +27,7 @@ #include "peripherals/gpio.h" #include "common-hal/microcontroller/Pin.h" -void stm32f4_peripherals_gpio_init(void) { +void stm32_peripherals_gpio_init(void) { //Enable all GPIO for now __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); diff --git a/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c b/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c index 97ec933eabeed..3ec1b5b7953a1 100644 --- a/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c +++ b/ports/stm/peripherals/stm32f4/stm32f412zx/gpio.c @@ -29,7 +29,6 @@ void stm32_peripherals_gpio_init(void) { - GPIO_InitTypeDef GPIO_InitStruct = {0}; __HAL_RCC_GPIOE_CLK_ENABLE(); __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOF_CLK_ENABLE(); diff --git a/ports/stm/peripherals/stm32f7/stm32f767xx/clocks.c b/ports/stm/peripherals/stm32f7/stm32f767xx/clocks.c index 15f1188706d9e..a0d58f4fcfe4a 100644 --- a/ports/stm/peripherals/stm32f7/stm32f767xx/clocks.c +++ b/ports/stm/peripherals/stm32f7/stm32f767xx/clocks.c @@ -44,7 +44,7 @@ void stm32_peripherals_clocks_init(void) { RCC_OscInitStruct.HSEState = RCC_HSE_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000; + RCC_OscInitStruct.PLL.PLLM = BOARD_OSC_DIV; RCC_OscInitStruct.PLL.PLLN = 432; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; RCC_OscInitStruct.PLL.PLLQ = 9; diff --git a/ports/stm/peripherals/stm32h7/stm32h743xx/clocks.c b/ports/stm/peripherals/stm32h7/stm32h743xx/clocks.c index a961362aa009e..d231f25d0bb47 100644 --- a/ports/stm/peripherals/stm32h7/stm32h743xx/clocks.c +++ b/ports/stm/peripherals/stm32h7/stm32h743xx/clocks.c @@ -28,56 +28,56 @@ #include "py/mpconfig.h" void stm32_peripherals_clocks_init(void) { - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; - /* The PWR block is always enabled on the H7 series- there is no clock + /* The PWR block is always enabled on the H7 series- there is no clock enable. For now, use the default VOS3 scale mode (lowest) and limit clock frequencies to avoid potential current draw problems from bus power when using the max clock speeds throughout the chip. */ - /* Enable HSE Oscillator and activate PLL1 with HSE as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - RCC_OscInitStruct.HSIState = RCC_HSI_OFF; - RCC_OscInitStruct.CSIState = RCC_CSI_OFF; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000; - RCC_OscInitStruct.PLL.PLLN = 336; - RCC_OscInitStruct.PLL.PLLP = 2; - RCC_OscInitStruct.PLL.PLLQ = 7; - RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_0; - RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOMEDIUM; - RCC_OscInitStruct.PLL.PLLFRACN = 0; - HAL_RCC_OscConfig(&RCC_OscInitStruct); + /* Enable HSE Oscillator and activate PLL1 with HSE as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.HSIState = RCC_HSI_OFF; + RCC_OscInitStruct.CSIState = RCC_CSI_OFF; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = BOARD_OSC_DIV; + RCC_OscInitStruct.PLL.PLLN = 336; + RCC_OscInitStruct.PLL.PLLP = 2; + RCC_OscInitStruct.PLL.PLLQ = 7; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_0; + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOMEDIUM; + RCC_OscInitStruct.PLL.PLLFRACN = 0; + HAL_RCC_OscConfig(&RCC_OscInitStruct); - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | \ - RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | \ - RCC_CLOCKTYPE_D3PCLK1); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | \ + RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | \ + RCC_CLOCKTYPE_D3PCLK1); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1; - /* Unlike on the STM32F4 family, it appears the maximum APB frequencies are + /* Unlike on the STM32F4 family, it appears the maximum APB frequencies are device-dependent- 120 MHz for this board according to Figure 2 of the datasheet. Dividing by half will be safe for now. */ - RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; - RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; - RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; - RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; + RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; + RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; + RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; - /* 4 wait states required for 168MHz and VOS3. */ - HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4); + /* 4 wait states required for 168MHz and VOS3. */ + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4); - /* Like on F4, on H7, USB's actual peripheral clock and bus clock are + /* Like on F4, on H7, USB's actual peripheral clock and bus clock are separate. However, the main system PLL (PLL1) doesn't have a direct connection to the USB peripheral clock to generate 48 MHz, so we do this dance. This will connect PLL1's Q output to the USB peripheral clock. */ - RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct; + RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct; - RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; - RCC_PeriphCLKInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL; - HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct); + RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; + RCC_PeriphCLKInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL; + HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct); } diff --git a/ports/stm/supervisor/internal_flash.h b/ports/stm/supervisor/internal_flash.h index e54cd92311e8a..53388d3544e55 100644 --- a/ports/stm/supervisor/internal_flash.h +++ b/ports/stm/supervisor/internal_flash.h @@ -40,8 +40,9 @@ #ifdef STM32F411xE #define STM32_FLASH_SIZE 0x80000 //512KiB -#ifdef CIRCUITPY_NVM +#if CIRCUITPY_NVM #define INTERNAL_FLASH_FILESYSTEM_SIZE 0x8000 //32KiB +#define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08004000 #else #define INTERNAL_FLASH_FILESYSTEM_SIZE 0xC000 //48KiB #define INTERNAL_FLASH_FILESYSTEM_START_ADDR 0x08004000 diff --git a/ports/stm/supervisor/port.c b/ports/stm/supervisor/port.c index 16796d9ce3a21..d9d720280da9e 100644 --- a/ports/stm/supervisor/port.c +++ b/ports/stm/supervisor/port.c @@ -31,11 +31,11 @@ #include "tick.h" #include "common-hal/microcontroller/Pin.h" +#include "common-hal/busio/I2C.h" +#include "common-hal/busio/SPI.h" +#include "common-hal/busio/UART.h" #if defined(STM32F4) - #include "common-hal/busio/I2C.h" - #include "common-hal/busio/SPI.h" - #include "common-hal/busio/UART.h" #include "common-hal/pulseio/PWMOut.h" #include "common-hal/pulseio/PulseOut.h" #include "common-hal/pulseio/PulseIn.h" @@ -187,12 +187,13 @@ safe_mode_t port_init(void) { void reset_port(void) { reset_all_pins(); + i2c_reset(); + spi_reset(); + uart_reset(); // TODO: it'd be nice if this was more automatic #if defined(STM32F4) - i2c_reset(); - spi_reset(); - uart_reset(); + pwmout_reset(); pulseout_reset(); pulsein_reset(); From 5ac38c95cc914c69e56a0f646131b34826b6f59a Mon Sep 17 00:00:00 2001 From: Lucian Copeland Date: Mon, 13 Apr 2020 12:03:05 -0400 Subject: [PATCH 10/17] Various requested fixes --- ports/stm/Makefile | 1 - .../stm/boards/nucleo_f767zi/mpconfigboard.mk | 4 +-- .../boards/nucleo_h743zi_2/mpconfigboard.mk | 4 +-- ports/stm/boards/thunderpack/mpconfigboard.mk | 2 +- ports/stm/common-hal/busio/I2C.c | 6 ++-- ports/stm/common-hal/busio/SPI.c | 24 ++++----------- ports/stm/common-hal/busio/UART.c | 12 +------- ports/stm/supervisor/internal_flash.c | 10 ------- ports/stm/supervisor/port.c | 30 +++++++++---------- ports/stm/supervisor/usb.c | 26 +++++++--------- supervisor/shared/stack.c | 2 +- 11 files changed, 40 insertions(+), 81 deletions(-) diff --git a/ports/stm/Makefile b/ports/stm/Makefile index 355fd1d026b1d..dc32f6c7a82e9 100755 --- a/ports/stm/Makefile +++ b/ports/stm/Makefile @@ -255,7 +255,6 @@ OBJ += $(addprefix $(BUILD)/, $(SRC_SHARED_MODULE_EXPANDED:.c=.o)) ifeq ($(INTERNAL_LIBM),1) OBJ += $(addprefix $(BUILD)/, $(SRC_LIBM:.c=.o)) endif -#OBJ += $(addprefix $(BUILD)/, $(SRC_O)) OBJ += $(addprefix $(BUILD)/, $(SRC_S:.s=.o)) OBJ += $(addprefix $(BUILD)/, $(SRC_MOD:.c=.o)) diff --git a/ports/stm/boards/nucleo_f767zi/mpconfigboard.mk b/ports/stm/boards/nucleo_f767zi/mpconfigboard.mk index cac4a273eb0a0..c8c2a3d2b1b6a 100644 --- a/ports/stm/boards/nucleo_f767zi/mpconfigboard.mk +++ b/ports/stm/boards/nucleo_f767zi/mpconfigboard.mk @@ -1,5 +1,5 @@ -USB_VID = 0x239A #REPLACE -USB_PID = 0x808A #REPLACE +USB_VID = 0x239A +USB_PID = 0x809A USB_PRODUCT = "Nucleo F767ZI - CPy" USB_MANUFACTURER = "STMicroelectronics" USB_DEVICES = "CDC,MSC" diff --git a/ports/stm/boards/nucleo_h743zi_2/mpconfigboard.mk b/ports/stm/boards/nucleo_h743zi_2/mpconfigboard.mk index dd7f05f290b89..01ace06a239a0 100644 --- a/ports/stm/boards/nucleo_h743zi_2/mpconfigboard.mk +++ b/ports/stm/boards/nucleo_h743zi_2/mpconfigboard.mk @@ -1,5 +1,5 @@ -USB_VID = 0x239A #REPLACE -USB_PID = 0x808A #REPLACE +USB_VID = 0x239A +USB_PID = 0x8098 USB_PRODUCT = "Nucleo H743ZI - CPy" USB_MANUFACTURER = "STMicroelectronics" USB_DEVICES = "CDC,MSC" diff --git a/ports/stm/boards/thunderpack/mpconfigboard.mk b/ports/stm/boards/thunderpack/mpconfigboard.mk index 37aded836621b..007b00cdd13f5 100644 --- a/ports/stm/boards/thunderpack/mpconfigboard.mk +++ b/ports/stm/boards/thunderpack/mpconfigboard.mk @@ -13,5 +13,5 @@ MCU_SERIES = F4 MCU_VARIANT = STM32F411xE MCU_PACKAGE = UFQFPN48 -LD_FILE = boards/common_nvm.ld +LD_COMMON = boards/common_nvm.ld LD_FILE = boards/STM32F411_nvm.ld diff --git a/ports/stm/common-hal/busio/I2C.c b/ports/stm/common-hal/busio/I2C.c index 31a1278d3501a..e3c59e7e05e96 100644 --- a/ports/stm/common-hal/busio/I2C.c +++ b/ports/stm/common-hal/busio/I2C.c @@ -64,7 +64,6 @@ void common_hal_busio_i2c_construct(busio_i2c_obj_t *self, uint8_t sda_len = MP_ARRAY_SIZE(mcu_i2c_sda_list); uint8_t scl_len = MP_ARRAY_SIZE(mcu_i2c_scl_list); bool i2c_taken = false; - bool search_done = false; for (uint i = 0; i < sda_len; i++) { if (mcu_i2c_sda_list[i].pin == sda) { @@ -78,12 +77,11 @@ void common_hal_busio_i2c_construct(busio_i2c_obj_t *self, } self->scl = &mcu_i2c_scl_list[j]; self->sda = &mcu_i2c_sda_list[i]; - // Multi-level break here, or it'll pick the highest numbered peripheral (inefficient) - search_done = true; break; } } - if (search_done) { + if (self->scl != NULL) { + // Multi-level break to pick lowest peripheral break; } } diff --git a/ports/stm/common-hal/busio/SPI.c b/ports/stm/common-hal/busio/SPI.c index a83f8703c722b..2572c7f26a7f9 100644 --- a/ports/stm/common-hal/busio/SPI.c +++ b/ports/stm/common-hal/busio/SPI.c @@ -118,7 +118,6 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self, uint8_t mosi_len = MP_ARRAY_SIZE(mcu_spi_mosi_list); uint8_t miso_len = MP_ARRAY_SIZE(mcu_spi_miso_list); bool spi_taken = false; - bool search_done = false; //SCK is not optional. MOSI and MISO are for (uint i = 0; i < sck_len; i++) { @@ -142,18 +141,15 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self, self->sck = &mcu_spi_sck_list[i]; self->mosi = &mcu_spi_mosi_list[j]; self->miso = &mcu_spi_miso_list[k]; - - // Multi-level break to pick lowest peripheral - search_done = true; break; } } - if (search_done) { - break; + if (self->sck != NULL) { + break; // Multi-level break to pick lowest peripheral } } } - if (search_done) { + if (self->sck != NULL) { break; } // if just MISO, reduce search @@ -161,22 +157,17 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self, for (uint j = 0; j < miso_len; j++) { if ((mcu_spi_miso_list[j].pin == miso) //only SCK and MISO need the same index && (mcu_spi_sck_list[i].periph_index == mcu_spi_miso_list[j].periph_index)) { - //keep looking if the SPI is taken, edge case if (reserved_spi[mcu_spi_sck_list[i].periph_index - 1]) { spi_taken = true; continue; } - //store pins if not self->sck = &mcu_spi_sck_list[i]; self->mosi = NULL; self->miso = &mcu_spi_miso_list[j]; - - // Multi-level break to pick lowest peripheral - search_done = true; break; } } - if (search_done) { + if (self->sck != NULL) { break; } // if just MOSI, reduce search @@ -184,22 +175,17 @@ void common_hal_busio_spi_construct(busio_spi_obj_t *self, for (uint j = 0; j < mosi_len; j++) { if ((mcu_spi_mosi_list[j].pin == mosi) //only SCK and MOSI need the same index && (mcu_spi_sck_list[i].periph_index == mcu_spi_mosi_list[j].periph_index)) { - //keep looking if the SPI is taken, edge case if (reserved_spi[mcu_spi_sck_list[i].periph_index - 1]) { spi_taken = true; continue; } - //store pins if not self->sck = &mcu_spi_sck_list[i]; self->mosi = &mcu_spi_mosi_list[j]; self->miso = NULL; - - // Multi-level break to pick lowest peripheral - search_done = true; break; } } - if (search_done) { + if (self->sck != NULL) { break; } } else { diff --git a/ports/stm/common-hal/busio/UART.c b/ports/stm/common-hal/busio/UART.c index a5a76ef828c60..cb5460c68e814 100644 --- a/ports/stm/common-hal/busio/UART.c +++ b/ports/stm/common-hal/busio/UART.c @@ -84,7 +84,6 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self, uint8_t rx_len = MP_ARRAY_SIZE(mcu_uart_rx_list); bool uart_taken = false; uint8_t periph_index = 0; //origin 0 corrected - bool search_done = false; if ((rts != NULL) || (cts != NULL) || (rs485_dir != NULL) || (rs485_invert == true)) { mp_raise_ValueError(translate("RTS/CTS/RS485 Not yet supported on this device")); @@ -107,13 +106,10 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self, //store pins if not self->tx = &mcu_uart_tx_list[i]; self->rx = &mcu_uart_rx_list[j]; - - // Multi-level break to pick lowest peripheral - search_done = true; break; } } - if (search_done) { + if (self->tx != NULL) { break; } } @@ -132,9 +128,6 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self, } //store pins if not self->rx = &mcu_uart_rx_list[i]; - - // Multi-level break to pick lowest peripheral - search_done = true; break; } } @@ -152,9 +145,6 @@ void common_hal_busio_uart_construct(busio_uart_obj_t *self, } //store pins if not self->tx = &mcu_uart_tx_list[i]; - - // Multi-level break to pick lowest peripheral - search_done = true; break; } } diff --git a/ports/stm/supervisor/internal_flash.c b/ports/stm/supervisor/internal_flash.c index 7d394d187a651..03fa73d5fbf26 100644 --- a/ports/stm/supervisor/internal_flash.c +++ b/ports/stm/supervisor/internal_flash.c @@ -181,8 +181,6 @@ void supervisor_flash_flush(void) { EraseInitStruct.Sector = flash_get_sector_info(_cache_flash_addr, §or_start_addr, §or_size); EraseInitStruct.NbSectors = 1; if (sector_size > sizeof(_flash_cache)) { - __ASM volatile ("bkpt"); - mp_printf(&mp_plat_print, "FLASH ERR: invalid sector\n"); reset_into_safe_mode(FLASH_WRITE_FAIL); } @@ -196,8 +194,6 @@ void supervisor_flash_flush(void) { if (HAL_FLASHEx_Erase(&EraseInitStruct, &SectorError) != HAL_OK) { // error occurred during sector erase HAL_FLASH_Lock(); // lock the flash - __ASM volatile ("bkpt"); - mp_printf(&mp_plat_print, "FLASH ERR: erase failure\n"); reset_into_safe_mode(FLASH_WRITE_FAIL); } @@ -211,7 +207,6 @@ void supervisor_flash_flush(void) { (uint32_t)cache_addr) != HAL_OK) { // error occurred during flash write HAL_FLASH_Lock(); // lock the flash - __ASM volatile ("bkpt"); reset_into_safe_mode(FLASH_WRITE_FAIL); } // RAM memory is by word (4 byte), but flash memory is by byte @@ -226,7 +221,6 @@ void supervisor_flash_flush(void) { (uint64_t)*cache_addr) != HAL_OK) { // error occurred during flash write HAL_FLASH_Lock(); // lock the flash - __ASM volatile ("bkpt"); reset_into_safe_mode(FLASH_WRITE_FAIL); } // RAM memory is by word (4 byte), but flash memory is by byte @@ -267,8 +261,6 @@ mp_uint_t supervisor_flash_write_blocks(const uint8_t *src, uint32_t block_num, int32_t dest = convert_block_to_flash_addr(block_num); if (dest == -1) { // bad block number - __ASM volatile ("bkpt"); - mp_printf(&mp_plat_print, "BAD FLASH BLOCK ERROR"); return false; } @@ -281,8 +273,6 @@ mp_uint_t supervisor_flash_write_blocks(const uint8_t *src, uint32_t block_num, // Fail for any sector outside the 16k ones for now if (sector_size > sizeof(_flash_cache)) { - __ASM volatile ("bkpt"); - mp_printf(&mp_plat_print, "FLASH ERR: invalid sector\n"); reset_into_safe_mode(FLASH_WRITE_FAIL); } diff --git a/ports/stm/supervisor/port.c b/ports/stm/supervisor/port.c index d9d720280da9e..81a12d6c4b66d 100644 --- a/ports/stm/supervisor/port.c +++ b/ports/stm/supervisor/port.c @@ -31,14 +31,16 @@ #include "tick.h" #include "common-hal/microcontroller/Pin.h" + +#if CIRCUITPY_BUSIO #include "common-hal/busio/I2C.h" #include "common-hal/busio/SPI.h" #include "common-hal/busio/UART.h" - -#if defined(STM32F4) - #include "common-hal/pulseio/PWMOut.h" - #include "common-hal/pulseio/PulseOut.h" - #include "common-hal/pulseio/PulseIn.h" +#endif +#if CIRCUITPY_PULSEIO +#include "common-hal/pulseio/PWMOut.h" +#include "common-hal/pulseio/PulseOut.h" +#include "common-hal/pulseio/PulseIn.h" #endif #include "clocks.h" @@ -114,7 +116,6 @@ __attribute__((used, naked)) void Reset_Handler(void) { // The first number in RBAR is the region number. When searching for a policy, the region with // the highest number wins. If none match, then the default policy set at enable applies. - // TODO: what is the default policy? Where is that set? // TODO: do I need to subdivide this up? // Mark all the flash the same until instructed otherwise. @@ -124,7 +125,7 @@ __attribute__((used, naked)) void Reset_Handler(void) { // This the ITCM. Set it to read-only because we've loaded everything already and it's easy to // accidentally write the wrong value to 0x00000000 (aka NULL). MPU->RBAR = ARM_MPU_RBAR(12, 0x00000000U); - MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_RO, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, NO_SUBREGIONS, ARM_MPU_REGION_SIZE_128KB); + MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_RO, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, NO_SUBREGIONS, ARM_MPU_REGION_SIZE_64KB); // This the DTCM. MPU->RBAR = ARM_MPU_RBAR(14, 0x20000000U); @@ -187,17 +188,16 @@ safe_mode_t port_init(void) { void reset_port(void) { reset_all_pins(); +#if CIRCUITPY_BUSIO i2c_reset(); spi_reset(); uart_reset(); - - // TODO: it'd be nice if this was more automatic - #if defined(STM32F4) - - pwmout_reset(); - pulseout_reset(); - pulsein_reset(); - #endif +#endif +#if CIRCUITPY_PULSEIO + pwmout_reset(); + pulseout_reset(); + pulsein_reset(); +#endif } void reset_to_bootloader(void) { diff --git a/ports/stm/supervisor/usb.c b/ports/stm/supervisor/usb.c index 501550aed7791..b66107b7ba626 100644 --- a/ports/stm/supervisor/usb.c +++ b/ports/stm/supervisor/usb.c @@ -78,58 +78,54 @@ void init_usb_hardware(void) { GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; - #if defined(STM32H7) + #if CPY_STM32H7 GPIO_InitStruct.Alternate = GPIO_AF10_OTG1_FS; - #elif defined(STM32F4) || defined(STM32F7) + #elif CPY_STM32F4 || CPY_STM32F7 GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; - #else - #error Unsupported processor #endif HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); never_reset_pin_number(0, 11); never_reset_pin_number(0, 12); /* Configure VBUS Pin */ -#if !(BOARD_NO_VBUS_SENSE) + #if !(BOARD_NO_VBUS_SENSE) GPIO_InitStruct.Pin = GPIO_PIN_9; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; GPIO_InitStruct.Pull = GPIO_NOPULL; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); never_reset_pin_number(0, 9); -#endif + #endif /* This for ID line debug */ GPIO_InitStruct.Pin = GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; - #if defined(STM32H7) + #if CPY_STM32H7 GPIO_InitStruct.Alternate = GPIO_AF10_OTG1_FS; - #elif defined(STM32F4) || defined(STM32F7) + #elif CPY_STM32F4 || CPY_STM32F7 GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; - #else - #error Unsupported processor #endif HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); never_reset_pin_number(0, 10); -#ifdef STM32F412Zx + #ifdef STM32F412Zx /* Configure POWER_SWITCH IO pin (F412 ONLY)*/ GPIO_InitStruct.Pin = GPIO_PIN_8; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD; GPIO_InitStruct.Pull = GPIO_NOPULL; HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); never_reset_pin_number(0, 8); -#endif + #endif -#if defined(STM32H7) + #if CPY_STM32H7 HAL_PWREx_EnableUSBVoltageDetector(); __HAL_RCC_USB2_OTG_FS_CLK_ENABLE(); -#else + #else /* Peripheral clock enable */ __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); -#endif + #endif init_usb_vbus_sense(); } diff --git a/supervisor/shared/stack.c b/supervisor/shared/stack.c index 2a7daf4658d78..2b7b1c03a48d9 100755 --- a/supervisor/shared/stack.c +++ b/supervisor/shared/stack.c @@ -46,7 +46,7 @@ void allocate_stack(void) { mp_uint_t c_size = (uint32_t) port_stack_get_top() - sp; - if (port_stack_get_top() != port_heap_get_top()) { //Why is this here? Doesn't apply to some chips. + if (port_stack_get_top() != port_heap_get_top()) { return; } From 426d2afe28a70ede4203f69a91b50ed436cbc4e1 Mon Sep 17 00:00:00 2001 From: Lucian Copeland Date: Mon, 13 Apr 2020 14:36:49 -0400 Subject: [PATCH 11/17] Fix pin mapping for the H7 Nucleo --- ports/stm/boards/nucleo_h743zi_2/pins.c | 53 +++----------- ports/stm/tools/pins.csv | 94 +++++++------------------ 2 files changed, 33 insertions(+), 114 deletions(-) diff --git a/ports/stm/boards/nucleo_h743zi_2/pins.c b/ports/stm/boards/nucleo_h743zi_2/pins.c index 3ba172df17add..d35f40dd2d63d 100644 --- a/ports/stm/boards/nucleo_h743zi_2/pins.c +++ b/ports/stm/boards/nucleo_h743zi_2/pins.c @@ -81,55 +81,18 @@ STATIC const mp_rom_map_elem_t board_module_globals_table[] = { { MP_ROM_QSTR(MP_QSTR_D68), MP_ROM_PTR(&pin_PF00) }, { MP_ROM_QSTR(MP_QSTR_D69), MP_ROM_PTR(&pin_PF01) }, { MP_ROM_QSTR(MP_QSTR_D70), MP_ROM_PTR(&pin_PF02) }, - { MP_ROM_QSTR(MP_QSTR_D71), MP_ROM_PTR(&pin_PE09) }, + { MP_ROM_QSTR(MP_QSTR_D71), MP_ROM_PTR(&pin_PE00) }, { MP_ROM_QSTR(MP_QSTR_D72), MP_ROM_PTR(&pin_PB02) }, - { MP_ROM_QSTR(MP_QSTR_DAC1), MP_ROM_PTR(&pin_PA04) }, - { MP_ROM_QSTR(MP_QSTR_DAC2), MP_ROM_PTR(&pin_PA05) }, + { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_PB09) }, + { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_PB08) }, + { MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_PB05) }, + { MP_ROM_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_PA06) }, + { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_PA05) }, + { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_PB07) }, + { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_PB06) }, { MP_ROM_QSTR(MP_QSTR_LED1), MP_ROM_PTR(&pin_PB00) }, { MP_ROM_QSTR(MP_QSTR_LED2), MP_ROM_PTR(&pin_PE01) }, { MP_ROM_QSTR(MP_QSTR_LED3), MP_ROM_PTR(&pin_PB14) }, { MP_ROM_QSTR(MP_QSTR_SW), MP_ROM_PTR(&pin_PC13) }, - { MP_ROM_QSTR(MP_QSTR_I2C1_SDA), MP_ROM_PTR(&pin_PB09) }, - { MP_ROM_QSTR(MP_QSTR_I2C1_SCL), MP_ROM_PTR(&pin_PB08) }, - { MP_ROM_QSTR(MP_QSTR_I2C2_SDA), MP_ROM_PTR(&pin_PF00) }, - { MP_ROM_QSTR(MP_QSTR_I2C2_SCL), MP_ROM_PTR(&pin_PF01) }, - { MP_ROM_QSTR(MP_QSTR_I2C4_SCL), MP_ROM_PTR(&pin_PF14) }, - { MP_ROM_QSTR(MP_QSTR_I2C4_SDA), MP_ROM_PTR(&pin_PF15) }, - { MP_ROM_QSTR(MP_QSTR_SD_D0), MP_ROM_PTR(&pin_PC08) }, - { MP_ROM_QSTR(MP_QSTR_SD_D1), MP_ROM_PTR(&pin_PC09) }, - { MP_ROM_QSTR(MP_QSTR_SD_D2), MP_ROM_PTR(&pin_PC10) }, - { MP_ROM_QSTR(MP_QSTR_SD_D3), MP_ROM_PTR(&pin_PC11) }, - { MP_ROM_QSTR(MP_QSTR_SD_CMD), MP_ROM_PTR(&pin_PD02) }, - { MP_ROM_QSTR(MP_QSTR_SD_CK), MP_ROM_PTR(&pin_PC12) }, - { MP_ROM_QSTR(MP_QSTR_SD_SW), MP_ROM_PTR(&pin_PG02) }, - { MP_ROM_QSTR(MP_QSTR_OTG_FS_POWER), MP_ROM_PTR(&pin_PG06) }, - { MP_ROM_QSTR(MP_QSTR_OTG_FS_OVER_CURRENT), MP_ROM_PTR(&pin_PG07) }, - { MP_ROM_QSTR(MP_QSTR_USB_VBUS), MP_ROM_PTR(&pin_PA09) }, - { MP_ROM_QSTR(MP_QSTR_USB_ID), MP_ROM_PTR(&pin_PA10) }, - { MP_ROM_QSTR(MP_QSTR_USB_DM), MP_ROM_PTR(&pin_PA11) }, - { MP_ROM_QSTR(MP_QSTR_USB_DP), MP_ROM_PTR(&pin_PA12) }, - { MP_ROM_QSTR(MP_QSTR_UART2_TX), MP_ROM_PTR(&pin_PD05) }, - { MP_ROM_QSTR(MP_QSTR_UART2_RX), MP_ROM_PTR(&pin_PD06) }, - { MP_ROM_QSTR(MP_QSTR_UART2_RTS), MP_ROM_PTR(&pin_PD04) }, - { MP_ROM_QSTR(MP_QSTR_UART2_CTS), MP_ROM_PTR(&pin_PD03) }, - { MP_ROM_QSTR(MP_QSTR_UART3_TX), MP_ROM_PTR(&pin_PD08) }, - { MP_ROM_QSTR(MP_QSTR_UART3_RX), MP_ROM_PTR(&pin_PD09) }, - { MP_ROM_QSTR(MP_QSTR_UART5_TX), MP_ROM_PTR(&pin_PB06) }, - { MP_ROM_QSTR(MP_QSTR_UART5_RX), MP_ROM_PTR(&pin_PB12) }, - { MP_ROM_QSTR(MP_QSTR_UART6_TX), MP_ROM_PTR(&pin_PC06) }, - { MP_ROM_QSTR(MP_QSTR_UART6_RX), MP_ROM_PTR(&pin_PC07) }, - { MP_ROM_QSTR(MP_QSTR_UART7_TX), MP_ROM_PTR(&pin_PF07) }, - { MP_ROM_QSTR(MP_QSTR_UART7_RX), MP_ROM_PTR(&pin_PF06) }, - { MP_ROM_QSTR(MP_QSTR_UART8_TX), MP_ROM_PTR(&pin_PE01) }, - { MP_ROM_QSTR(MP_QSTR_UART8_RX), MP_ROM_PTR(&pin_PE00) }, - { MP_ROM_QSTR(MP_QSTR_ETH_MDC), MP_ROM_PTR(&pin_PC01) }, - { MP_ROM_QSTR(MP_QSTR_ETH_MDIO), MP_ROM_PTR(&pin_PA02) }, - { MP_ROM_QSTR(MP_QSTR_ETH_RMII_REF_CLK), MP_ROM_PTR(&pin_PA01) }, - { MP_ROM_QSTR(MP_QSTR_ETH_RMII_CRS_DV), MP_ROM_PTR(&pin_PA07) }, - { MP_ROM_QSTR(MP_QSTR_ETH_RMII_RXD0), MP_ROM_PTR(&pin_PC04) }, - { MP_ROM_QSTR(MP_QSTR_ETH_RMII_RXD1), MP_ROM_PTR(&pin_PC05) }, - { MP_ROM_QSTR(MP_QSTR_ETH_RMII_TX_EN), MP_ROM_PTR(&pin_PG11) }, - { MP_ROM_QSTR(MP_QSTR_ETH_RMII_TXD0), MP_ROM_PTR(&pin_PG13) }, - { MP_ROM_QSTR(MP_QSTR_ETH_RMII_TXD1), MP_ROM_PTR(&pin_PB13) }, }; MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table); diff --git a/ports/stm/tools/pins.csv b/ports/stm/tools/pins.csv index e447b76b05b06..b424c2f78f7ff 100644 --- a/ports/stm/tools/pins.csv +++ b/ports/stm/tools/pins.csv @@ -1,24 +1,24 @@ A0,PA3 A1,PC0 A2,PC3 -A3,PF3 -A4,PF5 +A3,PB1 +A4,PC2 A5,PF10 -A6,PB1 -A7,PC2 -A8,PF4 -D0,PG9 -D1,PG14 -D2,PF15 +A6,PF4 +A7,PF5 +A8,PF6 +D0,PB7 +D1,PB6 +D2,PG14 D3,PE13 -D4,PF14 +D4,PE14 D5,PE11 D6,PE9 -D7,PF13 -D8,PF12 +D7,PG12 +D8,PF3 D9,PD15 D10,PD14 -D11,PA7 +D11,PB5 D12,PA6 D13,PA5 D14,PB9 @@ -33,7 +33,7 @@ D22,PB5 D23,PB3 D24,PA4 D25,PB4 -D26,PB6 +D26,PG6 D27,PB2 D28,PD13 D29,PD12 @@ -45,7 +45,7 @@ D34,PE0 D35,PB11 D36,PB10 D37,PE15 -D38,PE14 +D38,PE6 D39,PE12 D40,PE10 D41,PE7 @@ -78,60 +78,16 @@ D67,PD0 D68,PF0 D69,PF1 D70,PF2 -D71,PA7 -DAC1,PA4 -DAC2,PA5 -LED1,PB0 -LED2,PB7 +D71,PE0 +D72,PB2 +SDA,PB9 +SCL,PB8 +MOSI,PB5 +MISO,PA6 +SCK,PA5 +RX,PB7 +TX,PB6 +LED1,PB00 +LED2,PE01 LED3,PB14 SW,PC13 -SD_D0,PC8 -SD_D1,PC9 -SD_D2,PC10 -SD_D3,PC11 -SD_CMD,PD2 -SD_CK,PC12 -SD_SW,PG2 -OTG_FS_POWER,PG6 -OTG_FS_OVER_CURRENT,PG7 -USB_VBUS,PA9 -USB_ID,PA10 -USB_DM,PA11 -USB_DP,PA12 -UART2_TX,PD5 -UART2_RX,PD6 -UART2_RTS,PD4 -UART2_CTS,PD3 -VCP_TX,PD8 -VCP_RX,PD9 -UART3_TX,PD8 -UART3_RX,PD9 -UART5_TX,PB6 -UART5_RX,PB12 -UART6_TX,PC6 -UART6_RX,PC7 -UART7_TX,PF7 -UART7_RX,PF6 -UART8_TX,PE1 -UART8_RX,PE0 -SPI3_NSS,PA4 -SPI3_SCK,PB3 -SPI3_MISO,PB4 -SPI3_MOSI,PB5 -I2C1_SDA,PB9 -I2C1_SCL,PB8 -I2C2_SDA,PF0 -I2C2_SCL,PF1 -I2C4_SCL,PF14 -I2C4_SDA,PF15 -ETH_MDC,PC1 -ETH_MDIO,PA2 -ETH_RMII_REF_CLK,PA1 -ETH_RMII_CRS_DV,PA7 -ETH_RMII_RXD0,PC4 -ETH_RMII_RXD1,PC5 -ETH_RMII_TX_EN,PG11 -ETH_RMII_TXD0,PG13 -ETH_RMII_TXD1,PB13 -SWDIO,PA13 -SWDCLK,PA14 From 83a55f65a4ba5ffd2d99a808401807241840b2d0 Mon Sep 17 00:00:00 2001 From: Lucian Copeland Date: Mon, 13 Apr 2020 15:14:38 -0400 Subject: [PATCH 12/17] Implement cache-based reads --- ports/stm/supervisor/internal_flash.c | 27 +++++++++++++++++++++------ 1 file changed, 21 insertions(+), 6 deletions(-) diff --git a/ports/stm/supervisor/internal_flash.c b/ports/stm/supervisor/internal_flash.c index 03fa73d5fbf26..df4e97d8e1f4a 100644 --- a/ports/stm/supervisor/internal_flash.c +++ b/ports/stm/supervisor/internal_flash.c @@ -234,7 +234,7 @@ void supervisor_flash_flush(void) { } } -static int32_t convert_block_to_flash_addr(uint32_t block) { +static uint32_t convert_block_to_flash_addr(uint32_t block) { if (0 <= block && block < INTERNAL_FLASH_FILESYSTEM_NUM_BLOCKS) { // a block in partition 1 return INTERNAL_FLASH_FILESYSTEM_START_ADDR + block * FILESYSTEM_BLOCK_SIZE; @@ -244,15 +244,30 @@ static int32_t convert_block_to_flash_addr(uint32_t block) { } mp_uint_t supervisor_flash_read_blocks(uint8_t *dest, uint32_t block, uint32_t num_blocks) { - // Must write out anything in cache before trying to read. - supervisor_flash_flush(); - int32_t src = convert_block_to_flash_addr(block); if (src == -1) { // bad block number return false; } - memcpy(dest, (uint8_t*) src, FILESYSTEM_BLOCK_SIZE*num_blocks); + + // Determine whether the read is contained within the sector + uint32_t sector_size; + uint32_t sector_start_addr; + flash_get_sector_info(src, §or_start_addr, §or_size); + // Count how many blocks are left in the sector + uint32_t count = (sector_size - (src - sector_start_addr))/FILESYSTEM_BLOCK_SIZE; + count = MIN(num_blocks, count); + + if (count < num_blocks && _cache_flash_addr == sector_start_addr) { + // Read is contained in the cache, so just read cache + memcpy(dest, (_flash_cache + (src-sector_start_addr)), FILESYSTEM_BLOCK_SIZE*num_blocks); + } else { + // The read spans multiple sectors or is in another sector + // Must write out anything in cache before trying to read. + supervisor_flash_flush(); + memcpy(dest, (uint8_t*) src, FILESYSTEM_BLOCK_SIZE*num_blocks); + } + return 0; // success } @@ -271,7 +286,7 @@ mp_uint_t supervisor_flash_write_blocks(const uint8_t *src, uint32_t block_num, uint32_t sector_start_addr; flash_get_sector_info(dest, §or_start_addr, §or_size); - // Fail for any sector outside the 16k ones for now + // Fail for any sector outside what's supported by the cache if (sector_size > sizeof(_flash_cache)) { reset_into_safe_mode(FLASH_WRITE_FAIL); } From 6427994b146ff25e8bc7565031d90ab6d6744157 Mon Sep 17 00:00:00 2001 From: Lucian Copeland Date: Wed, 15 Apr 2020 10:18:09 -0400 Subject: [PATCH 13/17] Implement requested changes --- ports/stm/Makefile | 2 -- ports/stm/supervisor/internal_flash.c | 1 - ports/stm/supervisor/port.c | 28 +-------------------------- 3 files changed, 1 insertion(+), 30 deletions(-) diff --git a/ports/stm/Makefile b/ports/stm/Makefile index dc32f6c7a82e9..765f062fea3aa 100755 --- a/ports/stm/Makefile +++ b/ports/stm/Makefile @@ -137,8 +137,6 @@ endif LDFLAGS = $(CFLAGS) -fshort-enums -Wl,-nostdlib -Wl,-T,$(LD_FILE) -Wl,-T,$(LD_COMMON) -Wl,-Map=$@.map -Wl,-cref -Wl,-gc-sections -specs=nano.specs LIBS := -lgcc -lc -LDFLAGS += -mthumb $(MCU_FLAGS_$(MCU_SERIES)) - # Use toolchain libm if we're not using our own. ifndef INTERNAL_LIBM LIBS += -lm diff --git a/ports/stm/supervisor/internal_flash.c b/ports/stm/supervisor/internal_flash.c index df4e97d8e1f4a..8c04112c01194 100644 --- a/ports/stm/supervisor/internal_flash.c +++ b/ports/stm/supervisor/internal_flash.c @@ -202,7 +202,6 @@ void supervisor_flash_flush(void) { #if defined(STM32H7) for (uint32_t i = 0; i < (sector_size / 32); i++) { // Note that the STM32H7 HAL interface differs by taking an address, not 64 bit data - // This is because ST's code is written by a large room of chimpanzees if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_FLASHWORD, sector_start_addr, (uint32_t)cache_addr) != HAL_OK) { // error occurred during flash write diff --git a/ports/stm/supervisor/port.c b/ports/stm/supervisor/port.c index 81a12d6c4b66d..639abeb1869a3 100644 --- a/ports/stm/supervisor/port.c +++ b/ports/stm/supervisor/port.c @@ -89,22 +89,6 @@ __attribute__((used, naked)) void Reset_Handler(void) { __disable_irq(); __set_MSP((uint32_t) &_ld_stack_top); - // TODO: Is any of this commented stuff actually required? - - /* Disable I cache and D cache */ - // SCB_DisableICache(); - // SCB_DisableDCache(); // this causes an instant hardfault if used - - // #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) - // SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */ - // #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ - - // /* Disable Systick which might be enabled by bootrom */ - // if (SysTick->CTRL & SysTick_CTRL_ENABLE_Msk) - // { - // SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; - // } - /* Disable MPU */ ARM_MPU_Disable(); @@ -117,7 +101,6 @@ __attribute__((used, naked)) void Reset_Handler(void) { // The first number in RBAR is the region number. When searching for a policy, the region with // the highest number wins. If none match, then the default policy set at enable applies. - // TODO: do I need to subdivide this up? // Mark all the flash the same until instructed otherwise. MPU->RBAR = ARM_MPU_RBAR(11, 0x08000000U); MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_FULL, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, NO_SUBREGIONS, ARM_MPU_REGION_SIZE_2MB); @@ -135,14 +118,9 @@ __attribute__((used, naked)) void Reset_Handler(void) { MPU->RBAR = ARM_MPU_RBAR(15, 0x24000000U); MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_FULL, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, NO_SUBREGIONS, ARM_MPU_REGION_SIZE_512KB); - // TODO: what is the mask here doing? /* Enable MPU */ ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); - // We're done mucking with memory so enable I cache and D cache - // SCB_EnableDCache(); - // SCB_EnableICache(); - // Copy all of the data to run from DTCM. for (uint32_t i = 0; i < ((size_t) &_ld_dtcm_data_size) / 4; i++) { (&_ld_dtcm_data_destination)[i] = (&_ld_dtcm_data_flash_copy)[i]; @@ -226,8 +204,8 @@ uint32_t *port_stack_get_top(void) { return &_ld_stack_top; } -// TODO: what even are these extern uint32_t _ebss; + // Place the word to save just after our BSS section that gets blanked. void port_set_saved_word(uint32_t value) { _ebss = value; @@ -239,7 +217,6 @@ uint32_t port_get_saved_word(void) { __attribute__((used)) void MemManage_Handler(void) { - __ASM volatile ("bkpt"); reset_into_safe_mode(MEM_MANAGE); while (true) { asm("nop;"); @@ -248,7 +225,6 @@ __attribute__((used)) void MemManage_Handler(void) __attribute__((used)) void BusFault_Handler(void) { - __ASM volatile ("bkpt"); reset_into_safe_mode(MEM_MANAGE); while (true) { asm("nop;"); @@ -257,7 +233,6 @@ __attribute__((used)) void BusFault_Handler(void) __attribute__((used)) void UsageFault_Handler(void) { - __ASM volatile ("bkpt"); reset_into_safe_mode(MEM_MANAGE); while (true) { asm("nop;"); @@ -266,7 +241,6 @@ __attribute__((used)) void UsageFault_Handler(void) __attribute__((used)) void HardFault_Handler(void) { - __ASM volatile ("bkpt"); reset_into_safe_mode(HARD_CRASH); while (true) { asm("nop;"); From 0f87a75f4f0675ff55e31437907101226d5fb66b Mon Sep 17 00:00:00 2001 From: Lucian Copeland Date: Wed, 15 Apr 2020 10:24:51 -0400 Subject: [PATCH 14/17] translations --- locale/ID.po | 4 +++- locale/circuitpython.pot | 4 +++- locale/de_DE.po | 4 +++- locale/en_US.po | 4 +++- locale/en_x_pirate.po | 4 +++- locale/es.po | 4 +++- locale/fil.po | 4 +++- locale/fr.po | 4 +++- locale/it_IT.po | 4 +++- locale/ko.po | 4 +++- locale/pl.po | 4 +++- locale/pt_BR.po | 4 +++- locale/zh_Latn_pinyin.po | 4 +++- 13 files changed, 39 insertions(+), 13 deletions(-) diff --git a/locale/ID.po b/locale/ID.po index de158c568ac3f..4a628aad4268c 100644 --- a/locale/ID.po +++ b/locale/ID.po @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-04-01 12:29-0400\n" +"POT-Creation-Date: 2020-04-15 10:24-0400\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -900,6 +900,7 @@ msgid "Invalid number of bits" msgstr "" #: shared-bindings/bitbangio/SPI.c shared-bindings/busio/SPI.c +#: shared-bindings/displayio/FourWire.c msgid "Invalid phase" msgstr "" @@ -931,6 +932,7 @@ msgid "Invalid pins for PWMOut" msgstr "" #: shared-bindings/bitbangio/SPI.c shared-bindings/busio/SPI.c +#: shared-bindings/displayio/FourWire.c msgid "Invalid polarity" msgstr "" diff --git a/locale/circuitpython.pot b/locale/circuitpython.pot index 7e9b3aadf20e8..6da3148b73e2e 100644 --- a/locale/circuitpython.pot +++ b/locale/circuitpython.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-04-01 12:29-0400\n" +"POT-Creation-Date: 2020-04-15 10:24-0400\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -889,6 +889,7 @@ msgid "Invalid number of bits" msgstr "" #: shared-bindings/bitbangio/SPI.c shared-bindings/busio/SPI.c +#: shared-bindings/displayio/FourWire.c msgid "Invalid phase" msgstr "" @@ -920,6 +921,7 @@ msgid "Invalid pins for PWMOut" msgstr "" #: shared-bindings/bitbangio/SPI.c shared-bindings/busio/SPI.c +#: shared-bindings/displayio/FourWire.c msgid "Invalid polarity" msgstr "" diff --git a/locale/de_DE.po b/locale/de_DE.po index 709a34ed57adf..55d20e47ce858 100644 --- a/locale/de_DE.po +++ b/locale/de_DE.po @@ -7,7 +7,7 @@ msgid "" msgstr "" "Project-Id-Version: \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-04-01 12:29-0400\n" +"POT-Creation-Date: 2020-04-15 10:24-0400\n" "PO-Revision-Date: 2018-07-27 11:55-0700\n" "Last-Translator: Pascal Deneaux\n" "Language-Team: Sebastian Plamauer, Pascal Deneaux\n" @@ -897,6 +897,7 @@ msgid "Invalid number of bits" msgstr "Ungültige Anzahl von Bits" #: shared-bindings/bitbangio/SPI.c shared-bindings/busio/SPI.c +#: shared-bindings/displayio/FourWire.c msgid "Invalid phase" msgstr "Ungültige Phase" @@ -928,6 +929,7 @@ msgid "Invalid pins for PWMOut" msgstr "" #: shared-bindings/bitbangio/SPI.c shared-bindings/busio/SPI.c +#: shared-bindings/displayio/FourWire.c msgid "Invalid polarity" msgstr "Ungültige Polarität" diff --git a/locale/en_US.po b/locale/en_US.po index d516d41d9b9f3..ee4bff32b07bb 100644 --- a/locale/en_US.po +++ b/locale/en_US.po @@ -7,7 +7,7 @@ msgid "" msgstr "" "Project-Id-Version: \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-04-01 12:29-0400\n" +"POT-Creation-Date: 2020-04-15 10:24-0400\n" "PO-Revision-Date: 2018-07-27 11:55-0700\n" "Last-Translator: \n" "Language-Team: \n" @@ -889,6 +889,7 @@ msgid "Invalid number of bits" msgstr "" #: shared-bindings/bitbangio/SPI.c shared-bindings/busio/SPI.c +#: shared-bindings/displayio/FourWire.c msgid "Invalid phase" msgstr "" @@ -920,6 +921,7 @@ msgid "Invalid pins for PWMOut" msgstr "" #: shared-bindings/bitbangio/SPI.c shared-bindings/busio/SPI.c +#: shared-bindings/displayio/FourWire.c msgid "Invalid polarity" msgstr "" diff --git a/locale/en_x_pirate.po b/locale/en_x_pirate.po index e3f02c246ff6f..3b9d9f46c5a61 100644 --- a/locale/en_x_pirate.po +++ b/locale/en_x_pirate.po @@ -7,7 +7,7 @@ msgid "" msgstr "" "Project-Id-Version: \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-04-01 12:29-0400\n" +"POT-Creation-Date: 2020-04-15 10:24-0400\n" "PO-Revision-Date: 2018-07-27 11:55-0700\n" "Last-Translator: \n" "Language-Team: @sommersoft, @MrCertainly\n" @@ -893,6 +893,7 @@ msgid "Invalid number of bits" msgstr "" #: shared-bindings/bitbangio/SPI.c shared-bindings/busio/SPI.c +#: shared-bindings/displayio/FourWire.c msgid "Invalid phase" msgstr "" @@ -924,6 +925,7 @@ msgid "Invalid pins for PWMOut" msgstr "" #: shared-bindings/bitbangio/SPI.c shared-bindings/busio/SPI.c +#: shared-bindings/displayio/FourWire.c msgid "Invalid polarity" msgstr "" diff --git a/locale/es.po b/locale/es.po index 115fc8037e907..be4e1b0367013 100644 --- a/locale/es.po +++ b/locale/es.po @@ -7,7 +7,7 @@ msgid "" msgstr "" "Project-Id-Version: \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-04-01 12:29-0400\n" +"POT-Creation-Date: 2020-04-15 10:24-0400\n" "PO-Revision-Date: 2018-08-24 22:56-0500\n" "Last-Translator: \n" "Language-Team: \n" @@ -897,6 +897,7 @@ msgid "Invalid number of bits" msgstr "Numero inválido de bits" #: shared-bindings/bitbangio/SPI.c shared-bindings/busio/SPI.c +#: shared-bindings/displayio/FourWire.c msgid "Invalid phase" msgstr "Fase inválida" @@ -928,6 +929,7 @@ msgid "Invalid pins for PWMOut" msgstr "" #: shared-bindings/bitbangio/SPI.c shared-bindings/busio/SPI.c +#: shared-bindings/displayio/FourWire.c msgid "Invalid polarity" msgstr "Polaridad inválida" diff --git a/locale/fil.po b/locale/fil.po index da2bc9459e2aa..1fda3d0e3be64 100644 --- a/locale/fil.po +++ b/locale/fil.po @@ -7,7 +7,7 @@ msgid "" msgstr "" "Project-Id-Version: \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-04-01 12:29-0400\n" +"POT-Creation-Date: 2020-04-15 10:24-0400\n" "PO-Revision-Date: 2018-12-20 22:15-0800\n" "Last-Translator: Timothy \n" "Language-Team: fil\n" @@ -905,6 +905,7 @@ msgid "Invalid number of bits" msgstr "Mali ang bilang ng bits" #: shared-bindings/bitbangio/SPI.c shared-bindings/busio/SPI.c +#: shared-bindings/displayio/FourWire.c msgid "Invalid phase" msgstr "Mali ang phase" @@ -936,6 +937,7 @@ msgid "Invalid pins for PWMOut" msgstr "" #: shared-bindings/bitbangio/SPI.c shared-bindings/busio/SPI.c +#: shared-bindings/displayio/FourWire.c msgid "Invalid polarity" msgstr "Mali ang polarity" diff --git a/locale/fr.po b/locale/fr.po index 100fc2b9c210e..0ab6582d3a5a4 100644 --- a/locale/fr.po +++ b/locale/fr.po @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: 0.1\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-04-01 12:29-0400\n" +"POT-Creation-Date: 2020-04-15 10:24-0400\n" "PO-Revision-Date: 2019-04-14 20:05+0100\n" "Last-Translator: Pierrick Couturier \n" "Language-Team: fr\n" @@ -911,6 +911,7 @@ msgid "Invalid number of bits" msgstr "Nombre de bits invalide" #: shared-bindings/bitbangio/SPI.c shared-bindings/busio/SPI.c +#: shared-bindings/displayio/FourWire.c msgid "Invalid phase" msgstr "Phase invalide" @@ -942,6 +943,7 @@ msgid "Invalid pins for PWMOut" msgstr "" #: shared-bindings/bitbangio/SPI.c shared-bindings/busio/SPI.c +#: shared-bindings/displayio/FourWire.c msgid "Invalid polarity" msgstr "Polarité invalide" diff --git a/locale/it_IT.po b/locale/it_IT.po index 8b868f83fa269..6060f26d307a7 100644 --- a/locale/it_IT.po +++ b/locale/it_IT.po @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-04-01 12:29-0400\n" +"POT-Creation-Date: 2020-04-15 10:24-0400\n" "PO-Revision-Date: 2018-10-02 16:27+0200\n" "Last-Translator: Enrico Paganin \n" "Language-Team: \n" @@ -907,6 +907,7 @@ msgid "Invalid number of bits" msgstr "Numero di bit non valido" #: shared-bindings/bitbangio/SPI.c shared-bindings/busio/SPI.c +#: shared-bindings/displayio/FourWire.c msgid "Invalid phase" msgstr "Fase non valida" @@ -938,6 +939,7 @@ msgid "Invalid pins for PWMOut" msgstr "" #: shared-bindings/bitbangio/SPI.c shared-bindings/busio/SPI.c +#: shared-bindings/displayio/FourWire.c msgid "Invalid polarity" msgstr "Polarità non valida" diff --git a/locale/ko.po b/locale/ko.po index 5cc2bcf3a6ab2..46c4af22694d5 100644 --- a/locale/ko.po +++ b/locale/ko.po @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-04-01 12:29-0400\n" +"POT-Creation-Date: 2020-04-15 10:24-0400\n" "PO-Revision-Date: 2019-05-06 14:22-0700\n" "Last-Translator: \n" "Language-Team: LANGUAGE \n" @@ -893,6 +893,7 @@ msgid "Invalid number of bits" msgstr "비트 수가 유효하지 않습니다" #: shared-bindings/bitbangio/SPI.c shared-bindings/busio/SPI.c +#: shared-bindings/displayio/FourWire.c msgid "Invalid phase" msgstr "단계가 잘못되었습니다" @@ -924,6 +925,7 @@ msgid "Invalid pins for PWMOut" msgstr "" #: shared-bindings/bitbangio/SPI.c shared-bindings/busio/SPI.c +#: shared-bindings/displayio/FourWire.c msgid "Invalid polarity" msgstr "" diff --git a/locale/pl.po b/locale/pl.po index 659d6330136bd..a590761804c3e 100644 --- a/locale/pl.po +++ b/locale/pl.po @@ -7,7 +7,7 @@ msgid "" msgstr "" "Project-Id-Version: \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-04-01 12:29-0400\n" +"POT-Creation-Date: 2020-04-15 10:24-0400\n" "PO-Revision-Date: 2019-03-19 18:37-0700\n" "Last-Translator: Radomir Dopieralski \n" "Language-Team: pl\n" @@ -894,6 +894,7 @@ msgid "Invalid number of bits" msgstr "Zła liczba bitów" #: shared-bindings/bitbangio/SPI.c shared-bindings/busio/SPI.c +#: shared-bindings/displayio/FourWire.c msgid "Invalid phase" msgstr "Zła faza" @@ -925,6 +926,7 @@ msgid "Invalid pins for PWMOut" msgstr "" #: shared-bindings/bitbangio/SPI.c shared-bindings/busio/SPI.c +#: shared-bindings/displayio/FourWire.c msgid "Invalid polarity" msgstr "Zła polaryzacja" diff --git a/locale/pt_BR.po b/locale/pt_BR.po index 511f0a5bb618b..01024c23bd92c 100644 --- a/locale/pt_BR.po +++ b/locale/pt_BR.po @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-04-01 12:29-0400\n" +"POT-Creation-Date: 2020-04-15 10:24-0400\n" "PO-Revision-Date: 2018-10-02 21:14-0000\n" "Last-Translator: \n" "Language-Team: \n" @@ -900,6 +900,7 @@ msgid "Invalid number of bits" msgstr "Número inválido de bits" #: shared-bindings/bitbangio/SPI.c shared-bindings/busio/SPI.c +#: shared-bindings/displayio/FourWire.c msgid "Invalid phase" msgstr "Fase Inválida" @@ -931,6 +932,7 @@ msgid "Invalid pins for PWMOut" msgstr "" #: shared-bindings/bitbangio/SPI.c shared-bindings/busio/SPI.c +#: shared-bindings/displayio/FourWire.c msgid "Invalid polarity" msgstr "" diff --git a/locale/zh_Latn_pinyin.po b/locale/zh_Latn_pinyin.po index 2319bf4d7d93a..9305817461735 100644 --- a/locale/zh_Latn_pinyin.po +++ b/locale/zh_Latn_pinyin.po @@ -7,7 +7,7 @@ msgid "" msgstr "" "Project-Id-Version: circuitpython-cn\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-04-01 12:29-0400\n" +"POT-Creation-Date: 2020-04-15 10:24-0400\n" "PO-Revision-Date: 2019-04-13 10:10-0700\n" "Last-Translator: hexthat\n" "Language-Team: Chinese Hanyu Pinyin\n" @@ -902,6 +902,7 @@ msgid "Invalid number of bits" msgstr "Wèi shù wúxiào" #: shared-bindings/bitbangio/SPI.c shared-bindings/busio/SPI.c +#: shared-bindings/displayio/FourWire.c msgid "Invalid phase" msgstr "Jiēduàn wúxiào" @@ -933,6 +934,7 @@ msgid "Invalid pins for PWMOut" msgstr "" #: shared-bindings/bitbangio/SPI.c shared-bindings/busio/SPI.c +#: shared-bindings/displayio/FourWire.c msgid "Invalid polarity" msgstr "Wúxiào liǎng jí zhí" From a1451aae51305dd9e1f5b25bd56751bdee0b0b88 Mon Sep 17 00:00:00 2001 From: Lucian Copeland Date: Wed, 15 Apr 2020 11:32:50 -0400 Subject: [PATCH 15/17] Correct submodule desync --- extmod/ulab | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/extmod/ulab b/extmod/ulab index a91b36986d81f..a746bd8e09538 160000 --- a/extmod/ulab +++ b/extmod/ulab @@ -1 +1 @@ -Subproject commit a91b36986d81fd906a6232010778f2a93d690f8e +Subproject commit a746bd8e0953853056ee405e2fa02c8ebca4fb79 From 00b2e6a1db38dee707a2a8e71a1055748e7001a7 Mon Sep 17 00:00:00 2001 From: Lucian Copeland Date: Wed, 15 Apr 2020 12:25:13 -0400 Subject: [PATCH 16/17] Fix korea translation error, minor submodule change --- locale/circuitpython.pot | 2 +- locale/ko.po | 2 +- ports/atmel-samd/peripherals | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/locale/circuitpython.pot b/locale/circuitpython.pot index 73818046dce4f..e9e7838cbb30e 100644 --- a/locale/circuitpython.pot +++ b/locale/circuitpython.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-04-15 10:24-0400\n" +"POT-Creation-Date: 2020-04-15 12:24-0400\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" diff --git a/locale/ko.po b/locale/ko.po index 7adc2b7a3c095..d232133e2a46a 100644 --- a/locale/ko.po +++ b/locale/ko.po @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2020-04-15 10:24-0400\n +"POT-Creation-Date: 2020-04-15 10:24-0400\n" "PO-Revision-Date: 2019-05-06 14:22-0700\n" "Last-Translator: \n" "Language-Team: LANGUAGE \n" diff --git a/ports/atmel-samd/peripherals b/ports/atmel-samd/peripherals index b89811f22a24a..f528240c2a4c2 160000 --- a/ports/atmel-samd/peripherals +++ b/ports/atmel-samd/peripherals @@ -1 +1 @@ -Subproject commit b89811f22a24ac350079ceaf0cdf0e62aa03f4f4 +Subproject commit f528240c2a4c2d7a39de786f1aa56895c12227b4 From 9e49fc13f4f894855c464427f8725e58fb2d8557 Mon Sep 17 00:00:00 2001 From: Lucian Copeland Date: Thu, 16 Apr 2020 14:53:52 -0400 Subject: [PATCH 17/17] startup file crash fix, H7 bin fix --- ports/stm/Makefile | 15 +++++++++------ ports/stm/supervisor/port.c | 8 ++++++++ 2 files changed, 17 insertions(+), 6 deletions(-) diff --git a/ports/stm/Makefile b/ports/stm/Makefile index 765f062fea3aa..c152b76f1a7b2 100755 --- a/ports/stm/Makefile +++ b/ports/stm/Makefile @@ -93,8 +93,7 @@ endif # MCU Series is defined by the HAL package and doesn't need to be specified here C_DEFS = -D$(MCU_PACKAGE) -DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER -D$(MCU_VARIANT) -CFLAGS += $(INC) -Werror -Wall -std=gnu11 $(BASE_CFLAGS) $(C_DEFS) $(CFLAGS_MOD) $(COPT) -# Removed -nostdlib since it conflicts with stm32 startup files +CFLAGS += $(INC) -Werror -Wall -std=gnu11 $(BASE_CFLAGS) $(C_DEFS) $(CFLAGS_MOD) $(COPT) -nostdlib -nostartfiles # Undo some warnings. # STM32 HAL uses undefined preprocessor variables, shadowed variables, casts that change alignment reqs @@ -264,6 +263,12 @@ SRC_QSTR += $(SRC_C) $(SRC_SUPERVISOR) $(SRC_MOD) $(SRC_COMMON_HAL_EXPANDED) $(S # Sources that only hold QSTRs after pre-processing. SRC_QSTR_PREPROCESSOR += +# Bin section settings specific to the STM32H7 +ifeq ($(MCU_VARIANT),$(filter $(MCU_VARIANT),STM32H743xx)) +MCU_SECTIONS = -j .isr_vector -j .text -j .data -j .itcm -j .dtcm_data $^ $@ +else +MCU_SECTIONS = $^ $@ +endif all: $(BUILD)/firmware.bin $(BUILD)/firmware.uf2 @@ -274,13 +279,11 @@ $(BUILD)/firmware.elf: $(OBJ) $(BUILD)/firmware.bin: $(BUILD)/firmware.elf $(STEPECHO) "Create $@" - $(Q)$(OBJCOPY) -O binary $^ $@ -# $(Q)$(OBJCOPY) -O binary -j .vectors -j .text -j .data $^ $@ + $(Q)$(OBJCOPY) -O binary $(MCU_SECTIONS) $(BUILD)/firmware.hex: $(BUILD)/firmware.elf $(STEPECHO) "Create $@" - $(Q)$(OBJCOPY) -O ihex $^ $@ -# $(Q)$(OBJCOPY) -O ihex -j .vectors -j .text -j .data $^ $@ + $(Q)$(OBJCOPY) -O ihex $(MCU_SECTIONS) $(BUILD)/firmware.uf2: $(BUILD)/firmware.hex $(ECHO) "Create $@" diff --git a/ports/stm/supervisor/port.c b/ports/stm/supervisor/port.c index 639abeb1869a3..21ff0b5751ef2 100644 --- a/ports/stm/supervisor/port.c +++ b/ports/stm/supervisor/port.c @@ -246,3 +246,11 @@ __attribute__((used)) void HardFault_Handler(void) asm("nop;"); } } + +// Required by __libc_init_array in startup code if we are compiling using +// -nostdlib/-nostartfiles. +void _init(void) +{ + +} +