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dhalbertdhalbert
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Merge pull request #2132 from hierophect/stm32-f412-tinyusb
STM32: Add USB support to F412 Discovery
2 parents 6ad860a + c438468 commit 53b0b35

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6 files changed

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‎lib/tinyusb

Submodule tinyusb updated 176 files

‎ports/stm32f4/boards/STM32F412ZGTx_FLASH.ld

Lines changed: 94 additions & 178 deletions
Original file line numberDiff line numberDiff line change
@@ -1,189 +1,105 @@
11
/*
2-
******************************************************************************
3-
**
4-
5-
** File : LinkerScript.ld
6-
**
7-
** Author : Auto-generated by Ac6 System Workbench
8-
**
9-
** Abstract : Linker script for STM32F412ZGTx series
10-
** 1024Kbytes FLASH and 256Kbytes RAM
11-
**
12-
** Set heap size, stack size and stack location according
13-
** to application requirements.
14-
**
15-
** Set memory bank area and size if external memory is used.
16-
**
17-
** Target : STMicroelectronics STM32
18-
**
19-
** Distribution: The file is distributed “as is,” without any warranty
20-
** of any kind.
21-
**
22-
*****************************************************************************
23-
** @attention
24-
**
25-
** <h2><center>&copy; COPYRIGHT(c) 2014 Ac6</center></h2>
26-
**
27-
** Redistribution and use in source and binary forms, with or without modification,
28-
** are permitted provided that the following conditions are met:
29-
** 1. Redistributions of source code must retain the above copyright notice,
30-
** this list of conditions and the following disclaimer.
31-
** 2. Redistributions in binary form must reproduce the above copyright notice,
32-
** this list of conditions and the following disclaimer in the documentation
33-
** and/or other materials provided with the distribution.
34-
** 3. Neither the name of Ac6 nor the names of its contributors
35-
** may be used to endorse or promote products derived from this software
36-
** without specific prior written permission.
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**
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** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
39-
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
40-
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
41-
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
42-
** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
43-
** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
44-
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
46-
** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
47-
** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
48-
**
49-
*****************************************************************************
2+
GNU linker script for STM32F412
503
*/
514

52-
/* Entry Point */
53-
ENTRY(Reset_Handler)
54-
55-
/* Highest address of the user mode stack */
56-
_estack = 0x20040000; /* end of RAM */
57-
/* Generate a link error if heap and stack don't fit into RAM */
58-
_Min_Heap_Size = 0x200; /* required amount of heap */
59-
_Min_Stack_Size = 0x400; /* required amount of stack */
60-
615
/* Specify the memory areas */
626
MEMORY
637
{
64-
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 256K
65-
FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 1024K
8+
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K /* entire flash */
9+
FLASH_ISR (rx) : ORIGIN = 0x08000000, LENGTH = 16K /* sector 0 */
10+
FLASH_FS (rx) : ORIGIN = 0x08004000, LENGTH = 48K /* sectors 1,2,3 are 16K */
11+
FLASH_TEXT (rx) : ORIGIN = 0x08010000, LENGTH = 960K /* sector 4 is 64K, sectors 5,6,7 are 128K */
12+
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 256K
6613
}
6714

68-
/* Define output sections */
15+
/* produce a link error if there is not this amount of RAM for these sections */
16+
_minimum_stack_size = 2K;
17+
_minimum_heap_size = 16K;
18+
19+
/* Define tho top end of the stack. The stack is full descending so begins just
20+
above last byte of RAM. Note that EABI requires the stack to be 8-byte
21+
aligned for a call. */
22+
_estack = ORIGIN(RAM) + LENGTH(RAM);
23+
24+
/* RAM extents for the garbage collector */
25+
_ram_start = ORIGIN(RAM);
26+
_ram_end = ORIGIN(RAM) + LENGTH(RAM);
27+
_heap_start = _ebss; /* heap starts just after statically allocated memory */
28+
_heap_end = 0x20020000; /* tunable */
29+
30+
ENTRY(Reset_Handler)
31+
32+
/* define output sections */
6933
SECTIONS
7034
{
71-
/* The startup code goes first into FLASH */
72-
.isr_vector :
73-
{
74-
. = ALIGN(4);
75-
KEEP(*(.isr_vector)) /* Startup code */
76-
. = ALIGN(4);
77-
} >FLASH
78-
79-
/* The program code and other data goes into FLASH */
80-
.text :
81-
{
82-
. = ALIGN(4);
83-
*(.text) /* .text sections (code) */
84-
*(.text*) /* .text* sections (code) */
85-
*(.glue_7) /* glue arm to thumb code */
86-
*(.glue_7t) /* glue thumb to arm code */
87-
*(.eh_frame)
88-
89-
KEEP (*(.init))
90-
KEEP (*(.fini))
91-
92-
. = ALIGN(4);
93-
_etext = .; /* define a global symbols at end of code */
94-
} >FLASH
95-
96-
/* Constant data goes into FLASH */
97-
.rodata :
98-
{
99-
. = ALIGN(4);
100-
*(.rodata) /* .rodata sections (constants, strings, etc.) */
101-
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
102-
. = ALIGN(4);
103-
} >FLASH
104-
105-
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
106-
.ARM : {
107-
__exidx_start = .;
108-
*(.ARM.exidx*)
109-
__exidx_end = .;
110-
} >FLASH
111-
112-
.preinit_array :
113-
{
114-
PROVIDE_HIDDEN (__preinit_array_start = .);
115-
KEEP (*(.preinit_array*))
116-
PROVIDE_HIDDEN (__preinit_array_end = .);
117-
} >FLASH
118-
.init_array :
119-
{
120-
PROVIDE_HIDDEN (__init_array_start = .);
121-
KEEP (*(SORT(.init_array.*)))
122-
KEEP (*(.init_array*))
123-
PROVIDE_HIDDEN (__init_array_end = .);
124-
} >FLASH
125-
.fini_array :
126-
{
127-
PROVIDE_HIDDEN (__fini_array_start = .);
128-
KEEP (*(SORT(.fini_array.*)))
129-
KEEP (*(.fini_array*))
130-
PROVIDE_HIDDEN (__fini_array_end = .);
131-
} >FLASH
132-
133-
/* used by the startup to initialize data */
134-
_sidata = LOADADDR(.data);
135-
136-
/* Initialized data sections goes into RAM, load LMA copy after code */
137-
.data :
138-
{
139-
. = ALIGN(4);
140-
_sdata = .; /* create a global symbol at data start */
141-
*(.data) /* .data sections */
142-
*(.data*) /* .data* sections */
143-
144-
. = ALIGN(4);
145-
_edata = .; /* define a global symbol at data end */
146-
} >RAM AT> FLASH
147-
148-
149-
/* Uninitialized data section */
150-
. = ALIGN(4);
151-
.bss :
152-
{
153-
/* This is used by the startup in order to initialize the .bss secion */
154-
_sbss = .; /* define a global symbol at bss start */
155-
__bss_start__ = _sbss;
156-
*(.bss)
157-
*(.bss*)
158-
*(COMMON)
159-
160-
. = ALIGN(4);
161-
_ebss = .; /* define a global symbol at bss end */
162-
__bss_end__ = _ebss;
163-
} >RAM
164-
165-
/* User_heap_stack section, used to check that there is enough RAM left */
166-
._user_heap_stack :
167-
{
168-
. = ALIGN(8);
169-
PROVIDE ( end = . );
170-
PROVIDE ( _end = . );
171-
. = . + _Min_Heap_Size;
172-
. = . + _Min_Stack_Size;
173-
. = ALIGN(8);
174-
} >RAM
175-
176-
177-
178-
/* Remove information from the standard libraries */
179-
/DISCARD/ :
180-
{
181-
libc.a ( * )
182-
libm.a ( * )
183-
libgcc.a ( * )
184-
}
185-
186-
.ARM.attributes 0 : { *(.ARM.attributes) }
35+
/* The startup code goes first into FLASH */
36+
.isr_vector :
37+
{
38+
. = ALIGN(4);
39+
KEEP(*(.isr_vector)) /* Startup code */
40+
41+
/* This first flash block is 16K annd the isr vectors only take up
42+
about 400 bytes. Micropython pads this with files, but this didn't
43+
work with the size of Circuitpython's ff object. */
44+
45+
. = ALIGN(4);
46+
} >FLASH_ISR
47+
48+
/* The program code and other data goes into FLASH */
49+
.text :
50+
{
51+
. = ALIGN(4);
52+
*(.text*) /* .text* sections (code) */
53+
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
54+
55+
. = ALIGN(4);
56+
_etext = .; /* define a global symbol at end of code */
57+
} >FLASH_TEXT
58+
59+
/* used by the startup to initialize data */
60+
_sidata = LOADADDR(.data);
61+
62+
/* This is the initialized data section
63+
The program executes knowing that the data is in the RAM
64+
but the loader puts the initial values in the FLASH (inidata).
65+
It is one task of the startup to copy the initial values from FLASH to RAM. */
66+
.data :
67+
{
68+
. = ALIGN(4);
69+
_sdata = .; /* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM */
70+
*(.data*) /* .data* sections */
71+
72+
. = ALIGN(4);
73+
_edata = .; /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */
74+
} >RAM AT> FLASH_TEXT
75+
76+
/* Uninitialized data section */
77+
.bss :
78+
{
79+
. = ALIGN(4);
80+
_sbss = .; /* define a global symbol at bss start; used by startup code */
81+
*(.bss*)
82+
*(COMMON)
83+
84+
. = ALIGN(4);
85+
_ebss = .; /* define a global symbol at bss end; used by startup code and GC */
86+
} >RAM
87+
88+
/* this is to define the start of the heap, and make sure we have a minimum size */
89+
.heap :
90+
{
91+
. = ALIGN(4);
92+
. = . + _minimum_heap_size;
93+
. = ALIGN(4);
94+
} >RAM
95+
96+
/* this just checks there is enough RAM for the stack */
97+
.stack :
98+
{
99+
. = ALIGN(4);
100+
. = . + _minimum_stack_size;
101+
. = ALIGN(4);
102+
} >RAM
103+
104+
.ARM.attributes 0 : { *(.ARM.attributes) }
187105
}
188-
189-

‎ports/stm32f4/boards/stm32f412zg_discovery/mpconfigboard.mk

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,10 @@
1-
USB_VID = 0x483
2-
USB_PID = 0x572B
1+
USB_VID = 0x239A
2+
USB_PID = 0x8056
33
USB_PRODUCT = "STM32F412ZG Discovery Board - CPy"
44
USB_MANUFACTURER = "STMicroelectronics"
55

6-
DISABLE_FILESYSTEM = 1
6+
INTERNAL_FLASH_FILESYSTEM = 1
7+
LONGINT_IMPL = NONE
78

89
MCU_SERIES = m4
910
MCU_VARIANT = stm32f4

‎ports/stm32f4/peripherals/stm32f4/stm32f412zx/clocks.c

Lines changed: 41 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -28,48 +28,47 @@
2828

2929
void stm32f4_peripherals_clocks_init(void) {
3030
//System clock init
31-
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
32-
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
33-
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
34-
/** Configure the main internal regulator output voltage
35-
*/
36-
__HAL_RCC_PWR_CLK_ENABLE();
37-
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
38-
/** Initializes the CPU, AHB and APB busses clocks
39-
*/
40-
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSE;
41-
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
42-
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
43-
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
44-
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
45-
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
46-
RCC_OscInitStruct.PLL.PLLM = 4;
47-
RCC_OscInitStruct.PLL.PLLN = 72;
48-
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
49-
RCC_OscInitStruct.PLL.PLLQ = 3;
50-
RCC_OscInitStruct.PLL.PLLR = 2;
51-
HAL_RCC_OscConfig(&RCC_OscInitStruct);
52-
/** Initializes the CPU, AHB and APB busses clocks
53-
*/
54-
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
55-
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
56-
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
57-
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
58-
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
59-
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
60-
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2);
31+
RCC_ClkInitTypeDef RCC_ClkInitStruct;
32+
RCC_OscInitTypeDef RCC_OscInitStruct;
33+
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
6134

62-
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1|RCC_PERIPHCLK_SDIO
63-
|RCC_PERIPHCLK_CLK48;
64-
PeriphClkInitStruct.PLLI2S.PLLI2SN = 50;
65-
PeriphClkInitStruct.PLLI2S.PLLI2SM = 4;
66-
PeriphClkInitStruct.PLLI2S.PLLI2SR = 2;
67-
PeriphClkInitStruct.PLLI2S.PLLI2SQ = 2;
68-
PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLQ;
69-
PeriphClkInitStruct.SdioClockSelection = RCC_SDIOCLKSOURCE_CLK48;
70-
PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC;
71-
PeriphClkInitStruct.I2sApb1ClockSelection = RCC_I2SAPB1CLKSOURCE_PLLI2S;
72-
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
35+
/* Enable Power Control clock */
36+
__HAL_RCC_PWR_CLK_ENABLE();
7337

74-
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1);
38+
/* The voltage scaling allows optimizing the power consumption when the
39+
* device is clocked below the maximum system frequency, to update the
40+
* voltage scaling value regarding system frequency refer to product
41+
* datasheet. */
42+
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
43+
44+
/* Enable HSE Oscillator and activate PLL with HSE as source */
45+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
46+
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
47+
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
48+
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
49+
RCC_OscInitStruct.PLL.PLLM = 8;
50+
RCC_OscInitStruct.PLL.PLLN = 200;
51+
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
52+
RCC_OscInitStruct.PLL.PLLQ = 7;
53+
RCC_OscInitStruct.PLL.PLLR = 2;
54+
HAL_RCC_OscConfig(&RCC_OscInitStruct);
55+
56+
/* Select PLLSAI output as USB clock source */
57+
PeriphClkInitStruct.PLLI2S.PLLI2SM = 8;
58+
PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4;
59+
PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
60+
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CK48;
61+
PeriphClkInitStruct.Clk48ClockSelection = RCC_CK48CLKSOURCE_PLLI2SQ;
62+
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
63+
64+
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
65+
* clocks dividers */
66+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK |
67+
RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
68+
69+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
70+
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
71+
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
72+
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
73+
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3);
7574
}

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