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jeplerjepler
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CHECKPOINT
This code compiles and gets to (failing) card detection.
1 parent d4b3e12 commit 52e6ec5

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11 files changed

+650
-2
lines changed

11 files changed

+650
-2
lines changed

‎ports/atmel-samd/Makefile

+15
Original file line numberDiff line numberDiff line change
@@ -215,6 +215,14 @@ SRC_ASF += \
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216216
endif
217217

218+
ifeq ($(CIRCUITPY_SDCARDIO_SDIO),1)
219+
SRC_ASF += \
220+
hal/src/hal_mci_sync.c \
221+
hpl/sdhc/hpl_sdhc.c \
222+
223+
$(BUILD)/asf4/$(CHIP_FAMILY)/hpl/sdhc/hpl_sdhc.o: CFLAGS += -Wno-cast-align
224+
endif
225+
218226
SRC_ASF := $(addprefix asf4/$(CHIP_FAMILY)/, $(SRC_ASF))
219227

220228
SRC_C = \
@@ -259,6 +267,9 @@ SRC_C = \
259267
supervisor/shared/memory.c \
260268
timer_handler.c \
261269

270+
ifeq ($(CIRCUITPY_SDCARDIO_SDIO),1)
271+
SRC_C += ports/atmel-samd/sd_mmc/sd_mmc.c
272+
endif
262273

263274
ifeq ($(CIRCUITPY_NETWORK),1)
264275
CFLAGS += -DMICROPY_PY_NETWORK=1
@@ -315,6 +326,10 @@ endif
315326
OBJ += $(addprefix $(BUILD)/, $(SRC_S:.s=.o))
316327
OBJ += $(addprefix $(BUILD)/, $(SRC_MOD:.c=.o))
317328

329+
SRC_QSTR += $(HEADER_BUILD)/sdiodata.h
330+
$(HEADER_BUILD)/sdiodata.h: $(TOP)/tools/mksdiodata.py | $(HEADER_BUILD)
331+
$(Q)$(PYTHON3) $< > $@
332+
318333
SRC_QSTR += $(SRC_C) $(SRC_SUPERVISOR) $(SRC_COMMON_HAL_EXPANDED) $(SRC_SHARED_MODULE_EXPANDED)
319334
# Sources that only hold QSTRs after pre-processing.
320335
SRC_QSTR_PREPROCESSOR += peripherals/samd/$(CHIP_FAMILY)/clocks.c

‎ports/atmel-samd/asf4

‎ports/atmel-samd/asf4_conf/samd51/hpl_sdhc_config.h

+24
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,24 @@
1+
/* Auto-generated config file hpl_sdhc_config.h */
2+
#ifndef HPL_SDHC_CONFIG_H
3+
#define HPL_SDHC_CONFIG_H
4+
5+
// <<< Use Configuration Wizard in Context Menu >>>
6+
7+
#include "peripheral_clk_config.h"
8+
9+
#ifndef CONF_BASE_FREQUENCY
10+
#define CONF_BASE_FREQUENCY CONF_SDHC0_FREQUENCY
11+
#endif
12+
13+
// <o> Clock Generator Select
14+
// <0=> Divided Clock mode
15+
// <1=> Programmable Clock mode
16+
// <i> This defines the clock generator mode in the SDCLK Frequency Select field
17+
// <id> sdhc_clk_gsel
18+
#ifndef CONF_SDHC0_CLK_GEN_SEL
19+
#define CONF_SDHC0_CLK_GEN_SEL 0
20+
#endif
21+
22+
// <<< end of configuration section >>>
23+
24+
#endif // HPL_SDHC_CONFIG_H

‎ports/atmel-samd/asf4_conf/samd51/peripheral_clk_config.h

+164
Original file line numberDiff line numberDiff line change
@@ -1001,6 +1001,170 @@
10011001
#define CONF_GCLK_USB_FREQUENCY 48000000
10021002
#endif
10031003

1004+
// <h> SDHC Clock Settings
1005+
// <y> SDHC Clock source
1006+
1007+
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
1008+
1009+
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
1010+
1011+
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
1012+
1013+
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
1014+
1015+
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
1016+
1017+
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
1018+
1019+
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
1020+
1021+
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
1022+
1023+
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
1024+
1025+
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
1026+
1027+
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
1028+
1029+
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
1030+
1031+
// <i> Select the clock source for SDHC.
1032+
// <id> sdhc_gclk_selection
1033+
#ifndef CONF_GCLK_SDHC0_SRC
1034+
#define CONF_GCLK_SDHC0_SRC GCLK_GENCTRL_SRC_DFLL_Val
1035+
#endif
1036+
1037+
// <y> SDHC clock slow source
1038+
1039+
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
1040+
1041+
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
1042+
1043+
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
1044+
1045+
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
1046+
1047+
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
1048+
1049+
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
1050+
1051+
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
1052+
1053+
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
1054+
1055+
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
1056+
1057+
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
1058+
1059+
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
1060+
1061+
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
1062+
1063+
// <i> Select the clock source for SDHC.
1064+
// <id> sdhc_slow_gclk_selection
1065+
#ifndef CONF_GCLK_SDHC0_SLOW_SRC
1066+
#define CONF_GCLK_SDHC0_SLOW_SRC GCLK_GENCTRL_SRC_DFLL_Val
1067+
#endif
1068+
// </h>
1069+
1070+
/**
1071+
* \def SDHC FREQUENCY
1072+
* \brief SDHC's Clock frequency
1073+
*/
1074+
#ifndef CONF_SDHC0_FREQUENCY
1075+
#define CONF_SDHC0_FREQUENCY 48000000
1076+
#endif
1077+
1078+
/**
1079+
* \def SDHC FREQUENCY
1080+
* \brief SDHC's Clock slow frequency
1081+
*/
1082+
#ifndef CONF_SDHC0_SLOW_FREQUENCY
1083+
#define CONF_SDHC0_SLOW_FREQUENCY 48000000
1084+
#endif
1085+
1086+
// <h> SDHC Clock Settings
1087+
// <y> SDHC Clock source
1088+
1089+
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
1090+
1091+
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
1092+
1093+
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
1094+
1095+
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
1096+
1097+
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
1098+
1099+
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
1100+
1101+
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
1102+
1103+
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
1104+
1105+
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
1106+
1107+
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
1108+
1109+
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
1110+
1111+
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
1112+
1113+
// <i> Select the clock source for SDHC.
1114+
// <id> sdhc_gclk_selection
1115+
#ifndef CONF_GCLK_SDHC1_SRC
1116+
#define CONF_GCLK_SDHC1_SRC GCLK_GENCTRL_SRC_DFLL_Val
1117+
#endif
1118+
1119+
// <y> SDHC clock slow source
1120+
1121+
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
1122+
1123+
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
1124+
1125+
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
1126+
1127+
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
1128+
1129+
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
1130+
1131+
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
1132+
1133+
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
1134+
1135+
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
1136+
1137+
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
1138+
1139+
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
1140+
1141+
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
1142+
1143+
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
1144+
1145+
// <i> Select the clock source for SDHC.
1146+
// <id> sdhc_slow_gclk_selection
1147+
#ifndef CONF_GCLK_SDHC1_SLOW_SRC
1148+
#define CONF_GCLK_SDHC1_SLOW_SRC GCLK_GENCTRL_SRC_DFLL_Val
1149+
#endif
1150+
// </h>
1151+
1152+
/**
1153+
* \def SDHC FREQUENCY
1154+
* \brief SDHC's Clock frequency
1155+
*/
1156+
#ifndef CONF_SDHC1_FREQUENCY
1157+
#define CONF_SDHC1_FREQUENCY 48000000
1158+
#endif
1159+
1160+
/**
1161+
* \def SDHC FREQUENCY
1162+
* \brief SDHC's Clock slow frequency
1163+
*/
1164+
#ifndef CONF_SDHC1_SLOW_FREQUENCY
1165+
#define CONF_SDHC1_SLOW_FREQUENCY 48000000
1166+
#endif
1167+
10041168
// <<< end of configuration section >>>
10051169

10061170
#endif // PERIPHERAL_CLK_CONFIG_H

‎ports/atmel-samd/boards/grandcentral_m4_express/mpconfigboard.mk

+2
Original file line numberDiff line numberDiff line change
@@ -10,3 +10,5 @@ QSPI_FLASH_FILESYSTEM = 1
1010
EXTERNAL_FLASH_DEVICE_COUNT = 2
1111
EXTERNAL_FLASH_DEVICES = "W25Q64JV_IQ, GD25Q64C"
1212
LONGINT_IMPL = MPZ
13+
14+
CIRCUITPY_SDCARDIO_SDIO = 1

‎ports/atmel-samd/boards/grandcentral_m4_express/pins.c

+17
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,18 @@
1+
#include "py/objtuple.h"
12
#include "shared-bindings/board/__init__.h"
23

4+
STATIC const mp_rom_obj_tuple_t sdio_data_tuple = {
5+
{&mp_type_tuple},
6+
4,
7+
{
8+
MP_ROM_PTR(&pin_PB18),
9+
MP_ROM_PTR(&pin_PB19),
10+
MP_ROM_PTR(&pin_PB20),
11+
MP_ROM_PTR(&pin_PB21),
12+
}
13+
};
14+
15+
316
// This mapping only includes functional names because pins broken
417
// out on connectors are labeled with their MCU name available from
518
// microcontroller.pin.
@@ -129,5 +142,9 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = {
129142
{ MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) },
130143
{ MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) },
131144
{ MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) },
145+
146+
{ MP_ROM_QSTR(MP_QSTR_SDIO_CLOCK), MP_ROM_PTR(&pin_PA21) },
147+
{ MP_ROM_QSTR(MP_QSTR_SDIO_COMMAND), MP_ROM_PTR(&pin_PA20) },
148+
{ MP_ROM_QSTR(MP_QSTR_SDIO_DATA), MP_ROM_PTR(&sdio_data_tuple) },
132149
};
133150
MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table);

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