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[AArch64] Add a test to show incorrect latencies into Bundle instructions. NFC
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‎llvm/test/CodeGen/AArch64/misched-bundle.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
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# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a510 -run-pass=machine-scheduler -debug-only=machine-scheduler %s -o - 2>&1 | FileCheck %s
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# REQUIRES: asserts
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# CHECK: SU(0): renamable $z0 = LD1H renamable $p0, renamable $x1, renamable $x10 :: (load unknown-size, align 1)
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# CHECK-NEXT: # preds left : 0
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# CHECK-NEXT: # succs left : 4
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# CHECK-NEXT: # rdefs left : 0
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# CHECK-NEXT: Latency : 3
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# CHECK-NEXT: Depth : 0
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# CHECK-NEXT: Height : 7
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# CHECK-NEXT: Successors:
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# CHECK-NEXT: SU(6): Out Latency=1
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# CHECK-NEXT: SU(6): Data Latency=3 Reg=$z0
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# CHECK-NEXT: SU(9): Ord Latency=0 Memory
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# CHECK-NEXT: SU(8): Ord Latency=0 Memory
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# CHECK-NEXT: Single Issue : false;
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# CHECK-NEXT: SU(1): renamable $z1 = LD1H renamable $p0, renamable $x2, renamable $x10 :: (load unknown-size, align 1)
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# CHECK-NEXT: # preds left : 0
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# CHECK-NEXT: # succs left : 4
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# CHECK-NEXT: # rdefs left : 0
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# CHECK-NEXT: Latency : 3
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# CHECK-NEXT: Depth : 0
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# CHECK-NEXT: Height : 7
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# CHECK-NEXT: Successors:
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# CHECK-NEXT: SU(7): Out Latency=1
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# CHECK-NEXT: SU(6): Data Latency=3 Reg=$z1
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# CHECK-NEXT: SU(9): Ord Latency=0 Memory
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# CHECK-NEXT: SU(8): Ord Latency=0 Memory
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# CHECK-NEXT: Single Issue : false;
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# CHECK-NEXT: SU(2): renamable $z2 = LD1H renamable $p0, renamable $x0, renamable $x10 :: (load unknown-size, align 1)
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# CHECK-NEXT: # preds left : 0
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# CHECK-NEXT: # succs left : 3
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# CHECK-NEXT: # rdefs left : 0
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# CHECK-NEXT: Latency : 3
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# CHECK-NEXT: Depth : 0
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# CHECK-NEXT: Height : 7
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# CHECK-NEXT: Successors:
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# CHECK-NEXT: SU(6): Data Latency=3 Reg=$z2
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# CHECK-NEXT: SU(9): Ord Latency=0 Memory
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# CHECK-NEXT: SU(8): Ord Latency=0 Memory
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# CHECK-NEXT: Single Issue : false;
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# CHECK-NEXT: SU(3): renamable $z3 = LD1H renamable $p0, renamable $x11, renamable $x10 :: (load unknown-size, align 1)
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# CHECK-NEXT: # preds left : 0
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# CHECK-NEXT: # succs left : 3
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# CHECK-NEXT: # rdefs left : 0
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# CHECK-NEXT: Latency : 3
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# CHECK-NEXT: Depth : 0
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# CHECK-NEXT: Height : 0
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# CHECK-NEXT: Successors:
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# CHECK-NEXT: SU(7): Data Latency=0 Reg=$z3
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# CHECK-NEXT: SU(9): Ord Latency=0 Memory
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# CHECK-NEXT: SU(8): Ord Latency=0 Memory
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# CHECK-NEXT: Single Issue : false;
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# CHECK-NEXT: SU(4): renamable $z4 = LD1H renamable $p0, renamable $x12, renamable $x10 :: (load unknown-size, align 1)
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# CHECK-NEXT: # preds left : 0
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# CHECK-NEXT: # succs left : 3
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# CHECK-NEXT: # rdefs left : 0
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# CHECK-NEXT: Latency : 3
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# CHECK-NEXT: Depth : 0
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# CHECK-NEXT: Height : 0
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# CHECK-NEXT: Successors:
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# CHECK-NEXT: SU(7): Data Latency=0 Reg=$z4
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# CHECK-NEXT: SU(9): Ord Latency=0 Memory
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# CHECK-NEXT: SU(8): Ord Latency=0 Memory
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# CHECK-NEXT: Single Issue : false;
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# CHECK-NEXT: SU(5): renamable $z5 = LD1H renamable $p0, renamable $x13, renamable $x10 :: (load unknown-size, align 1)
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# CHECK-NEXT: # preds left : 0
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# CHECK-NEXT: # succs left : 3
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# CHECK-NEXT: # rdefs left : 0
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# CHECK-NEXT: Latency : 3
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# CHECK-NEXT: Depth : 0
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# CHECK-NEXT: Height : 0
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# CHECK-NEXT: Successors:
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# CHECK-NEXT: SU(7): Data Latency=0 Reg=$z5
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# CHECK-NEXT: SU(9): Ord Latency=0 Memory
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# CHECK-NEXT: SU(8): Ord Latency=0 Memory
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# CHECK-NEXT: Single Issue : false;
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# CHECK-NEXT: SU(6): $z0 = FMAD_ZPmZZ_H renamable $p0, killed $z0(tied-def 0), killed renamable $z1, killed renamable $z2
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# CHECK-NEXT: # preds left : 4
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# CHECK-NEXT: # succs left : 2
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# CHECK-NEXT: # rdefs left : 0
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# CHECK-NEXT: Latency : 4
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# CHECK-NEXT: Depth : 3
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# CHECK-NEXT: Height : 4
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# CHECK-NEXT: Predecessors:
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# CHECK-NEXT: SU(2): Data Latency=3 Reg=$z2
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# CHECK-NEXT: SU(1): Data Latency=3 Reg=$z1
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# CHECK-NEXT: SU(0): Out Latency=1
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# CHECK-NEXT: SU(0): Data Latency=3 Reg=$z0
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# CHECK-NEXT: Successors:
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# CHECK-NEXT: SU(8): Data Latency=4 Reg=$z0
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# CHECK-NEXT: SU(7): Anti Latency=0
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# CHECK-NEXT: Single Issue : false;
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# CHECK-NEXT: SU(7): BUNDLE implicit-def $z1, implicit-def $q1, implicit-def $d1, implicit-def $s1, implicit-def $h1, implicit-def $b1, implicit $z5, implicit $p0, implicit killed $z4, implicit killed $z3
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# CHECK-NEXT: # preds left : 5
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# CHECK-NEXT: # succs left : 1
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# CHECK-NEXT: # rdefs left : 0
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# CHECK-NEXT: Latency : 1
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# CHECK-NEXT: Depth : 3
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# CHECK-NEXT: Height : 0
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# CHECK-NEXT: Predecessors:
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# CHECK-NEXT: SU(6): Anti Latency=0
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# CHECK-NEXT: SU(5): Data Latency=0 Reg=$z5
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# CHECK-NEXT: SU(4): Data Latency=0 Reg=$z4
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# CHECK-NEXT: SU(3): Data Latency=0 Reg=$z3
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# CHECK-NEXT: SU(1): Out Latency=1
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# CHECK-NEXT: Successors:
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# CHECK-NEXT: SU(9): Data Latency=0 Reg=$z1
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# CHECK-NEXT: Single Issue : false;
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# CHECK-NEXT: SU(8): ST1H killed renamable $z0, renamable $p0, renamable $x0, renamable $x10 :: (store unknown-size, align 1)
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# CHECK-NEXT: # preds left : 7
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# CHECK-NEXT: # succs left : 1
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# CHECK-NEXT: # rdefs left : 0
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# CHECK-NEXT: Latency : 1
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# CHECK-NEXT: Depth : 7
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# CHECK-NEXT: Height : 0
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# CHECK-NEXT: Predecessors:
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# CHECK-NEXT: SU(6): Data Latency=4 Reg=$z0
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# CHECK-NEXT: SU(5): Ord Latency=0 Memory
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# CHECK-NEXT: SU(4): Ord Latency=0 Memory
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# CHECK-NEXT: SU(3): Ord Latency=0 Memory
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# CHECK-NEXT: SU(2): Ord Latency=0 Memory
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# CHECK-NEXT: SU(1): Ord Latency=0 Memory
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# CHECK-NEXT: SU(0): Ord Latency=0 Memory
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# CHECK-NEXT: Successors:
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# CHECK-NEXT: SU(9): Ord Latency=0 Memory
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# CHECK-NEXT: Single Issue : false;
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# CHECK-NEXT: SU(9): ST1H killed renamable $z1, renamable $p0, renamable $x13, renamable $x10 :: (store unknown-size, align 1)
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# CHECK-NEXT: # preds left : 8
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# CHECK-NEXT: # succs left : 0
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# CHECK-NEXT: # rdefs left : 0
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# CHECK-NEXT: Latency : 1
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# CHECK-NEXT: Depth : 7
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# CHECK-NEXT: Height : 0
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# CHECK-NEXT: Predecessors:
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# CHECK-NEXT: SU(8): Ord Latency=0 Memory
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# CHECK-NEXT: SU(7): Data Latency=0 Reg=$z1
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# CHECK-NEXT: SU(5): Ord Latency=0 Memory
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# CHECK-NEXT: SU(4): Ord Latency=0 Memory
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# CHECK-NEXT: SU(3): Ord Latency=0 Memory
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# CHECK-NEXT: SU(2): Ord Latency=0 Memory
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# CHECK-NEXT: SU(1): Ord Latency=0 Memory
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# CHECK-NEXT: SU(0): Ord Latency=0 Memory
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# CHECK-NEXT: Single Issue : false;
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# CHECK-NEXT: ExitSU: RET_ReallyLR
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# CHECK-NEXT: # preds left : 0
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# CHECK-NEXT: # succs left : 0
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# CHECK-NEXT: # rdefs left : 0
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# CHECK-NEXT: Latency : 0
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# CHECK-NEXT: Depth : 0
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# CHECK-NEXT: Height : 0
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---
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name: test
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $p0, $x0, $x1, $x2, $x10, $x11, $x12, $x13
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; CHECK-LABEL: name: test
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; CHECK: liveins: $p0, $x0, $x1, $x2, $x10, $x11, $x12, $x13
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: renamable $z0 = LD1H renamable $p0, renamable $x1, renamable $x10 :: (load unknown-size, align 1)
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; CHECK-NEXT: renamable $z1 = LD1H renamable $p0, renamable $x2, renamable $x10 :: (load unknown-size, align 1)
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; CHECK-NEXT: renamable $z2 = LD1H renamable $p0, renamable $x0, renamable $x10 :: (load unknown-size, align 1)
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; CHECK-NEXT: $z0 = FMAD_ZPmZZ_H renamable $p0, killed $z0, renamable $z1, killed renamable $z2
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; CHECK-NEXT: renamable $z3 = LD1H renamable $p0, renamable $x11, renamable $x10 :: (load unknown-size, align 1)
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; CHECK-NEXT: renamable $z4 = LD1H renamable $p0, renamable $x12, renamable $x10 :: (load unknown-size, align 1)
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; CHECK-NEXT: renamable $z5 = LD1H renamable $p0, renamable $x13, renamable $x10 :: (load unknown-size, align 1)
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; CHECK-NEXT: ST1H killed renamable $z0, renamable $p0, renamable $x0, renamable $x10 :: (store unknown-size, align 1)
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; CHECK-NEXT: BUNDLE implicit-def $z1, implicit-def $q1, implicit-def $d1, implicit-def $s1, implicit-def $h1, implicit-def $b1, implicit $z5, implicit $p0, implicit $z4, implicit $z3 {
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; CHECK-NEXT: $z1 = MOVPRFX_ZZ $z5
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; CHECK-NEXT: $z1 = FMLA_ZPmZZ_H renamable $p0, internal $z1, renamable $z4, renamable $z3
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; CHECK-NEXT: }
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; CHECK-NEXT: ST1H renamable $z1, renamable $p0, renamable $x13, renamable $x10 :: (store unknown-size, align 1)
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; CHECK-NEXT: RET_ReallyLR
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renamable $z0 = LD1H renamable $p0, renamable $x1, renamable $x10 :: (load unknown-size)
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renamable $z1 = LD1H renamable $p0, renamable $x2, renamable $x10 :: (load unknown-size)
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renamable $z2 = LD1H renamable $p0, renamable $x0, renamable $x10 :: (load unknown-size)
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renamable $z3 = LD1H renamable $p0, renamable $x11, renamable $x10 :: (load unknown-size)
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renamable $z4 = LD1H renamable $p0, renamable $x12, renamable $x10 :: (load unknown-size)
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renamable $z5 = LD1H renamable $p0, renamable $x13, renamable $x10 :: (load unknown-size)
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$z0 = FMAD_ZPmZZ_H renamable $p0, killed $z0, killed renamable $z1, killed renamable $z2
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BUNDLE implicit-def $z1, implicit-def $q1, implicit-def $d1, implicit-def $s1, implicit-def $h1, implicit-def $b1, implicit $z5, implicit $p0, implicit killed $z4, implicit killed $z3 {
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$z1 = MOVPRFX_ZZ $z5
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$z1 = FMLA_ZPmZZ_H renamable $p0, internal killed $z1, killed renamable $z4, killed renamable $z3
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}
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ST1H killed renamable $z0, renamable $p0, renamable $x0, renamable $x10 :: (store unknown-size)
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ST1H killed renamable $z1, renamable $p0, renamable $x13, renamable $x10 :: (store unknown-size)
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RET_ReallyLR
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...

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