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Merge pull request #2 from suvorovrain/riscvcpufeat
RISC-V cpufeatures
2 parents 72564cf + 9d566fe commit 7c575d2

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‎GraphBLAS/Source/cpu/GB_cpu_features_impl.c‎

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@@ -41,6 +41,7 @@
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#include "src/impl_x86_freebsd.c"
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#include "src/impl_x86_linux_or_android.c"
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#include "src/impl_x86_windows.c"
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#include "src/impl_riscv_linux.c"
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#if GBX86
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#if (defined(__apple__) || defined(__APPLE__) || defined(__MACH__))
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// needed for src/impl_x86_macos.c:

‎GraphBLAS/cpu_features/CMakeLists.txt‎

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@@ -49,6 +49,7 @@ set(PROCESSOR_IS_ARM FALSE)
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set(PROCESSOR_IS_AARCH64 FALSE)
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set(PROCESSOR_IS_X86 FALSE)
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set(PROCESSOR_IS_POWER FALSE)
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set(PROCESSOR_IS_RISCV FALSE)
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if(CMAKE_SYSTEM_PROCESSOR MATCHES "^mips")
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set(PROCESSOR_IS_MIPS TRUE)
@@ -60,6 +61,8 @@ elseif(CMAKE_SYSTEM_PROCESSOR MATCHES "(x86_64)|(AMD64|amd64)|(^i.86$)")
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set(PROCESSOR_IS_X86 TRUE)
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elseif(CMAKE_SYSTEM_PROCESSOR MATCHES "^(powerpc|ppc)")
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set(PROCESSOR_IS_POWER TRUE)
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elseif(CMAKE_SYSTEM_PROCESSOR MATCHES "riscv")
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set(PROCESSOR_IS_RISCV TRUE)
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endif()
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macro(add_cpu_features_headers_and_sources HDRS_LIST_NAME SRCS_LIST_NAME)
@@ -78,6 +81,8 @@ macro(add_cpu_features_headers_and_sources HDRS_LIST_NAME SRCS_LIST_NAME)
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list(APPEND ${SRCS_LIST_NAME} ${PROJECT_SOURCE_DIR}/include/internal/cpuid_x86.h)
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elseif(PROCESSOR_IS_POWER)
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list(APPEND ${HDRS_LIST_NAME} ${PROJECT_SOURCE_DIR}/include/cpuinfo_ppc.h)
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elseif(PROCESSOR_IS_RISCV)
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list(APPEND ${HDRS_LIST_NAME} ${PROJECT_SOURCE_DIR}/include/cpuinfo_riscv.h)
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else()
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message(FATAL_ERROR "Unsupported architectures ${CMAKE_SYSTEM_PROCESSOR}")
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endif()

‎GraphBLAS/cpu_features/include/cpuinfo_riscv.h‎

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// Copyright 2022 Google LLC
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef CPU_FEATURES_INCLUDE_CPUINFO_RISCV_H_
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#define CPU_FEATURES_INCLUDE_CPUINFO_RISCV_H_
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#include "cpu_features_cache_info.h"
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#include "cpu_features_macros.h"
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#if !defined(CPU_FEATURES_ARCH_RISCV)
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#error "Including cpuinfo_riscv.h from a non-riscv target."
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#endif
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CPU_FEATURES_START_CPP_NAMESPACE
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typedef struct {
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// Base
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int RV32I : 1; // Base Integer Instruction Set, 32-bit
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int RV64I : 1; // Base Integer Instruction Set, 64-bit
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// Extension
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int M : 1; // Standard Extension for Integer Multiplication/Division
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int A : 1; // Standard Extension for Atomic Instructions
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int F : 1; // Standard Extension for Single-Precision Floating-Point
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int D : 1; // Standard Extension for Double-Precision Floating-Point
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int Q : 1; // Standard Extension for Quad-Precision Floating-Point
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int C : 1; // Standard Extension for Compressed Instructions
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int V : 1; // Standard Extension for Vector Instructions
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int Zicsr : 1; // Control and Status Register (CSR)
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int Zifencei : 1; // Instruction-Fetch Fence
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} RiscvFeatures;
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typedef struct {
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RiscvFeatures features;
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char uarch[64]; // 0 terminated string
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char vendor[64]; // 0 terminated string
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} RiscvInfo;
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typedef enum {
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RISCV_RV32I,
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RISCV_RV64I,
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RISCV_M,
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RISCV_A,
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RISCV_F,
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RISCV_D,
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RISCV_Q,
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RISCV_C,
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RISCV_V,
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RISCV_Zicsr,
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RISCV_Zifencei,
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RISCV_LAST_,
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} RiscvFeaturesEnum;
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RiscvInfo GetRiscvInfo(void);
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int GetRiscvFeaturesEnumValue(const RiscvFeatures* features,
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RiscvFeaturesEnum value);
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const char* GetRiscvFeaturesEnumName(RiscvFeaturesEnum);
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CPU_FEATURES_END_CPP_NAMESPACE
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#endif // CPU_FEATURES_INCLUDE_CPUINFO_RISCV_H_

‎GraphBLAS/cpu_features/src/impl_riscv_linux.c‎

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// Copyright 2022 Google LLC
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "cpu_features_macros.h"
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#ifdef CPU_FEATURES_ARCH_RISCV
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#if defined(CPU_FEATURES_OS_LINUX)
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#include "cpuinfo_riscv.h"
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// According to
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// https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/riscv/cpus.yaml
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// isa string should match the following regex
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// ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:_[hsxz](?:[a-z])+)*$
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//
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// This means we can test for features in this exact order except for Z
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// extensions.
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////////////////////////////////////////////////////////////////////////////////
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// Definitions for introspection.
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////////////////////////////////////////////////////////////////////////////////
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#define INTROSPECTION_TABLE \
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LINE(RISCV_RV32I, RV32I, "rv32i", RISCV_HWCAP_32, 0) \
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LINE(RISCV_RV64I, RV64I, "rv64i", RISCV_HWCAP_64, 0) \
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LINE(RISCV_M, M, "m", RISCV_HWCAP_M, 0) \
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LINE(RISCV_A, A, "a", RISCV_HWCAP_A, 0) \
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LINE(RISCV_F, F, "f", RISCV_HWCAP_F, 0) \
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LINE(RISCV_D, D, "d", RISCV_HWCAP_D, 0) \
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LINE(RISCV_Q, Q, "q", RISCV_HWCAP_Q, 0) \
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LINE(RISCV_C, C, "c", RISCV_HWCAP_C, 0) \
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LINE(RISCV_V, V, "v", RISCV_HWCAP_V, 0) \
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LINE(RISCV_Zicsr, Zicsr, "_zicsr", 0, 0) \
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LINE(RISCV_Zifencei, Zifencei, "_zifencei", 0, 0)
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#define INTROSPECTION_PREFIX Riscv
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#define INTROSPECTION_ENUM_PREFIX RISCV
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#include "define_introspection_and_hwcaps.inl"
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////////////////////////////////////////////////////////////////////////////////
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// Implementation.
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////////////////////////////////////////////////////////////////////////////////
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#include <stdbool.h>
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#include <stdio.h>
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#include "internal/filesystem.h"
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#include "internal/stack_line_reader.h"
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static const RiscvInfo kEmptyRiscvInfo;
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static void HandleRiscVIsaLine(StringView line, RiscvFeatures* const features) {
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for (size_t i = 0; i < RISCV_LAST_; ++i) {
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StringView flag = str(kCpuInfoFlags[i]);
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int index_of_flag = CpuFeatures_StringView_IndexOf(line, flag);
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bool is_set = index_of_flag != -1;
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kSetters[i](features, is_set);
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if (is_set)
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line = CpuFeatures_StringView_PopFront(line, index_of_flag + flag.size);
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}
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}
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static bool HandleRiscVLine(const LineResult result, RiscvInfo* const info) {
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StringView line = result.line;
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StringView key, value;
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if (CpuFeatures_StringView_GetAttributeKeyValue(line, &key, &value)) {
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if (CpuFeatures_StringView_IsEquals(key, str("isa"))) {
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HandleRiscVIsaLine(value, &info->features);
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} else if (CpuFeatures_StringView_IsEquals(key, str("uarch"))) {
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int index = CpuFeatures_StringView_IndexOfChar(value, ',');
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if (index == -1) return true;
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StringView vendor = CpuFeatures_StringView_KeepFront(value, index);
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StringView uarch = CpuFeatures_StringView_PopFront(value, index + 1);
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CpuFeatures_StringView_CopyString(vendor, info->vendor,
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sizeof(info->vendor));
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CpuFeatures_StringView_CopyString(uarch, info->uarch,
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sizeof(info->uarch));
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}
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}
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return !result.eof;
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}
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static void FillProcCpuInfoData(RiscvInfo* const info) {
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const int fd = CpuFeatures_OpenFile("/proc/cpuinfo");
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if (fd >= 0) {
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StackLineReader reader;
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StackLineReader_Initialize(&reader, fd);
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for (;;) {
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if (!HandleRiscVLine(StackLineReader_NextLine(&reader), info)) break;
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}
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CpuFeatures_CloseFile(fd);
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}
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}
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RiscvInfo GetRiscvInfo(void) {
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RiscvInfo info = kEmptyRiscvInfo;
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FillProcCpuInfoData(&info);
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return info;
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}
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#endif // defined(CPU_FEATURES_OS_LINUX) || defined(CPU_FEATURES_OS_ANDROID)
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#endif // CPU_FEATURES_ARCH_RISCV

‎GraphBLAS/cpu_features/src/utils/list_cpu_features.c‎

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#include "cpuinfo_mips.h"
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#elif defined(CPU_FEATURES_ARCH_PPC)
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#include "cpuinfo_ppc.h"
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#elif defined(CPU_FEATURES_ARCH_RISCV)
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#include "cpuinfo_riscv.h"
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#endif
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// Design principles

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