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Merged main:08f77241c0d9 into amd-gfx:182209fab483
Local branch amd-gfx 182209f Merged main:d9111f19d2ea into amd-gfx:00799b092b24 Remote branch main 08f7724 [clang-tidy][doc] mention smart ptr in bugprone-unhandled-self-assignment.WarnOnlyIfThisHasSuspiciousField option (llvm#121316)
2 parents 182209f + 08f7724 commit 548f6ae

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-15
lines changed

6 files changed

+230
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lines changed

‎clang-tools-extra/docs/clang-tidy/checks/bugprone/unhandled-self-assignment.rst

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -120,5 +120,7 @@ temporary object into ``this`` (needs a move assignment operator):
120120
121121
.. option:: WarnOnlyIfThisHasSuspiciousField
122122

123-
When `true`, the check will warn only if the container class of the copy assignment operator
124-
has any suspicious fields (pointer or C array). This option is set to `true` by default.
123+
When `true`, the check will warn only if the container class of the copy
124+
assignment operator has any suspicious fields (pointer, C array and C++ smart
125+
pointer).
126+
This option is set to `true` by default.

‎compiler-rt/lib/tysan/CMakeLists.txt

Lines changed: 22 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -3,11 +3,25 @@ include_directories(..)
33
# Runtime library sources and build flags.
44
set(TYSAN_SOURCES
55
tysan.cpp
6-
tysan_interceptors.cpp)
6+
tysan_interceptors.cpp
7+
)
8+
9+
SET(TYSAN_HEADERS
10+
tysan.h
11+
tysan_flags.inc
12+
tysan_platform.h
13+
)
14+
715
set(TYSAN_COMMON_CFLAGS ${SANITIZER_COMMON_CFLAGS})
816
append_rtti_flag(OFF TYSAN_COMMON_CFLAGS)
917
# Prevent clang from generating libc calls.
1018
append_list_if(COMPILER_RT_HAS_FFREESTANDING_FLAG -ffreestanding TYSAN_COMMON_CFLAGS)
19+
set(TYSAN_DYNAMIC_CFLAGS ${TYSAN_COMMON_CFLAGS})
20+
21+
set(TYSAN_COMMON_DEFINITIONS "")
22+
set(TYSAN_DYNAMIC_DEFINITIONS ${TYSAN_COMMON_DEFINITIONS} TYSAN_DYNAMIC=1)
23+
24+
# Compile TYSan sources into an object library.
1125

1226
add_compiler_rt_object_libraries(RTTysan_dynamic
1327
OS ${SANITIZER_COMMON_SUPPORTED_OS}
@@ -47,17 +61,18 @@ if(APPLE)
4761
DEFS ${TYSAN_COMMON_DEFINITIONS}
4862
PARENT_TARGET tysan)
4963
else()
64+
set(TYSAN_CFLAGS ${TYSAN_COMMON_CFLAGS})
65+
append_list_if(COMPILER_RT_HAS_FPIE_FLAG -fPIE TYSAN_CFLAGS)
66+
5067
foreach(arch ${TYSAN_SUPPORTED_ARCH})
51-
set(TYSAN_CFLAGS ${TYSAN_COMMON_CFLAGS})
52-
append_list_if(COMPILER_RT_HAS_FPIE_FLAG -fPIE TYSAN_CFLAGS)
5368
add_compiler_rt_runtime(clang_rt.tysan
5469
STATIC
5570
ARCHS ${arch}
5671
SOURCES ${TYSAN_SOURCES}
57-
$<TARGET_OBJECTS:RTInterception.${arch}>
58-
$<TARGET_OBJECTS:RTSanitizerCommon.${arch}>
59-
$<TARGET_OBJECTS:RTSanitizerCommonLibc.${arch}>
60-
$<TARGET_OBJECTS:RTSanitizerCommonSymbolizer.${arch}>
72+
OBJECT_LIBS RTInterception
73+
RTSanitizerCommon
74+
RTSanitizerCommonLibc
75+
RTSanitizerCommonSymbolizer
6176
CFLAGS ${TYSAN_CFLAGS}
6277
PARENT_TARGET tysan)
6378
endforeach()

‎compiler-rt/test/fuzzer/noasan-strcmp.test

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
UNSUPPORTED: darwin, target={{.*(freebsd|windows).*}}
1+
UNSUPPORTED: darwin, target={{.*(freebsd|windows).*}}, target=aarch64{{.*}}
22

33
RUN: %cpp_compiler -fno-sanitize=address %S/StrcmpTest.cpp -o %t-NoAsanStrcmpTest
44
RUN: not %run %t-NoAsanStrcmpTest -seed=1 -runs=2000000 2>&1 | FileCheck %s

‎llvm/include/llvm/Config/llvm-config.h.cmake

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@
1616

1717
/* Indicate that this is LLVM compiled from the amd-gfx branch. */
1818
#define LLVM_HAVE_BRANCH_AMD_GFX
19-
#define LLVM_MAIN_REVISION 522518
19+
#define LLVM_MAIN_REVISION 522523
2020

2121
/* Define if LLVM_ENABLE_DUMP is enabled */
2222
#cmakedefine LLVM_ENABLE_DUMP

‎llvm/test/Transforms/LoopVectorize/iv_outside_user.ll

Lines changed: 202 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --replace-value-regex "!llvm.loop ![0-9]+" --version 5
22
; RUN: opt -S -passes=loop-vectorize -force-vector-interleave=1 -force-vector-width=2 < %s | FileCheck --check-prefixes=CHECK,VEC %s
3-
; RUN: opt -S -passes=loop-vectorize -force-vector-interleave=2 -force-vector-width=1 < %s | FileCheck --check-prefixes=CHECK %s
3+
; RUN: opt -S -passes=loop-vectorize -force-vector-interleave=2 -force-vector-width=1 < %s | FileCheck --check-prefixes=CHECK,INTERLEAVE %s
44

55
define i32 @postinc(i32 %k) {
66
; CHECK-LABEL: define i32 @postinc(
@@ -430,6 +430,39 @@ define i64 @iv_scalar_steps_and_outside_users(ptr %ptr) {
430430
; VEC-NEXT: [[IV_LCSSA:%.*]] = phi i64 [ [[IV]], %[[LOOP]] ], [ 1001, %[[MIDDLE_BLOCK]] ]
431431
; VEC-NEXT: ret i64 [[IV_LCSSA]]
432432
;
433+
; INTERLEAVE-LABEL: define i64 @iv_scalar_steps_and_outside_users(
434+
; INTERLEAVE-SAME: ptr [[PTR:%.*]]) {
435+
; INTERLEAVE-NEXT: [[ENTRY:.*]]:
436+
; INTERLEAVE-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
437+
; INTERLEAVE: [[VECTOR_PH]]:
438+
; INTERLEAVE-NEXT: br label %[[VECTOR_BODY:.*]]
439+
; INTERLEAVE: [[VECTOR_BODY]]:
440+
; INTERLEAVE-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
441+
; INTERLEAVE-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0
442+
; INTERLEAVE-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1
443+
; INTERLEAVE-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[PTR]], i64 [[TMP0]]
444+
; INTERLEAVE-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[PTR]], i64 [[TMP1]]
445+
; INTERLEAVE-NEXT: store i64 [[TMP0]], ptr [[TMP2]], align 4
446+
; INTERLEAVE-NEXT: store i64 [[TMP1]], ptr [[TMP3]], align 4
447+
; INTERLEAVE-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
448+
; INTERLEAVE-NEXT: [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1002
449+
; INTERLEAVE-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], {{!llvm.loop ![0-9]+}}
450+
; INTERLEAVE: [[MIDDLE_BLOCK]]:
451+
; INTERLEAVE-NEXT: br i1 true, label %[[EXIT:.*]], label %[[SCALAR_PH]]
452+
; INTERLEAVE: [[SCALAR_PH]]:
453+
; INTERLEAVE-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 1002, %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
454+
; INTERLEAVE-NEXT: br label %[[LOOP:.*]]
455+
; INTERLEAVE: [[LOOP]]:
456+
; INTERLEAVE-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
457+
; INTERLEAVE-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], 1
458+
; INTERLEAVE-NEXT: [[GEP_PTR:%.*]] = getelementptr inbounds i64, ptr [[PTR]], i64 [[IV]]
459+
; INTERLEAVE-NEXT: store i64 [[IV]], ptr [[GEP_PTR]], align 4
460+
; INTERLEAVE-NEXT: [[EXITCOND:%.*]] = icmp ugt i64 [[IV]], 1000
461+
; INTERLEAVE-NEXT: br i1 [[EXITCOND]], label %[[EXIT]], label %[[LOOP]], {{!llvm.loop ![0-9]+}}
462+
; INTERLEAVE: [[EXIT]]:
463+
; INTERLEAVE-NEXT: [[IV_LCSSA:%.*]] = phi i64 [ [[IV]], %[[LOOP]] ], [ 1001, %[[MIDDLE_BLOCK]] ]
464+
; INTERLEAVE-NEXT: ret i64 [[IV_LCSSA]]
465+
;
433466
entry:
434467
br label %loop
435468

@@ -485,6 +518,42 @@ define i32 @iv_2_dead_in_loop_only_used_outside(ptr %ptr) {
485518
; VEC-NEXT: [[IV_2_LCSSA:%.*]] = phi i32 [ [[IV_2]], %[[LOOP]] ], [ 2002, %[[MIDDLE_BLOCK]] ]
486519
; VEC-NEXT: ret i32 [[IV_2_LCSSA]]
487520
;
521+
; INTERLEAVE-LABEL: define i32 @iv_2_dead_in_loop_only_used_outside(
522+
; INTERLEAVE-SAME: ptr [[PTR:%.*]]) {
523+
; INTERLEAVE-NEXT: [[ENTRY:.*]]:
524+
; INTERLEAVE-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
525+
; INTERLEAVE: [[VECTOR_PH]]:
526+
; INTERLEAVE-NEXT: br label %[[VECTOR_BODY:.*]]
527+
; INTERLEAVE: [[VECTOR_BODY]]:
528+
; INTERLEAVE-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
529+
; INTERLEAVE-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0
530+
; INTERLEAVE-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1
531+
; INTERLEAVE-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[PTR]], i64 [[TMP0]]
532+
; INTERLEAVE-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[PTR]], i64 [[TMP1]]
533+
; INTERLEAVE-NEXT: store i64 [[TMP0]], ptr [[TMP2]], align 4
534+
; INTERLEAVE-NEXT: store i64 [[TMP1]], ptr [[TMP3]], align 4
535+
; INTERLEAVE-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
536+
; INTERLEAVE-NEXT: [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1002
537+
; INTERLEAVE-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], {{!llvm.loop ![0-9]+}}
538+
; INTERLEAVE: [[MIDDLE_BLOCK]]:
539+
; INTERLEAVE-NEXT: br i1 true, label %[[EXIT:.*]], label %[[SCALAR_PH]]
540+
; INTERLEAVE: [[SCALAR_PH]]:
541+
; INTERLEAVE-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 1002, %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
542+
; INTERLEAVE-NEXT: [[BC_RESUME_VAL1:%.*]] = phi i32 [ 2004, %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
543+
; INTERLEAVE-NEXT: br label %[[LOOP:.*]]
544+
; INTERLEAVE: [[LOOP]]:
545+
; INTERLEAVE-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
546+
; INTERLEAVE-NEXT: [[IV_2:%.*]] = phi i32 [ [[BC_RESUME_VAL1]], %[[SCALAR_PH]] ], [ [[IV_2_NEXT:%.*]], %[[LOOP]] ]
547+
; INTERLEAVE-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], 1
548+
; INTERLEAVE-NEXT: [[IV_2_NEXT]] = add nuw i32 [[IV_2]], 2
549+
; INTERLEAVE-NEXT: [[GEP_PTR:%.*]] = getelementptr inbounds i64, ptr [[PTR]], i64 [[IV]]
550+
; INTERLEAVE-NEXT: store i64 [[IV]], ptr [[GEP_PTR]], align 4
551+
; INTERLEAVE-NEXT: [[EXITCOND:%.*]] = icmp ugt i64 [[IV]], 1000
552+
; INTERLEAVE-NEXT: br i1 [[EXITCOND]], label %[[EXIT]], label %[[LOOP]], {{!llvm.loop ![0-9]+}}
553+
; INTERLEAVE: [[EXIT]]:
554+
; INTERLEAVE-NEXT: [[IV_2_LCSSA:%.*]] = phi i32 [ [[IV_2]], %[[LOOP]] ], [ 2002, %[[MIDDLE_BLOCK]] ]
555+
; INTERLEAVE-NEXT: ret i32 [[IV_2_LCSSA]]
556+
;
488557
entry:
489558
br label %loop
490559

@@ -625,6 +694,38 @@ define i32 @postinc_not_iv_backedge_value(i32 %k) {
625694
; VEC-NEXT: [[INC_2_LCSSA:%.*]] = phi i32 [ [[INC_2]], %[[FOR_BODY]] ], [ [[TMP2]], %[[MIDDLE_BLOCK]] ]
626695
; VEC-NEXT: ret i32 [[INC_2_LCSSA]]
627696
;
697+
; INTERLEAVE-LABEL: define i32 @postinc_not_iv_backedge_value(
698+
; INTERLEAVE-SAME: i32 [[K:%.*]]) {
699+
; INTERLEAVE-NEXT: [[ENTRY:.*]]:
700+
; INTERLEAVE-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[K]], 2
701+
; INTERLEAVE-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
702+
; INTERLEAVE: [[VECTOR_PH]]:
703+
; INTERLEAVE-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[K]], 2
704+
; INTERLEAVE-NEXT: [[N_VEC:%.*]] = sub i32 [[K]], [[N_MOD_VF]]
705+
; INTERLEAVE-NEXT: br label %[[VECTOR_BODY:.*]]
706+
; INTERLEAVE: [[VECTOR_BODY]]:
707+
; INTERLEAVE-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
708+
; INTERLEAVE-NEXT: [[TMP0:%.*]] = add i32 [[INDEX]], 1
709+
; INTERLEAVE-NEXT: [[TMP1:%.*]] = add i32 [[TMP0]], 2
710+
; INTERLEAVE-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2
711+
; INTERLEAVE-NEXT: [[TMP2:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
712+
; INTERLEAVE-NEXT: br i1 [[TMP2]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], {{!llvm.loop ![0-9]+}}
713+
; INTERLEAVE: [[MIDDLE_BLOCK]]:
714+
; INTERLEAVE-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[K]], [[N_VEC]]
715+
; INTERLEAVE-NEXT: br i1 [[CMP_N]], label %[[FOR_END:.*]], label %[[SCALAR_PH]]
716+
; INTERLEAVE: [[SCALAR_PH]]:
717+
; INTERLEAVE-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
718+
; INTERLEAVE-NEXT: br label %[[FOR_BODY:.*]]
719+
; INTERLEAVE: [[FOR_BODY]]:
720+
; INTERLEAVE-NEXT: [[INC_PHI:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[INC:%.*]], %[[FOR_BODY]] ]
721+
; INTERLEAVE-NEXT: [[INC]] = add nsw i32 [[INC_PHI]], 1
722+
; INTERLEAVE-NEXT: [[INC_2:%.*]] = add i32 [[INC_PHI]], 2
723+
; INTERLEAVE-NEXT: [[CMP:%.*]] = icmp eq i32 [[INC]], [[K]]
724+
; INTERLEAVE-NEXT: br i1 [[CMP]], label %[[FOR_END]], label %[[FOR_BODY]], {{!llvm.loop ![0-9]+}}
725+
; INTERLEAVE: [[FOR_END]]:
726+
; INTERLEAVE-NEXT: [[INC_2_LCSSA:%.*]] = phi i32 [ [[INC_2]], %[[FOR_BODY]] ], [ [[TMP1]], %[[MIDDLE_BLOCK]] ]
727+
; INTERLEAVE-NEXT: ret i32 [[INC_2_LCSSA]]
728+
;
628729
entry:
629730
br label %for.body
630731

@@ -692,6 +793,56 @@ define float @fp_postinc_use_fadd(float %init, ptr noalias nocapture %A, i64 %N,
692793
; VEC-NEXT: [[ADD_LCSSA:%.*]] = phi float [ [[ADD]], %[[LOOP]] ], [ [[TMP1]], %[[MIDDLE_BLOCK]] ]
693794
; VEC-NEXT: ret float [[ADD_LCSSA]]
694795
;
796+
; INTERLEAVE-LABEL: define float @fp_postinc_use_fadd(
797+
; INTERLEAVE-SAME: float [[INIT:%.*]], ptr noalias nocapture [[A:%.*]], i64 [[N:%.*]], float [[FPINC:%.*]]) {
798+
; INTERLEAVE-NEXT: [[ENTRY:.*]]:
799+
; INTERLEAVE-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 2
800+
; INTERLEAVE-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
801+
; INTERLEAVE: [[VECTOR_PH]]:
802+
; INTERLEAVE-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 2
803+
; INTERLEAVE-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
804+
; INTERLEAVE-NEXT: [[DOTCAST:%.*]] = sitofp i64 [[N_VEC]] to float
805+
; INTERLEAVE-NEXT: [[TMP0:%.*]] = fmul fast float [[FPINC]], [[DOTCAST]]
806+
; INTERLEAVE-NEXT: [[TMP1:%.*]] = fadd fast float [[INIT]], [[TMP0]]
807+
; INTERLEAVE-NEXT: br label %[[VECTOR_BODY:.*]]
808+
; INTERLEAVE: [[VECTOR_BODY]]:
809+
; INTERLEAVE-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
810+
; INTERLEAVE-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 0
811+
; INTERLEAVE-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 1
812+
; INTERLEAVE-NEXT: [[DOTCAST1:%.*]] = sitofp i64 [[INDEX]] to float
813+
; INTERLEAVE-NEXT: [[TMP4:%.*]] = fmul fast float [[FPINC]], [[DOTCAST1]]
814+
; INTERLEAVE-NEXT: [[OFFSET_IDX:%.*]] = fadd fast float [[INIT]], [[TMP4]]
815+
; INTERLEAVE-NEXT: [[TMP5:%.*]] = fmul fast float 0.000000e+00, [[FPINC]]
816+
; INTERLEAVE-NEXT: [[TMP6:%.*]] = fadd fast float [[OFFSET_IDX]], [[TMP5]]
817+
; INTERLEAVE-NEXT: [[TMP7:%.*]] = fmul fast float 1.000000e+00, [[FPINC]]
818+
; INTERLEAVE-NEXT: [[TMP8:%.*]] = fadd fast float [[OFFSET_IDX]], [[TMP7]]
819+
; INTERLEAVE-NEXT: [[TMP9:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP2]]
820+
; INTERLEAVE-NEXT: [[TMP10:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP3]]
821+
; INTERLEAVE-NEXT: store float [[TMP6]], ptr [[TMP9]], align 4
822+
; INTERLEAVE-NEXT: store float [[TMP8]], ptr [[TMP10]], align 4
823+
; INTERLEAVE-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
824+
; INTERLEAVE-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
825+
; INTERLEAVE-NEXT: br i1 [[TMP11]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], {{!llvm.loop ![0-9]+}}
826+
; INTERLEAVE: [[MIDDLE_BLOCK]]:
827+
; INTERLEAVE-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
828+
; INTERLEAVE-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
829+
; INTERLEAVE: [[SCALAR_PH]]:
830+
; INTERLEAVE-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
831+
; INTERLEAVE-NEXT: [[BC_RESUME_VAL2:%.*]] = phi float [ [[TMP1]], %[[MIDDLE_BLOCK]] ], [ [[INIT]], %[[ENTRY]] ]
832+
; INTERLEAVE-NEXT: br label %[[LOOP:.*]]
833+
; INTERLEAVE: [[LOOP]]:
834+
; INTERLEAVE-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
835+
; INTERLEAVE-NEXT: [[FP_IV:%.*]] = phi float [ [[BC_RESUME_VAL2]], %[[SCALAR_PH]] ], [ [[ADD:%.*]], %[[LOOP]] ]
836+
; INTERLEAVE-NEXT: [[GEP_A:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[IV]]
837+
; INTERLEAVE-NEXT: store float [[FP_IV]], ptr [[GEP_A]], align 4
838+
; INTERLEAVE-NEXT: [[ADD]] = fadd fast float [[FP_IV]], [[FPINC]]
839+
; INTERLEAVE-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
840+
; INTERLEAVE-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
841+
; INTERLEAVE-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], {{!llvm.loop ![0-9]+}}
842+
; INTERLEAVE: [[EXIT]]:
843+
; INTERLEAVE-NEXT: [[ADD_LCSSA:%.*]] = phi float [ [[ADD]], %[[LOOP]] ], [ [[TMP1]], %[[MIDDLE_BLOCK]] ]
844+
; INTERLEAVE-NEXT: ret float [[ADD_LCSSA]]
845+
;
695846
entry:
696847
br label %loop
697848

@@ -762,6 +913,56 @@ define float @fp_postinc_use_fsub(float %init, ptr noalias nocapture %A, i64 %N,
762913
; VEC-NEXT: [[ADD_LCSSA:%.*]] = phi float [ [[ADD]], %[[LOOP]] ], [ [[TMP1]], %[[MIDDLE_BLOCK]] ]
763914
; VEC-NEXT: ret float [[ADD_LCSSA]]
764915
;
916+
; INTERLEAVE-LABEL: define float @fp_postinc_use_fsub(
917+
; INTERLEAVE-SAME: float [[INIT:%.*]], ptr noalias nocapture [[A:%.*]], i64 [[N:%.*]], float [[FPINC:%.*]]) {
918+
; INTERLEAVE-NEXT: [[ENTRY:.*]]:
919+
; INTERLEAVE-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 2
920+
; INTERLEAVE-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
921+
; INTERLEAVE: [[VECTOR_PH]]:
922+
; INTERLEAVE-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 2
923+
; INTERLEAVE-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
924+
; INTERLEAVE-NEXT: [[DOTCAST:%.*]] = sitofp i64 [[N_VEC]] to float
925+
; INTERLEAVE-NEXT: [[TMP0:%.*]] = fmul fast float [[FPINC]], [[DOTCAST]]
926+
; INTERLEAVE-NEXT: [[TMP1:%.*]] = fsub fast float [[INIT]], [[TMP0]]
927+
; INTERLEAVE-NEXT: br label %[[VECTOR_BODY:.*]]
928+
; INTERLEAVE: [[VECTOR_BODY]]:
929+
; INTERLEAVE-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
930+
; INTERLEAVE-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 0
931+
; INTERLEAVE-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 1
932+
; INTERLEAVE-NEXT: [[DOTCAST1:%.*]] = sitofp i64 [[INDEX]] to float
933+
; INTERLEAVE-NEXT: [[TMP4:%.*]] = fmul fast float [[FPINC]], [[DOTCAST1]]
934+
; INTERLEAVE-NEXT: [[OFFSET_IDX:%.*]] = fsub fast float [[INIT]], [[TMP4]]
935+
; INTERLEAVE-NEXT: [[TMP5:%.*]] = fmul fast float 0.000000e+00, [[FPINC]]
936+
; INTERLEAVE-NEXT: [[TMP6:%.*]] = fsub fast float [[OFFSET_IDX]], [[TMP5]]
937+
; INTERLEAVE-NEXT: [[TMP7:%.*]] = fmul fast float 1.000000e+00, [[FPINC]]
938+
; INTERLEAVE-NEXT: [[TMP8:%.*]] = fsub fast float [[OFFSET_IDX]], [[TMP7]]
939+
; INTERLEAVE-NEXT: [[TMP9:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP2]]
940+
; INTERLEAVE-NEXT: [[TMP10:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP3]]
941+
; INTERLEAVE-NEXT: store float [[TMP6]], ptr [[TMP9]], align 4
942+
; INTERLEAVE-NEXT: store float [[TMP8]], ptr [[TMP10]], align 4
943+
; INTERLEAVE-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
944+
; INTERLEAVE-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
945+
; INTERLEAVE-NEXT: br i1 [[TMP11]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], {{!llvm.loop ![0-9]+}}
946+
; INTERLEAVE: [[MIDDLE_BLOCK]]:
947+
; INTERLEAVE-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
948+
; INTERLEAVE-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
949+
; INTERLEAVE: [[SCALAR_PH]]:
950+
; INTERLEAVE-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
951+
; INTERLEAVE-NEXT: [[BC_RESUME_VAL2:%.*]] = phi float [ [[TMP1]], %[[MIDDLE_BLOCK]] ], [ [[INIT]], %[[ENTRY]] ]
952+
; INTERLEAVE-NEXT: br label %[[LOOP:.*]]
953+
; INTERLEAVE: [[LOOP]]:
954+
; INTERLEAVE-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
955+
; INTERLEAVE-NEXT: [[FP_IV:%.*]] = phi float [ [[BC_RESUME_VAL2]], %[[SCALAR_PH]] ], [ [[ADD:%.*]], %[[LOOP]] ]
956+
; INTERLEAVE-NEXT: [[GEP_A:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[IV]]
957+
; INTERLEAVE-NEXT: store float [[FP_IV]], ptr [[GEP_A]], align 4
958+
; INTERLEAVE-NEXT: [[ADD]] = fsub fast float [[FP_IV]], [[FPINC]]
959+
; INTERLEAVE-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
960+
; INTERLEAVE-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
961+
; INTERLEAVE-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], {{!llvm.loop ![0-9]+}}
962+
; INTERLEAVE: [[EXIT]]:
963+
; INTERLEAVE-NEXT: [[ADD_LCSSA:%.*]] = phi float [ [[ADD]], %[[LOOP]] ], [ [[TMP1]], %[[MIDDLE_BLOCK]] ]
964+
; INTERLEAVE-NEXT: ret float [[ADD_LCSSA]]
965+
;
765966
entry:
766967
br label %loop
767968

‎mlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOps.td

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -472,9 +472,6 @@ def TransposeOp : LinalgStructuredBase_Op<"transpose", [
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getRegionBuilder() {
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return regionBuilder;
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}
475-
476-
static void createRegion(::mlir::OpBuilder &opBuilder,
477-
::mlir::OperationState & odsState);
478475
}];
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480477
let hasFolder = 1;

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