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Merged main:40c2aaf54e9a7b5c560bb68796d444180ad67b5d into amd-gfx:86625b660a80
Local branch amd-gfx 86625b6 Merged main:b7730a23efb222944b732bbdb3a7b965b7bffd98 into amd-gfx:0616aed9b07e Remote branch main 40c2aaf [RISCV][sema] Correct the requirement of `vf[n|w]cvt.x[|u].f` intrinsics (llvm#101811)
2 parents 86625b6 + 40c2aaf commit 00d817b

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‎clang/include/clang/Basic/riscv_vector.td

Lines changed: 69 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1378,6 +1378,9 @@ let HasMasked = false,
13781378
let RequiredFeatures = ["Zvfhmin"] in
13791379
defm vmv_v : RVVOutBuiltinSet<"vmv_v_v", "x",
13801380
[["v", "v", "vv"]]>;
1381+
let RequiredFeatures = ["Zvfbfmin"] in
1382+
defm vmv_v : RVVOutBuiltinSet<"vmv_v_v", "y",
1383+
[["v", "v", "vv"]]>;
13811384
let SupportOverloading = false in
13821385
defm vmv_v : RVVOutBuiltinSet<"vmv_v_x", "csil",
13831386
[["x", "v", "ve"],
@@ -1890,6 +1893,9 @@ let HasMasked = false,
18901893
let RequiredFeatures = ["Zvfhmin"] in
18911894
defm vmerge : RVVOutOp1BuiltinSet<"vmerge", "x",
18921895
[["vvm", "v", "vvvm"]]>;
1896+
let RequiredFeatures = ["Zvfbfmin"] in
1897+
defm vmerge : RVVOutOp1BuiltinSet<"vmerge", "y",
1898+
[["vvm", "v", "vvvm"]]>;
18931899
defm vfmerge : RVVOutOp1BuiltinSet<"vfmerge", "xfd",
18941900
[["vfm", "v", "vvem"]]>;
18951901
}
@@ -1912,8 +1918,18 @@ def vfcvt_rtz_x_f_v : RVVConvToSignedBuiltin<"vfcvt_rtz_x">;
19121918
let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
19131919
def vfwcvt_rtz_xu_f_v : RVVConvToWidenUnsignedBuiltin<"vfwcvt_rtz_xu">;
19141920
def vfwcvt_rtz_x_f_v : RVVConvToWidenSignedBuiltin<"vfwcvt_rtz_x">;
1915-
def vfwcvt_f_xu_v : RVVConvBuiltin<"Fw", "FwUv", "csi", "vfwcvt_f">;
1916-
def vfwcvt_f_x_v : RVVConvBuiltin<"Fw", "Fwv", "csi", "vfwcvt_f">;
1921+
def vfwcvt_f_xu_v : RVVConvBuiltin<"Fw", "FwUv", "si", "vfwcvt_f">;
1922+
def vfwcvt_f_x_v : RVVConvBuiltin<"Fw", "Fwv", "si", "vfwcvt_f">;
1923+
let RequiredFeatures = ["Zvfh"] in {
1924+
let Name = "vfwcvt_f_xu_v",
1925+
IRName = "vfwcvt_f_xu_v",
1926+
MaskedIRName = "vfwcvt_f_xu_v_mask" in
1927+
def : RVVConvBuiltin<"Fw", "FwUv", "c", "vfwcvt_f">;
1928+
let Name = "vfwcvt_f_x_v",
1929+
IRName = "vfwcvt_f_x_v",
1930+
MaskedIRName = "vfwcvt_f_x_v_mask" in
1931+
def : RVVConvBuiltin<"Fw", "Fwv", "c", "vfwcvt_f">;
1932+
}
19171933
def vfwcvt_f_f_v : RVVConvBuiltin<"w", "wv", "f", "vfwcvt_f">;
19181934
let RequiredFeatures = ["Zvfhmin"] in
19191935
def vfwcvt_f_f_v_fp16 : RVVConvBuiltin<"w", "wv", "x", "vfwcvt_f"> {
@@ -1927,6 +1943,16 @@ let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
19271943
let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
19281944
def vfncvt_rtz_xu_f_w : RVVConvToNarrowingUnsignedBuiltin<"vfncvt_rtz_xu">;
19291945
def vfncvt_rtz_x_f_w : RVVConvToNarrowingSignedBuiltin<"vfncvt_rtz_x">;
1946+
let RequiredFeatures = ["Zvfh"] in {
1947+
let Name = "vfncvt_rtz_xu_f_w",
1948+
IRName = "vfncvt_rtz_xu_f_w",
1949+
MaskedIRName = "vfncvt_rtz_xu_f_w_mask" in
1950+
def : RVVConvBuiltin<"Uv", "UvFw", "c", "vfncvt_rtz_xu">;
1951+
let Name = "vfncvt_rtz_x_f_w",
1952+
IRName = "vfncvt_rtz_x_f_w",
1953+
MaskedIRName = "vfncvt_rtz_x_f_w_mask" in
1954+
def : RVVConvBuiltin<"Iv", "IvFw", "c", "vfncvt_rtz_x">;
1955+
}
19301956
def vfncvt_rod_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_rod_f">;
19311957
}
19321958

@@ -2005,10 +2031,18 @@ let ManualCodegen = [{
20052031
let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
20062032
let OverloadedName = "vfncvt_x" in
20072033
defm :
2008-
RVVConvBuiltinSet<"vfncvt_x_f_w", "csi", [["Iv", "IvFwu"]]>;
2034+
RVVConvBuiltinSet<"vfncvt_x_f_w", "si", [["Iv", "IvFwu"]]>;
20092035
let OverloadedName = "vfncvt_xu" in
20102036
defm :
2011-
RVVConvBuiltinSet<"vfncvt_xu_f_w", "csi", [["Uv", "UvFwu"]]>;
2037+
RVVConvBuiltinSet<"vfncvt_xu_f_w", "si", [["Uv", "UvFwu"]]>;
2038+
let RequiredFeatures = ["Zvfh"] in {
2039+
let OverloadedName = "vfncvt_x" in
2040+
defm :
2041+
RVVConvBuiltinSet<"vfncvt_x_f_w", "c", [["Iv", "IvFwu"]]>;
2042+
let OverloadedName = "vfncvt_xu" in
2043+
defm :
2044+
RVVConvBuiltinSet<"vfncvt_xu_f_w", "c", [["Uv", "UvFwu"]]>;
2045+
}
20122046
let OverloadedName = "vfncvt_f" in {
20132047
defm :
20142048
RVVConvBuiltinSet<"vfncvt_f_x_w", "xf", [["v", "vIwu"]]>;
@@ -2055,10 +2089,18 @@ let ManualCodegen = [{
20552089
let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
20562090
let OverloadedName = "vfncvt_x" in
20572091
defm :
2058-
RVVConvBuiltinSet<"vfncvt_x_f_w", "csi", [["Iv", "IvFw"]]>;
2092+
RVVConvBuiltinSet<"vfncvt_x_f_w", "si", [["Iv", "IvFw"]]>;
20592093
let OverloadedName = "vfncvt_xu" in
20602094
defm :
2061-
RVVConvBuiltinSet<"vfncvt_xu_f_w", "csi", [["Uv", "UvFw"]]>;
2095+
RVVConvBuiltinSet<"vfncvt_xu_f_w", "si", [["Uv", "UvFw"]]>;
2096+
let RequiredFeatures = ["Zvfh"] in {
2097+
let OverloadedName = "vfncvt_x" in
2098+
defm :
2099+
RVVConvBuiltinSet<"vfncvt_x_f_w", "c", [["Iv", "IvFw"]]>;
2100+
let OverloadedName = "vfncvt_xu" in
2101+
defm :
2102+
RVVConvBuiltinSet<"vfncvt_xu_f_w", "c", [["Uv", "UvFw"]]>;
2103+
}
20622104
let OverloadedName = "vfncvt_f" in {
20632105
defm :
20642106
RVVConvBuiltinSet<"vfncvt_f_x_w", "xf", [["v", "vIw"]]>;
@@ -2256,10 +2298,22 @@ defm vfslide1down : RVVFloatingBinVFBuiltinSet;
22562298

22572299
// 16.4. Vector Register Gather Instructions
22582300
// signed and floating type
2259-
defm vrgather : RVVOutBuiltinSet<"vrgather_vv", "csilxfd",
2301+
defm vrgather : RVVOutBuiltinSet<"vrgather_vv", "csilfd",
22602302
[["vv", "v", "vvUv"]]>;
2261-
defm vrgather : RVVOutBuiltinSet<"vrgather_vx", "csilxfd",
2303+
defm vrgather : RVVOutBuiltinSet<"vrgather_vx", "csilfd",
22622304
[["vx", "v", "vvz"]]>;
2305+
let RequiredFeatures = ["Zvfhmin"] in {
2306+
defm vrgather : RVVOutBuiltinSet<"vrgather_vv", "x",
2307+
[["vv", "v", "vvUv"]]>;
2308+
defm vrgather : RVVOutBuiltinSet<"vrgather_vx", "x",
2309+
[["vx", "v", "vvz"]]>;
2310+
}
2311+
let RequiredFeatures = ["Zvfbfmin"] in {
2312+
defm vrgather : RVVOutBuiltinSet<"vrgather_vv", "y",
2313+
[["vv", "v", "vvUv"]]>;
2314+
defm vrgather : RVVOutBuiltinSet<"vrgather_vx", "y",
2315+
[["vx", "v", "vvz"]]>;
2316+
}
22632317
defm vrgatherei16 : RVVOutBuiltinSet<"vrgatherei16_vv", "csilxfd",
22642318
[["vv", "v", "vv(Log2EEW:4)Uv"]]>;
22652319
// unsigned type
@@ -2282,8 +2336,14 @@ let HasMasked = false,
22822336
IntrinsicTypes = {ResultType, Ops.back()->getType()};
22832337
}] in {
22842338
// signed and floating type
2285-
defm vcompress : RVVOutBuiltinSet<"vcompress", "csilxfd",
2339+
defm vcompress : RVVOutBuiltinSet<"vcompress", "csilfd",
22862340
[["vm", "v", "vvm"]]>;
2341+
let RequiredFeatures = ["Zvfhmin"] in
2342+
defm vcompress : RVVOutBuiltinSet<"vcompress", "x",
2343+
[["vm", "v", "vvm"]]>;
2344+
let RequiredFeatures = ["Zvfbfmin"] in
2345+
defm vcompress : RVVOutBuiltinSet<"vcompress", "y",
2346+
[["vm", "v", "vvm"]]>;
22872347
// unsigned type
22882348
defm vcompress : RVVOutBuiltinSet<"vcompress", "csil",
22892349
[["vm", "Uv", "UvUvm"]]>;

‎clang/include/clang/Basic/riscv_vector_common.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -604,10 +604,10 @@ class RVVConvToWidenUnsignedBuiltin<string overloaded_name>
604604
: RVVConvBuiltin<"Uw", "Uwv", "xf", overloaded_name>;
605605

606606
class RVVConvToNarrowingSignedBuiltin<string overloaded_name>
607-
: RVVConvBuiltin<"Iv", "IvFw", "csi", overloaded_name>;
607+
: RVVConvBuiltin<"Iv", "IvFw", "si", overloaded_name>;
608608

609609
class RVVConvToNarrowingUnsignedBuiltin<string overloaded_name>
610-
: RVVConvBuiltin<"Uv", "UvFw", "csi", overloaded_name>;
610+
: RVVConvBuiltin<"Uv", "UvFw", "si", overloaded_name>;
611611

612612
let HasMaskedOffOperand = true in {
613613
multiclass RVVSignedReductionBuiltin {

‎clang/include/clang/Support/RISCVVIntrinsicUtils.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -502,7 +502,8 @@ enum RVVRequire : uint32_t {
502502
RVV_REQ_Zvksh = 1 << 15,
503503
RVV_REQ_Zvfbfwma = 1 << 16,
504504
RVV_REQ_Zvfbfmin = 1 << 17,
505-
RVV_REQ_Experimental = 1 << 18,
505+
RVV_REQ_Zvfh = 1 << 18,
506+
RVV_REQ_Experimental = 1 << 19,
506507

507508
LLVM_MARK_AS_BITMASK_ENUM(RVV_REQ_Experimental)
508509
};

‎clang/lib/Sema/SemaRISCV.cpp

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -222,6 +222,7 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(
222222
{"zvksh", RVV_REQ_Zvksh},
223223
{"zvfbfwma", RVV_REQ_Zvfbfwma},
224224
{"zvfbfmin", RVV_REQ_Zvfbfmin},
225+
{"zvfh", RVV_REQ_Zvfh},
225226
{"experimental", RVV_REQ_Experimental}};
226227

227228
// Construction of RVVIntrinsicRecords need to sync with createRVVIntrinsics
@@ -280,6 +281,11 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(
280281
if ((BaseTypeI & Record.TypeRangeMask) != BaseTypeI)
281282
continue;
282283

284+
// TODO: Remove the check below and use RequiredFeatures in
285+
// riscv_vector.td to check the intrinsics instead, the type check should
286+
// be done in checkRVVTypeSupport. This check also not able to work on the
287+
// intrinsics that have Float16 but the BaseType is not Float16 such as
288+
// `vfcvt_f_x_v`.
283289
if (BaseType == BasicType::Float16) {
284290
if ((Record.RequiredExtensions & RVV_REQ_Zvfhmin) == RVV_REQ_Zvfhmin) {
285291
if (!TI.hasFeature("zvfhmin"))

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c

Lines changed: 61 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +zvfh -disable-O0-optnone \
4+
// RUN: -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

@@ -597,3 +597,63 @@ vuint64m8_t test_vcompress_vm_u64m8(vuint64m8_t src, vbool8_t mask, size_t vl) {
597597
return __riscv_vcompress_vm_u64m8(src, mask, vl);
598598
}
599599

600+
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vcompress_vm_bf16mf4
601+
// CHECK-RV64-SAME: (<vscale x 1 x bfloat> [[SRC:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
602+
// CHECK-RV64-NEXT: entry:
603+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vcompress.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
604+
// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]
605+
//
606+
vbfloat16mf4_t test_vcompress_vm_bf16mf4(vbfloat16mf4_t src, vbool64_t mask, size_t vl) {
607+
return __riscv_vcompress_vm_bf16mf4(src, mask, vl);
608+
}
609+
610+
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vcompress_vm_bf16mf2
611+
// CHECK-RV64-SAME: (<vscale x 2 x bfloat> [[SRC:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
612+
// CHECK-RV64-NEXT: entry:
613+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vcompress.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
614+
// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]
615+
//
616+
vbfloat16mf2_t test_vcompress_vm_bf16mf2(vbfloat16mf2_t src, vbool32_t mask, size_t vl) {
617+
return __riscv_vcompress_vm_bf16mf2(src, mask, vl);
618+
}
619+
620+
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vcompress_vm_bf16m1
621+
// CHECK-RV64-SAME: (<vscale x 4 x bfloat> [[SRC:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
622+
// CHECK-RV64-NEXT: entry:
623+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vcompress.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
624+
// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]
625+
//
626+
vbfloat16m1_t test_vcompress_vm_bf16m1(vbfloat16m1_t src, vbool16_t mask, size_t vl) {
627+
return __riscv_vcompress_vm_bf16m1(src, mask, vl);
628+
}
629+
630+
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vcompress_vm_bf16m2
631+
// CHECK-RV64-SAME: (<vscale x 8 x bfloat> [[SRC:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
632+
// CHECK-RV64-NEXT: entry:
633+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vcompress.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
634+
// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
635+
//
636+
vbfloat16m2_t test_vcompress_vm_bf16m2(vbfloat16m2_t src, vbool8_t mask, size_t vl) {
637+
return __riscv_vcompress_vm_bf16m2(src, mask, vl);
638+
}
639+
640+
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vcompress_vm_bf16m4
641+
// CHECK-RV64-SAME: (<vscale x 16 x bfloat> [[SRC:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
642+
// CHECK-RV64-NEXT: entry:
643+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vcompress.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
644+
// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]
645+
//
646+
vbfloat16m4_t test_vcompress_vm_bf16m4(vbfloat16m4_t src, vbool4_t mask, size_t vl) {
647+
return __riscv_vcompress_vm_bf16m4(src, mask, vl);
648+
}
649+
650+
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x bfloat> @test_vcompress_vm_bf16m8
651+
// CHECK-RV64-SAME: (<vscale x 32 x bfloat> [[SRC:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
652+
// CHECK-RV64-NEXT: entry:
653+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.riscv.vcompress.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> [[SRC]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])
654+
// CHECK-RV64-NEXT: ret <vscale x 32 x bfloat> [[TMP0]]
655+
//
656+
vbfloat16m8_t test_vcompress_vm_bf16m8(vbfloat16m8_t src, vbool2_t mask, size_t vl) {
657+
return __riscv_vcompress_vm_bf16m8(src, mask, vl);
658+
}
659+

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c

Lines changed: 60 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +zvfhmin -disable-O0-optnone \
4+
// RUN: -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

@@ -1037,3 +1037,62 @@ vfloat64m8_t test_vmerge_vvm_f64m8(vfloat64m8_t op1, vfloat64m8_t op2, vbool8_t
10371037
return __riscv_vmerge_vvm_f64m8(op1, op2, mask, vl);
10381038
}
10391039

1040+
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vmerge_vvm_bf16mf4
1041+
// CHECK-RV64-SAME: (<vscale x 1 x bfloat> [[OP1:%.*]], <vscale x 1 x bfloat> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1042+
// CHECK-RV64-NEXT: entry:
1043+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vmerge.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> [[OP1]], <vscale x 1 x bfloat> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
1044+
// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]
1045+
//
1046+
vbfloat16mf4_t test_vmerge_vvm_bf16mf4(vbfloat16mf4_t op1, vbfloat16mf4_t op2, vbool64_t mask, size_t vl) {
1047+
return __riscv_vmerge_vvm_bf16mf4(op1, op2, mask, vl);
1048+
}
1049+
1050+
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vmerge_vvm_bf16mf2
1051+
// CHECK-RV64-SAME: (<vscale x 2 x bfloat> [[OP1:%.*]], <vscale x 2 x bfloat> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1052+
// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vmerge.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> [[OP1]], <vscale x 2 x bfloat> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
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// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]
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//
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vbfloat16mf2_t test_vmerge_vvm_bf16mf2(vbfloat16mf2_t op1, vbfloat16mf2_t op2, vbool32_t mask, size_t vl) {
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return __riscv_vmerge_vvm_bf16mf2(op1, op2, mask, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vmerge_vvm_bf16m1
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// CHECK-RV64-SAME: (<vscale x 4 x bfloat> [[OP1:%.*]], <vscale x 4 x bfloat> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vmerge.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> [[OP1]], <vscale x 4 x bfloat> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
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// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]
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//
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vbfloat16m1_t test_vmerge_vvm_bf16m1(vbfloat16m1_t op1, vbfloat16m1_t op2, vbool16_t mask, size_t vl) {
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return __riscv_vmerge_vvm_bf16m1(op1, op2, mask, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vmerge_vvm_bf16m2
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// CHECK-RV64-SAME: (<vscale x 8 x bfloat> [[OP1:%.*]], <vscale x 8 x bfloat> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vmerge.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> [[OP1]], <vscale x 8 x bfloat> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
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// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
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//
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vbfloat16m2_t test_vmerge_vvm_bf16m2(vbfloat16m2_t op1, vbfloat16m2_t op2, vbool8_t mask, size_t vl) {
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return __riscv_vmerge_vvm_bf16m2(op1, op2, mask, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vmerge_vvm_bf16m4
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// CHECK-RV64-SAME: (<vscale x 16 x bfloat> [[OP1:%.*]], <vscale x 16 x bfloat> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vmerge.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> [[OP1]], <vscale x 16 x bfloat> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
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// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]
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//
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vbfloat16m4_t test_vmerge_vvm_bf16m4(vbfloat16m4_t op1, vbfloat16m4_t op2, vbool4_t mask, size_t vl) {
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return __riscv_vmerge_vvm_bf16m4(op1, op2, mask, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 32 x bfloat> @test_vmerge_vvm_bf16m8
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// CHECK-RV64-SAME: (<vscale x 32 x bfloat> [[OP1:%.*]], <vscale x 32 x bfloat> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.riscv.vmerge.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> [[OP1]], <vscale x 32 x bfloat> [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])
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// CHECK-RV64-NEXT: ret <vscale x 32 x bfloat> [[TMP0]]
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//
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vbfloat16m8_t test_vmerge_vvm_bf16m8(vbfloat16m8_t op1, vbfloat16m8_t op2, vbool2_t mask, size_t vl) {
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return __riscv_vmerge_vvm_bf16m8(op1, op2, mask, vl);
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}

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