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Update testcase after llvm#92860 land
1 parent e8e051e commit f2a60bd

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4 files changed

+20
-43
lines changed

4 files changed

+20
-43
lines changed

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -39,9 +39,8 @@ define <4 x float> @hang_when_merging_stores_after_legalization(<8 x float> %x,
3939
; CHECK-NEXT: vmul.vx v14, v12, a0
4040
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
4141
; CHECK-NEXT: vrgatherei16.vv v12, v8, v14
42-
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
43-
; CHECK-NEXT: vmv.v.i v0, 12
4442
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
43+
; CHECK-NEXT: vmv.v.i v0, 12
4544
; CHECK-NEXT: vadd.vi v8, v14, -14
4645
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
4746
; CHECK-NEXT: vrgatherei16.vv v12, v10, v8, v0.t

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -140,9 +140,8 @@ define <4 x i1> @buildvec_mask_v4i1() {
140140
define <4 x i1> @buildvec_mask_nonconst_v4i1(i1 %x, i1 %y) {
141141
; CHECK-LABEL: buildvec_mask_nonconst_v4i1:
142142
; CHECK: # %bb.0:
143-
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
144-
; CHECK-NEXT: vmv.v.i v0, 3
145143
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
144+
; CHECK-NEXT: vmv.v.i v0, 3
146145
; CHECK-NEXT: vmv.v.x v8, a1
147146
; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
148147
; CHECK-NEXT: vand.vi v8, v8, 1
@@ -151,9 +150,8 @@ define <4 x i1> @buildvec_mask_nonconst_v4i1(i1 %x, i1 %y) {
151150
;
152151
; ZVE32F-LABEL: buildvec_mask_nonconst_v4i1:
153152
; ZVE32F: # %bb.0:
154-
; ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
155-
; ZVE32F-NEXT: vmv.v.i v0, 3
156153
; ZVE32F-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
154+
; ZVE32F-NEXT: vmv.v.i v0, 3
157155
; ZVE32F-NEXT: vmv.v.x v8, a1
158156
; ZVE32F-NEXT: vmerge.vxm v8, v8, a0, v0
159157
; ZVE32F-NEXT: vand.vi v8, v8, 1

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll

Lines changed: 9 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -12623,16 +12623,15 @@ define <4 x i32> @mgather_unit_stride_load_wide_idx(ptr %base) {
1262312623

1262412624
; This looks like a strided load (at i8), but isn't at index type.
1262512625
define <4 x i32> @mgather_narrow_edge_case(ptr %base) {
12626-
; RV32V-LABEL: mgather_narrow_edge_case:
12627-
; RV32V: # %bb.0:
12628-
; RV32V-NEXT: li a1, -512
12629-
; RV32V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
12630-
; RV32V-NEXT: vmv.v.i v0, 5
12631-
; RV32V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
12632-
; RV32V-NEXT: vmv.v.x v8, a1
12633-
; RV32V-NEXT: vmerge.vim v8, v8, 0, v0
12634-
; RV32V-NEXT: vluxei32.v v8, (a0), v8
12635-
; RV32V-NEXT: ret
12626+
; RV32-LABEL: mgather_narrow_edge_case:
12627+
; RV32: # %bb.0:
12628+
; RV32-NEXT: li a1, -512
12629+
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
12630+
; RV32-NEXT: vmv.v.i v0, 5
12631+
; RV32-NEXT: vmv.v.x v8, a1
12632+
; RV32-NEXT: vmerge.vim v8, v8, 0, v0
12633+
; RV32-NEXT: vluxei32.v v8, (a0), v8
12634+
; RV32-NEXT: ret
1263612635
;
1263712636
; RV64V-LABEL: mgather_narrow_edge_case:
1263812637
; RV64V: # %bb.0:
@@ -12646,17 +12645,6 @@ define <4 x i32> @mgather_narrow_edge_case(ptr %base) {
1264612645
; RV64V-NEXT: vluxei64.v v8, (a0), v10
1264712646
; RV64V-NEXT: ret
1264812647
;
12649-
; RV32ZVE32F-LABEL: mgather_narrow_edge_case:
12650-
; RV32ZVE32F: # %bb.0:
12651-
; RV32ZVE32F-NEXT: li a1, -512
12652-
; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
12653-
; RV32ZVE32F-NEXT: vmv.v.i v0, 5
12654-
; RV32ZVE32F-NEXT: vsetivli zero, 4, e32, m1, ta, ma
12655-
; RV32ZVE32F-NEXT: vmv.v.x v8, a1
12656-
; RV32ZVE32F-NEXT: vmerge.vim v8, v8, 0, v0
12657-
; RV32ZVE32F-NEXT: vluxei32.v v8, (a0), v8
12658-
; RV32ZVE32F-NEXT: ret
12659-
;
1266012648
; RV64ZVE32F-LABEL: mgather_narrow_edge_case:
1266112649
; RV64ZVE32F: # %bb.0:
1266212650
; RV64ZVE32F-NEXT: addi a1, a0, -512

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-transpose.ll

Lines changed: 8 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -72,9 +72,8 @@ define <4 x i16> @trn1.v4i16(<4 x i16> %v0, <4 x i16> %v1) {
7272
define <4 x i16> @trn2.v4i16(<4 x i16> %v0, <4 x i16> %v1) {
7373
; CHECK-LABEL: trn2.v4i16:
7474
; CHECK: # %bb.0:
75-
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
76-
; CHECK-NEXT: vmv.v.i v0, 10
7775
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
76+
; CHECK-NEXT: vmv.v.i v0, 10
7877
; CHECK-NEXT: vslidedown.vi v8, v8, 1
7978
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
8079
; CHECK-NEXT: ret
@@ -120,9 +119,8 @@ define <2 x i32> @trn1.v2i32(<2 x i32> %v0, <2 x i32> %v1) {
120119
define <2 x i32> @trn2.v2i32(<2 x i32> %v0, <2 x i32> %v1) {
121120
; CHECK-LABEL: trn2.v2i32:
122121
; CHECK: # %bb.0:
123-
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
124-
; CHECK-NEXT: vmv.v.i v0, 2
125122
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
123+
; CHECK-NEXT: vmv.v.i v0, 2
126124
; CHECK-NEXT: vrgather.vi v10, v8, 1
127125
; CHECK-NEXT: vmerge.vvm v8, v10, v9, v0
128126
; CHECK-NEXT: ret
@@ -144,9 +142,8 @@ define <4 x i32> @trn1.v4i32(<4 x i32> %v0, <4 x i32> %v1) {
144142
define <4 x i32> @trn2.v4i32(<4 x i32> %v0, <4 x i32> %v1) {
145143
; CHECK-LABEL: trn2.v4i32:
146144
; CHECK: # %bb.0:
147-
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
148-
; CHECK-NEXT: vmv.v.i v0, 10
149145
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
146+
; CHECK-NEXT: vmv.v.i v0, 10
150147
; CHECK-NEXT: vslidedown.vi v8, v8, 1
151148
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
152149
; CHECK-NEXT: ret
@@ -167,9 +164,8 @@ define <2 x i64> @trn1.v2i64(<2 x i64> %v0, <2 x i64> %v1) {
167164
define <2 x i64> @trn2.v2i64(<2 x i64> %v0, <2 x i64> %v1) {
168165
; CHECK-LABEL: trn2.v2i64:
169166
; CHECK: # %bb.0:
170-
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
171-
; CHECK-NEXT: vmv.v.i v0, 2
172167
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
168+
; CHECK-NEXT: vmv.v.i v0, 2
173169
; CHECK-NEXT: vrgather.vi v10, v8, 1
174170
; CHECK-NEXT: vmerge.vvm v8, v10, v9, v0
175171
; CHECK-NEXT: ret
@@ -190,9 +186,8 @@ define <2 x float> @trn1.v2f32(<2 x float> %v0, <2 x float> %v1) {
190186
define <2 x float> @trn2.v2f32(<2 x float> %v0, <2 x float> %v1) {
191187
; CHECK-LABEL: trn2.v2f32:
192188
; CHECK: # %bb.0:
193-
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
194-
; CHECK-NEXT: vmv.v.i v0, 2
195189
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
190+
; CHECK-NEXT: vmv.v.i v0, 2
196191
; CHECK-NEXT: vrgather.vi v10, v8, 1
197192
; CHECK-NEXT: vmerge.vvm v8, v10, v9, v0
198193
; CHECK-NEXT: ret
@@ -214,9 +209,8 @@ define <4 x float> @trn1.v4f32(<4 x float> %v0, <4 x float> %v1) {
214209
define <4 x float> @trn2.v4f32(<4 x float> %v0, <4 x float> %v1) {
215210
; CHECK-LABEL: trn2.v4f32:
216211
; CHECK: # %bb.0:
217-
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
218-
; CHECK-NEXT: vmv.v.i v0, 10
219212
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
213+
; CHECK-NEXT: vmv.v.i v0, 10
220214
; CHECK-NEXT: vslidedown.vi v8, v8, 1
221215
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
222216
; CHECK-NEXT: ret
@@ -237,9 +231,8 @@ define <2 x double> @trn1.v2f64(<2 x double> %v0, <2 x double> %v1) {
237231
define <2 x double> @trn2.v2f64(<2 x double> %v0, <2 x double> %v1) {
238232
; CHECK-LABEL: trn2.v2f64:
239233
; CHECK: # %bb.0:
240-
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
241-
; CHECK-NEXT: vmv.v.i v0, 2
242234
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
235+
; CHECK-NEXT: vmv.v.i v0, 2
243236
; CHECK-NEXT: vrgather.vi v10, v8, 1
244237
; CHECK-NEXT: vmerge.vvm v8, v10, v9, v0
245238
; CHECK-NEXT: ret
@@ -261,9 +254,8 @@ define <4 x half> @trn1.v4f16(<4 x half> %v0, <4 x half> %v1) {
261254
define <4 x half> @trn2.v4f16(<4 x half> %v0, <4 x half> %v1) {
262255
; CHECK-LABEL: trn2.v4f16:
263256
; CHECK: # %bb.0:
264-
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
265-
; CHECK-NEXT: vmv.v.i v0, 10
266257
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
258+
; CHECK-NEXT: vmv.v.i v0, 10
267259
; CHECK-NEXT: vslidedown.vi v8, v8, 1
268260
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
269261
; CHECK-NEXT: ret

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