diff --git a/arch/ARM/Nordic/devices/nrf51-device.ads b/arch/ARM/Nordic/devices/nrf51/nrf-device.ads similarity index 75% rename from arch/ARM/Nordic/devices/nrf51-device.ads rename to arch/ARM/Nordic/devices/nrf51/nrf-device.ads index a7c8c712d..95e71b877 100644 --- a/arch/ARM/Nordic/devices/nrf51-device.ads +++ b/arch/ARM/Nordic/devices/nrf51/nrf-device.ads @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2016, AdaCore -- +-- Copyright (C) 2016-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -29,19 +29,19 @@ -- -- ------------------------------------------------------------------------------ -with nRF51.GPIO; use nRF51.GPIO; -with nRF51.RTC; use nRF51.RTC; -with NRF51_SVD.RTC; -with nRF51.TWI; use nRF51.TWI; -with NRF51_SVD.TWI; -with nRF51.SPI_Master; use nRF51.SPI_Master; -with NRF51_SVD.SPI; -with nRF51.Timers; use nRF51.Timers; -with NRF51_SVD.TIMER; -with nRF51.UART; use nRF51.UART; -with NRF51_SVD.UART; +with nRF.GPIO; use nRF.GPIO; +with nRF.RTC; use nRF.RTC; +with NRF_SVD.RTC; +with nRF.TWI; use nRF.TWI; +with NRF_SVD.TWI; +with nRF.SPI_Master; use nRF.SPI_Master; +with NRF_SVD.SPI; +with nRF.Timers; use nRF.Timers; +with NRF_SVD.TIMER; +with nRF.UART; use nRF.UART; +with NRF_SVD.UART; -package nRF51.Device is +package nRF.Device is P00 : aliased GPIO_Point := (Pin => 00); P01 : aliased GPIO_Point := (Pin => 01); @@ -76,27 +76,27 @@ package nRF51.Device is P30 : aliased GPIO_Point := (Pin => 30); P31 : aliased GPIO_Point := (Pin => 31); - RTC_0 : aliased Real_Time_Counter (NRF51_SVD.RTC.RTC0_Periph'Access); - RTC_1 : aliased Real_Time_Counter (NRF51_SVD.RTC.RTC1_Periph'Access); + RTC_0 : aliased Real_Time_Counter (NRF_SVD.RTC.RTC0_Periph'Access); + RTC_1 : aliased Real_Time_Counter (NRF_SVD.RTC.RTC1_Periph'Access); -- Be carefull of shared resources between the TWI and SPI controllers. -- TWI_O and SPI_Master_0 cannot be used at the same time. -- TWI_1 and SPI_Master_1 cannot be used at the same time. -- - -- See nRF51 Series Reference Manual, chapter Memory.Instantiation. + -- See nRF Series Reference Manual, chapter Memory.Instantiation. - TWI_0 : aliased TWI_Master (NRF51_SVD.TWI.TWI0_Periph'Access); - TWI_1 : aliased TWI_Master (NRF51_SVD.TWI.TWI1_Periph'Access); + TWI_0 : aliased TWI_Master (NRF_SVD.TWI.TWI0_Periph'Access); + TWI_1 : aliased TWI_Master (NRF_SVD.TWI.TWI1_Periph'Access); - SPI_Master_0 : aliased nRF51.SPI_Master.SPI_Master (NRF51_SVD.SPI.SPI0_Periph'Access); - SPI_Master_1 : aliased nRF51.SPI_Master.SPI_Master (NRF51_SVD.SPI.SPI1_Periph'Access); + SPI_Master_0 : aliased nRF.SPI_Master.SPI_Master (NRF_SVD.SPI.SPI0_Periph'Access); + SPI_Master_1 : aliased nRF.SPI_Master.SPI_Master (NRF_SVD.SPI.SPI1_Periph'Access); - Timer_0 : aliased Timer (NRF51_SVD.TIMER.TIMER0_Periph'Access); - Timer_1 : aliased Timer (NRF51_SVD.TIMER.TIMER1_Periph'Access); - Timer_2 : aliased Timer (NRF51_SVD.TIMER.TIMER2_Periph'Access); + Timer_0 : aliased Timer (NRF_SVD.TIMER.TIMER0_Periph'Access); + Timer_1 : aliased Timer (NRF_SVD.TIMER.TIMER1_Periph'Access); + Timer_2 : aliased Timer (NRF_SVD.TIMER.TIMER2_Periph'Access); - UART_0 : aliased UART_Device (NRF51_SVD.UART.UART0_Periph'Access); -end nRF51.Device; + UART_0 : aliased UART_Device (NRF_SVD.UART.UART0_Periph'Access); +end nRF.Device; diff --git a/arch/ARM/Nordic/devices/nrf52/nrf-device.adb b/arch/ARM/Nordic/devices/nrf52/nrf-device.adb new file mode 100644 index 000000000..8734ed124 --- /dev/null +++ b/arch/ARM/Nordic/devices/nrf52/nrf-device.adb @@ -0,0 +1,307 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright (C) 2020, AdaCore -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of the copyright holder nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +------------------------------------------------------------------------------ + +with System; +with HAL; use HAL; + +with Cortex_M_SVD.Debug; use Cortex_M_SVD.Debug; +with NRF_SVD.CLOCK; use NRF_SVD.CLOCK; +with NRF_SVD.FICR; use NRF_SVD.FICR; +with NRF_SVD.POWER; use NRF_SVD.POWER; +with NRF_SVD.TEMP; use NRF_SVD.TEMP; + +package body nRF.Device is + + Undocumented_Reg_FE0 : UInt32 + with Address => System'To_Address (16#F0000FE0#); + Undocumented_Reg_FE4 : UInt32 + with Address => System'To_Address (16#F0000FE4#); + Undocumented_Reg_FE8 : UInt32 + with Address => System'To_Address (16#F0000FE8#); + FE0_Is_Six : constant Boolean := (Undocumented_Reg_FE0 and 16#FF#) = 6; + FE4_Is_Zero : constant Boolean := (Undocumented_Reg_FE0 and 16#0F#) = 0; + + function Errata_12 return Boolean; + function Errata_16 return Boolean; + function Errata_31 return Boolean; + function Errata_32 return Boolean; + function Errata_36 return Boolean; + function Errata_37 return Boolean; + function Errata_57 return Boolean; + function Errata_66 return Boolean; + function Errata_136 return Boolean; + function Errata_182 return Boolean; + function Errata_108 return Boolean; + + --------------- + -- Errata_12 -- + --------------- + + function Errata_12 return Boolean is + begin + if FE0_Is_Six and FE4_Is_Zero then + case Undocumented_Reg_FE8 and 16#F0# is + when 16#30# => return True; + when 16#40# => return True; + when 16#50# => return True; + when others => return False; + end case; + end if; + return False; + end Errata_12; + + E12_Undocumented_COMP_Reg_540 : UInt32 + with Address => System'To_Address (16#40013540#); + E12_Undocumented_FICR_Reg_324 : UInt32 + with Address => System'To_Address (16#10000324#); + + --------------- + -- Errata_16 -- + --------------- + + function Errata_16 return Boolean is + begin + if FE0_Is_Six and FE4_Is_Zero and Undocumented_Reg_FE8 = 16#30# then + return True; + end if; + return False; + end Errata_16; + + E16_Undocumented_Reg_074 : UInt32 + with Address => System'To_Address (16#4007C074#); + + --------------- + -- Errata_31 -- + --------------- + + function Errata_31 return Boolean is + begin + return Errata_12; + end Errata_31; + + E31_Undocumented_CLOCK_Reg_53C : UInt32 with + Address => System'To_Address (16#4000053C#); + E31_Undocumented_FICR_Reg_244 : UInt32 with + Address => System'To_Address (16#10000244#); + + --------------- + -- Errata_32 -- + --------------- + + function Errata_32 return Boolean is + begin + return Errata_16; + end Errata_32; + + --------------- + -- Errata_36 -- + --------------- + + function Errata_36 return Boolean is + begin + return Errata_12; + end Errata_36; + + --------------- + -- Errata_37 -- + --------------- + + function Errata_37 return Boolean is + begin + return Errata_16; + end Errata_37; + + E37_Undocumented_Reg_5A0 : UInt32 with + Address => System'To_Address (16#400005A0#); + + --------------- + -- Errata_57 -- + --------------- + + function Errata_57 return Boolean is + begin + return Errata_16; + end Errata_57; + + E57_Undocumented_NFCT_Reg_610 : UInt32 with + Address => System'To_Address (16#40005610#); + E57_Undocumented_NFCT_Reg_614 : UInt32 with + Address => System'To_Address (16#40005614#); + E57_Undocumented_NFCT_Reg_618 : UInt32 with + Address => System'To_Address (16#40005618#); + E57_Undocumented_NFCT_Reg_688 : UInt32 with + Address => System'To_Address (16#40005688#); + + --------------- + -- Errata_66 -- + --------------- + + function Errata_66 return Boolean is + begin + if FE0_Is_Six and FE4_Is_Zero and Undocumented_Reg_FE8 = 16#50# then + return True; + end if; + return False; + end Errata_66; + + ---------------- + -- Errata_108 -- + ---------------- + + function Errata_108 return Boolean is + begin + return Errata_12; + end Errata_108; + + E108_Undocumented_Reg_EE4 : UInt32 with + Address => System'To_Address (16#40000EE4#); + E108_Undocumented_FICR_Reg_258 : UInt32 with + Address => System'To_Address (16#10000258#); + + ---------------- + -- Errata_136 -- + ---------------- + + function Errata_136 return Boolean is + begin + return Errata_12; + end Errata_136; + + ---------------- + -- Errata_182 -- + ---------------- + + function Errata_182 return Boolean is + Undocumented_FICR_Reg_130 : UInt32 + with Address => System'To_Address (16#10000130#); + Undocumented_FICR_Reg_134 : UInt32 + with Address => System'To_Address (16#10000130#); + begin + return Undocumented_FICR_Reg_130 = 6 and Undocumented_FICR_Reg_134 = 6; + end Errata_182; + + E182_Undocumented_Reg_73C : UInt32 with + Address => System'To_Address (16#4000173C#); + +begin + if Errata_12 then + -- Workaround for Errata 12 "COMP: Reference ladder not correctly + -- calibrated" + E12_Undocumented_COMP_Reg_540 := + Shift_Right (E12_Undocumented_FICR_Reg_324 and 16#1F00#, 8); + end if; + + if Errata_16 then + -- Workaround for Errata 16 "System: RAM may be corrupt on wakeup from CPU + -- IDLE" + E16_Undocumented_Reg_074 := 3131961357; + end if; + + if Errata_31 then + -- Workaround for Errata 31 "CLOCK: Calibration values are not correctly + -- loaded from FICR at reset" + E31_Undocumented_CLOCK_Reg_53C := + Shift_Right (E31_Undocumented_FICR_Reg_244 and 16#E000#, 13); + end if; + + if Errata_32 then + -- Workaround for Errata 32 "DIF: Debug session automatically enables + -- TracePort pins" + Debug_Periph.DEMCR.TRCENA := False; + end if; + + if Errata_36 then + -- Workaround for Errata 36 "CLOCK: Some registers are not reset when + -- expected" + CLOCK_Periph.EVENTS_DONE := 0; + CLOCK_Periph.EVENTS_CTTO := 0; + CLOCK_Periph.CTIV.CTIV := 0; + end if; + + if Errata_37 then + -- Workaround for Errata 37 "RADIO: Encryption engine is slow by default" + E37_Undocumented_Reg_5A0 := 3; + end if; + + if Errata_57 then + -- Workaround for Errata 57 "NFCT: NFC Modulation amplitude" + E57_Undocumented_NFCT_Reg_610 := 5; + E57_Undocumented_NFCT_Reg_688 := 1; + E57_Undocumented_NFCT_Reg_618 := 0; + E57_Undocumented_NFCT_Reg_614 := 16#3F#; + end if; + + if Errata_66 then + -- Workaround for Errata 66 "TEMP: Linearity specification not met with + -- default settings" + TEMP_Periph.A0.A0 := FICR_Periph.TEMP.A0.A; + TEMP_Periph.A1.A1 := FICR_Periph.TEMP.A1.A; + TEMP_Periph.A2.A2 := FICR_Periph.TEMP.A2.A; + TEMP_Periph.A3.A3 := FICR_Periph.TEMP.A3.A; + TEMP_Periph.A4.A4 := FICR_Periph.TEMP.A4.A; + TEMP_Periph.A5.A5 := FICR_Periph.TEMP.A5.A; + + TEMP_Periph.B0.B0 := FICR_Periph.TEMP.B0.B; + TEMP_Periph.B1.B1 := FICR_Periph.TEMP.B1.B; + TEMP_Periph.B2.B2 := FICR_Periph.TEMP.B2.B; + TEMP_Periph.B3.B3 := FICR_Periph.TEMP.B3.B; + TEMP_Periph.B4.B4 := FICR_Periph.TEMP.B4.B; + TEMP_Periph.B5.B5 := FICR_Periph.TEMP.B5.B; + + TEMP_Periph.T0.T0 := FICR_Periph.TEMP.T0.T; + TEMP_Periph.T1.T1 := FICR_Periph.TEMP.T1.T; + TEMP_Periph.T2.T2 := FICR_Periph.TEMP.T2.T; + TEMP_Periph.T3.T3 := FICR_Periph.TEMP.T3.T; + TEMP_Periph.T4.T4 := FICR_Periph.TEMP.T4.T; + end if; + + if Errata_108 then + -- Workaround for Errata 108 "RAM: RAM content cannot be trusted upon + -- waking up from System ON Idle or System OFF mode" + E108_Undocumented_Reg_EE4 := E108_Undocumented_FICR_Reg_258 and 16#4F#; + end if; + + if Errata_136 then + -- Workaround for Errata 136 "System: Bits in RESETREAS are set when they + -- should not be" + if POWER_Periph.RESETREAS.RESETPIN = Detected then + POWER_Periph.RESETREAS.RESETPIN := Notdetected; + end if; + end if; + + if Errata_182 then + -- Workaround for Errata 182 "RADIO: Fixes for anomalies #102, #106, and + -- #107 do not take effect" + E182_Undocumented_Reg_73C := + E182_Undocumented_Reg_73C or Shift_Left (1, 10); + end if; + +end nRF.Device; diff --git a/arch/ARM/Nordic/devices/nrf52/nrf-device.ads b/arch/ARM/Nordic/devices/nrf52/nrf-device.ads new file mode 100644 index 000000000..75489b2ac --- /dev/null +++ b/arch/ARM/Nordic/devices/nrf52/nrf-device.ads @@ -0,0 +1,108 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright (C) 2016-2020, AdaCore -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of the copyright holder nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +------------------------------------------------------------------------------ + +with nRF.GPIO; use nRF.GPIO; +with nRF.RTC; use nRF.RTC; +with NRF_SVD.RTC; +with nRF.TWI; use nRF.TWI; +with NRF_SVD.TWI; +with nRF.SPI_Master; use nRF.SPI_Master; +with NRF_SVD.SPI; +with nRF.Timers; use nRF.Timers; +with NRF_SVD.TIMER; +with nRF.UART; use nRF.UART; +with NRF_SVD.UART; + +package nRF.Device is + pragma Elaborate_Body; + + P00 : aliased GPIO_Point := (Pin => 00); + P01 : aliased GPIO_Point := (Pin => 01); + P02 : aliased GPIO_Point := (Pin => 02); + P03 : aliased GPIO_Point := (Pin => 03); + P04 : aliased GPIO_Point := (Pin => 04); + P05 : aliased GPIO_Point := (Pin => 05); + P06 : aliased GPIO_Point := (Pin => 06); + P07 : aliased GPIO_Point := (Pin => 07); + P08 : aliased GPIO_Point := (Pin => 08); + P09 : aliased GPIO_Point := (Pin => 09); + P10 : aliased GPIO_Point := (Pin => 10); + P11 : aliased GPIO_Point := (Pin => 11); + P12 : aliased GPIO_Point := (Pin => 12); + P13 : aliased GPIO_Point := (Pin => 13); + P14 : aliased GPIO_Point := (Pin => 14); + P15 : aliased GPIO_Point := (Pin => 15); + P16 : aliased GPIO_Point := (Pin => 16); + P17 : aliased GPIO_Point := (Pin => 17); + P18 : aliased GPIO_Point := (Pin => 18); + P19 : aliased GPIO_Point := (Pin => 19); + P20 : aliased GPIO_Point := (Pin => 20); + P21 : aliased GPIO_Point := (Pin => 21); + P22 : aliased GPIO_Point := (Pin => 22); + P23 : aliased GPIO_Point := (Pin => 23); + P24 : aliased GPIO_Point := (Pin => 24); + P25 : aliased GPIO_Point := (Pin => 25); + P26 : aliased GPIO_Point := (Pin => 26); + P27 : aliased GPIO_Point := (Pin => 27); + P28 : aliased GPIO_Point := (Pin => 28); + P29 : aliased GPIO_Point := (Pin => 29); + P30 : aliased GPIO_Point := (Pin => 30); + P31 : aliased GPIO_Point := (Pin => 31); + + RTC_0 : aliased Real_Time_Counter (NRF_SVD.RTC.RTC0_Periph'Access); + RTC_1 : aliased Real_Time_Counter (NRF_SVD.RTC.RTC1_Periph'Access); + RTC_2 : aliased Real_Time_Counter (NRF_SVD.RTC.RTC2_Periph'Access); + + + -- Be carefull of shared resources between the TWI and SPI controllers. + -- TWI_O and SPI_Master_0 cannot be used at the same time. + -- TWI_1 and SPI_Master_1 cannot be used at the same time. + -- + -- See nRF Series Reference Manual, chapter Memory.Instantiation. + + TWI_0 : aliased TWI_Master (NRF_SVD.TWI.TWI0_Periph'Access); + TWI_1 : aliased TWI_Master (NRF_SVD.TWI.TWI1_Periph'Access); + + + SPI_Master_0 : aliased nRF.SPI_Master.SPI_Master (NRF_SVD.SPI.SPI0_Periph'Access); + SPI_Master_1 : aliased nRF.SPI_Master.SPI_Master (NRF_SVD.SPI.SPI1_Periph'Access); + SPI_Master_2 : aliased nRF.SPI_Master.SPI_Master (NRF_SVD.SPI.SPI2_Periph'Access); + + + Timer_0 : aliased Timer (NRF_SVD.TIMER.TIMER0_Periph'Access); + Timer_1 : aliased Timer (NRF_SVD.TIMER.TIMER1_Periph'Access); + Timer_2 : aliased Timer (NRF_SVD.TIMER.TIMER2_Periph'Access); + Timer_3 : aliased Timer (NRF_SVD.TIMER.TIMER3_Periph'Access); + Timer_4 : aliased Timer (NRF_SVD.TIMER.TIMER4_Periph'Access); + + + UART_0 : aliased UART_Device (NRF_SVD.UART.UART0_Periph'Access); +end nRF.Device; diff --git a/arch/ARM/Nordic/drivers/nrf51-adc.adb b/arch/ARM/Nordic/drivers/nrf51/nrf-adc.adb similarity index 94% rename from arch/ARM/Nordic/drivers/nrf51-adc.adb rename to arch/ARM/Nordic/drivers/nrf51/nrf-adc.adb index b894e5fe4..d79a8563a 100644 --- a/arch/ARM/Nordic/drivers/nrf51-adc.adb +++ b/arch/ARM/Nordic/drivers/nrf51/nrf-adc.adb @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2017, AdaCore -- +-- Copyright (C) 2017-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -29,10 +29,10 @@ -- -- ------------------------------------------------------------------------------ -with NRF51_SVD.ADC; use NRF51_SVD.ADC; -with nRF51.Tasks; use nRF51.Tasks; +with NRF_SVD.ADC; use NRF_SVD.ADC; +with nRF.Tasks; use nRF.Tasks; -package body nRF51.ADC is +package body nRF.ADC is procedure Set_Resolution (Res : Bits_Resolution); procedure Set_Reference (Ref : Reference_Selection); @@ -45,9 +45,9 @@ package body nRF51.ADC is begin ADC_Periph.CONFIG.RES := (case Res is - when 8 => CONFIG_RES_Field_8BIT, - when 9 => CONFIG_RES_Field_9BIT, - when 10 => CONFIG_RES_Field_10BIT); + when 8 => Val_8BIT, + when 9 => Val_9BIT, + when 10 => Val_10BIT); end Set_Resolution; ------------------- @@ -166,4 +166,4 @@ package body nRF51.ADC is return ADC_Periph.RESULT.RESULT; end Wait_For_Result; -end nRF51.ADC; +end nRF.ADC; diff --git a/arch/ARM/Nordic/drivers/nrf51-adc.ads b/arch/ARM/Nordic/drivers/nrf51/nrf-adc.ads similarity index 96% rename from arch/ARM/Nordic/drivers/nrf51-adc.ads rename to arch/ARM/Nordic/drivers/nrf51/nrf-adc.ads index 0438757bb..99637f66d 100644 --- a/arch/ARM/Nordic/drivers/nrf51-adc.ads +++ b/arch/ARM/Nordic/drivers/nrf51/nrf-adc.ads @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2017, AdaCore -- +-- Copyright (C) 2017-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -31,7 +31,7 @@ with HAL; use HAL; -package nRF51.ADC is +package nRF.ADC is type Bits_Resolution is range 8 .. 10; @@ -58,4 +58,4 @@ package nRF51.ADC is function Wait_For_Result return UInt10; -end nRF51.ADC; +end nRF.ADC; diff --git a/arch/ARM/Nordic/drivers/nrf51/nrf-clock-set_high_freq_external_frequency.adb b/arch/ARM/Nordic/drivers/nrf51/nrf-clock-set_high_freq_external_frequency.adb new file mode 100644 index 000000000..05038185b --- /dev/null +++ b/arch/ARM/Nordic/drivers/nrf51/nrf-clock-set_high_freq_external_frequency.adb @@ -0,0 +1,38 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright (C) 2020, AdaCore -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of the copyright holder nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +------------------------------------------------------------------------------ + +separate (nRF.Clock) +procedure Set_High_Freq_External_Frequency (Freq : High_Freq_Ext_Freq) is +begin + CLOCK_Periph.XTALFREQ.XTALFREQ := (case Freq is + when HFCLK_16MHz => Val_16Mhz, + when HFCLK_32MHz => Val_32Mhz); +end Set_High_Freq_External_Frequency; diff --git a/arch/ARM/Nordic/drivers/nrf51-events.ads b/arch/ARM/Nordic/drivers/nrf51/nrf-events.ads similarity index 66% rename from arch/ARM/Nordic/drivers/nrf51-events.ads rename to arch/ARM/Nordic/drivers/nrf51/nrf-events.ads index 20c4fe0e2..b693fb5c3 100644 --- a/arch/ARM/Nordic/drivers/nrf51-events.ads +++ b/arch/ARM/Nordic/drivers/nrf51/nrf-events.ads @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2016, AdaCore -- +-- Copyright (C) 2016-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -30,27 +30,26 @@ ------------------------------------------------------------------------------ with System; -with NRF51_SVD.POWER; -with NRF51_SVD.CLOCK; -with NRF51_SVD.GPIOTE; -with NRF51_SVD.RADIO; -with NRF51_SVD.TIMER; -with NRF51_SVD.RTC; -with NRF51_SVD.WDT; -with NRF51_SVD.RNG; -with NRF51_SVD.TEMP; -with NRF51_SVD.ECB; -with NRF51_SVD.CCM; -with NRF51_SVD.AAR; -with NRF51_SVD.SPI; -with NRF51_SVD.TWI; -with NRF51_SVD.UART; -with NRF51_SVD.QDEC; -with NRF51_SVD.ADC; +with NRF_SVD.POWER; +with NRF_SVD.CLOCK; +with NRF_SVD.GPIOTE; +with NRF_SVD.RADIO; +with NRF_SVD.TIMER; +with NRF_SVD.RTC; +with NRF_SVD.WDT; +with NRF_SVD.RNG; +with NRF_SVD.TEMP; +with NRF_SVD.ECB; +with NRF_SVD.CCM; +with NRF_SVD.AAR; +with NRF_SVD.SPI; +with NRF_SVD.TWI; +with NRF_SVD.UART; +with NRF_SVD.QDEC; +with NRF_SVD.ADC; with HAL; use HAL; - -package nRF51.Events is +package nRF.Events is function Triggered (Evt : Event_Type) return Boolean; @@ -187,196 +186,196 @@ private -- Power management events Power_POFWARN : constant Event_Type := - Event_Type (NRF51_SVD.POWER.POWER_Periph.EVENTS_POFWARN'Address); + Event_Type (NRF_SVD.POWER.POWER_Periph.EVENTS_POFWARN'Address); -- Clock events Clock_HFCLKSTARTED : constant Event_Type := - Event_Type (NRF51_SVD.CLOCK.CLOCK_Periph.EVENTS_HFCLKSTARTED'Address); + Event_Type (NRF_SVD.CLOCK.CLOCK_Periph.EVENTS_HFCLKSTARTED'Address); Clock_LFCLKSTARTED : constant Event_Type := - Event_Type (NRF51_SVD.CLOCK.CLOCK_Periph.EVENTS_LFCLKSTARTED'Address); + Event_Type (NRF_SVD.CLOCK.CLOCK_Periph.EVENTS_LFCLKSTARTED'Address); Clock_DONE : constant Event_Type := - Event_Type (NRF51_SVD.CLOCK.CLOCK_Periph.EVENTS_DONE'Address); + Event_Type (NRF_SVD.CLOCK.CLOCK_Periph.EVENTS_DONE'Address); Clock_CTTO : constant Event_Type := - Event_Type (NRF51_SVD.CLOCK.CLOCK_Periph.EVENTS_CTTO'Address); + Event_Type (NRF_SVD.CLOCK.CLOCK_Periph.EVENTS_CTTO'Address); -- GPIOTE events GPIOTE_IN_0 : constant Event_Type := - Event_Type (NRF51_SVD.GPIOTE.GPIOTE_Periph.EVENTS_IN (0)'Address); + Event_Type (NRF_SVD.GPIOTE.GPIOTE_Periph.EVENTS_IN (0)'Address); GPIOTE_IN_1 : constant Event_Type := - Event_Type (NRF51_SVD.GPIOTE.GPIOTE_Periph.EVENTS_IN (1)'Address); + Event_Type (NRF_SVD.GPIOTE.GPIOTE_Periph.EVENTS_IN (1)'Address); GPIOTE_IN_2 : constant Event_Type := - Event_Type (NRF51_SVD.GPIOTE.GPIOTE_Periph.EVENTS_IN (2)'Address); + Event_Type (NRF_SVD.GPIOTE.GPIOTE_Periph.EVENTS_IN (2)'Address); GPIOTE_IN_3 : constant Event_Type := - Event_Type (NRF51_SVD.GPIOTE.GPIOTE_Periph.EVENTS_IN (3)'Address); + Event_Type (NRF_SVD.GPIOTE.GPIOTE_Periph.EVENTS_IN (3)'Address); GPIOTE_PORT : constant Event_Type := - Event_Type (NRF51_SVD.GPIOTE.GPIOTE_Periph.EVENTS_PORT'Address); + Event_Type (NRF_SVD.GPIOTE.GPIOTE_Periph.EVENTS_PORT'Address); -- Radio events Radio_READY : constant Event_Type := - Event_Type (NRF51_SVD.RADIO.RADIO_Periph.EVENTS_READY'Address); + Event_Type (NRF_SVD.RADIO.RADIO_Periph.EVENTS_READY'Address); Radio_ADDRESS : constant Event_Type := - Event_Type (NRF51_SVD.RADIO.RADIO_Periph.EVENTS_ADDRESS'Address); + Event_Type (NRF_SVD.RADIO.RADIO_Periph.EVENTS_ADDRESS'Address); Radio_PAYLOAD : constant Event_Type := - Event_Type (NRF51_SVD.RADIO.RADIO_Periph.EVENTS_PAYLOAD'Address); + Event_Type (NRF_SVD.RADIO.RADIO_Periph.EVENTS_PAYLOAD'Address); Radio_END : constant Event_Type := - Event_Type (NRF51_SVD.RADIO.RADIO_Periph.EVENTS_END'Address); + Event_Type (NRF_SVD.RADIO.RADIO_Periph.EVENTS_END'Address); Radio_DISABLED : constant Event_Type := - Event_Type (NRF51_SVD.RADIO.RADIO_Periph.EVENTS_DISABLED'Address); + Event_Type (NRF_SVD.RADIO.RADIO_Periph.EVENTS_DISABLED'Address); Radio_DEVMATCH : constant Event_Type := - Event_Type (NRF51_SVD.RADIO.RADIO_Periph.EVENTS_DEVMATCH'Address); + Event_Type (NRF_SVD.RADIO.RADIO_Periph.EVENTS_DEVMATCH'Address); Radio_DEVMISS : constant Event_Type := - Event_Type (NRF51_SVD.RADIO.RADIO_Periph.EVENTS_DEVMISS'Address); + Event_Type (NRF_SVD.RADIO.RADIO_Periph.EVENTS_DEVMISS'Address); Radio_RSSIEND : constant Event_Type := - Event_Type (NRF51_SVD.RADIO.RADIO_Periph.EVENTS_RSSIEND'Address); + Event_Type (NRF_SVD.RADIO.RADIO_Periph.EVENTS_RSSIEND'Address); Radio_BCMATCH : constant Event_Type := - Event_Type (NRF51_SVD.RADIO.RADIO_Periph.EVENTS_BCMATCH'Address); + Event_Type (NRF_SVD.RADIO.RADIO_Periph.EVENTS_BCMATCH'Address); -- Timer 0 events Timer_0_COMPARE_0 : constant Event_Type := - Event_Type (NRF51_SVD.TIMER.TIMER0_Periph.EVENTS_COMPARE (0)'Address); + Event_Type (NRF_SVD.TIMER.TIMER0_Periph.EVENTS_COMPARE (0)'Address); Timer_0_COMPARE_1 : constant Event_Type := - Event_Type (NRF51_SVD.TIMER.TIMER0_Periph.EVENTS_COMPARE (1)'Address); + Event_Type (NRF_SVD.TIMER.TIMER0_Periph.EVENTS_COMPARE (1)'Address); Timer_0_COMPARE_2 : constant Event_Type := - Event_Type (NRF51_SVD.TIMER.TIMER0_Periph.EVENTS_COMPARE (2)'Address); + Event_Type (NRF_SVD.TIMER.TIMER0_Periph.EVENTS_COMPARE (2)'Address); Timer_0_COMPARE_3 : constant Event_Type := - Event_Type (NRF51_SVD.TIMER.TIMER0_Periph.EVENTS_COMPARE (3)'Address); + Event_Type (NRF_SVD.TIMER.TIMER0_Periph.EVENTS_COMPARE (3)'Address); -- Timer 1 events Timer_1_COMPARE_0 : constant Event_Type := - Event_Type (NRF51_SVD.TIMER.TIMER1_Periph.EVENTS_COMPARE (0)'Address); + Event_Type (NRF_SVD.TIMER.TIMER1_Periph.EVENTS_COMPARE (0)'Address); Timer_1_COMPARE_1 : constant Event_Type := - Event_Type (NRF51_SVD.TIMER.TIMER1_Periph.EVENTS_COMPARE (1)'Address); + Event_Type (NRF_SVD.TIMER.TIMER1_Periph.EVENTS_COMPARE (1)'Address); Timer_1_COMPARE_2 : constant Event_Type := - Event_Type (NRF51_SVD.TIMER.TIMER1_Periph.EVENTS_COMPARE (2)'Address); + Event_Type (NRF_SVD.TIMER.TIMER1_Periph.EVENTS_COMPARE (2)'Address); Timer_1_COMPARE_3 : constant Event_Type := - Event_Type (NRF51_SVD.TIMER.TIMER1_Periph.EVENTS_COMPARE (3)'Address); + Event_Type (NRF_SVD.TIMER.TIMER1_Periph.EVENTS_COMPARE (3)'Address); -- Timer 2 events Timer_2_COMPARE_0 : constant Event_Type := - Event_Type (NRF51_SVD.TIMER.TIMER2_Periph.EVENTS_COMPARE (0)'Address); + Event_Type (NRF_SVD.TIMER.TIMER2_Periph.EVENTS_COMPARE (0)'Address); Timer_2_COMPARE_1 : constant Event_Type := - Event_Type (NRF51_SVD.TIMER.TIMER2_Periph.EVENTS_COMPARE (1)'Address); + Event_Type (NRF_SVD.TIMER.TIMER2_Periph.EVENTS_COMPARE (1)'Address); Timer_2_COMPARE_2 : constant Event_Type := - Event_Type (NRF51_SVD.TIMER.TIMER2_Periph.EVENTS_COMPARE (2)'Address); + Event_Type (NRF_SVD.TIMER.TIMER2_Periph.EVENTS_COMPARE (2)'Address); Timer_2_COMPARE_3 : constant Event_Type := - Event_Type (NRF51_SVD.TIMER.TIMER2_Periph.EVENTS_COMPARE (3)'Address); + Event_Type (NRF_SVD.TIMER.TIMER2_Periph.EVENTS_COMPARE (3)'Address); -- RTC 0 events RTC_0_TICK : constant Event_Type := - Event_Type (NRF51_SVD.RTC.RTC0_Periph.EVENTS_TICK'Address); + Event_Type (NRF_SVD.RTC.RTC0_Periph.EVENTS_TICK'Address); RTC_0_OVERFLW : constant Event_Type := - Event_Type (NRF51_SVD.RTC.RTC0_Periph.EVENTS_OVRFLW'Address); + Event_Type (NRF_SVD.RTC.RTC0_Periph.EVENTS_OVRFLW'Address); RTC_0_COMPARE_0 : constant Event_Type := - Event_Type (NRF51_SVD.RTC.RTC0_Periph.EVENTS_COMPARE (0)'Address); + Event_Type (NRF_SVD.RTC.RTC0_Periph.EVENTS_COMPARE (0)'Address); RTC_0_COMPARE_1 : constant Event_Type := - Event_Type (NRF51_SVD.RTC.RTC0_Periph.EVENTS_COMPARE (1)'Address); + Event_Type (NRF_SVD.RTC.RTC0_Periph.EVENTS_COMPARE (1)'Address); RTC_0_COMPARE_2 : constant Event_Type := - Event_Type (NRF51_SVD.RTC.RTC0_Periph.EVENTS_COMPARE (2)'Address); + Event_Type (NRF_SVD.RTC.RTC0_Periph.EVENTS_COMPARE (2)'Address); RTC_0_COMPARE_3 : constant Event_Type := - Event_Type (NRF51_SVD.RTC.RTC0_Periph.EVENTS_COMPARE (3)'Address); + Event_Type (NRF_SVD.RTC.RTC0_Periph.EVENTS_COMPARE (3)'Address); -- RTC 1 events RTC_1_TICK : constant Event_Type := - Event_Type (NRF51_SVD.RTC.RTC1_Periph.EVENTS_TICK'Address); + Event_Type (NRF_SVD.RTC.RTC1_Periph.EVENTS_TICK'Address); RTC_1_OVERFLW : constant Event_Type := - Event_Type (NRF51_SVD.RTC.RTC1_Periph.EVENTS_OVRFLW'Address); + Event_Type (NRF_SVD.RTC.RTC1_Periph.EVENTS_OVRFLW'Address); RTC_1_COMPARE_0 : constant Event_Type := - Event_Type (NRF51_SVD.RTC.RTC1_Periph.EVENTS_COMPARE (0)'Address); + Event_Type (NRF_SVD.RTC.RTC1_Periph.EVENTS_COMPARE (0)'Address); RTC_1_COMPARE_1 : constant Event_Type := - Event_Type (NRF51_SVD.RTC.RTC1_Periph.EVENTS_COMPARE (1)'Address); + Event_Type (NRF_SVD.RTC.RTC1_Periph.EVENTS_COMPARE (1)'Address); RTC_1_COMPARE_2 : constant Event_Type := - Event_Type (NRF51_SVD.RTC.RTC1_Periph.EVENTS_COMPARE (2)'Address); + Event_Type (NRF_SVD.RTC.RTC1_Periph.EVENTS_COMPARE (2)'Address); RTC_1_COMPARE_3 : constant Event_Type := - Event_Type (NRF51_SVD.RTC.RTC1_Periph.EVENTS_COMPARE (3)'Address); + Event_Type (NRF_SVD.RTC.RTC1_Periph.EVENTS_COMPARE (3)'Address); -- Watchdog task Watchdog_TIMEOUT : constant Event_Type := - Event_Type (NRF51_SVD.WDT.WDT_Periph.EVENTS_TIMEOUT'Address); + Event_Type (NRF_SVD.WDT.WDT_Periph.EVENTS_TIMEOUT'Address); -- Random Number Genrator events RNG_VALRDY : constant Event_Type := - Event_Type (NRF51_SVD.RNG.RNG_Periph.EVENTS_VALRDY'Address); + Event_Type (NRF_SVD.RNG.RNG_Periph.EVENTS_VALRDY'Address); -- Temperature events Temperature_DATARDY : constant Event_Type := - Event_Type (NRF51_SVD.TEMP.TEMP_Periph.EVENTS_DATARDY'Address); + Event_Type (NRF_SVD.TEMP.TEMP_Periph.EVENTS_DATARDY'Address); -- AES Electronic Codebook mode encryption (ECB) events ECB_END : constant Event_Type := - Event_Type (NRF51_SVD.ECB.ECB_Periph.EVENTS_ENDECB'Address); + Event_Type (NRF_SVD.ECB.ECB_Periph.EVENTS_ENDECB'Address); ECB_ERROR : constant Event_Type := - Event_Type (NRF51_SVD.ECB.ECB_Periph.EVENTS_ERRORECB'Address); + Event_Type (NRF_SVD.ECB.ECB_Periph.EVENTS_ERRORECB'Address); -- AES CCM mode encryption (CCM) events CCM_KSGEN_END : constant Event_Type := - Event_Type (NRF51_SVD.CCM.CCM_Periph.EVENTS_ENDKSGEN'Address); + Event_Type (NRF_SVD.CCM.CCM_Periph.EVENTS_ENDKSGEN'Address); CCM_CRYPT_END : constant Event_Type := - Event_Type (NRF51_SVD.CCM.CCM_Periph.EVENTS_ENDCRYPT'Address); + Event_Type (NRF_SVD.CCM.CCM_Periph.EVENTS_ENDCRYPT'Address); CCM_ERROR : constant Event_Type := - Event_Type (NRF51_SVD.CCM.CCM_Periph.EVENTS_ERROR'Address); + Event_Type (NRF_SVD.CCM.CCM_Periph.EVENTS_ERROR'Address); -- Accelerated Address Resolver (AAR) events AAR_END : constant Event_Type := - Event_Type (NRF51_SVD.AAR.AAR_Periph.EVENTS_END'Address); + Event_Type (NRF_SVD.AAR.AAR_Periph.EVENTS_END'Address); AAR_RESOLVED : constant Event_Type := - Event_Type (NRF51_SVD.AAR.AAR_Periph.EVENTS_RESOLVED'Address); + Event_Type (NRF_SVD.AAR.AAR_Periph.EVENTS_RESOLVED'Address); AAR_NOTRESOLVED : constant Event_Type := - Event_Type (NRF51_SVD.AAR.AAR_Periph.EVENTS_NOTRESOLVED'Address); + Event_Type (NRF_SVD.AAR.AAR_Periph.EVENTS_NOTRESOLVED'Address); -- Serial Peripheral Interface (SPI) events SPI_0_READY : constant Event_Type := - Event_Type (NRF51_SVD.SPI.SPI0_Periph.EVENTS_READY'Address); + Event_Type (NRF_SVD.SPI.SPI0_Periph.EVENTS_READY'Address); -- Serial Peripheral Interface (SPI) events SPI_1_READY : constant Event_Type := - Event_Type (NRF51_SVD.SPI.SPI1_Periph.EVENTS_READY'Address); + Event_Type (NRF_SVD.SPI.SPI1_Periph.EVENTS_READY'Address); -- Two Wire Interface (TWI) 0 events TWI_0_STOPPED : constant Event_Type := - Event_Type (NRF51_SVD.TWI.TWI0_Periph.EVENTS_STOPPED'Address); + Event_Type (NRF_SVD.TWI.TWI0_Periph.EVENTS_STOPPED'Address); TWI_0_RXDRDY : constant Event_Type := - Event_Type (NRF51_SVD.TWI.TWI0_Periph.EVENTS_RXDREADY'Address); + Event_Type (NRF_SVD.TWI.TWI0_Periph.EVENTS_RXDREADY'Address); TWI_0_TXDENT : constant Event_Type := - Event_Type (NRF51_SVD.TWI.TWI0_Periph.EVENTS_TXDSENT'Address); + Event_Type (NRF_SVD.TWI.TWI0_Periph.EVENTS_TXDSENT'Address); TWI_0_ERRO : constant Event_Type := - Event_Type (NRF51_SVD.TWI.TWI0_Periph.EVENTS_ERROR'Address); + Event_Type (NRF_SVD.TWI.TWI0_Periph.EVENTS_ERROR'Address); TWI_0_BB : constant Event_Type := - Event_Type (NRF51_SVD.TWI.TWI0_Periph.EVENTS_BB'Address); + Event_Type (NRF_SVD.TWI.TWI0_Periph.EVENTS_BB'Address); TWI_0_SUSPENDED : constant Event_Type := - Event_Type (NRF51_SVD.TWI.TWI0_Periph.EVENTS_SUSPENDED'Address); + Event_Type (NRF_SVD.TWI.TWI0_Periph.EVENTS_SUSPENDED'Address); -- Two Wire Interface (TWI) 1 events TWI_1_STOPPED : constant Event_Type := - Event_Type (NRF51_SVD.TWI.TWI1_Periph.EVENTS_STOPPED'Address); + Event_Type (NRF_SVD.TWI.TWI1_Periph.EVENTS_STOPPED'Address); TWI_1_RXDRDY : constant Event_Type := - Event_Type (NRF51_SVD.TWI.TWI1_Periph.EVENTS_RXDREADY'Address); + Event_Type (NRF_SVD.TWI.TWI1_Periph.EVENTS_RXDREADY'Address); TWI_1_TXDENT : constant Event_Type := - Event_Type (NRF51_SVD.TWI.TWI1_Periph.EVENTS_TXDSENT'Address); + Event_Type (NRF_SVD.TWI.TWI1_Periph.EVENTS_TXDSENT'Address); TWI_1_ERRO : constant Event_Type := - Event_Type (NRF51_SVD.TWI.TWI1_Periph.EVENTS_ERROR'Address); + Event_Type (NRF_SVD.TWI.TWI1_Periph.EVENTS_ERROR'Address); TWI_1_BB : constant Event_Type := - Event_Type (NRF51_SVD.TWI.TWI1_Periph.EVENTS_BB'Address); + Event_Type (NRF_SVD.TWI.TWI1_Periph.EVENTS_BB'Address); TWI_1_SUSPENDED : constant Event_Type := - Event_Type (NRF51_SVD.TWI.TWI1_Periph.EVENTS_SUSPENDED'Address); + Event_Type (NRF_SVD.TWI.TWI1_Periph.EVENTS_SUSPENDED'Address); -- Universal Asynchronous Receiver/Transmitter (UART) Events UART_RXDRDY : constant Event_Type := - Event_Type (NRF51_SVD.UART.UART0_Periph.EVENTS_RXDRDY'Address); + Event_Type (NRF_SVD.UART.UART0_Periph.EVENTS_RXDRDY'Address); UART_TXDRDY : constant Event_Type := - Event_Type (NRF51_SVD.UART.UART0_Periph.EVENTS_TXDRDY'Address); + Event_Type (NRF_SVD.UART.UART0_Periph.EVENTS_TXDRDY'Address); UART_ERROR : constant Event_Type := - Event_Type (NRF51_SVD.UART.UART0_Periph.EVENTS_ERROR'Address); + Event_Type (NRF_SVD.UART.UART0_Periph.EVENTS_ERROR'Address); -- Quadrature Decoder (QDEC) QDEC_SAMPLERDY : constant Event_Type := - Event_Type (NRF51_SVD.QDEC.QDEC_Periph.EVENTS_SAMPLERDY'Address); + Event_Type (NRF_SVD.QDEC.QDEC_Periph.EVENTS_SAMPLERDY'Address); QDEC_REPORTRDY : constant Event_Type := - Event_Type (NRF51_SVD.QDEC.QDEC_Periph.EVENTS_REPORTRDY'Address); + Event_Type (NRF_SVD.QDEC.QDEC_Periph.EVENTS_REPORTRDY'Address); QDEC_ACCOF : constant Event_Type := - Event_Type (NRF51_SVD.QDEC.QDEC_Periph.EVENTS_ACCOF'Address); + Event_Type (NRF_SVD.QDEC.QDEC_Periph.EVENTS_ACCOF'Address); -- Analof to Digital Converter (ADC) ADC_END : constant Event_Type := - Event_Type (NRF51_SVD.ADC.ADC_Periph.EVENTS_END'Address); + Event_Type (NRF_SVD.ADC.ADC_Periph.EVENTS_END'Address); -end nRF51.Events; +end nRF.Events; diff --git a/arch/ARM/Nordic/drivers/nrf51-interrupts.ads b/arch/ARM/Nordic/drivers/nrf51/nrf-interrupts.ads similarity index 94% rename from arch/ARM/Nordic/drivers/nrf51-interrupts.ads rename to arch/ARM/Nordic/drivers/nrf51/nrf-interrupts.ads index fe80487bc..d9a619837 100644 --- a/arch/ARM/Nordic/drivers/nrf51-interrupts.ads +++ b/arch/ARM/Nordic/drivers/nrf51/nrf-interrupts.ads @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2016, AdaCore -- +-- Copyright (C) 2016-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -29,9 +29,10 @@ -- -- ------------------------------------------------------------------------------ -with HAL; use HAL; +with Cortex_M.NVIC; + +package nRF.Interrupts is -package nRF51.Interrupts is type Interrupt_Name is (POWER_CLOCK_Interrupt, RADIO_Interrupt, @@ -66,7 +67,7 @@ package nRF51.Interrupts is Unused_Interrupt_6, Unused_Interrupt_7); - subtype Interrupt_Priority is UInt8; + subtype Interrupt_Priority is Cortex_M.NVIC.Interrupt_Priority; procedure Set_Priority (Int : Interrupt_Name; Prio : Interrupt_Priority); procedure Enable (Int : Interrupt_Name); @@ -75,7 +76,7 @@ package nRF51.Interrupts is type Handler is access procedure; - procedure Register (Id : nRF51.Interrupts.Interrupt_Name; + procedure Register (Id : nRF.Interrupts.Interrupt_Name; Hdl : Handler); -- Register a handler for the given interrupt. There can be only one handler -- for each interrupt so the previous one, if any, will be removed. @@ -115,4 +116,4 @@ private Unused_Interrupt_6 => 30, Unused_Interrupt_7 => 31); -end nRF51.Interrupts; +end nRF.Interrupts; diff --git a/arch/ARM/Nordic/drivers/nrf51-ppi.adb b/arch/ARM/Nordic/drivers/nrf51/nrf-ppi.adb similarity index 94% rename from arch/ARM/Nordic/drivers/nrf51-ppi.adb rename to arch/ARM/Nordic/drivers/nrf51/nrf-ppi.adb index e30c87865..2dfc0cbf7 100644 --- a/arch/ARM/Nordic/drivers/nrf51-ppi.adb +++ b/arch/ARM/Nordic/drivers/nrf51/nrf-ppi.adb @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2016, AdaCore -- +-- Copyright (C) 2016-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -29,11 +29,11 @@ -- -- ------------------------------------------------------------------------------ -with NRF51_SVD.PPI; use NRF51_SVD.PPI; -with nRF51.Events; use nRF51.Events; -with nRF51.Tasks; use nRF51.Tasks; +with NRF_SVD.PPI; use NRF_SVD.PPI; +with nRF.Events; use nRF.Events; +with nRF.Tasks; use nRF.Tasks; -package body nRF51.PPI is +package body nRF.PPI is --------------- -- Configure -- @@ -113,4 +113,4 @@ package body nRF51.PPI is PPI_Periph.TASKS_CHG (Group).DIS := 1; end Disable_Group; -end nRF51.PPI; +end nRF.PPI; diff --git a/arch/ARM/Nordic/drivers/nrf51-ppi.ads b/arch/ARM/Nordic/drivers/nrf51/nrf-ppi.ads similarity index 96% rename from arch/ARM/Nordic/drivers/nrf51-ppi.ads rename to arch/ARM/Nordic/drivers/nrf51/nrf-ppi.ads index 2839c292a..04e903c98 100644 --- a/arch/ARM/Nordic/drivers/nrf51-ppi.ads +++ b/arch/ARM/Nordic/drivers/nrf51/nrf-ppi.ads @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2016, AdaCore -- +-- Copyright (C) 2016-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -29,7 +29,7 @@ -- -- ------------------------------------------------------------------------------ -package nRF51.PPI is +package nRF.PPI is subtype Channel_ID is Natural range 0 .. 15; subtype Group_ID is Natural range 0 .. 3; @@ -48,4 +48,4 @@ package nRF51.PPI is procedure Enable_Group (Group : Group_ID); procedure Disable_Group (Group : Group_ID); -end nRF51.PPI; +end nRF.PPI; diff --git a/arch/ARM/Nordic/drivers/nrf51/nrf-tasks.ads b/arch/ARM/Nordic/drivers/nrf51/nrf-tasks.ads new file mode 100644 index 000000000..2542d295c --- /dev/null +++ b/arch/ARM/Nordic/drivers/nrf51/nrf-tasks.ads @@ -0,0 +1,424 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright (C) 2016-2020, AdaCore -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of the copyright holder nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +------------------------------------------------------------------------------ + +with System; +with NRF_SVD.POWER; +with NRF_SVD.CLOCK; +with NRF_SVD.GPIOTE; +with NRF_SVD.PPI; +with NRF_SVD.RADIO; +with NRF_SVD.TIMER; +with NRF_SVD.RTC; +with NRF_SVD.WDT; +with NRF_SVD.RNG; +with NRF_SVD.TEMP; +with NRF_SVD.ECB; +with NRF_SVD.CCM; +with NRF_SVD.AAR; +with NRF_SVD.TWI; +with NRF_SVD.UART; +with NRF_SVD.QDEC; +with NRF_SVD.ADC; +with HAL; use HAL; + +package nRF.Tasks is + + procedure Trigger (T : Task_Type); + -- Software task trigger + + function Get_Address (T : Task_Type) return System.Address; + function Get_Address (T : Task_Type) return UInt32; + + -- Power management tasks + Power_CONSTLAT : constant Task_Type; + Power_LOWPWR : constant Task_Type; + + -- Clock tasks + Clock_HFCLKSTART : constant Task_Type; + Clock_HFCLKSTOP : constant Task_Type; + Clock_LFCLKSTART : constant Task_Type; + Clock_LFCLKSTOP : constant Task_Type; + Clock_CAL : constant Task_Type; + Clock_CTSTART : constant Task_Type; + Clock_CTSTOP : constant Task_Type; + + -- GPIO tasks + GPIOTE_OUT_0 : constant Task_Type; + GPIOTE_OUT_1 : constant Task_Type; + GPIOTE_OUT_2 : constant Task_Type; + GPIOTE_OUT_3 : constant Task_Type; + + -- Programmable Peripheral Interconnect tasks + PPI_CHG_0_EN : constant Task_Type; + PPI_CHG_0_DIS : constant Task_Type; + PPI_CHG_1_EN : constant Task_Type; + PPI_CHG_1_DIS : constant Task_Type; + PPI_CHG_2_EN : constant Task_Type; + PPI_CHG_2_DIS : constant Task_Type; + PPI_CHG_3_EN : constant Task_Type; + PPI_CHG_3_DIS : constant Task_Type; + + -- Radio tasks + Radio_TXEN : constant Task_Type; + Radio_RXEN : constant Task_Type; + Radio_START : constant Task_Type; + Radio_STOP : constant Task_Type; + Radio_DISABLE : constant Task_Type; + Radio_RSSISTART : constant Task_Type; + Radio_RSSISTOP : constant Task_Type; + Radio_BCSTART : constant Task_Type; + Radio_BCSTOP : constant Task_Type; + + -- Timer 0 tasks + Timer_0_START : constant Task_Type; + Timer_0_STOP : constant Task_Type; + Timer_0_COUNT : constant Task_Type; + Timer_0_CLEAR : constant Task_Type; + Timer_0_CAPTURE_0 : constant Task_Type; + Timer_0_CAPTURE_1 : constant Task_Type; + Timer_0_CAPTURE_2 : constant Task_Type; + Timer_0_CAPTURE_3 : constant Task_Type; + + -- Timer 1 tasks + Timer_1_START : constant Task_Type; + Timer_1_STOP : constant Task_Type; + Timer_1_COUNT : constant Task_Type; + Timer_1_CLEAR : constant Task_Type; + Timer_1_CAPTURE_0 : constant Task_Type; + Timer_1_CAPTURE_1 : constant Task_Type; + Timer_1_CAPTURE_2 : constant Task_Type; + Timer_1_CAPTURE_3 : constant Task_Type; + + -- Timer 2 tasks + Timer_2_START : constant Task_Type; + Timer_2_STOP : constant Task_Type; + Timer_2_COUNT : constant Task_Type; + Timer_2_CLEAR : constant Task_Type; + Timer_2_CAPTURE_0 : constant Task_Type; + Timer_2_CAPTURE_1 : constant Task_Type; + Timer_2_CAPTURE_2 : constant Task_Type; + Timer_2_CAPTURE_3 : constant Task_Type; + + -- RTC 0 tasks + RTC_0_START : constant Task_Type; + RTC_0_STOP : constant Task_Type; + RTC_0_CLEAR : constant Task_Type; + RTC_0_TRIGOVRFLW : constant Task_Type; + + -- RTC 1 tasks + RTC_1_START : constant Task_Type; + RTC_1_STOP : constant Task_Type; + RTC_1_CLEAR : constant Task_Type; + RTC_1_TRIGOVRFLW : constant Task_Type; + + -- Watchdog task + Watchdog_START : constant Task_Type; + + -- Random Number Genrator tasks + RNG_START : constant Task_Type; + RNG_STOP : constant Task_Type; + + -- Temperature tasks + Temperature_START : constant Task_Type; + Temperature_STOP : constant Task_Type; + + -- AES Electronic Codebook mode encryption (ECB) tasks + ECB_START : constant Task_Type; + ECB_STOP : constant Task_Type; + + -- AES CCM mode encryption (CCM) tasks + CCM_KSGEN : constant Task_Type; + CCM_CRYPT : constant Task_Type; + CCM_STOP : constant Task_Type; + + -- Accelerated Address Resolver (AAR) tasks + AAR_START : constant Task_Type; + AAR_STOP : constant Task_Type; + + -- Two Wire Interface (TWI) 0 tasks + TWI_0_STARTRX : constant Task_Type; + TWI_0_STARTTX : constant Task_Type; + TWI_0_STOP : constant Task_Type; + TWI_0_SUSPEND : constant Task_Type; + TWI_0_RESUME : constant Task_Type; + + -- Two Wire Interface (TWI) 1 tasks + TWI_1_STARTRX : constant Task_Type; + TWI_1_STARTTX : constant Task_Type; + TWI_1_STOP : constant Task_Type; + TWI_1_SUSPEND : constant Task_Type; + TWI_1_RESUME : constant Task_Type; + + -- Universal Asynchronous Receiver/Transmitter (UART) Tasks + UART_STARTRX : constant Task_Type; + UART_STOPRX : constant Task_Type; + UART_STARTTX : constant Task_Type; + UART_STOPTX : constant Task_Type; + + -- Quadrature Decoder (QDEC) + QDEC_START : constant Task_Type; + QDEC_STOP : constant Task_Type; + QDEC_READCLRACC : constant Task_Type; + + -- Analof to Digital Converter (ADC) + ADC_START : constant Task_Type; + ADC_STOP : constant Task_Type; +private + + -- Power management tasks + Power_CONSTLAT : constant Task_Type := + Task_Type (NRF_SVD.POWER.POWER_Periph.TASKS_CONSTLAT'Address); + Power_LOWPWR : constant Task_Type := + Task_Type (NRF_SVD.POWER.POWER_Periph.TASKS_LOWPWR'Address); + + -- Clock tasks + Clock_HFCLKSTART : constant Task_Type := + Task_Type (NRF_SVD.CLOCK.CLOCK_Periph.TASKS_HFCLKSTART'Address); + Clock_HFCLKSTOP : constant Task_Type := + Task_Type (NRF_SVD.CLOCK.CLOCK_Periph.TASKS_HFCLKSTOP'Address); + Clock_LFCLKSTART : constant Task_Type := + Task_Type (NRF_SVD.CLOCK.CLOCK_Periph.TASKS_LFCLKSTART'Address); + Clock_LFCLKSTOP : constant Task_Type := + Task_Type (NRF_SVD.CLOCK.CLOCK_Periph.TASKS_LFCLKSTOP'Address); + Clock_CAL : constant Task_Type := + Task_Type (NRF_SVD.CLOCK.CLOCK_Periph.TASKS_CAL'Address); + Clock_CTSTART : constant Task_Type := + Task_Type (NRF_SVD.CLOCK.CLOCK_Periph.TASKS_CTSTART'Address); + Clock_CTSTOP : constant Task_Type := + Task_Type (NRF_SVD.CLOCK.CLOCK_Periph.TASKS_CTSTOP'Address); + + -- GPIOTE tasks + GPIOTE_OUT_0 : constant Task_Type := + Task_Type (NRF_SVD.GPIOTE.GPIOTE_Periph.TASKS_OUT (0)'Address); + GPIOTE_OUT_1 : constant Task_Type := + Task_Type (NRF_SVD.GPIOTE.GPIOTE_Periph.TASKS_OUT (1)'Address); + GPIOTE_OUT_2 : constant Task_Type := + Task_Type (NRF_SVD.GPIOTE.GPIOTE_Periph.TASKS_OUT (2)'Address); + GPIOTE_OUT_3 : constant Task_Type := + Task_Type (NRF_SVD.GPIOTE.GPIOTE_Periph.TASKS_OUT (3)'Address); + + -- Programmable Peripheral Interconnect Tasks + PPI_CHG_0_EN : constant Task_Type := + Task_Type (NRF_SVD.PPI.PPI_Periph.TASKS_CHG (0).EN'Address); + PPI_CHG_0_DIS : constant Task_Type := + Task_Type (NRF_SVD.PPI.PPI_Periph.TASKS_CHG (0).DIS'Address); + PPI_CHG_1_EN : constant Task_Type := + Task_Type (NRF_SVD.PPI.PPI_Periph.TASKS_CHG (1).EN'Address); + PPI_CHG_1_DIS : constant Task_Type := + Task_Type (NRF_SVD.PPI.PPI_Periph.TASKS_CHG (1).DIS'Address); + PPI_CHG_2_EN : constant Task_Type := + Task_Type (NRF_SVD.PPI.PPI_Periph.TASKS_CHG (2).EN'Address); + PPI_CHG_2_DIS : constant Task_Type := + Task_Type (NRF_SVD.PPI.PPI_Periph.TASKS_CHG (2).DIS'Address); + PPI_CHG_3_EN : constant Task_Type := + Task_Type (NRF_SVD.PPI.PPI_Periph.TASKS_CHG (3).EN'Address); + PPI_CHG_3_DIS : constant Task_Type := + Task_Type (NRF_SVD.PPI.PPI_Periph.TASKS_CHG (3).DIS'Address); + + -- Radio tasks + Radio_TXEN : constant Task_Type := + Task_Type (NRF_SVD.RADIO.RADIO_Periph.TASKS_TXEN'Address); + Radio_RXEN : constant Task_Type := + Task_Type (NRF_SVD.RADIO.RADIO_Periph.TASKS_RXEN'Address); + Radio_START : constant Task_Type := + Task_Type (NRF_SVD.RADIO.RADIO_Periph.TASKS_START'Address); + Radio_STOP : constant Task_Type := + Task_Type (NRF_SVD.RADIO.RADIO_Periph.TASKS_STOP'Address); + Radio_DISABLE : constant Task_Type := + Task_Type (NRF_SVD.RADIO.RADIO_Periph.TASKS_DISABLE'Address); + Radio_RSSISTART : constant Task_Type := + Task_Type (NRF_SVD.RADIO.RADIO_Periph.TASKS_RSSISTART'Address); + Radio_RSSISTOP : constant Task_Type := + Task_Type (NRF_SVD.RADIO.RADIO_Periph.TASKS_RSSISTOP'Address); + Radio_BCSTART : constant Task_Type := + Task_Type (NRF_SVD.RADIO.RADIO_Periph.TASKS_BCSTART'Address); + Radio_BCSTOP : constant Task_Type := + Task_Type (NRF_SVD.RADIO.RADIO_Periph.TASKS_BCSTOP'Address); + + -- Timer 0 tasks + Timer_0_START : constant Task_Type := + Task_Type (NRF_SVD.TIMER.TIMER0_Periph.TASKS_START'Address); + Timer_0_STOP : constant Task_Type := + Task_Type (NRF_SVD.TIMER.TIMER0_Periph.TASKS_START'Address); + Timer_0_COUNT : constant Task_Type := + Task_Type (NRF_SVD.TIMER.TIMER0_Periph.TASKS_START'Address); + Timer_0_CLEAR : constant Task_Type := + Task_Type (NRF_SVD.TIMER.TIMER0_Periph.TASKS_START'Address); + Timer_0_CAPTURE_0 : constant Task_Type := + Task_Type (NRF_SVD.TIMER.TIMER0_Periph.TASKS_START'Address); + Timer_0_CAPTURE_1 : constant Task_Type := + Task_Type (NRF_SVD.TIMER.TIMER0_Periph.TASKS_START'Address); + Timer_0_CAPTURE_2 : constant Task_Type := + Task_Type (NRF_SVD.TIMER.TIMER0_Periph.TASKS_START'Address); + Timer_0_CAPTURE_3 : constant Task_Type := + Task_Type (NRF_SVD.TIMER.TIMER0_Periph.TASKS_START'Address); + + -- Timer 1 tasks + Timer_1_START : constant Task_Type := + Task_Type (NRF_SVD.TIMER.TIMER1_Periph.TASKS_START'Address); + Timer_1_STOP : constant Task_Type := + Task_Type (NRF_SVD.TIMER.TIMER1_Periph.TASKS_START'Address); + Timer_1_COUNT : constant Task_Type := + Task_Type (NRF_SVD.TIMER.TIMER1_Periph.TASKS_START'Address); + Timer_1_CLEAR : constant Task_Type := + Task_Type (NRF_SVD.TIMER.TIMER1_Periph.TASKS_START'Address); + Timer_1_CAPTURE_0 : constant Task_Type := + Task_Type (NRF_SVD.TIMER.TIMER1_Periph.TASKS_START'Address); + Timer_1_CAPTURE_1 : constant Task_Type := + Task_Type (NRF_SVD.TIMER.TIMER1_Periph.TASKS_START'Address); + Timer_1_CAPTURE_2 : constant Task_Type := + Task_Type (NRF_SVD.TIMER.TIMER1_Periph.TASKS_START'Address); + Timer_1_CAPTURE_3 : constant Task_Type := + Task_Type (NRF_SVD.TIMER.TIMER1_Periph.TASKS_START'Address); + + -- Timer 2 tasks + Timer_2_START : constant Task_Type := + Task_Type (NRF_SVD.TIMER.TIMER2_Periph.TASKS_START'Address); + Timer_2_STOP : constant Task_Type := + Task_Type (NRF_SVD.TIMER.TIMER2_Periph.TASKS_START'Address); + Timer_2_COUNT : constant Task_Type := + Task_Type (NRF_SVD.TIMER.TIMER2_Periph.TASKS_START'Address); + Timer_2_CLEAR : constant Task_Type := + Task_Type (NRF_SVD.TIMER.TIMER2_Periph.TASKS_START'Address); + Timer_2_CAPTURE_0 : constant Task_Type := + Task_Type (NRF_SVD.TIMER.TIMER2_Periph.TASKS_START'Address); + Timer_2_CAPTURE_1 : constant Task_Type := + Task_Type (NRF_SVD.TIMER.TIMER2_Periph.TASKS_START'Address); + Timer_2_CAPTURE_2 : constant Task_Type := + Task_Type (NRF_SVD.TIMER.TIMER2_Periph.TASKS_START'Address); + Timer_2_CAPTURE_3 : constant Task_Type := + Task_Type (NRF_SVD.TIMER.TIMER2_Periph.TASKS_START'Address); + + -- RTC 0 tasks + RTC_0_START : constant Task_Type := + Task_Type (NRF_SVD.RTC.RTC0_Periph.TASKS_START'Address); + RTC_0_STOP : constant Task_Type := + Task_Type (NRF_SVD.RTC.RTC0_Periph.TASKS_STOP'Address); + RTC_0_CLEAR : constant Task_Type := + Task_Type (NRF_SVD.RTC.RTC0_Periph.TASKS_CLEAR'Address); + RTC_0_TRIGOVRFLW : constant Task_Type := + Task_Type (NRF_SVD.RTC.RTC0_Periph.TASKS_TRIGOVRFLW'Address); + + -- RTC 1 tasks + RTC_1_START : constant Task_Type := + Task_Type (NRF_SVD.RTC.RTC1_Periph.TASKS_START'Address); + RTC_1_STOP : constant Task_Type := + Task_Type (NRF_SVD.RTC.RTC1_Periph.TASKS_STOP'Address); + RTC_1_CLEAR : constant Task_Type := + Task_Type (NRF_SVD.RTC.RTC1_Periph.TASKS_CLEAR'Address); + RTC_1_TRIGOVRFLW : constant Task_Type := + Task_Type (NRF_SVD.RTC.RTC1_Periph.TASKS_TRIGOVRFLW'Address); + + -- Watchdog tasks + Watchdog_START : constant Task_Type := + Task_Type (NRF_SVD.WDT.WDT_Periph.TASKS_START'Address); + + -- Random Number Genrator tasks + RNG_START : constant Task_Type := + Task_Type (NRF_SVD.RNG.RNG_Periph.TASKS_START'Address); + RNG_STOP : constant Task_Type := + Task_Type (NRF_SVD.RNG.RNG_Periph.TASKS_START'Address); + + -- Temperature tasks + Temperature_START : constant Task_Type := + Task_Type (NRF_SVD.TEMP.TEMP_Periph.TASKS_START'Address); + Temperature_STOP : constant Task_Type := + Task_Type (NRF_SVD.TEMP.TEMP_Periph.TASKS_STOP'Address); + + -- AES Electronic Codebook mode encryption (ECB) tasks + ECB_START : constant Task_Type := + Task_Type (NRF_SVD.ECB.ECB_Periph.TASKS_STARTECB'Address); + ECB_STOP : constant Task_Type := + Task_Type (NRF_SVD.ECB.ECB_Periph.TASKS_STOPECB'Address); + + -- AES CCM mode encryption (CCM) tasks + CCM_KSGEN : constant Task_Type := + Task_Type (NRF_SVD.CCM.CCM_Periph.TASKS_KSGEN'Address); + CCM_CRYPT : constant Task_Type := + Task_Type (NRF_SVD.CCM.CCM_Periph.TASKS_CRYPT'Address); + CCM_STOP : constant Task_Type := + Task_Type (NRF_SVD.CCM.CCM_Periph.TASKS_STOP'Address); + + -- Accelerated Address Resolver (AAR) tasks + AAR_START : constant Task_Type := + Task_Type (NRF_SVD.AAR.AAR_Periph.TASKS_START'Address); + AAR_STOP : constant Task_Type := + Task_Type (NRF_SVD.AAR.AAR_Periph.TASKS_STOP'Address); + + -- Two Wire Interface (TWI) 0 tasks + TWI_0_STARTRX : constant Task_Type := + Task_Type (NRF_SVD.TWI.TWI0_Periph.TASKS_STARTRX'Address); + TWI_0_STARTTX : constant Task_Type := + Task_Type (NRF_SVD.TWI.TWI0_Periph.TASKS_STARTTX'Address); + TWI_0_STOP : constant Task_Type := + Task_Type (NRF_SVD.TWI.TWI0_Periph.TASKS_STOP'Address); + TWI_0_SUSPEND : constant Task_Type := + Task_Type (NRF_SVD.TWI.TWI0_Periph.TASKS_SUSPEND'Address); + TWI_0_RESUME : constant Task_Type := + Task_Type (NRF_SVD.TWI.TWI0_Periph.TASKS_RESUME'Address); + + -- Two Wire Interface (TWI) 1 tasks + TWI_1_STARTRX : constant Task_Type := + Task_Type (NRF_SVD.TWI.TWI1_Periph.TASKS_STARTRX'Address); + TWI_1_STARTTX : constant Task_Type := + Task_Type (NRF_SVD.TWI.TWI1_Periph.TASKS_STARTTX'Address); + TWI_1_STOP : constant Task_Type := + Task_Type (NRF_SVD.TWI.TWI1_Periph.TASKS_STOP'Address); + TWI_1_SUSPEND : constant Task_Type := + Task_Type (NRF_SVD.TWI.TWI1_Periph.TASKS_SUSPEND'Address); + TWI_1_RESUME : constant Task_Type := + Task_Type (NRF_SVD.TWI.TWI1_Periph.TASKS_RESUME'Address); + + -- Universal Asynchronous Receiver/Transmitter (UART) Tasks + UART_STARTRX : constant Task_Type := + Task_Type (NRF_SVD.UART.UART0_Periph.TASKS_STARTRX'Address); + UART_STOPRX : constant Task_Type := + Task_Type (NRF_SVD.UART.UART0_Periph.TASKS_STOPRX'Address); + UART_STARTTX : constant Task_Type := + Task_Type (NRF_SVD.UART.UART0_Periph.TASKS_STARTTX'Address); + UART_STOPTX : constant Task_Type := + Task_Type (NRF_SVD.UART.UART0_Periph.TASKS_STOPTX'Address); + + -- Quadrature Decoder (QDEC) + QDEC_START : constant Task_Type := + Task_Type (NRF_SVD.QDEC.QDEC_Periph.TASKS_START'Address); + QDEC_STOP : constant Task_Type := + Task_Type (NRF_SVD.QDEC.QDEC_Periph.TASKS_STOP'Address); + QDEC_READCLRACC : constant Task_Type := + Task_Type (NRF_SVD.QDEC.QDEC_Periph.TASKS_READCLRACC'Address); + + -- Analof to Digital Converter (ADC) + ADC_START : constant Task_Type := + Task_Type (NRF_SVD.ADC.ADC_Periph.TASKS_START'Address); + ADC_STOP : constant Task_Type := + Task_Type (NRF_SVD.ADC.ADC_Periph.TASKS_STOP'Address); + +end nRF.Tasks; diff --git a/arch/ARM/Nordic/drivers/nrf52/nrf-adc.adb b/arch/ARM/Nordic/drivers/nrf52/nrf-adc.adb new file mode 100644 index 000000000..871fbc81b --- /dev/null +++ b/arch/ARM/Nordic/drivers/nrf52/nrf-adc.adb @@ -0,0 +1,184 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright © AdaCore and other contributors, 2017-2020 -- +-- See https://github.com/AdaCore/Ada_Drivers_Library/graphs/contributors -- +-- for more information -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of the copyright holder nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +------------------------------------------------------------------------------ + +with NRF_SVD.SAADC; use NRF_SVD.SAADC; +with nRF.Tasks; use nRF.Tasks; +with System.Storage_Elements; + +package body nRF.ADC is + + procedure Set_Resolution (Res : Bits_Resolution); + procedure Set_Reference (Ref : Reference_Selection); + procedure Wait_For_Result; + + -------------------- + -- Set_Resolution -- + -------------------- + + procedure Set_Resolution (Res : Bits_Resolution) is + + begin + SAADC_Periph.RESOLUTION.VAL := + (case Res is + when Res_8bit => Val_8BIT, + when Res_10bit => Val_10BIT, + when Res_12bit => Val_12BIT); + end Set_Resolution; + + ------------------- + -- Set_Reference -- + ------------------- + + procedure Set_Reference (Ref : Reference_Selection) is + begin + case Ref is + when Internal_0V6 => + SAADC_Periph.CH (0).CONFIG.REFSEL := Internal; + when VDD_One_Forth => + SAADC_Periph.CH (0).CONFIG.REFSEL := Vdd1_4; + end case; + end Set_Reference; + + -------------------------- + -- Start_Pin_Conversion -- + -------------------------- + + function Do_Pin_Conversion + (Pin : Analog_Pin; + Input : Pin_Input_Selection; + Ref : Reference_Selection; + Res : Bits_Resolution) return UInt16 + is + Result : UInt16 with Volatile; + begin + Set_Resolution (Res); + Set_Reference (Ref); + + SAADC_Periph.RESULT.PTR := UInt32 (System.Storage_Elements.To_Integer (Result'Address)); + SAADC_Periph.RESULT.MAXCNT.MAXCNT := 1; + + case Input is + when Pin_Quadruple => + SAADC_Periph.CH (0).CONFIG.GAIN := Gain4; + when Pin_Double => + SAADC_Periph.CH (0).CONFIG.GAIN := Gain2; + when Pin_Full => + SAADC_Periph.CH (0).CONFIG.GAIN := Gain1; + when Pin_Half => + SAADC_Periph.CH (0).CONFIG.GAIN := Gain1_2; + when Pin_One_Third => + SAADC_Periph.CH (0).CONFIG.GAIN := Gain1_3; + when Pin_One_Forth => + SAADC_Periph.CH (0).CONFIG.GAIN := Gain1_4; + when Pin_One_Fifth => + SAADC_Periph.CH (0).CONFIG.GAIN := Gain1_5; + when Pin_One_Sixth => + SAADC_Periph.CH (0).CONFIG.GAIN := Gain1_6; + end case; + + case Pin is + when 0 => + SAADC_Periph.CH (0).PSELP.PSELP := Analoginput0; + when 1 => + SAADC_Periph.CH (0).PSELP.PSELP := Analoginput1; + when 2 => + SAADC_Periph.CH (0).PSELP.PSELP := Analoginput2; + when 3 => + SAADC_Periph.CH (0).PSELP.PSELP := Analoginput3; + when 4 => + SAADC_Periph.CH (0).PSELP.PSELP := Analoginput4; + when 5 => + SAADC_Periph.CH (0).PSELP.PSELP := Analoginput5; + when 6 => + SAADC_Periph.CH (0).PSELP.PSELP := Analoginput6; + when 7 => + SAADC_Periph.CH (0).PSELP.PSELP := Analoginput7; + end case; + + SAADC_Periph.ENABLE.ENABLE := Enabled; + Trigger (ADC_START); + Wait_For_Result; + return Result; + end Do_Pin_Conversion; + + -------------------------- + -- Start_VDD_Conversion -- + -------------------------- + + function Do_VDD_Conversion + (Input : VDD_Input_Selection; + Ref : Reference_Selection; + Res : Bits_Resolution) return UInt16 + is + Result : UInt16 with Volatile; + begin + Set_Resolution (Res); + Set_Reference (Ref); + + SAADC_Periph.CH (0).PSELP.PSELP := Vdd; + SAADC_Periph.RESULT.PTR := UInt32 (System.Storage_Elements.To_Integer (Result'Address)); + SAADC_Periph.RESULT.MAXCNT.MAXCNT := 1; + + case Input is + when VDD_One_Fifth => + SAADC_Periph.CH (0).CONFIG.GAIN := Gain1_5; + when VDD_One_Sixth => + SAADC_Periph.CH (0).CONFIG.GAIN := Gain1_6; + end case; + + SAADC_Periph.ENABLE.ENABLE := Enabled; + Trigger (ADC_START); + Wait_For_Result; + return Result; + end Do_VDD_Conversion; + + ---------- + -- Busy -- + ---------- + + function Busy return Boolean + is (SAADC_Periph.STATUS.STATUS = Busy); + + --------------------- + -- Wait_For_Result -- + --------------------- + + procedure Wait_For_Result is + begin + while Busy loop + null; + end loop; + SAADC_Periph.ENABLE.ENABLE := Enabled; + end Wait_For_Result; + +end nRF.ADC; diff --git a/arch/ARM/Nordic/drivers/nrf52/nrf-adc.ads b/arch/ARM/Nordic/drivers/nrf52/nrf-adc.ads new file mode 100644 index 000000000..e00b09784 --- /dev/null +++ b/arch/ARM/Nordic/drivers/nrf52/nrf-adc.ads @@ -0,0 +1,62 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright © AdaCore and other contributors, 2017-2020 -- +-- See https://github.com/AdaCore/Ada_Drivers_Library/graphs/contributors -- +-- for more information -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of the copyright holder nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +------------------------------------------------------------------------------ + +with HAL; use HAL; + +package nRF.ADC is + + type Bits_Resolution is (Res_8bit, Res_10bit, Res_12bit); + + type Analog_Pin is range 0 .. 7; + + type Pin_Input_Selection is (Pin_Quadruple, Pin_Double, Pin_Full, Pin_Half, + Pin_One_Third, Pin_One_Forth, Pin_One_Fifth, + Pin_One_Sixth); + type VDD_Input_Selection is (VDD_One_Fifth, VDD_One_Sixth); + + type Reference_Selection is (Internal_0V6, VDD_One_Forth); + + function Do_Pin_Conversion + (Pin : Analog_Pin; + Input : Pin_Input_Selection; + Ref : Reference_Selection; + Res : Bits_Resolution) return UInt16; + + function Do_VDD_Conversion + (Input : VDD_Input_Selection; + Ref : Reference_Selection; + Res : Bits_Resolution) return UInt16; + + function Busy return Boolean; + +end nRF.ADC; diff --git a/arch/ARM/Nordic/drivers/nrf52/nrf-clock-set_high_freq_external_frequency.adb b/arch/ARM/Nordic/drivers/nrf52/nrf-clock-set_high_freq_external_frequency.adb new file mode 100644 index 000000000..c737a4c1c --- /dev/null +++ b/arch/ARM/Nordic/drivers/nrf52/nrf-clock-set_high_freq_external_frequency.adb @@ -0,0 +1,36 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright (C) 2020, AdaCore -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of the copyright holder nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +------------------------------------------------------------------------------ + +separate (nRF.Clock) +procedure Set_High_Freq_External_Frequency (Freq : High_Freq_Ext_Freq) is +begin + null; +end Set_High_Freq_External_Frequency; diff --git a/arch/ARM/Nordic/drivers/nrf52/nrf-events.ads b/arch/ARM/Nordic/drivers/nrf52/nrf-events.ads new file mode 100644 index 000000000..aa31e0214 --- /dev/null +++ b/arch/ARM/Nordic/drivers/nrf52/nrf-events.ads @@ -0,0 +1,381 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright (C) 2016-2020, AdaCore -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of the copyright holder nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +------------------------------------------------------------------------------ + +with System; +with NRF_SVD.POWER; +with NRF_SVD.CLOCK; +with NRF_SVD.GPIOTE; +with NRF_SVD.RADIO; +with NRF_SVD.TIMER; +with NRF_SVD.RTC; +with NRF_SVD.WDT; +with NRF_SVD.RNG; +with NRF_SVD.TEMP; +with NRF_SVD.ECB; +with NRF_SVD.CCM; +with NRF_SVD.AAR; +with NRF_SVD.SPI; +with NRF_SVD.TWI; +with NRF_SVD.UART; +with NRF_SVD.QDEC; +with NRF_SVD.SAADC; +with HAL; use HAL; + +package nRF.Events is + + function Triggered (Evt : Event_Type) return Boolean; + + procedure Enable_Interrupt (Evt : Event_Type); + + procedure Disable_Interrupt (Evt : Event_Type); + + procedure Clear (Evt : Event_Type); + -- Software event clear + + function Get_Address (Evt : Event_Type) return System.Address; + function Get_Address (Evt : Event_Type) return UInt32; + + -- Power management events + Power_POFWARN : constant Event_Type; + + -- Clock events + Clock_HFCLKSTARTED : constant Event_Type; + Clock_LFCLKSTARTED : constant Event_Type; + Clock_DONE : constant Event_Type; + Clock_CTTO : constant Event_Type; + + -- GPIOTE events + GPIOTE_IN_0 : constant Event_Type; + GPIOTE_IN_1 : constant Event_Type; + GPIOTE_IN_2 : constant Event_Type; + GPIOTE_IN_3 : constant Event_Type; + GPIOTE_PORT : constant Event_Type; + + -- Radio events + Radio_READY : constant Event_Type; + Radio_ADDRESS : constant Event_Type; + Radio_PAYLOAD : constant Event_Type; + Radio_END : constant Event_Type; + Radio_DISABLED : constant Event_Type; + Radio_DEVMATCH : constant Event_Type; + Radio_DEVMISS : constant Event_Type; + Radio_RSSIEND : constant Event_Type; + Radio_BCMATCH : constant Event_Type; + + -- Timer 0 events + Timer_0_COMPARE_0 : constant Event_Type; + Timer_0_COMPARE_1 : constant Event_Type; + Timer_0_COMPARE_2 : constant Event_Type; + Timer_0_COMPARE_3 : constant Event_Type; + + -- Timer 1 events + Timer_1_COMPARE_0 : constant Event_Type; + Timer_1_COMPARE_1 : constant Event_Type; + Timer_1_COMPARE_2 : constant Event_Type; + Timer_1_COMPARE_3 : constant Event_Type; + + -- Timer 2 events + Timer_2_COMPARE_0 : constant Event_Type; + Timer_2_COMPARE_1 : constant Event_Type; + Timer_2_COMPARE_2 : constant Event_Type; + Timer_2_COMPARE_3 : constant Event_Type; + + -- RTC 0 events + RTC_0_TICK : constant Event_Type; + RTC_0_OVERFLW : constant Event_Type; + RTC_0_COMPARE_0 : constant Event_Type; + RTC_0_COMPARE_1 : constant Event_Type; + RTC_0_COMPARE_2 : constant Event_Type; + RTC_0_COMPARE_3 : constant Event_Type; + + -- RTC 1 events + RTC_1_TICK : constant Event_Type; + RTC_1_OVERFLW : constant Event_Type; + RTC_1_COMPARE_0 : constant Event_Type; + RTC_1_COMPARE_1 : constant Event_Type; + RTC_1_COMPARE_2 : constant Event_Type; + RTC_1_COMPARE_3 : constant Event_Type; + + -- Watchdog task + Watchdog_TIMEOUT : constant Event_Type; + + -- Random Number Genrator events + RNG_VALRDY : constant Event_Type; + + -- Temperature events + Temperature_DATARDY : constant Event_Type; + + -- AES Electronic Codebook mode encryption (ECB) events + ECB_END : constant Event_Type; + ECB_ERROR : constant Event_Type; + + -- AES CCM mode encryption (CCM) events + CCM_KSGEN_END : constant Event_Type; + CCM_CRYPT_END : constant Event_Type; + CCM_ERROR : constant Event_Type; + + -- Accelerated Address Resolver (AAR) events + AAR_END : constant Event_Type; + AAR_RESOLVED : constant Event_Type; + AAR_NOTRESOLVED : constant Event_Type; + + -- Serial Peripheral Interface (SPI) 0 events + SPI_0_READY : constant Event_Type; + + -- Serial Peripheral Interface (SPI) 1 events + SPI_1_READY : constant Event_Type; + + -- Two Wire Interface (TWI) 0 events + TWI_0_STOPPED : constant Event_Type; + TWI_0_RXDRDY : constant Event_Type; + TWI_0_TXDENT : constant Event_Type; + TWI_0_ERRO : constant Event_Type; + TWI_0_BB : constant Event_Type; + TWI_0_SUSPENDED : constant Event_Type; + + -- Two Wire Interface (TWI) 1 events + TWI_1_STOPPED : constant Event_Type; + TWI_1_RXDRDY : constant Event_Type; + TWI_1_TXDENT : constant Event_Type; + TWI_1_ERRO : constant Event_Type; + TWI_1_BB : constant Event_Type; + TWI_1_SUSPENDED : constant Event_Type; + + -- Universal Asynchronous Receiver/Transmitter (UART) Events + UART_RXDRDY : constant Event_Type; + UART_TXDRDY : constant Event_Type; + UART_ERROR : constant Event_Type; + + -- Quadrature Decoder (QDEC) + QDEC_SAMPLERDY : constant Event_Type; + QDEC_REPORTRDY : constant Event_Type; + QDEC_ACCOF : constant Event_Type; + + -- Analof to Digital Converter (ADC) + ADC_END : constant Event_Type; + +private + + -- Power management events + Power_POFWARN : constant Event_Type := + Event_Type (NRF_SVD.POWER.POWER_Periph.EVENTS_POFWARN'Address); + + -- Clock events + Clock_HFCLKSTARTED : constant Event_Type := + Event_Type (NRF_SVD.CLOCK.CLOCK_Periph.EVENTS_HFCLKSTARTED'Address); + Clock_LFCLKSTARTED : constant Event_Type := + Event_Type (NRF_SVD.CLOCK.CLOCK_Periph.EVENTS_LFCLKSTARTED'Address); + Clock_DONE : constant Event_Type := + Event_Type (NRF_SVD.CLOCK.CLOCK_Periph.EVENTS_DONE'Address); + Clock_CTTO : constant Event_Type := + Event_Type (NRF_SVD.CLOCK.CLOCK_Periph.EVENTS_CTTO'Address); + + -- GPIOTE events + GPIOTE_IN_0 : constant Event_Type := + Event_Type (NRF_SVD.GPIOTE.GPIOTE_Periph.EVENTS_IN (0)'Address); + GPIOTE_IN_1 : constant Event_Type := + Event_Type (NRF_SVD.GPIOTE.GPIOTE_Periph.EVENTS_IN (1)'Address); + GPIOTE_IN_2 : constant Event_Type := + Event_Type (NRF_SVD.GPIOTE.GPIOTE_Periph.EVENTS_IN (2)'Address); + GPIOTE_IN_3 : constant Event_Type := + Event_Type (NRF_SVD.GPIOTE.GPIOTE_Periph.EVENTS_IN (3)'Address); + GPIOTE_PORT : constant Event_Type := + Event_Type (NRF_SVD.GPIOTE.GPIOTE_Periph.EVENTS_PORT'Address); + + -- Radio events + Radio_READY : constant Event_Type := + Event_Type (NRF_SVD.RADIO.RADIO_Periph.EVENTS_READY'Address); + Radio_ADDRESS : constant Event_Type := + Event_Type (NRF_SVD.RADIO.RADIO_Periph.EVENTS_ADDRESS'Address); + Radio_PAYLOAD : constant Event_Type := + Event_Type (NRF_SVD.RADIO.RADIO_Periph.EVENTS_PAYLOAD'Address); + Radio_END : constant Event_Type := + Event_Type (NRF_SVD.RADIO.RADIO_Periph.EVENTS_END'Address); + Radio_DISABLED : constant Event_Type := + Event_Type (NRF_SVD.RADIO.RADIO_Periph.EVENTS_DISABLED'Address); + Radio_DEVMATCH : constant Event_Type := + Event_Type (NRF_SVD.RADIO.RADIO_Periph.EVENTS_DEVMATCH'Address); + Radio_DEVMISS : constant Event_Type := + Event_Type (NRF_SVD.RADIO.RADIO_Periph.EVENTS_DEVMISS'Address); + Radio_RSSIEND : constant Event_Type := + Event_Type (NRF_SVD.RADIO.RADIO_Periph.EVENTS_RSSIEND'Address); + Radio_BCMATCH : constant Event_Type := + Event_Type (NRF_SVD.RADIO.RADIO_Periph.EVENTS_BCMATCH'Address); + + -- Timer 0 events + Timer_0_COMPARE_0 : constant Event_Type := + Event_Type (NRF_SVD.TIMER.TIMER0_Periph.EVENTS_COMPARE (0)'Address); + Timer_0_COMPARE_1 : constant Event_Type := + Event_Type (NRF_SVD.TIMER.TIMER0_Periph.EVENTS_COMPARE (1)'Address); + Timer_0_COMPARE_2 : constant Event_Type := + Event_Type (NRF_SVD.TIMER.TIMER0_Periph.EVENTS_COMPARE (2)'Address); + Timer_0_COMPARE_3 : constant Event_Type := + Event_Type (NRF_SVD.TIMER.TIMER0_Periph.EVENTS_COMPARE (3)'Address); + + -- Timer 1 events + Timer_1_COMPARE_0 : constant Event_Type := + Event_Type (NRF_SVD.TIMER.TIMER1_Periph.EVENTS_COMPARE (0)'Address); + Timer_1_COMPARE_1 : constant Event_Type := + Event_Type (NRF_SVD.TIMER.TIMER1_Periph.EVENTS_COMPARE (1)'Address); + Timer_1_COMPARE_2 : constant Event_Type := + Event_Type (NRF_SVD.TIMER.TIMER1_Periph.EVENTS_COMPARE (2)'Address); + Timer_1_COMPARE_3 : constant Event_Type := + Event_Type (NRF_SVD.TIMER.TIMER1_Periph.EVENTS_COMPARE (3)'Address); + + -- Timer 2 events + Timer_2_COMPARE_0 : constant Event_Type := + Event_Type (NRF_SVD.TIMER.TIMER2_Periph.EVENTS_COMPARE (0)'Address); + Timer_2_COMPARE_1 : constant Event_Type := + Event_Type (NRF_SVD.TIMER.TIMER2_Periph.EVENTS_COMPARE (1)'Address); + Timer_2_COMPARE_2 : constant Event_Type := + Event_Type (NRF_SVD.TIMER.TIMER2_Periph.EVENTS_COMPARE (2)'Address); + Timer_2_COMPARE_3 : constant Event_Type := + Event_Type (NRF_SVD.TIMER.TIMER2_Periph.EVENTS_COMPARE (3)'Address); + + -- RTC 0 events + RTC_0_TICK : constant Event_Type := + Event_Type (NRF_SVD.RTC.RTC0_Periph.EVENTS_TICK'Address); + RTC_0_OVERFLW : constant Event_Type := + Event_Type (NRF_SVD.RTC.RTC0_Periph.EVENTS_OVRFLW'Address); + RTC_0_COMPARE_0 : constant Event_Type := + Event_Type (NRF_SVD.RTC.RTC0_Periph.EVENTS_COMPARE (0)'Address); + RTC_0_COMPARE_1 : constant Event_Type := + Event_Type (NRF_SVD.RTC.RTC0_Periph.EVENTS_COMPARE (1)'Address); + RTC_0_COMPARE_2 : constant Event_Type := + Event_Type (NRF_SVD.RTC.RTC0_Periph.EVENTS_COMPARE (2)'Address); + RTC_0_COMPARE_3 : constant Event_Type := + Event_Type (NRF_SVD.RTC.RTC0_Periph.EVENTS_COMPARE (3)'Address); + + -- RTC 1 events + RTC_1_TICK : constant Event_Type := + Event_Type (NRF_SVD.RTC.RTC1_Periph.EVENTS_TICK'Address); + RTC_1_OVERFLW : constant Event_Type := + Event_Type (NRF_SVD.RTC.RTC1_Periph.EVENTS_OVRFLW'Address); + RTC_1_COMPARE_0 : constant Event_Type := + Event_Type (NRF_SVD.RTC.RTC1_Periph.EVENTS_COMPARE (0)'Address); + RTC_1_COMPARE_1 : constant Event_Type := + Event_Type (NRF_SVD.RTC.RTC1_Periph.EVENTS_COMPARE (1)'Address); + RTC_1_COMPARE_2 : constant Event_Type := + Event_Type (NRF_SVD.RTC.RTC1_Periph.EVENTS_COMPARE (2)'Address); + RTC_1_COMPARE_3 : constant Event_Type := + Event_Type (NRF_SVD.RTC.RTC1_Periph.EVENTS_COMPARE (3)'Address); + + -- Watchdog task + Watchdog_TIMEOUT : constant Event_Type := + Event_Type (NRF_SVD.WDT.WDT_Periph.EVENTS_TIMEOUT'Address); + + -- Random Number Genrator events + RNG_VALRDY : constant Event_Type := + Event_Type (NRF_SVD.RNG.RNG_Periph.EVENTS_VALRDY'Address); + + -- Temperature events + Temperature_DATARDY : constant Event_Type := + Event_Type (NRF_SVD.TEMP.TEMP_Periph.EVENTS_DATARDY'Address); + + -- AES Electronic Codebook mode encryption (ECB) events + ECB_END : constant Event_Type := + Event_Type (NRF_SVD.ECB.ECB_Periph.EVENTS_ENDECB'Address); + ECB_ERROR : constant Event_Type := + Event_Type (NRF_SVD.ECB.ECB_Periph.EVENTS_ERRORECB'Address); + + -- AES CCM mode encryption (CCM) events + CCM_KSGEN_END : constant Event_Type := + Event_Type (NRF_SVD.CCM.CCM_Periph.EVENTS_ENDKSGEN'Address); + CCM_CRYPT_END : constant Event_Type := + Event_Type (NRF_SVD.CCM.CCM_Periph.EVENTS_ENDCRYPT'Address); + CCM_ERROR : constant Event_Type := + Event_Type (NRF_SVD.CCM.CCM_Periph.EVENTS_ERROR'Address); + + -- Accelerated Address Resolver (AAR) events + AAR_END : constant Event_Type := + Event_Type (NRF_SVD.AAR.AAR_Periph.EVENTS_END'Address); + AAR_RESOLVED : constant Event_Type := + Event_Type (NRF_SVD.AAR.AAR_Periph.EVENTS_RESOLVED'Address); + AAR_NOTRESOLVED : constant Event_Type := + Event_Type (NRF_SVD.AAR.AAR_Periph.EVENTS_NOTRESOLVED'Address); + + -- Serial Peripheral Interface (SPI) events + SPI_0_READY : constant Event_Type := + Event_Type (NRF_SVD.SPI.SPI0_Periph.EVENTS_READY'Address); + + -- Serial Peripheral Interface (SPI) events + SPI_1_READY : constant Event_Type := + Event_Type (NRF_SVD.SPI.SPI1_Periph.EVENTS_READY'Address); + + -- Two Wire Interface (TWI) 0 events + TWI_0_STOPPED : constant Event_Type := + Event_Type (NRF_SVD.TWI.TWI0_Periph.EVENTS_STOPPED'Address); + TWI_0_RXDRDY : constant Event_Type := + Event_Type (NRF_SVD.TWI.TWI0_Periph.EVENTS_RXDREADY'Address); + TWI_0_TXDENT : constant Event_Type := + Event_Type (NRF_SVD.TWI.TWI0_Periph.EVENTS_TXDSENT'Address); + TWI_0_ERRO : constant Event_Type := + Event_Type (NRF_SVD.TWI.TWI0_Periph.EVENTS_ERROR'Address); + TWI_0_BB : constant Event_Type := + Event_Type (NRF_SVD.TWI.TWI0_Periph.EVENTS_BB'Address); + TWI_0_SUSPENDED : constant Event_Type := + Event_Type (NRF_SVD.TWI.TWI0_Periph.EVENTS_SUSPENDED'Address); + + -- Two Wire Interface (TWI) 1 events + TWI_1_STOPPED : constant Event_Type := + Event_Type (NRF_SVD.TWI.TWI1_Periph.EVENTS_STOPPED'Address); + TWI_1_RXDRDY : constant Event_Type := + Event_Type (NRF_SVD.TWI.TWI1_Periph.EVENTS_RXDREADY'Address); + TWI_1_TXDENT : constant Event_Type := + Event_Type (NRF_SVD.TWI.TWI1_Periph.EVENTS_TXDSENT'Address); + TWI_1_ERRO : constant Event_Type := + Event_Type (NRF_SVD.TWI.TWI1_Periph.EVENTS_ERROR'Address); + TWI_1_BB : constant Event_Type := + Event_Type (NRF_SVD.TWI.TWI1_Periph.EVENTS_BB'Address); + TWI_1_SUSPENDED : constant Event_Type := + Event_Type (NRF_SVD.TWI.TWI1_Periph.EVENTS_SUSPENDED'Address); + + -- Universal Asynchronous Receiver/Transmitter (UART) Events + UART_RXDRDY : constant Event_Type := + Event_Type (NRF_SVD.UART.UART0_Periph.EVENTS_RXDRDY'Address); + UART_TXDRDY : constant Event_Type := + Event_Type (NRF_SVD.UART.UART0_Periph.EVENTS_TXDRDY'Address); + UART_ERROR : constant Event_Type := + Event_Type (NRF_SVD.UART.UART0_Periph.EVENTS_ERROR'Address); + + -- Quadrature Decoder (QDEC) + QDEC_SAMPLERDY : constant Event_Type := + Event_Type (NRF_SVD.QDEC.QDEC_Periph.EVENTS_SAMPLERDY'Address); + QDEC_REPORTRDY : constant Event_Type := + Event_Type (NRF_SVD.QDEC.QDEC_Periph.EVENTS_REPORTRDY'Address); + QDEC_ACCOF : constant Event_Type := + Event_Type (NRF_SVD.QDEC.QDEC_Periph.EVENTS_ACCOF'Address); + + -- Analof to Digital Converter (ADC) + ADC_END : constant Event_Type := + Event_Type (NRF_SVD.SAADC.SAADC_Periph.EVENTS_END'Address); + +end nRF.Events; diff --git a/arch/ARM/Nordic/drivers/nrf52/nrf-interrupts.ads b/arch/ARM/Nordic/drivers/nrf52/nrf-interrupts.ads new file mode 100644 index 000000000..d9a619837 --- /dev/null +++ b/arch/ARM/Nordic/drivers/nrf52/nrf-interrupts.ads @@ -0,0 +1,119 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright (C) 2016-2020, AdaCore -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of the copyright holder nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +------------------------------------------------------------------------------ + +with Cortex_M.NVIC; + +package nRF.Interrupts is + + type Interrupt_Name is + (POWER_CLOCK_Interrupt, + RADIO_Interrupt, + UART0_Interrupt, + SPI0_TWI0_Interrupt, + SPI1_TWI1_Interrupt, + Unused_Interrupt_1, + GPIOTE_Interrupt, + ADC_Interrupt, + TIMER0_Interrupt, + TIMER1_Interrupt, + TIMER2_Interrupt, + RTC0_Interrupt, + TEMP_Interrupt, + RNG_Interrupt, + ECB_Interrupt, + CCM_AAR_Interrupt, + WDT_Interrupt, + RTC1_Interrupt, + QDEC_Interrupt, + LPCOMP_Interrupt, + SWI0_Interrupt, + SWI1_Interrupt, + SWI2_Interrupt, + SWI3_Interrupt, + SWI4_Interrupt, + SWI5_Interrupt, + Unused_Interrupt_2, + Unused_Interrupt_3, + Unused_Interrupt_4, + Unused_Interrupt_5, + Unused_Interrupt_6, + Unused_Interrupt_7); + + subtype Interrupt_Priority is Cortex_M.NVIC.Interrupt_Priority; + + procedure Set_Priority (Int : Interrupt_Name; Prio : Interrupt_Priority); + procedure Enable (Int : Interrupt_Name); + procedure Disable (Int : Interrupt_Name); + function Pending (Int : Interrupt_Name) return Boolean; + + type Handler is access procedure; + + procedure Register (Id : nRF.Interrupts.Interrupt_Name; + Hdl : Handler); + -- Register a handler for the given interrupt. There can be only one handler + -- for each interrupt so the previous one, if any, will be removed. + +private + for Interrupt_Name use + (POWER_CLOCK_Interrupt => 0, + RADIO_Interrupt => 1, + UART0_Interrupt => 2, + SPI0_TWI0_Interrupt => 3, + SPI1_TWI1_Interrupt => 4, + Unused_Interrupt_1 => 5, + GPIOTE_Interrupt => 6, + ADC_Interrupt => 7, + TIMER0_Interrupt => 8, + TIMER1_Interrupt => 9, + TIMER2_Interrupt => 10, + RTC0_Interrupt => 11, + TEMP_Interrupt => 12, + RNG_Interrupt => 13, + ECB_Interrupt => 14, + CCM_AAR_Interrupt => 15, + WDT_Interrupt => 16, + RTC1_Interrupt => 17, + QDEC_Interrupt => 18, + LPCOMP_Interrupt => 19, + SWI0_Interrupt => 20, + SWI1_Interrupt => 21, + SWI2_Interrupt => 22, + SWI3_Interrupt => 23, + SWI4_Interrupt => 24, + SWI5_Interrupt => 25, + Unused_Interrupt_2 => 26, + Unused_Interrupt_3 => 27, + Unused_Interrupt_4 => 28, + Unused_Interrupt_5 => 29, + Unused_Interrupt_6 => 30, + Unused_Interrupt_7 => 31); + +end nRF.Interrupts; diff --git a/arch/ARM/Nordic/drivers/nrf52/nrf-ppi.adb b/arch/ARM/Nordic/drivers/nrf52/nrf-ppi.adb new file mode 100644 index 000000000..2db5b797b --- /dev/null +++ b/arch/ARM/Nordic/drivers/nrf52/nrf-ppi.adb @@ -0,0 +1,116 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright (C) 2016-2020, AdaCore -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of the copyright holder nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +------------------------------------------------------------------------------ + +with NRF_SVD.PPI; use NRF_SVD.PPI; +with nRF.Events; use nRF.Events; +with nRF.Tasks; use nRF.Tasks; + +package body nRF.PPI is + + --------------- + -- Configure -- + --------------- + + procedure Configure + (Chan : Channel_ID; + Evt_EP : Event_Type; + Task_EP : Task_Type) + is + begin + PPI_Periph.CH (Chan).EEP := Get_Address (Evt_EP); + PPI_Periph.CH (Chan).TEP := Get_Address (Task_EP); + end Configure; + + -------------------- + -- Enable_Channel -- + -------------------- + + procedure Enable_Channel (Chan : Channel_ID) is + Arr : CHENSET_CH_Field_Array := (others => Chenset_Ch0_Field_Reset); + begin + Arr (Chan) := Set; + PPI_Periph.CHENSET.Arr := Arr; + end Enable_Channel; + + --------------------- + -- Disable_Channel -- + --------------------- + + procedure Disable_Channel (Chan : Channel_ID) is + Arr : CHENCLR_CH_Field_Array := (others => Chenclr_Ch0_Field_Reset); + begin + Arr (Chan) := Clear; + PPI_Periph.CHENCLR.Arr := Arr; + end Disable_Channel; + + ------------------ + -- Add_To_Group -- + ------------------ + + procedure Add_To_Group + (Chan : Channel_ID; + Group : Group_ID) + is + begin + PPI_Periph.CHG (Group).Arr (Chan) := Included; + end Add_To_Group; + + ----------------------- + -- Remove_From_Group -- + ----------------------- + + procedure Remove_From_Group + (Chan : Channel_ID; + Group : Group_ID) + is + begin + PPI_Periph.CHG (Group).Arr (Chan) := Excluded; + end Remove_From_Group; + + ------------------ + -- Enable_Group -- + ------------------ + + procedure Enable_Group (Group : Group_ID) is + begin + PPI_Periph.TASKS_CHG (Group).EN := 1; + end Enable_Group; + + ------------------- + -- Disable_Group -- + ------------------- + + procedure Disable_Group (Group : Group_ID) is + begin + PPI_Periph.TASKS_CHG (Group).DIS := 1; + end Disable_Group; + +end nRF.PPI; diff --git a/arch/ARM/Nordic/drivers/nrf52/nrf-ppi.ads b/arch/ARM/Nordic/drivers/nrf52/nrf-ppi.ads new file mode 100644 index 000000000..7d283d704 --- /dev/null +++ b/arch/ARM/Nordic/drivers/nrf52/nrf-ppi.ads @@ -0,0 +1,51 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright (C) 2016-2020, AdaCore -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of the copyright holder nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +------------------------------------------------------------------------------ + +package nRF.PPI is + + subtype Channel_ID is Natural range 0 .. 15; + subtype Group_ID is Natural range 0 .. 5; + + procedure Configure (Chan : Channel_ID; + Evt_EP : Event_Type; + Task_EP : Task_Type); + + procedure Enable_Channel (Chan : Channel_ID); + procedure Disable_Channel (Chan : Channel_ID); + + procedure Add_To_Group (Chan : Channel_ID; + Group : Group_ID); + procedure Remove_From_Group (Chan : Channel_ID; + Group : Group_ID); + + procedure Enable_Group (Group : Group_ID); + procedure Disable_Group (Group : Group_ID); +end nRF.PPI; diff --git a/arch/ARM/Nordic/drivers/nrf51-tasks.ads b/arch/ARM/Nordic/drivers/nrf52/nrf-tasks.ads similarity index 65% rename from arch/ARM/Nordic/drivers/nrf51-tasks.ads rename to arch/ARM/Nordic/drivers/nrf52/nrf-tasks.ads index 74b89d239..a18192200 100644 --- a/arch/ARM/Nordic/drivers/nrf51-tasks.ads +++ b/arch/ARM/Nordic/drivers/nrf52/nrf-tasks.ads @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2016, AdaCore -- +-- Copyright (C) 2016-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -30,27 +30,26 @@ ------------------------------------------------------------------------------ with System; -with NRF51_SVD.POWER; -with NRF51_SVD.CLOCK; -with NRF51_SVD.GPIOTE; -with NRF51_SVD.PPI; -with NRF51_SVD.RADIO; -with NRF51_SVD.TIMER; -with NRF51_SVD.RTC; -with NRF51_SVD.WDT; -with NRF51_SVD.RNG; -with NRF51_SVD.TEMP; -with NRF51_SVD.ECB; -with NRF51_SVD.CCM; -with NRF51_SVD.AAR; -with NRF51_SVD.TWI; -with NRF51_SVD.UART; -with NRF51_SVD.QDEC; -with NRF51_SVD.ADC; +with NRF_SVD.POWER; +with NRF_SVD.CLOCK; +with NRF_SVD.GPIOTE; +with NRF_SVD.PPI; +with NRF_SVD.RADIO; +with NRF_SVD.TIMER; +with NRF_SVD.RTC; +with NRF_SVD.WDT; +with NRF_SVD.RNG; +with NRF_SVD.TEMP; +with NRF_SVD.ECB; +with NRF_SVD.CCM; +with NRF_SVD.AAR; +with NRF_SVD.TWI; +with NRF_SVD.UART; +with NRF_SVD.QDEC; +with NRF_SVD.SAADC; with HAL; use HAL; - -package nRF51.Tasks is +package nRF.Tasks is procedure Trigger (T : Task_Type); -- Software task trigger @@ -196,230 +195,230 @@ private -- Power management tasks Power_CONSTLAT : constant Task_Type := - Task_Type (NRF51_SVD.POWER.POWER_Periph.TASKS_CONSTLAT'Address); + Task_Type (NRF_SVD.POWER.POWER_Periph.TASKS_CONSTLAT'Address); Power_LOWPWR : constant Task_Type := - Task_Type (NRF51_SVD.POWER.POWER_Periph.TASKS_LOWPWR'Address); + Task_Type (NRF_SVD.POWER.POWER_Periph.TASKS_LOWPWR'Address); -- Clock tasks Clock_HFCLKSTART : constant Task_Type := - Task_Type (NRF51_SVD.CLOCK.CLOCK_Periph.TASKS_HFCLKSTART'Address); + Task_Type (NRF_SVD.CLOCK.CLOCK_Periph.TASKS_HFCLKSTART'Address); Clock_HFCLKSTOP : constant Task_Type := - Task_Type (NRF51_SVD.CLOCK.CLOCK_Periph.TASKS_HFCLKSTOP'Address); + Task_Type (NRF_SVD.CLOCK.CLOCK_Periph.TASKS_HFCLKSTOP'Address); Clock_LFCLKSTART : constant Task_Type := - Task_Type (NRF51_SVD.CLOCK.CLOCK_Periph.TASKS_LFCLKSTART'Address); + Task_Type (NRF_SVD.CLOCK.CLOCK_Periph.TASKS_LFCLKSTART'Address); Clock_LFCLKSTOP : constant Task_Type := - Task_Type (NRF51_SVD.CLOCK.CLOCK_Periph.TASKS_LFCLKSTOP'Address); + Task_Type (NRF_SVD.CLOCK.CLOCK_Periph.TASKS_LFCLKSTOP'Address); Clock_CAL : constant Task_Type := - Task_Type (NRF51_SVD.CLOCK.CLOCK_Periph.TASKS_CAL'Address); + Task_Type (NRF_SVD.CLOCK.CLOCK_Periph.TASKS_CAL'Address); Clock_CTSTART : constant Task_Type := - Task_Type (NRF51_SVD.CLOCK.CLOCK_Periph.TASKS_CTSTART'Address); + Task_Type (NRF_SVD.CLOCK.CLOCK_Periph.TASKS_CTSTART'Address); Clock_CTSTOP : constant Task_Type := - Task_Type (NRF51_SVD.CLOCK.CLOCK_Periph.TASKS_CTSTOP'Address); + Task_Type (NRF_SVD.CLOCK.CLOCK_Periph.TASKS_CTSTOP'Address); -- GPIOTE tasks GPIOTE_OUT_0 : constant Task_Type := - Task_Type (NRF51_SVD.GPIOTE.GPIOTE_Periph.TASKS_OUT (0)'Address); + Task_Type (NRF_SVD.GPIOTE.GPIOTE_Periph.TASKS_OUT (0)'Address); GPIOTE_OUT_1 : constant Task_Type := - Task_Type (NRF51_SVD.GPIOTE.GPIOTE_Periph.TASKS_OUT (1)'Address); + Task_Type (NRF_SVD.GPIOTE.GPIOTE_Periph.TASKS_OUT (1)'Address); GPIOTE_OUT_2 : constant Task_Type := - Task_Type (NRF51_SVD.GPIOTE.GPIOTE_Periph.TASKS_OUT (2)'Address); + Task_Type (NRF_SVD.GPIOTE.GPIOTE_Periph.TASKS_OUT (2)'Address); GPIOTE_OUT_3 : constant Task_Type := - Task_Type (NRF51_SVD.GPIOTE.GPIOTE_Periph.TASKS_OUT (3)'Address); + Task_Type (NRF_SVD.GPIOTE.GPIOTE_Periph.TASKS_OUT (3)'Address); -- Programmable Peripheral Interconnect Tasks PPI_CHG_0_EN : constant Task_Type := - Task_Type (NRF51_SVD.PPI.PPI_Periph.TASKS_CHG (0).EN'Address); + Task_Type (NRF_SVD.PPI.PPI_Periph.TASKS_CHG (0).EN'Address); PPI_CHG_0_DIS : constant Task_Type := - Task_Type (NRF51_SVD.PPI.PPI_Periph.TASKS_CHG (0).DIS'Address); + Task_Type (NRF_SVD.PPI.PPI_Periph.TASKS_CHG (0).DIS'Address); PPI_CHG_1_EN : constant Task_Type := - Task_Type (NRF51_SVD.PPI.PPI_Periph.TASKS_CHG (1).EN'Address); + Task_Type (NRF_SVD.PPI.PPI_Periph.TASKS_CHG (1).EN'Address); PPI_CHG_1_DIS : constant Task_Type := - Task_Type (NRF51_SVD.PPI.PPI_Periph.TASKS_CHG (1).DIS'Address); + Task_Type (NRF_SVD.PPI.PPI_Periph.TASKS_CHG (1).DIS'Address); PPI_CHG_2_EN : constant Task_Type := - Task_Type (NRF51_SVD.PPI.PPI_Periph.TASKS_CHG (2).EN'Address); + Task_Type (NRF_SVD.PPI.PPI_Periph.TASKS_CHG (2).EN'Address); PPI_CHG_2_DIS : constant Task_Type := - Task_Type (NRF51_SVD.PPI.PPI_Periph.TASKS_CHG (2).DIS'Address); + Task_Type (NRF_SVD.PPI.PPI_Periph.TASKS_CHG (2).DIS'Address); PPI_CHG_3_EN : constant Task_Type := - Task_Type (NRF51_SVD.PPI.PPI_Periph.TASKS_CHG (3).EN'Address); + Task_Type (NRF_SVD.PPI.PPI_Periph.TASKS_CHG (3).EN'Address); PPI_CHG_3_DIS : constant Task_Type := - Task_Type (NRF51_SVD.PPI.PPI_Periph.TASKS_CHG (3).DIS'Address); + Task_Type (NRF_SVD.PPI.PPI_Periph.TASKS_CHG (3).DIS'Address); -- Radio tasks Radio_TXEN : constant Task_Type := - Task_Type (NRF51_SVD.RADIO.RADIO_Periph.TASKS_TXEN'Address); + Task_Type (NRF_SVD.RADIO.RADIO_Periph.TASKS_TXEN'Address); Radio_RXEN : constant Task_Type := - Task_Type (NRF51_SVD.RADIO.RADIO_Periph.TASKS_RXEN'Address); + Task_Type (NRF_SVD.RADIO.RADIO_Periph.TASKS_RXEN'Address); Radio_START : constant Task_Type := - Task_Type (NRF51_SVD.RADIO.RADIO_Periph.TASKS_START'Address); + Task_Type (NRF_SVD.RADIO.RADIO_Periph.TASKS_START'Address); Radio_STOP : constant Task_Type := - Task_Type (NRF51_SVD.RADIO.RADIO_Periph.TASKS_STOP'Address); + Task_Type (NRF_SVD.RADIO.RADIO_Periph.TASKS_STOP'Address); Radio_DISABLE : constant Task_Type := - Task_Type (NRF51_SVD.RADIO.RADIO_Periph.TASKS_DISABLE'Address); + Task_Type (NRF_SVD.RADIO.RADIO_Periph.TASKS_DISABLE'Address); Radio_RSSISTART : constant Task_Type := - Task_Type (NRF51_SVD.RADIO.RADIO_Periph.TASKS_RSSISTART'Address); + Task_Type (NRF_SVD.RADIO.RADIO_Periph.TASKS_RSSISTART'Address); Radio_RSSISTOP : constant Task_Type := - Task_Type (NRF51_SVD.RADIO.RADIO_Periph.TASKS_RSSISTOP'Address); + Task_Type (NRF_SVD.RADIO.RADIO_Periph.TASKS_RSSISTOP'Address); Radio_BCSTART : constant Task_Type := - Task_Type (NRF51_SVD.RADIO.RADIO_Periph.TASKS_BCSTART'Address); + Task_Type (NRF_SVD.RADIO.RADIO_Periph.TASKS_BCSTART'Address); Radio_BCSTOP : constant Task_Type := - Task_Type (NRF51_SVD.RADIO.RADIO_Periph.TASKS_BCSTOP'Address); + Task_Type (NRF_SVD.RADIO.RADIO_Periph.TASKS_BCSTOP'Address); -- Timer 0 tasks Timer_0_START : constant Task_Type := - Task_Type (NRF51_SVD.TIMER.TIMER0_Periph.TASKS_START'Address); + Task_Type (NRF_SVD.TIMER.TIMER0_Periph.TASKS_START'Address); Timer_0_STOP : constant Task_Type := - Task_Type (NRF51_SVD.TIMER.TIMER0_Periph.TASKS_START'Address); + Task_Type (NRF_SVD.TIMER.TIMER0_Periph.TASKS_START'Address); Timer_0_COUNT : constant Task_Type := - Task_Type (NRF51_SVD.TIMER.TIMER0_Periph.TASKS_START'Address); + Task_Type (NRF_SVD.TIMER.TIMER0_Periph.TASKS_START'Address); Timer_0_CLEAR : constant Task_Type := - Task_Type (NRF51_SVD.TIMER.TIMER0_Periph.TASKS_START'Address); + Task_Type (NRF_SVD.TIMER.TIMER0_Periph.TASKS_START'Address); Timer_0_CAPTURE_0 : constant Task_Type := - Task_Type (NRF51_SVD.TIMER.TIMER0_Periph.TASKS_START'Address); + Task_Type (NRF_SVD.TIMER.TIMER0_Periph.TASKS_START'Address); Timer_0_CAPTURE_1 : constant Task_Type := - Task_Type (NRF51_SVD.TIMER.TIMER0_Periph.TASKS_START'Address); + Task_Type (NRF_SVD.TIMER.TIMER0_Periph.TASKS_START'Address); Timer_0_CAPTURE_2 : constant Task_Type := - Task_Type (NRF51_SVD.TIMER.TIMER0_Periph.TASKS_START'Address); + Task_Type (NRF_SVD.TIMER.TIMER0_Periph.TASKS_START'Address); Timer_0_CAPTURE_3 : constant Task_Type := - Task_Type (NRF51_SVD.TIMER.TIMER0_Periph.TASKS_START'Address); + Task_Type (NRF_SVD.TIMER.TIMER0_Periph.TASKS_START'Address); -- Timer 1 tasks Timer_1_START : constant Task_Type := - Task_Type (NRF51_SVD.TIMER.TIMER1_Periph.TASKS_START'Address); + Task_Type (NRF_SVD.TIMER.TIMER1_Periph.TASKS_START'Address); Timer_1_STOP : constant Task_Type := - Task_Type (NRF51_SVD.TIMER.TIMER1_Periph.TASKS_START'Address); + Task_Type (NRF_SVD.TIMER.TIMER1_Periph.TASKS_START'Address); Timer_1_COUNT : constant Task_Type := - Task_Type (NRF51_SVD.TIMER.TIMER1_Periph.TASKS_START'Address); + Task_Type (NRF_SVD.TIMER.TIMER1_Periph.TASKS_START'Address); Timer_1_CLEAR : constant Task_Type := - Task_Type (NRF51_SVD.TIMER.TIMER1_Periph.TASKS_START'Address); + Task_Type (NRF_SVD.TIMER.TIMER1_Periph.TASKS_START'Address); Timer_1_CAPTURE_0 : constant Task_Type := - Task_Type (NRF51_SVD.TIMER.TIMER1_Periph.TASKS_START'Address); + Task_Type (NRF_SVD.TIMER.TIMER1_Periph.TASKS_START'Address); Timer_1_CAPTURE_1 : constant Task_Type := - Task_Type (NRF51_SVD.TIMER.TIMER1_Periph.TASKS_START'Address); + Task_Type (NRF_SVD.TIMER.TIMER1_Periph.TASKS_START'Address); Timer_1_CAPTURE_2 : constant Task_Type := - Task_Type (NRF51_SVD.TIMER.TIMER1_Periph.TASKS_START'Address); + Task_Type (NRF_SVD.TIMER.TIMER1_Periph.TASKS_START'Address); Timer_1_CAPTURE_3 : constant Task_Type := - Task_Type (NRF51_SVD.TIMER.TIMER1_Periph.TASKS_START'Address); + Task_Type (NRF_SVD.TIMER.TIMER1_Periph.TASKS_START'Address); -- Timer 2 tasks Timer_2_START : constant Task_Type := - Task_Type (NRF51_SVD.TIMER.TIMER2_Periph.TASKS_START'Address); + Task_Type (NRF_SVD.TIMER.TIMER2_Periph.TASKS_START'Address); Timer_2_STOP : constant Task_Type := - Task_Type (NRF51_SVD.TIMER.TIMER2_Periph.TASKS_START'Address); + Task_Type (NRF_SVD.TIMER.TIMER2_Periph.TASKS_START'Address); Timer_2_COUNT : constant Task_Type := - Task_Type (NRF51_SVD.TIMER.TIMER2_Periph.TASKS_START'Address); + Task_Type (NRF_SVD.TIMER.TIMER2_Periph.TASKS_START'Address); Timer_2_CLEAR : constant Task_Type := - Task_Type (NRF51_SVD.TIMER.TIMER2_Periph.TASKS_START'Address); + Task_Type (NRF_SVD.TIMER.TIMER2_Periph.TASKS_START'Address); Timer_2_CAPTURE_0 : constant Task_Type := - Task_Type (NRF51_SVD.TIMER.TIMER2_Periph.TASKS_START'Address); + Task_Type (NRF_SVD.TIMER.TIMER2_Periph.TASKS_START'Address); Timer_2_CAPTURE_1 : constant Task_Type := - Task_Type (NRF51_SVD.TIMER.TIMER2_Periph.TASKS_START'Address); + Task_Type (NRF_SVD.TIMER.TIMER2_Periph.TASKS_START'Address); Timer_2_CAPTURE_2 : constant Task_Type := - Task_Type (NRF51_SVD.TIMER.TIMER2_Periph.TASKS_START'Address); + Task_Type (NRF_SVD.TIMER.TIMER2_Periph.TASKS_START'Address); Timer_2_CAPTURE_3 : constant Task_Type := - Task_Type (NRF51_SVD.TIMER.TIMER2_Periph.TASKS_START'Address); + Task_Type (NRF_SVD.TIMER.TIMER2_Periph.TASKS_START'Address); -- RTC 0 tasks RTC_0_START : constant Task_Type := - Task_Type (NRF51_SVD.RTC.RTC0_Periph.TASKS_START'Address); + Task_Type (NRF_SVD.RTC.RTC0_Periph.TASKS_START'Address); RTC_0_STOP : constant Task_Type := - Task_Type (NRF51_SVD.RTC.RTC0_Periph.TASKS_STOP'Address); + Task_Type (NRF_SVD.RTC.RTC0_Periph.TASKS_STOP'Address); RTC_0_CLEAR : constant Task_Type := - Task_Type (NRF51_SVD.RTC.RTC0_Periph.TASKS_CLEAR'Address); + Task_Type (NRF_SVD.RTC.RTC0_Periph.TASKS_CLEAR'Address); RTC_0_TRIGOVRFLW : constant Task_Type := - Task_Type (NRF51_SVD.RTC.RTC0_Periph.TASKS_TRIGOVRFLW'Address); + Task_Type (NRF_SVD.RTC.RTC0_Periph.TASKS_TRIGOVRFLW'Address); -- RTC 1 tasks RTC_1_START : constant Task_Type := - Task_Type (NRF51_SVD.RTC.RTC1_Periph.TASKS_START'Address); + Task_Type (NRF_SVD.RTC.RTC1_Periph.TASKS_START'Address); RTC_1_STOP : constant Task_Type := - Task_Type (NRF51_SVD.RTC.RTC1_Periph.TASKS_STOP'Address); + Task_Type (NRF_SVD.RTC.RTC1_Periph.TASKS_STOP'Address); RTC_1_CLEAR : constant Task_Type := - Task_Type (NRF51_SVD.RTC.RTC1_Periph.TASKS_CLEAR'Address); + Task_Type (NRF_SVD.RTC.RTC1_Periph.TASKS_CLEAR'Address); RTC_1_TRIGOVRFLW : constant Task_Type := - Task_Type (NRF51_SVD.RTC.RTC1_Periph.TASKS_TRIGOVRFLW'Address); + Task_Type (NRF_SVD.RTC.RTC1_Periph.TASKS_TRIGOVRFLW'Address); -- Watchdog tasks Watchdog_START : constant Task_Type := - Task_Type (NRF51_SVD.WDT.WDT_Periph.TASKS_START'Address); + Task_Type (NRF_SVD.WDT.WDT_Periph.TASKS_START'Address); -- Random Number Genrator tasks RNG_START : constant Task_Type := - Task_Type (NRF51_SVD.RNG.RNG_Periph.TASKS_START'Address); + Task_Type (NRF_SVD.RNG.RNG_Periph.TASKS_START'Address); RNG_STOP : constant Task_Type := - Task_Type (NRF51_SVD.RNG.RNG_Periph.TASKS_START'Address); + Task_Type (NRF_SVD.RNG.RNG_Periph.TASKS_START'Address); -- Temperature tasks Temperature_START : constant Task_Type := - Task_Type (NRF51_SVD.TEMP.TEMP_Periph.TASKS_START'Address); + Task_Type (NRF_SVD.TEMP.TEMP_Periph.TASKS_START'Address); Temperature_STOP : constant Task_Type := - Task_Type (NRF51_SVD.TEMP.TEMP_Periph.TASKS_STOP'Address); + Task_Type (NRF_SVD.TEMP.TEMP_Periph.TASKS_STOP'Address); -- AES Electronic Codebook mode encryption (ECB) tasks ECB_START : constant Task_Type := - Task_Type (NRF51_SVD.ECB.ECB_Periph.TASKS_STARTECB'Address); + Task_Type (NRF_SVD.ECB.ECB_Periph.TASKS_STARTECB'Address); ECB_STOP : constant Task_Type := - Task_Type (NRF51_SVD.ECB.ECB_Periph.TASKS_STOPECB'Address); + Task_Type (NRF_SVD.ECB.ECB_Periph.TASKS_STOPECB'Address); -- AES CCM mode encryption (CCM) tasks CCM_KSGEN : constant Task_Type := - Task_Type (NRF51_SVD.CCM.CCM_Periph.TASKS_KSGEN'Address); + Task_Type (NRF_SVD.CCM.CCM_Periph.TASKS_KSGEN'Address); CCM_CRYPT : constant Task_Type := - Task_Type (NRF51_SVD.CCM.CCM_Periph.TASKS_CRYPT'Address); + Task_Type (NRF_SVD.CCM.CCM_Periph.TASKS_CRYPT'Address); CCM_STOP : constant Task_Type := - Task_Type (NRF51_SVD.CCM.CCM_Periph.TASKS_STOP'Address); + Task_Type (NRF_SVD.CCM.CCM_Periph.TASKS_STOP'Address); -- Accelerated Address Resolver (AAR) tasks AAR_START : constant Task_Type := - Task_Type (NRF51_SVD.AAR.AAR_Periph.TASKS_START'Address); + Task_Type (NRF_SVD.AAR.AAR_Periph.TASKS_START'Address); AAR_STOP : constant Task_Type := - Task_Type (NRF51_SVD.AAR.AAR_Periph.TASKS_STOP'Address); + Task_Type (NRF_SVD.AAR.AAR_Periph.TASKS_STOP'Address); -- Two Wire Interface (TWI) 0 tasks TWI_0_STARTRX : constant Task_Type := - Task_Type (NRF51_SVD.TWI.TWI0_Periph.TASKS_STARTRX'Address); + Task_Type (NRF_SVD.TWI.TWI0_Periph.TASKS_STARTRX'Address); TWI_0_STARTTX : constant Task_Type := - Task_Type (NRF51_SVD.TWI.TWI0_Periph.TASKS_STARTTX'Address); + Task_Type (NRF_SVD.TWI.TWI0_Periph.TASKS_STARTTX'Address); TWI_0_STOP : constant Task_Type := - Task_Type (NRF51_SVD.TWI.TWI0_Periph.TASKS_STOP'Address); + Task_Type (NRF_SVD.TWI.TWI0_Periph.TASKS_STOP'Address); TWI_0_SUSPEND : constant Task_Type := - Task_Type (NRF51_SVD.TWI.TWI0_Periph.TASKS_SUSPEND'Address); + Task_Type (NRF_SVD.TWI.TWI0_Periph.TASKS_SUSPEND'Address); TWI_0_RESUME : constant Task_Type := - Task_Type (NRF51_SVD.TWI.TWI0_Periph.TASKS_RESUME'Address); + Task_Type (NRF_SVD.TWI.TWI0_Periph.TASKS_RESUME'Address); -- Two Wire Interface (TWI) 1 tasks TWI_1_STARTRX : constant Task_Type := - Task_Type (NRF51_SVD.TWI.TWI1_Periph.TASKS_STARTRX'Address); + Task_Type (NRF_SVD.TWI.TWI1_Periph.TASKS_STARTRX'Address); TWI_1_STARTTX : constant Task_Type := - Task_Type (NRF51_SVD.TWI.TWI1_Periph.TASKS_STARTTX'Address); + Task_Type (NRF_SVD.TWI.TWI1_Periph.TASKS_STARTTX'Address); TWI_1_STOP : constant Task_Type := - Task_Type (NRF51_SVD.TWI.TWI1_Periph.TASKS_STOP'Address); + Task_Type (NRF_SVD.TWI.TWI1_Periph.TASKS_STOP'Address); TWI_1_SUSPEND : constant Task_Type := - Task_Type (NRF51_SVD.TWI.TWI1_Periph.TASKS_SUSPEND'Address); + Task_Type (NRF_SVD.TWI.TWI1_Periph.TASKS_SUSPEND'Address); TWI_1_RESUME : constant Task_Type := - Task_Type (NRF51_SVD.TWI.TWI1_Periph.TASKS_RESUME'Address); + Task_Type (NRF_SVD.TWI.TWI1_Periph.TASKS_RESUME'Address); -- Universal Asynchronous Receiver/Transmitter (UART) Tasks UART_STARTRX : constant Task_Type := - Task_Type (NRF51_SVD.UART.UART0_Periph.TASKS_STARTRX'Address); + Task_Type (NRF_SVD.UART.UART0_Periph.TASKS_STARTRX'Address); UART_STOPRX : constant Task_Type := - Task_Type (NRF51_SVD.UART.UART0_Periph.TASKS_STOPRX'Address); + Task_Type (NRF_SVD.UART.UART0_Periph.TASKS_STOPRX'Address); UART_STARTTX : constant Task_Type := - Task_Type (NRF51_SVD.UART.UART0_Periph.TASKS_STARTTX'Address); + Task_Type (NRF_SVD.UART.UART0_Periph.TASKS_STARTTX'Address); UART_STOPTX : constant Task_Type := - Task_Type (NRF51_SVD.UART.UART0_Periph.TASKS_STOPTX'Address); + Task_Type (NRF_SVD.UART.UART0_Periph.TASKS_STOPTX'Address); -- Quadrature Decoder (QDEC) QDEC_START : constant Task_Type := - Task_Type (NRF51_SVD.QDEC.QDEC_Periph.TASKS_START'Address); + Task_Type (NRF_SVD.QDEC.QDEC_Periph.TASKS_START'Address); QDEC_STOP : constant Task_Type := - Task_Type (NRF51_SVD.QDEC.QDEC_Periph.TASKS_STOP'Address); + Task_Type (NRF_SVD.QDEC.QDEC_Periph.TASKS_STOP'Address); QDEC_READCLRACC : constant Task_Type := - Task_Type (NRF51_SVD.QDEC.QDEC_Periph.TASKS_READCLRACC'Address); + Task_Type (NRF_SVD.QDEC.QDEC_Periph.TASKS_READCLRACC'Address); -- Analof to Digital Converter (ADC) ADC_START : constant Task_Type := - Task_Type (NRF51_SVD.ADC.ADC_Periph.TASKS_START'Address); + Task_Type (NRF_SVD.SAADC.SAADC_Periph.TASKS_START'Address); ADC_STOP : constant Task_Type := - Task_Type (NRF51_SVD.ADC.ADC_Periph.TASKS_STOP'Address); + Task_Type (NRF_SVD.SAADC.SAADC_Periph.TASKS_STOP'Address); -end nRF51.Tasks; +end nRF.Tasks; diff --git a/arch/ARM/Nordic/drivers/nrf51-clock.adb b/arch/ARM/Nordic/drivers/nrf_common/nrf-clock.adb similarity index 89% rename from arch/ARM/Nordic/drivers/nrf51-clock.adb rename to arch/ARM/Nordic/drivers/nrf_common/nrf-clock.adb index 12c43dd6e..55d17d3c3 100644 --- a/arch/ARM/Nordic/drivers/nrf51-clock.adb +++ b/arch/ARM/Nordic/drivers/nrf_common/nrf-clock.adb @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2016, AdaCore -- +-- Copyright (C) 2016-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -29,21 +29,17 @@ -- -- ------------------------------------------------------------------------------ -with NRF51_SVD.CLOCK; use NRF51_SVD.CLOCK; -with nRF51.Tasks; use nRF51.Tasks; +with NRF_SVD.CLOCK; use NRF_SVD.CLOCK; +with nRF.Tasks; use nRF.Tasks; -package body nRF51.Clock is +package body nRF.Clock is -------------------------------------- -- Set_High_Freq_External_Frequency -- -------------------------------------- - procedure Set_High_Freq_External_Frequency (Freq : High_Freq_Ext_Freq) is - begin - CLOCK_Periph.XTALFREQ.XTALFREQ := (case Freq is - when HFCLK_16MHz => XTALFREQ_XTALFREQ_Field_16Mhz, - when HFCLK_32MHz => XTALFREQ_XTALFREQ_Field_16Mhz); - end Set_High_Freq_External_Frequency; + procedure Set_High_Freq_External_Frequency + (Freq : High_Freq_Ext_Freq) is separate; -------------------------- -- Set_High_Freq_Source -- @@ -147,4 +143,4 @@ package body nRF51.Clock is Tasks.Trigger (Tasks.Clock_LFCLKSTOP); end Stop_Low_Freq; -end nRF51.Clock; +end nRF.Clock; diff --git a/arch/ARM/Nordic/drivers/nrf51-clock.ads b/arch/ARM/Nordic/drivers/nrf_common/nrf-clock.ads similarity index 96% rename from arch/ARM/Nordic/drivers/nrf51-clock.ads rename to arch/ARM/Nordic/drivers/nrf_common/nrf-clock.ads index 36a224769..883bf4c4c 100644 --- a/arch/ARM/Nordic/drivers/nrf51-clock.ads +++ b/arch/ARM/Nordic/drivers/nrf_common/nrf-clock.ads @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2016, AdaCore -- +-- Copyright (C) 2016-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -29,7 +29,7 @@ -- -- ------------------------------------------------------------------------------ -package nRF51.Clock is +package nRF.Clock is -------------------------- -- High frequency clock -- @@ -66,4 +66,4 @@ package nRF51.Clock is procedure Stop_Low_Freq; -end nRF51.Clock; +end nRF.Clock; diff --git a/arch/ARM/Nordic/drivers/nrf51-events.adb b/arch/ARM/Nordic/drivers/nrf_common/nrf-events.adb similarity index 92% rename from arch/ARM/Nordic/drivers/nrf51-events.adb rename to arch/ARM/Nordic/drivers/nrf_common/nrf-events.adb index 4d02e4220..d43521997 100644 --- a/arch/ARM/Nordic/drivers/nrf51-events.adb +++ b/arch/ARM/Nordic/drivers/nrf_common/nrf-events.adb @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2016, AdaCore -- +-- Copyright (C) 2016-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -31,7 +31,7 @@ with Ada.Unchecked_Conversion; -package body nRF51.Events is +package body nRF.Events is function To_UInt32 is new Ada.Unchecked_Conversion (System.Address, UInt32); function To_Address is new Ada.Unchecked_Conversion (UInt32, System.Address); @@ -58,11 +58,11 @@ package body nRF51.Events is Event_Index : constant UInt7 := UInt7 (Reg_Addr and 16#0000_007F#) / 4; -- The bit corresponding to an event is determined by the offset of the - -- event. (nRF51 Series Reference Manual, section 9.1.6) + -- event. (nRF Series Reference Manual, section 9.1.6) Set_Register_Addr : constant UInt32 := Device_Base + 16#0000_0304#; -- For each device the "Interrupt enable set register" is always located - -- at the same offset: 0x304. (nRF51 Series Reference Manual, + -- at the same offset: 0x304. (nRF Series Reference Manual, -- section 9.1.6) Set_Register : UInt32 with Address => To_Address (Set_Register_Addr); @@ -81,11 +81,11 @@ package body nRF51.Events is Event_Index : constant UInt7 := UInt7 (Reg_Addr and 16#0000_007F#) / 4; -- The bit corresponding to an event is determined by the offset of the - -- event. (nRF51 Series Reference Manual, section 9.1.6) + -- event. (nRF Series Reference Manual, section 9.1.6) Clear_Register_Addr : constant UInt32 := Device_Base + 16#0000_0308#; -- For each device the "Interrupt enable clear register" is always - -- located at the same offset: 0x308. (nRF51 Series Reference Manual, + -- located at the same offset: 0x308. (nRF Series Reference Manual, -- section 9.1.6) Clear_Register : UInt32 with Address => To_Address (Clear_Register_Addr); @@ -122,4 +122,4 @@ package body nRF51.Events is end Get_Address; -end nRF51.Events; +end nRF.Events; diff --git a/arch/ARM/Nordic/drivers/nrf51-gpio-tasks_and_events.adb b/arch/ARM/Nordic/drivers/nrf_common/nrf-gpio-tasks_and_events.adb similarity index 95% rename from arch/ARM/Nordic/drivers/nrf51-gpio-tasks_and_events.adb rename to arch/ARM/Nordic/drivers/nrf_common/nrf-gpio-tasks_and_events.adb index 7edd8bebd..18b8a9c1b 100644 --- a/arch/ARM/Nordic/drivers/nrf51-gpio-tasks_and_events.adb +++ b/arch/ARM/Nordic/drivers/nrf_common/nrf-gpio-tasks_and_events.adb @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2016, AdaCore -- +-- Copyright (C) 2016-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -29,10 +29,10 @@ -- -- ------------------------------------------------------------------------------ -with NRF51_SVD.GPIOTE; use NRF51_SVD.GPIOTE; +with NRF_SVD.GPIOTE; use NRF_SVD.GPIOTE; with HAL; use HAL; -package body nRF51.GPIO.Tasks_And_Events is +package body nRF.GPIO.Tasks_And_Events is ------------- -- Disable -- @@ -99,4 +99,4 @@ package body nRF51.GPIO.Tasks_And_Events is function In_Event (Chan : GPIOTE_Channel) return Event_Type is (Event_Type (GPIOTE_Periph.EVENTS_IN (Integer (Chan))'Address)); -end nRF51.GPIO.Tasks_And_Events; +end nRF.GPIO.Tasks_And_Events; diff --git a/arch/ARM/Nordic/drivers/nrf51-gpio-tasks_and_events.ads b/arch/ARM/Nordic/drivers/nrf_common/nrf-gpio-tasks_and_events.ads similarity index 93% rename from arch/ARM/Nordic/drivers/nrf51-gpio-tasks_and_events.ads rename to arch/ARM/Nordic/drivers/nrf_common/nrf-gpio-tasks_and_events.ads index c3697f401..e1a6badad 100644 --- a/arch/ARM/Nordic/drivers/nrf51-gpio-tasks_and_events.ads +++ b/arch/ARM/Nordic/drivers/nrf_common/nrf-gpio-tasks_and_events.ads @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2016, AdaCore -- +-- Copyright (C) 2016-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -29,7 +29,7 @@ -- -- ------------------------------------------------------------------------------ -package nRF51.GPIO.Tasks_And_Events is +package nRF.GPIO.Tasks_And_Events is type GPIOTE_Channel is range 0 .. 3; @@ -53,9 +53,9 @@ package nRF51.GPIO.Tasks_And_Events is -- Toggle) is applied to GPIO_Pin. function Out_Task (Chan : GPIOTE_Channel) return Task_Type; - -- Return the nRF51 task associated with Chan + -- Return the nRF task associated with Chan function In_Event (Chan : GPIOTE_Channel) return Event_Type; - -- Return the nRF51 event associated with Chan + -- Return the nRF event associated with Chan -end nRF51.GPIO.Tasks_And_Events; +end nRF.GPIO.Tasks_And_Events; diff --git a/arch/ARM/Nordic/drivers/nrf51-gpio.adb b/arch/ARM/Nordic/drivers/nrf_common/nrf-gpio.adb similarity index 97% rename from arch/ARM/Nordic/drivers/nrf51-gpio.adb rename to arch/ARM/Nordic/drivers/nrf_common/nrf-gpio.adb index 265266b0a..aed694d97 100644 --- a/arch/ARM/Nordic/drivers/nrf51-gpio.adb +++ b/arch/ARM/Nordic/drivers/nrf_common/nrf-gpio.adb @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2016-2018, AdaCore -- +-- Copyright (C) 2016-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -29,9 +29,9 @@ -- -- ------------------------------------------------------------------------------ -with NRF51_SVD.GPIO; use NRF51_SVD.GPIO; +with NRF_SVD.GPIO; use NRF_SVD.GPIO; -package body nRF51.GPIO is +package body nRF.GPIO is overriding function Mode (This : GPIO_Point) return HAL.GPIO.GPIO_Mode is @@ -182,4 +182,4 @@ package body nRF51.GPIO is when Sense_For_Low_Level => Low); end Configure_IO; -end nRF51.GPIO; +end nRF.GPIO; diff --git a/arch/ARM/Nordic/drivers/nrf51-gpio.ads b/arch/ARM/Nordic/drivers/nrf_common/nrf-gpio.ads similarity index 97% rename from arch/ARM/Nordic/drivers/nrf51-gpio.ads rename to arch/ARM/Nordic/drivers/nrf_common/nrf-gpio.ads index ed25ae768..cb5b4748a 100644 --- a/arch/ARM/Nordic/drivers/nrf51-gpio.ads +++ b/arch/ARM/Nordic/drivers/nrf_common/nrf-gpio.ads @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2016-2018, AdaCore -- +-- Copyright (C) 2016-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -31,7 +31,7 @@ with HAL.GPIO; -package nRF51.GPIO is +package nRF.GPIO is subtype GPIO_Pin_Index is Natural range 0 .. 31; @@ -73,7 +73,7 @@ package nRF51.GPIO is return Boolean is (case Capa is when others => True); - -- nRF51 supports all GPIO capabilities + -- nRF supports all GPIO capabilities overriding function Mode (This : GPIO_Point) return HAL.GPIO.GPIO_Mode; @@ -119,4 +119,4 @@ package nRF51.GPIO is Config : GPIO_Configuration); -- Configures the characteristics specified by Config -end nRF51.GPIO; +end nRF.GPIO; diff --git a/arch/ARM/Nordic/drivers/nrf51-interrupts.adb b/arch/ARM/Nordic/drivers/nrf_common/nrf-interrupts.adb similarity index 91% rename from arch/ARM/Nordic/drivers/nrf51-interrupts.adb rename to arch/ARM/Nordic/drivers/nrf_common/nrf-interrupts.adb index 797e5d154..30ff931cd 100644 --- a/arch/ARM/Nordic/drivers/nrf51-interrupts.adb +++ b/arch/ARM/Nordic/drivers/nrf_common/nrf-interrupts.adb @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2016-2019, AdaCore -- +-- Copyright (C) 2016-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -29,12 +29,13 @@ -- -- ------------------------------------------------------------------------------ -with Cortex_M.NVIC; +with HAL; use HAL; + with System.Machine_Code; use System.Machine_Code; -package body nRF51.Interrupts is +package body nRF.Interrupts is - Handlers : array (nRF51.Interrupts.Interrupt_Name) of Handler + Handlers : array (nRF.Interrupts.Interrupt_Name) of Handler := (others => null); procedure GNAT_IRQ_Handler; @@ -80,7 +81,7 @@ package body nRF51.Interrupts is -- Register -- -------------- - procedure Register (Id : nRF51.Interrupts.Interrupt_Name; + procedure Register (Id : nRF.Interrupts.Interrupt_Name; Hdl : Handler) is begin @@ -92,7 +93,7 @@ package body nRF51.Interrupts is ---------------------- procedure GNAT_IRQ_Handler is - Id : nRF51.Interrupts.Interrupt_Name; + Id : nRF.Interrupts.Interrupt_Name; IPSR : UInt32; begin Asm ("mrs %0, ipsr", @@ -101,11 +102,11 @@ package body nRF51.Interrupts is IPSR := IPSR and 16#FF#; - Id := nRF51.Interrupts.Interrupt_Name'Val (IPSR - 16); + Id := nRF.Interrupts.Interrupt_Name'Val (IPSR - 16); if Handlers (Id) /= null then Handlers (Id).all; end if; end GNAT_IRQ_Handler; -end nRF51.Interrupts; +end nRF.Interrupts; diff --git a/arch/ARM/Nordic/drivers/nrf51-radio.adb b/arch/ARM/Nordic/drivers/nrf_common/nrf-radio.adb similarity index 98% rename from arch/ARM/Nordic/drivers/nrf51-radio.adb rename to arch/ARM/Nordic/drivers/nrf_common/nrf-radio.adb index 3c3d5d47f..8811e57e6 100644 --- a/arch/ARM/Nordic/drivers/nrf51-radio.adb +++ b/arch/ARM/Nordic/drivers/nrf_common/nrf-radio.adb @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2016, AdaCore -- +-- Copyright (C) 2016-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -29,10 +29,10 @@ -- -- ------------------------------------------------------------------------------ -with NRF51_SVD.RADIO; use NRF51_SVD.RADIO; +with NRF_SVD.RADIO; use NRF_SVD.RADIO; with System.Storage_Elements; use System.Storage_Elements; -package body nRF51.Radio is +package body nRF.Radio is ------------------------------------ -- Setup_For_Bluetooth_Low_Energy -- @@ -316,4 +316,4 @@ package body nRF51.Radio is else Big); end Configure_Packet; -end nRF51.Radio; +end nRF.Radio; diff --git a/arch/ARM/Nordic/drivers/nrf51-radio.ads b/arch/ARM/Nordic/drivers/nrf_common/nrf-radio.ads similarity index 98% rename from arch/ARM/Nordic/drivers/nrf51-radio.ads rename to arch/ARM/Nordic/drivers/nrf_common/nrf-radio.ads index 8e1d88295..2d1006689 100644 --- a/arch/ARM/Nordic/drivers/nrf51-radio.ads +++ b/arch/ARM/Nordic/drivers/nrf_common/nrf-radio.ads @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2016, AdaCore -- +-- Copyright (C) 2016-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -31,7 +31,7 @@ with HAL; use HAL; -package nRF51.Radio is +package nRF.Radio is procedure Setup_For_Bluetooth_Low_Energy; -- Configure the radio for Bluetooth Low Energy (BLE) operations @@ -41,7 +41,7 @@ package nRF51.Radio is -- - Shortcuts -- - Adresses - -- nRF51 radio packet format: + -- nRF radio packet format: -- -- --------------------------------------------------------------- -- | PREAMBLE | BASE | PREFIX | S0 | LENGTH | S1 | PAYLOAD | CRC | @@ -187,4 +187,4 @@ private Neg_8_Dbm => 16#F8#, Neg_4_Dbm => 16#FC#); -end nRF51.Radio; +end nRF.Radio; diff --git a/arch/ARM/Nordic/drivers/nrf51-rng.adb b/arch/ARM/Nordic/drivers/nrf_common/nrf-rng.adb similarity index 95% rename from arch/ARM/Nordic/drivers/nrf51-rng.adb rename to arch/ARM/Nordic/drivers/nrf_common/nrf-rng.adb index 7ed400801..ec37c7013 100644 --- a/arch/ARM/Nordic/drivers/nrf51-rng.adb +++ b/arch/ARM/Nordic/drivers/nrf_common/nrf-rng.adb @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2016, AdaCore -- +-- Copyright (C) 2016-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -29,9 +29,9 @@ -- -- ------------------------------------------------------------------------------ -with NRF51_SVD.RNG; use NRF51_SVD.RNG; +with NRF_SVD.RNG; use NRF_SVD.RNG; -package body nRF51.RNG is +package body nRF.RNG is ------------------------------------- -- Enable_Digital_Error_Correction -- @@ -70,4 +70,5 @@ package body nRF51.RNG is return RNG_Periph.VALUE.VALUE; end Read; -end nRF51.RNG; +end nRF.RNG; + diff --git a/arch/ARM/Nordic/drivers/nrf51-rng.ads b/arch/ARM/Nordic/drivers/nrf_common/nrf-rng.ads similarity index 96% rename from arch/ARM/Nordic/drivers/nrf51-rng.ads rename to arch/ARM/Nordic/drivers/nrf_common/nrf-rng.ads index 8811f3ccc..111d6fa17 100644 --- a/arch/ARM/Nordic/drivers/nrf51-rng.ads +++ b/arch/ARM/Nordic/drivers/nrf_common/nrf-rng.ads @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2016, AdaCore -- +-- Copyright (C) 2016-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -31,7 +31,7 @@ with HAL; use HAL; -package nRF51.RNG is +package nRF.RNG is procedure Enable_Digital_Error_Correction; @@ -39,4 +39,4 @@ package nRF51.RNG is function Read return UInt8; -end nRF51.RNG; +end nRF.RNG; diff --git a/arch/ARM/Nordic/drivers/nrf51-rtc.adb b/arch/ARM/Nordic/drivers/nrf_common/nrf-rtc.adb similarity index 97% rename from arch/ARM/Nordic/drivers/nrf51-rtc.adb rename to arch/ARM/Nordic/drivers/nrf_common/nrf-rtc.adb index 6440c457c..98cb19756 100644 --- a/arch/ARM/Nordic/drivers/nrf51-rtc.adb +++ b/arch/ARM/Nordic/drivers/nrf_common/nrf-rtc.adb @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2016, AdaCore -- +-- Copyright (C) 2016-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -29,9 +29,9 @@ -- -- ------------------------------------------------------------------------------ -with NRF51_SVD.RTC; use NRF51_SVD.RTC; +with NRF_SVD.RTC; use NRF_SVD.RTC; -package body nRF51.RTC is +package body nRF.RTC is ----------- -- Start -- @@ -45,7 +45,6 @@ package body nRF51.RTC is ---------- -- Stop -- ---------- - procedure Stop (This : Real_Time_Counter) is begin This.Periph.TASKS_STOP := 1; @@ -170,4 +169,4 @@ package body nRF51.RTC is end case; end Disable_Event; -end nRF51.RTC; +end nRF.RTC; diff --git a/arch/ARM/Nordic/drivers/nrf51-rtc.ads b/arch/ARM/Nordic/drivers/nrf_common/nrf-rtc.ads similarity index 91% rename from arch/ARM/Nordic/drivers/nrf51-rtc.ads rename to arch/ARM/Nordic/drivers/nrf_common/nrf-rtc.ads index f2512b0f5..4ad5db74c 100644 --- a/arch/ARM/Nordic/drivers/nrf51-rtc.ads +++ b/arch/ARM/Nordic/drivers/nrf_common/nrf-rtc.ads @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2016, AdaCore -- +-- Copyright (C) 2016-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -29,17 +29,17 @@ -- -- ------------------------------------------------------------------------------ -with NRF51_SVD.RTC; +with NRF_SVD.RTC; with HAL; use HAL; -package nRF51.RTC is +package nRF.RTC is type RTC_Events is (Tick_Event, Overflow_Event, Compare_0_Event, Compare_1_Event, Compare_2_Event, Compare_3_Event); type Compare_Channel is range 0 .. 3; - type Real_Time_Counter (Periph : not null access NRF51_SVD.RTC.RTC_Peripheral) is private; + type Real_Time_Counter (Periph : not null access NRF_SVD.RTC.RTC_Peripheral) is private; procedure Start (This : Real_Time_Counter); procedure Stop (This : Real_Time_Counter); @@ -62,5 +62,5 @@ package nRF51.RTC is procedure Disable_Event (This : Real_Time_Counter; Evt : RTC_Events); private - type Real_Time_Counter (Periph : not null access NRF51_SVD.RTC.RTC_Peripheral) is null record; -end nRF51.RTC; + type Real_Time_Counter (Periph : not null access NRF_SVD.RTC.RTC_Peripheral) is null record; +end nRF.RTC; diff --git a/arch/ARM/Nordic/drivers/nrf51-spi_master.adb b/arch/ARM/Nordic/drivers/nrf_common/nrf-spi_master.adb similarity index 98% rename from arch/ARM/Nordic/drivers/nrf51-spi_master.adb rename to arch/ARM/Nordic/drivers/nrf_common/nrf-spi_master.adb index df1dc6af3..1681672dd 100644 --- a/arch/ARM/Nordic/drivers/nrf51-spi_master.adb +++ b/arch/ARM/Nordic/drivers/nrf_common/nrf-spi_master.adb @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2018, AdaCore -- +-- Copyright (C) 2018-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -29,9 +29,9 @@ -- -- ------------------------------------------------------------------------------ -with NRF51_SVD.SPI; use NRF51_SVD.SPI; +with NRF_SVD.SPI; use NRF_SVD.SPI; -package body nRF51.SPI_Master is +package body nRF.SPI_Master is procedure Transfer (This : in out SPI_Master; Data_Out : UInt8; @@ -271,4 +271,4 @@ package body nRF51.SPI_Master is Status := HAL.SPI.Ok; end Receive; -end nRF51.SPI_Master; +end nRF.SPI_Master; diff --git a/arch/ARM/Nordic/drivers/nrf51-spi_master.ads b/arch/ARM/Nordic/drivers/nrf_common/nrf-spi_master.ads similarity index 91% rename from arch/ARM/Nordic/drivers/nrf51-spi_master.ads rename to arch/ARM/Nordic/drivers/nrf_common/nrf-spi_master.ads index af981822c..032ae3d32 100644 --- a/arch/ARM/Nordic/drivers/nrf51-spi_master.ads +++ b/arch/ARM/Nordic/drivers/nrf_common/nrf-spi_master.ads @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2018, AdaCore -- +-- Copyright (C) 2018-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -29,16 +29,16 @@ -- -- ------------------------------------------------------------------------------ -with HAL; use HAL; -with HAL.SPI; use HAL.SPI; -with nRF51.GPIO; use nRF51.GPIO; -with NRF51_SVD.SPI; +with HAL; use HAL; +with HAL.SPI; use HAL.SPI; +with nRF.GPIO; use nRF.GPIO; +with NRF_SVD.SPI; -package nRF51.SPI_Master is +package nRF.SPI_Master is type Clock_Speed is (SPI_125kbps, SPI_250kbps, SPI_500kbps, SPI_1Mbps, SPI_2Mbps, SPI_4Mbps, SPI_8Mbps); - -- nRF51 SPI device has a limited number of speeds available + -- nRF SPI device has a limited number of speeds available type Data_Bit_Order is (Most_Significant_First, Least_Significant_First); @@ -53,9 +53,9 @@ package nRF51.SPI_Master is -- CPOL = 0 -> Active_High -- CPOL = 1 -> Active_Low - type SPI_Master (Periph : not null access NRF51_SVD.SPI.SPI_Peripheral) is + type SPI_Master (Periph : not null access NRF_SVD.SPI.SPI_Peripheral) is new HAL.SPI.SPI_Port with private; - -- nRF51 SPI Master device + -- nRF SPI Master device procedure Enable (This : in out SPI_Master) with Post => This.Enabled; @@ -127,7 +127,7 @@ package nRF51.SPI_Master is private - type SPI_Master (Periph : not null access NRF51_SVD.SPI.SPI_Peripheral) is + type SPI_Master (Periph : not null access NRF_SVD.SPI.SPI_Peripheral) is new HAL.SPI.SPI_Port with null record; -end nRF51.SPI_Master; +end nRF.SPI_Master; diff --git a/arch/ARM/Nordic/drivers/nrf51-tasks.adb b/arch/ARM/Nordic/drivers/nrf_common/nrf-tasks.adb similarity index 96% rename from arch/ARM/Nordic/drivers/nrf51-tasks.adb rename to arch/ARM/Nordic/drivers/nrf_common/nrf-tasks.adb index b506e4a7e..a4b50b325 100644 --- a/arch/ARM/Nordic/drivers/nrf51-tasks.adb +++ b/arch/ARM/Nordic/drivers/nrf_common/nrf-tasks.adb @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2016, AdaCore -- +-- Copyright (C) 2016-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -31,7 +31,7 @@ with Ada.Unchecked_Conversion; -package body nRF51.Tasks is +package body nRF.Tasks is function To_UInt32 is new Ada.Unchecked_Conversion (System.Address, UInt32); @@ -63,5 +63,4 @@ package body nRF51.Tasks is return To_UInt32 (System.Address (T)); end Get_Address; - -end nRF51.Tasks; +end nRF.Tasks; diff --git a/arch/ARM/Nordic/drivers/nrf51-temperature.adb b/arch/ARM/Nordic/drivers/nrf_common/nrf-temperature.adb similarity index 93% rename from arch/ARM/Nordic/drivers/nrf51-temperature.adb rename to arch/ARM/Nordic/drivers/nrf_common/nrf-temperature.adb index 73b4b8cf5..a0b777574 100644 --- a/arch/ARM/Nordic/drivers/nrf51-temperature.adb +++ b/arch/ARM/Nordic/drivers/nrf_common/nrf-temperature.adb @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2016, AdaCore -- +-- Copyright (C) 2016-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -29,10 +29,10 @@ -- -- ------------------------------------------------------------------------------ -with NRF51_SVD.TEMP; use NRF51_SVD.TEMP; -with HAL; use HAL; +with NRF_SVD.TEMP; use NRF_SVD.TEMP; +with HAL; -package body nRF51.Temperature is +package body nRF.Temperature is type RAW_Temp is delta 0.25 range Temp_Celsius'First * 4.0 .. Temp_Celsius'Last * 4.0; @@ -42,7 +42,10 @@ package body nRF51.Temperature is ---------- function Read return Temp_Celsius is + use type HAL.UInt32; + Raw : RAW_Temp; + begin -- Clear event @@ -59,4 +62,5 @@ package body nRF51.Temperature is return Temp_Celsius (Raw / 4); end Read; -end nRF51.Temperature; +end nRF.Temperature; + diff --git a/arch/ARM/Nordic/drivers/nrf51-temperature.ads b/arch/ARM/Nordic/drivers/nrf_common/nrf-temperature.ads similarity index 95% rename from arch/ARM/Nordic/drivers/nrf51-temperature.ads rename to arch/ARM/Nordic/drivers/nrf_common/nrf-temperature.ads index aa046e48d..c761376ca 100644 --- a/arch/ARM/Nordic/drivers/nrf51-temperature.ads +++ b/arch/ARM/Nordic/drivers/nrf_common/nrf-temperature.ads @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2016, AdaCore -- +-- Copyright (C) 2016-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -29,11 +29,11 @@ -- -- ------------------------------------------------------------------------------ -package nRF51.Temperature is +package nRF.Temperature is type Temp_Celsius is delta 0.25 range -2_147_483_648.0 / 4 .. 2_147_483_647.0 / 4; function Read return Temp_Celsius; -end nRF51.Temperature; +end nRF.Temperature; diff --git a/arch/ARM/Nordic/drivers/nrf51-timers.adb b/arch/ARM/Nordic/drivers/nrf_common/nrf-timers.adb similarity index 90% rename from arch/ARM/Nordic/drivers/nrf51-timers.adb rename to arch/ARM/Nordic/drivers/nrf_common/nrf-timers.adb index ad1dfa4e3..b555d708c 100644 --- a/arch/ARM/Nordic/drivers/nrf51-timers.adb +++ b/arch/ARM/Nordic/drivers/nrf_common/nrf-timers.adb @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2017, AdaCore -- +-- Copyright (C) 2017-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -29,9 +29,9 @@ -- -- ------------------------------------------------------------------------------ -with NRF51_SVD.TIMER; use NRF51_SVD.TIMER; +with NRF_SVD.TIMER; use NRF_SVD.TIMER; -package body nRF51.Timers is +package body nRF.Timers is ----------- -- Start -- @@ -60,6 +60,7 @@ package body nRF51.Timers is This.Periph.TASKS_CLEAR := 1; end Clear; + ------------------- -- Set_Prescaler -- ------------------- @@ -83,8 +84,8 @@ package body nRF51.Timers is begin This.Periph.MODE.MODE := (case Mode is - when Mode_Timer => NRF51_SVD.TIMER.Timer, - when Mode_Counter => NRF51_SVD.TIMER.Counter); + when Mode_Timer => NRF_SVD.TIMER.Timer, + when Mode_Counter => NRF_SVD.TIMER.Counter); end Set_Mode; ----------------- @@ -98,10 +99,10 @@ package body nRF51.Timers is begin This.Periph.BITMODE.BITMODE := (case Mode is - when Bitmode_8bit => BITMODE_BITMODE_Field_08Bit, - when Bitmode_16bit => BITMODE_BITMODE_Field_16Bit, - when Bitmode_24bit => BITMODE_BITMODE_Field_24Bit, - when Bitmode_32bit => BITMODE_BITMODE_Field_32Bit); + when Bitmode_8bit => Val_08Bit, + when Bitmode_16bit => Val_16Bit, + when Bitmode_24bit => Val_24Bit, + when Bitmode_32bit => Val_32Bit); end Set_Bitmode; ------------- @@ -112,10 +113,10 @@ package body nRF51.Timers is begin return (case This.Periph.BITMODE.BITMODE is - when BITMODE_BITMODE_Field_08Bit => Bitmode_8bit, - when BITMODE_BITMODE_Field_16Bit => Bitmode_16bit, - when BITMODE_BITMODE_Field_24Bit => Bitmode_24bit, - when BITMODE_BITMODE_Field_32Bit => Bitmode_32bit); + when Val_08Bit => Bitmode_8bit, + when Val_16Bit => Bitmode_16bit, + when Val_24Bit => Bitmode_24bit, + when Val_32Bit => Bitmode_32bit); end Bitmode; ----------------------- @@ -178,8 +179,7 @@ package body nRF51.Timers is ------------- procedure Capture (This : in out Timer; - Chan : Timer_Channel) - is + Chan : Timer_Channel) is begin This.Periph.TASKS_CAPTURE (Integer (Chan)) := 1; end Capture; @@ -260,4 +260,5 @@ package body nRF51.Timers is return Event_Type is (Event_Type (This.Periph.EVENTS_COMPARE (Integer (Chan))'Address)); -end nRF51.Timers; +end nRF.Timers; + diff --git a/arch/ARM/Nordic/drivers/nrf51-timers.ads b/arch/ARM/Nordic/drivers/nrf_common/nrf-timers.ads similarity index 95% rename from arch/ARM/Nordic/drivers/nrf51-timers.ads rename to arch/ARM/Nordic/drivers/nrf_common/nrf-timers.ads index 7e995516d..05a8451fc 100644 --- a/arch/ARM/Nordic/drivers/nrf51-timers.ads +++ b/arch/ARM/Nordic/drivers/nrf_common/nrf-timers.ads @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2017, AdaCore -- +-- Copyright (C) 2017-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -29,12 +29,12 @@ -- -- ------------------------------------------------------------------------------ -with NRF51_SVD.TIMER; +with NRF_SVD.TIMER; with HAL; use HAL; -package nRF51.Timers is +package nRF.Timers is - type Timer (Periph : not null access NRF51_SVD.TIMER.TIMER_Peripheral) + type Timer (Periph : not null access NRF_SVD.TIMER.TIMER_Peripheral) is tagged private; type Timer_Channel is range 0 .. 3; @@ -152,7 +152,7 @@ package nRF51.Timers is private - type Timer (Periph : not null access NRF51_SVD.TIMER.TIMER_Peripheral) + type Timer (Periph : not null access NRF_SVD.TIMER.TIMER_Peripheral) is tagged null record; -end nRF51.Timers; +end nRF.Timers; diff --git a/arch/ARM/Nordic/drivers/nrf51-twi.adb b/arch/ARM/Nordic/drivers/nrf_common/nrf-twi.adb similarity index 98% rename from arch/ARM/Nordic/drivers/nrf51-twi.adb rename to arch/ARM/Nordic/drivers/nrf_common/nrf-twi.adb index cdb6dc215..434b433a3 100644 --- a/arch/ARM/Nordic/drivers/nrf51-twi.adb +++ b/arch/ARM/Nordic/drivers/nrf_common/nrf-twi.adb @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2016, AdaCore -- +-- Copyright (C) 2016-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -29,9 +29,9 @@ -- -- ------------------------------------------------------------------------------ -with NRF51_SVD.TWI; use NRF51_SVD.TWI; +with NRF_SVD.TWI; use NRF_SVD.TWI; -package body nRF51.TWI is +package body nRF.TWI is procedure Stop_Sequence (This : in out TWI_Master'Class); @@ -176,6 +176,7 @@ package body nRF51.TWI is Status := Ok; end Master_Transmit; + -------------------- -- Master_Receive -- -------------------- @@ -338,4 +339,4 @@ package body nRF51.TWI is Timeout => Timeout); end Mem_Read; -end nRF51.TWI; +end nRF.TWI; diff --git a/arch/ARM/Nordic/drivers/nrf51-twi.ads b/arch/ARM/Nordic/drivers/nrf_common/nrf-twi.ads similarity index 92% rename from arch/ARM/Nordic/drivers/nrf51-twi.ads rename to arch/ARM/Nordic/drivers/nrf_common/nrf-twi.ads index acc1005e9..4af0c6861 100644 --- a/arch/ARM/Nordic/drivers/nrf51-twi.ads +++ b/arch/ARM/Nordic/drivers/nrf_common/nrf-twi.ads @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2016, AdaCore -- +-- Copyright (C) 2016-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -31,14 +31,14 @@ with HAL; use HAL; with HAL.I2C; use HAL.I2C; -with nRF51.GPIO; use nRF51.GPIO; -with NRF51_SVD.TWI; +with nRF.GPIO; use nRF.GPIO; +with NRF_SVD.TWI; -package nRF51.TWI is +package nRF.TWI is type TWI_Speed is (TWI_100kbps, TWI_250kbps, TWI_400kbps); - type TWI_Master (Periph : not null access NRF51_SVD.TWI.TWI_Peripheral) is + type TWI_Master (Periph : not null access NRF_SVD.TWI.TWI_Peripheral) is new HAL.I2C.I2C_Port with private; procedure Enable (This : in out TWI_Master); @@ -96,9 +96,9 @@ package nRF51.TWI is private - type TWI_Master (Periph : not null access NRF51_SVD.TWI.TWI_Peripheral) is + type TWI_Master (Periph : not null access NRF_SVD.TWI.TWI_Peripheral) is new HAL.I2C.I2C_Port with record Do_Stop_Sequence : Boolean := True; end record; -end nRF51.TWI; +end nRF.TWI; diff --git a/arch/ARM/Nordic/drivers/nrf51-uart.adb b/arch/ARM/Nordic/drivers/nrf_common/nrf-uart.adb similarity index 96% rename from arch/ARM/Nordic/drivers/nrf51-uart.adb rename to arch/ARM/Nordic/drivers/nrf_common/nrf-uart.adb index 17258b9e7..bbc7b6b4c 100644 --- a/arch/ARM/Nordic/drivers/nrf51-uart.adb +++ b/arch/ARM/Nordic/drivers/nrf_common/nrf-uart.adb @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2019, AdaCore -- +-- Copyright (C) 2019-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -29,9 +29,9 @@ -- -- ------------------------------------------------------------------------------ -with NRF51_SVD.UART; use NRF51_SVD.UART; +with NRF_SVD.UART; use NRF_SVD.UART; -package body nRF51.UART is +package body nRF.UART is --------------- -- Configure -- @@ -50,8 +50,7 @@ package body nRF51.UART is ------------ procedure Enable (This : in out UART_Device; - Tx, Rx : GPIO_Pin_Index) - is + Tx, Rx : GPIO_Pin_Index) is begin This.Periph.PSELTXD := UInt32 (Tx); This.Periph.PSELRXD := UInt32 (Rx); @@ -61,11 +60,10 @@ package body nRF51.UART is This.Periph.TASKS_STARTRX := 1; This.Periph.TASKS_STARTTX := 1; - -- Send a first character to start the TXREADY events (See nRF51 Series + -- Send a first character to start the TXREADY events (See nRF Series -- Reference Manual Version 3.0 Figure 68: UART transmission). This.Periph.TXD.TXD := 0; end Enable; - ------------- -- Disable -- ------------- @@ -79,7 +77,6 @@ package body nRF51.UART is -- Stop TX and RX This.Periph.TASKS_STOPTX := 1; This.Periph.TASKS_STOPRX := 1; - end Disable; ------------------------- @@ -131,7 +128,7 @@ package body nRF51.UART is null; end loop; - -- Clear the event + -- Clear the event This.Periph.EVENTS_TXDRDY := 0; -- Send a character @@ -205,4 +202,4 @@ package body nRF51.UART is raise Program_Error; end Receive; -end nRF51.UART; +end nRF.UART; diff --git a/arch/ARM/Nordic/drivers/nrf51-uart.ads b/arch/ARM/Nordic/drivers/nrf_common/nrf-uart.ads similarity index 94% rename from arch/ARM/Nordic/drivers/nrf51-uart.ads rename to arch/ARM/Nordic/drivers/nrf_common/nrf-uart.ads index 8adaa236e..5f20659b1 100644 --- a/arch/ARM/Nordic/drivers/nrf51-uart.ads +++ b/arch/ARM/Nordic/drivers/nrf_common/nrf-uart.ads @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2019, AdaCore -- +-- Copyright (C) 2019-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -31,12 +31,12 @@ with HAL; use HAL; with HAL.UART; use HAL.UART; -with nRF51.GPIO; use nRF51.GPIO; -with NRF51_SVD.UART; +with nRF.GPIO; use nRF.GPIO; +with NRF_SVD.UART; -package nRF51.UART is +package nRF.UART is - type UART_Device (Periph : not null access NRF51_SVD.UART.UART_Peripheral) + type UART_Device (Periph : not null access NRF_SVD.UART.UART_Peripheral) is new HAL.UART.UART_Port with private; @@ -102,7 +102,7 @@ package nRF51.UART is private - type UART_Device (Periph : not null access NRF51_SVD.UART.UART_Peripheral) + type UART_Device (Periph : not null access NRF_SVD.UART.UART_Peripheral) is new HAL.UART.UART_Port with record Do_Stop_Sequence : Boolean := True; @@ -126,4 +126,4 @@ private Baud921600 => 16#0EBEDFA4#, Baud1M => 16#10000000#); -end nRF51.UART; +end nRF.UART; diff --git a/arch/ARM/Nordic/drivers/nrf51.ads b/arch/ARM/Nordic/drivers/nrf_common/nrf.ads similarity index 96% rename from arch/ARM/Nordic/drivers/nrf51.ads rename to arch/ARM/Nordic/drivers/nrf_common/nrf.ads index 49c36ef6d..b4f853144 100644 --- a/arch/ARM/Nordic/drivers/nrf51.ads +++ b/arch/ARM/Nordic/drivers/nrf_common/nrf.ads @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2016, AdaCore -- +-- Copyright (C) 2016-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -31,7 +31,7 @@ with System; -package nRF51 is +package nRF is type Event_Type is private; @@ -40,4 +40,4 @@ package nRF51 is private type Event_Type is new System.Address; type Task_Type is new System.Address; -end nRF51; +end nRF; diff --git a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-swi.ads b/arch/ARM/Nordic/svd/nrf51/nrf51_svd-swi.ads deleted file mode 100644 index 46806dc92..000000000 --- a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-swi.ads +++ /dev/null @@ -1,65 +0,0 @@ --- Copyright (c) 2013, Nordic Semiconductor ASA --- All rights reserved. --- --- Redistribution and use in source and binary forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- * Redistributions of source code must retain the above copyright notice, this --- list of conditions and the following disclaimer. --- --- * Redistributions in binary form must reproduce the above copyright notice, --- this list of conditions and the following disclaimer in the documentation --- and/or other materials provided with the distribution. --- --- * Neither the name of Nordic Semiconductor ASA nor the names of its --- contributors may be used to endorse or promote products derived from --- this software without specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE --- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE --- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE --- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL --- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR --- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER --- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, --- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE --- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --- - --- This spec has been automatically generated from nrf51.svd - -pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; -pragma Style_Checks (Off); - -with HAL; -with System; - -package NRF51_SVD.SWI is - pragma Preelaborate; - - --------------- - -- Registers -- - --------------- - - ----------------- - -- Peripherals -- - ----------------- - - -- SW Interrupts. - type SWI_Peripheral is record - -- Unused. - UNUSED : aliased HAL.UInt32; - end record - with Volatile; - - for SWI_Peripheral use record - UNUSED at 0 range 0 .. 31; - end record; - - -- SW Interrupts. - SWI_Periph : aliased SWI_Peripheral - with Import, Address => System'To_Address (16#40014000#); - -end NRF51_SVD.SWI; diff --git a/arch/ARM/Nordic/svd/nrf51/nrf51_svd.ads b/arch/ARM/Nordic/svd/nrf51/nrf51_svd.ads deleted file mode 100644 index 6fa097da8..000000000 --- a/arch/ARM/Nordic/svd/nrf51/nrf51_svd.ads +++ /dev/null @@ -1,114 +0,0 @@ --- Copyright (c) 2013, Nordic Semiconductor ASA --- All rights reserved. --- --- Redistribution and use in source and binary forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- * Redistributions of source code must retain the above copyright notice, this --- list of conditions and the following disclaimer. --- --- * Redistributions in binary form must reproduce the above copyright notice, --- this list of conditions and the following disclaimer in the documentation --- and/or other materials provided with the distribution. --- --- * Neither the name of Nordic Semiconductor ASA nor the names of its --- contributors may be used to endorse or promote products derived from --- this software without specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE --- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE --- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE --- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL --- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR --- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER --- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, --- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE --- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --- - --- This spec has been automatically generated from nrf51.svd - -pragma Restrictions (No_Elaboration_Code); -pragma Ada_2012; -pragma Style_Checks (Off); - -with System; - --- nRF51 reference description for radio MCU with ARM 32-bit Cortex-M0 --- Microcontroller at 16MHz CPU clock -package NRF51_SVD is - pragma Preelaborate; - - -------------------- - -- Base addresses -- - -------------------- - - POWER_Base : constant System.Address := - System'To_Address (16#40000000#); - CLOCK_Base : constant System.Address := - System'To_Address (16#40000000#); - MPU_Base : constant System.Address := - System'To_Address (16#40000000#); - AMLI_Base : constant System.Address := - System'To_Address (16#40000000#); - RADIO_Base : constant System.Address := - System'To_Address (16#40001000#); - UART0_Base : constant System.Address := - System'To_Address (16#40002000#); - SPI0_Base : constant System.Address := - System'To_Address (16#40003000#); - TWI0_Base : constant System.Address := - System'To_Address (16#40003000#); - SPI1_Base : constant System.Address := - System'To_Address (16#40004000#); - TWI1_Base : constant System.Address := - System'To_Address (16#40004000#); - SPIS1_Base : constant System.Address := - System'To_Address (16#40004000#); - SPIM1_Base : constant System.Address := - System'To_Address (16#40004000#); - GPIOTE_Base : constant System.Address := - System'To_Address (16#40006000#); - ADC_Base : constant System.Address := - System'To_Address (16#40007000#); - TIMER0_Base : constant System.Address := - System'To_Address (16#40008000#); - TIMER1_Base : constant System.Address := - System'To_Address (16#40009000#); - TIMER2_Base : constant System.Address := - System'To_Address (16#4000A000#); - RTC0_Base : constant System.Address := - System'To_Address (16#4000B000#); - TEMP_Base : constant System.Address := - System'To_Address (16#4000C000#); - RNG_Base : constant System.Address := - System'To_Address (16#4000D000#); - ECB_Base : constant System.Address := - System'To_Address (16#4000E000#); - AAR_Base : constant System.Address := - System'To_Address (16#4000F000#); - CCM_Base : constant System.Address := - System'To_Address (16#4000F000#); - WDT_Base : constant System.Address := - System'To_Address (16#40010000#); - RTC1_Base : constant System.Address := - System'To_Address (16#40011000#); - QDEC_Base : constant System.Address := - System'To_Address (16#40012000#); - LPCOMP_Base : constant System.Address := - System'To_Address (16#40013000#); - SWI_Base : constant System.Address := - System'To_Address (16#40014000#); - NVMC_Base : constant System.Address := - System'To_Address (16#4001E000#); - PPI_Base : constant System.Address := - System'To_Address (16#4001F000#); - FICR_Base : constant System.Address := - System'To_Address (16#10000000#); - UICR_Base : constant System.Address := - System'To_Address (16#10001000#); - GPIO_Base : constant System.Address := - System'To_Address (16#50000000#); - -end NRF51_SVD; diff --git a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-aar.ads b/arch/ARM/Nordic/svd/nrf51/nrf_svd-aar.ads similarity index 91% rename from arch/ARM/Nordic/svd/nrf51/nrf51_svd-aar.ads rename to arch/ARM/Nordic/svd/nrf51/nrf_svd-aar.ads index 4fbba49a0..93fb4db7d 100644 --- a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-aar.ads +++ b/arch/ARM/Nordic/svd/nrf51/nrf_svd-aar.ads @@ -36,7 +36,7 @@ pragma Style_Checks (Off); with HAL; with System; -package NRF51_SVD.AAR is +package NRF_SVD.AAR is pragma Preelaborate; --------------- @@ -45,8 +45,7 @@ package NRF51_SVD.AAR is -- Enable interrupt on END event. type INTENSET_END_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -57,8 +56,7 @@ package NRF51_SVD.AAR is -- Enable interrupt on END event. type INTENSET_END_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_End_Field_Reset, -- Enable interrupt on write. Set) @@ -69,8 +67,7 @@ package NRF51_SVD.AAR is -- Enable interrupt on RESOLVED event. type INTENSET_RESOLVED_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -81,8 +78,7 @@ package NRF51_SVD.AAR is -- Enable interrupt on RESOLVED event. type INTENSET_RESOLVED_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Resolved_Field_Reset, -- Enable interrupt on write. Set) @@ -93,8 +89,7 @@ package NRF51_SVD.AAR is -- Enable interrupt on NOTRESOLVED event. type INTENSET_NOTRESOLVED_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -105,8 +100,7 @@ package NRF51_SVD.AAR is -- Enable interrupt on NOTRESOLVED event. type INTENSET_NOTRESOLVED_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Notresolved_Field_Reset, -- Enable interrupt on write. Set) @@ -128,7 +122,7 @@ package NRF51_SVD.AAR is -- unspecified Reserved_3_31 : HAL.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENSET_Register use record @@ -140,8 +134,7 @@ package NRF51_SVD.AAR is -- Disable interrupt on ENDKSGEN event. type INTENCLR_END_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -152,8 +145,7 @@ package NRF51_SVD.AAR is -- Disable interrupt on ENDKSGEN event. type INTENCLR_END_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_End_Field_Reset, -- Disable interrupt on write. Clear) @@ -164,8 +156,7 @@ package NRF51_SVD.AAR is -- Disable interrupt on RESOLVED event. type INTENCLR_RESOLVED_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -176,8 +167,7 @@ package NRF51_SVD.AAR is -- Disable interrupt on RESOLVED event. type INTENCLR_RESOLVED_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Resolved_Field_Reset, -- Disable interrupt on write. Clear) @@ -188,8 +178,7 @@ package NRF51_SVD.AAR is -- Disable interrupt on NOTRESOLVED event. type INTENCLR_NOTRESOLVED_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -200,8 +189,7 @@ package NRF51_SVD.AAR is -- Disable interrupt on NOTRESOLVED event. type INTENCLR_NOTRESOLVED_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Notresolved_Field_Reset, -- Disable interrupt on write. Clear) @@ -223,7 +211,7 @@ package NRF51_SVD.AAR is -- unspecified Reserved_3_31 : HAL.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENCLR_Register use record @@ -242,7 +230,7 @@ package NRF51_SVD.AAR is -- unspecified Reserved_4_31 : HAL.UInt28; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for STATUS_Register use record @@ -252,8 +240,7 @@ package NRF51_SVD.AAR is -- Enable AAR. type ENABLE_ENABLE_Field is - ( - -- Disabled AAR. + (-- Disabled AAR. Disabled, -- Enable AAR. Enabled) @@ -265,11 +252,11 @@ package NRF51_SVD.AAR is -- Enable AAR. type ENABLE_Register is record -- Enable AAR. - ENABLE : ENABLE_ENABLE_Field := NRF51_SVD.AAR.Disabled; + ENABLE : ENABLE_ENABLE_Field := NRF_SVD.AAR.Disabled; -- unspecified Reserved_2_31 : HAL.UInt30 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for ENABLE_Register use record @@ -286,7 +273,7 @@ package NRF51_SVD.AAR is -- unspecified Reserved_5_31 : HAL.UInt27 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for NIRK_Register use record @@ -296,8 +283,7 @@ package NRF51_SVD.AAR is -- Peripheral power control. type POWER_POWER_Field is - ( - -- Module power disabled. + (-- Module power disabled. Disabled, -- Module power enabled. Enabled) @@ -309,11 +295,11 @@ package NRF51_SVD.AAR is -- Peripheral power control. type POWER_Register is record -- Peripheral power control. - POWER : POWER_POWER_Field := NRF51_SVD.AAR.Disabled; + POWER : POWER_POWER_Field := NRF_SVD.AAR.Disabled; -- unspecified Reserved_1_31 : HAL.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for POWER_Register use record @@ -379,6 +365,6 @@ package NRF51_SVD.AAR is -- Accelerated Address Resolver. AAR_Periph : aliased AAR_Peripheral - with Import, Address => System'To_Address (16#4000F000#); + with Import, Address => AAR_Base; -end NRF51_SVD.AAR; +end NRF_SVD.AAR; diff --git a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-adc.ads b/arch/ARM/Nordic/svd/nrf51/nrf_svd-adc.ads similarity index 83% rename from arch/ARM/Nordic/svd/nrf51/nrf51_svd-adc.ads rename to arch/ARM/Nordic/svd/nrf51/nrf_svd-adc.ads index 524be0658..cac18c68d 100644 --- a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-adc.ads +++ b/arch/ARM/Nordic/svd/nrf51/nrf_svd-adc.ads @@ -36,7 +36,7 @@ pragma Style_Checks (Off); with HAL; with System; -package NRF51_SVD.ADC is +package NRF_SVD.ADC is pragma Preelaborate; --------------- @@ -45,8 +45,7 @@ package NRF51_SVD.ADC is -- Enable interrupt on END event. type INTENSET_END_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -57,8 +56,7 @@ package NRF51_SVD.ADC is -- Enable interrupt on END event. type INTENSET_END_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_End_Field_Reset, -- Enable interrupt on write. Set) @@ -74,7 +72,7 @@ package NRF51_SVD.ADC is -- unspecified Reserved_1_31 : HAL.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENSET_Register use record @@ -84,8 +82,7 @@ package NRF51_SVD.ADC is -- Disable interrupt on END event. type INTENCLR_END_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -96,8 +93,7 @@ package NRF51_SVD.ADC is -- Disable interrupt on END event. type INTENCLR_END_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_End_Field_Reset, -- Disable interrupt on write. Clear) @@ -113,7 +109,7 @@ package NRF51_SVD.ADC is -- unspecified Reserved_1_31 : HAL.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENCLR_Register use record @@ -123,8 +119,7 @@ package NRF51_SVD.ADC is -- ADC busy register. type BUSY_BUSY_Field is - ( - -- No ongoing ADC conversion is taking place. ADC is ready. + (-- No ongoing ADC conversion is taking place. ADC is ready. Ready, -- An ADC conversion is taking place. ADC is busy. Busy) @@ -140,7 +135,7 @@ package NRF51_SVD.ADC is -- unspecified Reserved_1_31 : HAL.UInt31; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for BUSY_Register use record @@ -150,11 +145,10 @@ package NRF51_SVD.ADC is -- ADC enable. type ENABLE_ENABLE_Field is - ( - -- ADC is disabled. + (-- ADC is disabled. Disabled, -- ADC is enabled. If an analog input pin is selected as source of the - -- conversion, the selected pin is configured as an analog input. +-- conversion, the selected pin is configured as an analog input. Enabled) with Size => 2; for ENABLE_ENABLE_Field use @@ -164,11 +158,11 @@ package NRF51_SVD.ADC is -- ADC enable. type ENABLE_Register is record -- ADC enable. - ENABLE : ENABLE_ENABLE_Field := NRF51_SVD.ADC.Disabled; + ENABLE : ENABLE_ENABLE_Field := NRF_SVD.ADC.Disabled; -- unspecified Reserved_2_31 : HAL.UInt30 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for ENABLE_Register use record @@ -178,30 +172,28 @@ package NRF51_SVD.ADC is -- ADC resolution. type CONFIG_RES_Field is - ( - -- 8bit ADC resolution. - CONFIG_RES_Field_8BIT, + (-- 8bit ADC resolution. + Val_8BIT, -- 9bit ADC resolution. - CONFIG_RES_Field_9BIT, + Val_9BIT, -- 10bit ADC resolution. - CONFIG_RES_Field_10BIT) + Val_10BIT) with Size => 2; for CONFIG_RES_Field use - (CONFIG_RES_Field_8BIT => 0, - CONFIG_RES_Field_9BIT => 1, - CONFIG_RES_Field_10BIT => 2); + (Val_8BIT => 0, + Val_9BIT => 1, + Val_10BIT => 2); -- ADC input selection. type CONFIG_INPSEL_Field is - ( - -- Analog input specified by PSEL with no prescaling used as input for - -- the conversion. + (-- Analog input specified by PSEL with no prescaling used as input for the +-- conversion. Analoginputnoprescaling, - -- Analog input specified by PSEL with 2/3 prescaling used as input for - -- the conversion. + -- Analog input specified by PSEL with 2/3 prescaling used as input for the +-- conversion. Analoginputtwothirdsprescaling, - -- Analog input specified by PSEL with 1/3 prescaling used as input for - -- the conversion. + -- Analog input specified by PSEL with 1/3 prescaling used as input for the +-- conversion. Analoginputonethirdprescaling, -- Supply voltage with 2/3 prescaling used as input for the conversion. Supplytwothirdsprescaling, @@ -217,17 +209,15 @@ package NRF51_SVD.ADC is -- ADC reference selection. type CONFIG_REFSEL_Field is - ( - -- Use internal 1.2V bandgap voltage as reference for conversion. + (-- Use internal 1.2V bandgap voltage as reference for conversion. Vbg, - -- Use external source configured by EXTREFSEL as reference for - -- conversion. + -- Use external source configured by EXTREFSEL as reference for conversion. External, - -- Use supply voltage with 1/2 prescaling as reference for conversion. - -- Only usable when supply voltage is between 1.7V and 2.6V. + -- Use supply voltage with 1/2 prescaling as reference for conversion. Only +-- usable when supply voltage is between 1.7V and 2.6V. Supplyonehalfprescaling, - -- Use supply voltage with 1/3 prescaling as reference for conversion. - -- Only usable when supply voltage is between 2.5V and 3.6V. + -- Use supply voltage with 1/3 prescaling as reference for conversion. Only +-- usable when supply voltage is between 2.5V and 3.6V. Supplyonethirdprescaling) with Size => 2; for CONFIG_REFSEL_Field use @@ -238,8 +228,7 @@ package NRF51_SVD.ADC is -- ADC analog pin selection. type CONFIG_PSEL_Field is - ( - -- Analog input pins disabled. + (-- Analog input pins disabled. Disabled, -- Use analog input 0 as analog input. Analoginput0, @@ -271,8 +260,7 @@ package NRF51_SVD.ADC is -- ADC external reference pin selection. type CONFIG_EXTREFSEL_Field is - ( - -- Analog external reference inputs disabled. + (-- Analog external reference inputs disabled. None, -- Use analog reference 0 as reference. Analogreference0, @@ -287,23 +275,22 @@ package NRF51_SVD.ADC is -- ADC configuration register. type CONFIG_Register is record -- ADC resolution. - RES : CONFIG_RES_Field := - NRF51_SVD.ADC.CONFIG_RES_Field_8BIT; + RES : CONFIG_RES_Field := NRF_SVD.ADC.Val_8BIT; -- ADC input selection. INPSEL : CONFIG_INPSEL_Field := - NRF51_SVD.ADC.Supplyonethirdprescaling; + NRF_SVD.ADC.Supplyonethirdprescaling; -- ADC reference selection. - REFSEL : CONFIG_REFSEL_Field := NRF51_SVD.ADC.Vbg; + REFSEL : CONFIG_REFSEL_Field := NRF_SVD.ADC.Vbg; -- unspecified Reserved_7_7 : HAL.Bit := 16#0#; -- ADC analog pin selection. - PSEL : CONFIG_PSEL_Field := NRF51_SVD.ADC.Disabled; + PSEL : CONFIG_PSEL_Field := NRF_SVD.ADC.Disabled; -- ADC external reference pin selection. - EXTREFSEL : CONFIG_EXTREFSEL_Field := NRF51_SVD.ADC.None; + EXTREFSEL : CONFIG_EXTREFSEL_Field := NRF_SVD.ADC.None; -- unspecified Reserved_18_31 : HAL.UInt14 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for CONFIG_Register use record @@ -325,7 +312,7 @@ package NRF51_SVD.ADC is -- unspecified Reserved_10_31 : HAL.UInt22; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for RESULT_Register use record @@ -335,8 +322,7 @@ package NRF51_SVD.ADC is -- Peripheral power control. type POWER_POWER_Field is - ( - -- Module power disabled. + (-- Module power disabled. Disabled, -- Module power enabled. Enabled) @@ -348,11 +334,11 @@ package NRF51_SVD.ADC is -- Peripheral power control. type POWER_Register is record -- Peripheral power control. - POWER : POWER_POWER_Field := NRF51_SVD.ADC.Disabled; + POWER : POWER_POWER_Field := NRF_SVD.ADC.Disabled; -- unspecified Reserved_1_31 : HAL.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for POWER_Register use record @@ -404,6 +390,6 @@ package NRF51_SVD.ADC is -- Analog to digital converter. ADC_Periph : aliased ADC_Peripheral - with Import, Address => System'To_Address (16#40007000#); + with Import, Address => ADC_Base; -end NRF51_SVD.ADC; +end NRF_SVD.ADC; diff --git a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-amli.ads b/arch/ARM/Nordic/svd/nrf51/nrf_svd-amli.ads similarity index 93% rename from arch/ARM/Nordic/svd/nrf51/nrf51_svd-amli.ads rename to arch/ARM/Nordic/svd/nrf51/nrf_svd-amli.ads index 7233386ec..9073f8a3a 100644 --- a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-amli.ads +++ b/arch/ARM/Nordic/svd/nrf51/nrf_svd-amli.ads @@ -36,7 +36,7 @@ pragma Style_Checks (Off); with HAL; with System; -package NRF51_SVD.AMLI is +package NRF_SVD.AMLI is pragma Preelaborate; --------------- @@ -49,8 +49,7 @@ package NRF51_SVD.AMLI is -- Configuration field for RAM block 0. type CPU0_RAM0_Field is - ( - -- Priority 0. + (-- Priority 0. Pri0, -- Priority 2. Pri2, @@ -94,7 +93,7 @@ package NRF51_SVD.AMLI is Arr : CPU0_RAMPRI_RAM_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for CPU0_RAMPRI_Register use record @@ -104,8 +103,7 @@ package NRF51_SVD.AMLI is -- Configuration field for RAM block 0. type SPIS1_RAM0_Field is - ( - -- Priority 0. + (-- Priority 0. Pri0, -- Priority 2. Pri2, @@ -149,7 +147,7 @@ package NRF51_SVD.AMLI is Arr : SPIS1_RAMPRI_RAM_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for SPIS1_RAMPRI_Register use record @@ -159,8 +157,7 @@ package NRF51_SVD.AMLI is -- Configuration field for RAM block 0. type RADIO_RAM0_Field is - ( - -- Priority 0. + (-- Priority 0. Pri0, -- Priority 2. Pri2, @@ -204,7 +201,7 @@ package NRF51_SVD.AMLI is Arr : RADIO_RAMPRI_RAM_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for RADIO_RAMPRI_Register use record @@ -214,8 +211,7 @@ package NRF51_SVD.AMLI is -- Configuration field for RAM block 0. type ECB_RAM0_Field is - ( - -- Priority 0. + (-- Priority 0. Pri0, -- Priority 2. Pri2, @@ -259,7 +255,7 @@ package NRF51_SVD.AMLI is Arr : ECB_RAMPRI_RAM_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for ECB_RAMPRI_Register use record @@ -269,8 +265,7 @@ package NRF51_SVD.AMLI is -- Configuration field for RAM block 0. type CCM_RAM0_Field is - ( - -- Priority 0. + (-- Priority 0. Pri0, -- Priority 2. Pri2, @@ -314,7 +309,7 @@ package NRF51_SVD.AMLI is Arr : CCM_RAMPRI_RAM_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for CCM_RAMPRI_Register use record @@ -324,8 +319,7 @@ package NRF51_SVD.AMLI is -- Configuration field for RAM block 0. type AAR_RAM0_Field is - ( - -- Priority 0. + (-- Priority 0. Pri0, -- Priority 2. Pri2, @@ -369,7 +363,7 @@ package NRF51_SVD.AMLI is Arr : AAR_RAMPRI_RAM_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for AAR_RAMPRI_Register use record @@ -392,7 +386,7 @@ package NRF51_SVD.AMLI is -- Configurable priority configuration register for AAR. AAR : aliased AAR_RAMPRI_Register; end record - with Volatile, Size => 192; + with Size => 192; for AMLI_RAMPRI_Cluster use record CPU0 at 16#0# range 0 .. 31; @@ -420,6 +414,6 @@ package NRF51_SVD.AMLI is -- AHB Multi-Layer Interface. AMLI_Periph : aliased AMLI_Peripheral - with Import, Address => System'To_Address (16#40000000#); + with Import, Address => AMLI_Base; -end NRF51_SVD.AMLI; +end NRF_SVD.AMLI; diff --git a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-ccm.ads b/arch/ARM/Nordic/svd/nrf51/nrf_svd-ccm.ads similarity index 90% rename from arch/ARM/Nordic/svd/nrf51/nrf51_svd-ccm.ads rename to arch/ARM/Nordic/svd/nrf51/nrf_svd-ccm.ads index 6d48a0d91..b4b535ffd 100644 --- a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-ccm.ads +++ b/arch/ARM/Nordic/svd/nrf51/nrf_svd-ccm.ads @@ -36,7 +36,7 @@ pragma Style_Checks (Off); with HAL; with System; -package NRF51_SVD.CCM is +package NRF_SVD.CCM is pragma Preelaborate; --------------- @@ -45,8 +45,7 @@ package NRF51_SVD.CCM is -- Shortcut between ENDKSGEN event and CRYPT task. type SHORTS_ENDKSGEN_CRYPT_Field is - ( - -- Shortcut disabled. + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) @@ -58,11 +57,11 @@ package NRF51_SVD.CCM is -- Shortcuts for the CCM. type SHORTS_Register is record -- Shortcut between ENDKSGEN event and CRYPT task. - ENDKSGEN_CRYPT : SHORTS_ENDKSGEN_CRYPT_Field := NRF51_SVD.CCM.Disabled; + ENDKSGEN_CRYPT : SHORTS_ENDKSGEN_CRYPT_Field := NRF_SVD.CCM.Disabled; -- unspecified Reserved_1_31 : HAL.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for SHORTS_Register use record @@ -72,8 +71,7 @@ package NRF51_SVD.CCM is -- Enable interrupt on ENDKSGEN event. type INTENSET_ENDKSGEN_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -84,8 +82,7 @@ package NRF51_SVD.CCM is -- Enable interrupt on ENDKSGEN event. type INTENSET_ENDKSGEN_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Endksgen_Field_Reset, -- Enable interrupt on write. Set) @@ -96,8 +93,7 @@ package NRF51_SVD.CCM is -- Enable interrupt on ENDCRYPT event. type INTENSET_ENDCRYPT_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -108,8 +104,7 @@ package NRF51_SVD.CCM is -- Enable interrupt on ENDCRYPT event. type INTENSET_ENDCRYPT_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Endcrypt_Field_Reset, -- Enable interrupt on write. Set) @@ -120,8 +115,7 @@ package NRF51_SVD.CCM is -- Enable interrupt on ERROR event. type INTENSET_ERROR_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -132,8 +126,7 @@ package NRF51_SVD.CCM is -- Enable interrupt on ERROR event. type INTENSET_ERROR_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Error_Field_Reset, -- Enable interrupt on write. Set) @@ -155,7 +148,7 @@ package NRF51_SVD.CCM is -- unspecified Reserved_3_31 : HAL.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENSET_Register use record @@ -167,8 +160,7 @@ package NRF51_SVD.CCM is -- Disable interrupt on ENDKSGEN event. type INTENCLR_ENDKSGEN_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -179,8 +171,7 @@ package NRF51_SVD.CCM is -- Disable interrupt on ENDKSGEN event. type INTENCLR_ENDKSGEN_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Endksgen_Field_Reset, -- Disable interrupt on write. Clear) @@ -191,8 +182,7 @@ package NRF51_SVD.CCM is -- Disable interrupt on ENDCRYPT event. type INTENCLR_ENDCRYPT_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -203,8 +193,7 @@ package NRF51_SVD.CCM is -- Disable interrupt on ENDCRYPT event. type INTENCLR_ENDCRYPT_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Endcrypt_Field_Reset, -- Disable interrupt on write. Clear) @@ -215,8 +204,7 @@ package NRF51_SVD.CCM is -- Disable interrupt on ERROR event. type INTENCLR_ERROR_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -227,8 +215,7 @@ package NRF51_SVD.CCM is -- Disable interrupt on ERROR event. type INTENCLR_ERROR_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Error_Field_Reset, -- Disable interrupt on write. Clear) @@ -250,7 +237,7 @@ package NRF51_SVD.CCM is -- unspecified Reserved_3_31 : HAL.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENCLR_Register use record @@ -262,8 +249,7 @@ package NRF51_SVD.CCM is -- Result of the MIC check performed during the previous CCM RX STARTCRYPT type MICSTATUS_MICSTATUS_Field is - ( - -- MIC check failed. + (-- MIC check failed. Checkfailed, -- MIC check passed. Checkpassed) @@ -280,7 +266,7 @@ package NRF51_SVD.CCM is -- unspecified Reserved_1_31 : HAL.UInt31; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for MICSTATUS_Register use record @@ -290,8 +276,7 @@ package NRF51_SVD.CCM is -- CCM enable. type ENABLE_ENABLE_Field is - ( - -- CCM is disabled. + (-- CCM is disabled. Disabled, -- CCM is enabled. Enabled) @@ -303,11 +288,11 @@ package NRF51_SVD.CCM is -- CCM enable. type ENABLE_Register is record -- CCM enable. - ENABLE : ENABLE_ENABLE_Field := NRF51_SVD.CCM.Disabled; + ENABLE : ENABLE_ENABLE_Field := NRF_SVD.CCM.Disabled; -- unspecified Reserved_2_31 : HAL.UInt30 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for ENABLE_Register use record @@ -317,8 +302,7 @@ package NRF51_SVD.CCM is -- CCM mode operation. type MODE_MODE_Field is - ( - -- CCM mode TX + (-- CCM mode TX Encryption, -- CCM mode TX Decryption) @@ -330,11 +314,11 @@ package NRF51_SVD.CCM is -- Operation mode. type MODE_Register is record -- CCM mode operation. - MODE : MODE_MODE_Field := NRF51_SVD.CCM.Decryption; + MODE : MODE_MODE_Field := NRF_SVD.CCM.Decryption; -- unspecified Reserved_1_31 : HAL.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for MODE_Register use record @@ -344,8 +328,7 @@ package NRF51_SVD.CCM is -- Peripheral power control. type POWER_POWER_Field is - ( - -- Module power disabled. + (-- Module power disabled. Disabled, -- Module power enabled. Enabled) @@ -357,11 +340,11 @@ package NRF51_SVD.CCM is -- Peripheral power control. type POWER_Register is record -- Peripheral power control. - POWER : POWER_POWER_Field := NRF51_SVD.CCM.Disabled; + POWER : POWER_POWER_Field := NRF_SVD.CCM.Disabled; -- unspecified Reserved_1_31 : HAL.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for POWER_Register use record @@ -437,6 +420,6 @@ package NRF51_SVD.CCM is -- AES CCM Mode Encryption. CCM_Periph : aliased CCM_Peripheral - with Import, Address => System'To_Address (16#4000F000#); + with Import, Address => CCM_Base; -end NRF51_SVD.CCM; +end NRF_SVD.CCM; diff --git a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-clock.ads b/arch/ARM/Nordic/svd/nrf51/nrf_svd-clock.ads similarity index 89% rename from arch/ARM/Nordic/svd/nrf51/nrf51_svd-clock.ads rename to arch/ARM/Nordic/svd/nrf51/nrf_svd-clock.ads index 4e61aa15f..bf8be4daa 100644 --- a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-clock.ads +++ b/arch/ARM/Nordic/svd/nrf51/nrf_svd-clock.ads @@ -36,7 +36,7 @@ pragma Style_Checks (Off); with HAL; with System; -package NRF51_SVD.CLOCK is +package NRF_SVD.CLOCK is pragma Preelaborate; --------------- @@ -45,8 +45,7 @@ package NRF51_SVD.CLOCK is -- Enable interrupt on HFCLKSTARTED event. type INTENSET_HFCLKSTARTED_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -57,8 +56,7 @@ package NRF51_SVD.CLOCK is -- Enable interrupt on HFCLKSTARTED event. type INTENSET_HFCLKSTARTED_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Hfclkstarted_Field_Reset, -- Enable interrupt on write. Set) @@ -69,8 +67,7 @@ package NRF51_SVD.CLOCK is -- Enable interrupt on LFCLKSTARTED event. type INTENSET_LFCLKSTARTED_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -81,8 +78,7 @@ package NRF51_SVD.CLOCK is -- Enable interrupt on LFCLKSTARTED event. type INTENSET_LFCLKSTARTED_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Lfclkstarted_Field_Reset, -- Enable interrupt on write. Set) @@ -93,8 +89,7 @@ package NRF51_SVD.CLOCK is -- Enable interrupt on DONE event. type INTENSET_DONE_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -105,8 +100,7 @@ package NRF51_SVD.CLOCK is -- Enable interrupt on DONE event. type INTENSET_DONE_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Done_Field_Reset, -- Enable interrupt on write. Set) @@ -117,8 +111,7 @@ package NRF51_SVD.CLOCK is -- Enable interrupt on CTTO event. type INTENSET_CTTO_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -129,8 +122,7 @@ package NRF51_SVD.CLOCK is -- Enable interrupt on CTTO event. type INTENSET_CTTO_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Ctto_Field_Reset, -- Enable interrupt on write. Set) @@ -156,7 +148,7 @@ package NRF51_SVD.CLOCK is -- unspecified Reserved_5_31 : HAL.UInt27 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENSET_Register use record @@ -170,8 +162,7 @@ package NRF51_SVD.CLOCK is -- Disable interrupt on HFCLKSTARTED event. type INTENCLR_HFCLKSTARTED_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -182,8 +173,7 @@ package NRF51_SVD.CLOCK is -- Disable interrupt on HFCLKSTARTED event. type INTENCLR_HFCLKSTARTED_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Hfclkstarted_Field_Reset, -- Disable interrupt on write. Clear) @@ -194,8 +184,7 @@ package NRF51_SVD.CLOCK is -- Disable interrupt on LFCLKSTARTED event. type INTENCLR_LFCLKSTARTED_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -206,8 +195,7 @@ package NRF51_SVD.CLOCK is -- Disable interrupt on LFCLKSTARTED event. type INTENCLR_LFCLKSTARTED_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Lfclkstarted_Field_Reset, -- Disable interrupt on write. Clear) @@ -218,8 +206,7 @@ package NRF51_SVD.CLOCK is -- Disable interrupt on DONE event. type INTENCLR_DONE_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -230,8 +217,7 @@ package NRF51_SVD.CLOCK is -- Disable interrupt on DONE event. type INTENCLR_DONE_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Done_Field_Reset, -- Disable interrupt on write. Clear) @@ -242,8 +228,7 @@ package NRF51_SVD.CLOCK is -- Disable interrupt on CTTO event. type INTENCLR_CTTO_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -254,8 +239,7 @@ package NRF51_SVD.CLOCK is -- Disable interrupt on CTTO event. type INTENCLR_CTTO_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Ctto_Field_Reset, -- Disable interrupt on write. Clear) @@ -281,7 +265,7 @@ package NRF51_SVD.CLOCK is -- unspecified Reserved_5_31 : HAL.UInt27 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENCLR_Register use record @@ -295,8 +279,7 @@ package NRF51_SVD.CLOCK is -- Task HFCLKSTART trigger status. type HFCLKRUN_STATUS_Field is - ( - -- Task HFCLKSTART has not been triggered. + (-- Task HFCLKSTART has not been triggered. Nottriggered, -- Task HFCLKSTART has been triggered. Triggered) @@ -312,7 +295,7 @@ package NRF51_SVD.CLOCK is -- unspecified Reserved_1_31 : HAL.UInt31; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for HFCLKRUN_Register use record @@ -322,11 +305,10 @@ package NRF51_SVD.CLOCK is -- Active clock source for the HF clock. type HFCLKSTAT_SRC_Field is - ( - -- Internal 16MHz RC oscillator running and generating the HFCLK clock. + (-- Internal 16MHz RC oscillator running and generating the HFCLK clock. Rc, - -- External 16MHz/32MHz crystal oscillator running and generating the - -- HFCLK clock. + -- External 16MHz/32MHz crystal oscillator running and generating the HFCLK +-- clock. Xtal) with Size => 1; for HFCLKSTAT_SRC_Field use @@ -335,8 +317,7 @@ package NRF51_SVD.CLOCK is -- State for the HFCLK. type HFCLKSTAT_STATE_Field is - ( - -- HFCLK clock not running. + (-- HFCLK clock not running. Notrunning, -- HFCLK clock running. Running) @@ -356,7 +337,7 @@ package NRF51_SVD.CLOCK is -- unspecified Reserved_17_31 : HAL.UInt15; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for HFCLKSTAT_Register use record @@ -368,8 +349,7 @@ package NRF51_SVD.CLOCK is -- Task LFCLKSTART triggered status. type LFCLKRUN_STATUS_Field is - ( - -- Task LFCLKSTART has not been triggered. + (-- Task LFCLKSTART has not been triggered. Nottriggered, -- Task LFCLKSTART has been triggered. Triggered) @@ -385,7 +365,7 @@ package NRF51_SVD.CLOCK is -- unspecified Reserved_1_31 : HAL.UInt31; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for LFCLKRUN_Register use record @@ -395,14 +375,12 @@ package NRF51_SVD.CLOCK is -- Active clock source for the LF clock. type LFCLKSTAT_SRC_Field is - ( - -- Internal 32KiHz RC oscillator running and generating the LFCLK clock. + (-- Internal 32KiHz RC oscillator running and generating the LFCLK clock. Rc, - -- External 32KiHz crystal oscillator running and generating the LFCLK - -- clock. + -- External 32KiHz crystal oscillator running and generating the LFCLK clock. Xtal, - -- Internal 32KiHz synthesizer from the HFCLK running and generating the - -- LFCLK clock. + -- Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK +-- clock. Synth) with Size => 2; for LFCLKSTAT_SRC_Field use @@ -412,8 +390,7 @@ package NRF51_SVD.CLOCK is -- State for the LF clock. type LFCLKSTAT_STATE_Field is - ( - -- LFCLK clock not running. + (-- LFCLK clock not running. Notrunning, -- LFCLK clock running. Running) @@ -433,7 +410,7 @@ package NRF51_SVD.CLOCK is -- unspecified Reserved_17_31 : HAL.UInt15; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for LFCLKSTAT_Register use record @@ -445,8 +422,7 @@ package NRF51_SVD.CLOCK is -- Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. type LFCLKSRCCOPY_SRC_Field is - ( - -- Internal 32KiHz RC oscillator. + (-- Internal 32KiHz RC oscillator. Rc, -- External 32KiHz crystal. Xtal, @@ -466,7 +442,7 @@ package NRF51_SVD.CLOCK is -- unspecified Reserved_2_31 : HAL.UInt30; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for LFCLKSRCCOPY_Register use record @@ -476,8 +452,7 @@ package NRF51_SVD.CLOCK is -- Clock source. type LFCLKSRC_SRC_Field is - ( - -- Internal 32KiHz RC oscillator. + (-- Internal 32KiHz RC oscillator. Rc, -- External 32KiHz crystal. Xtal, @@ -492,11 +467,11 @@ package NRF51_SVD.CLOCK is -- Clock source for the LFCLK clock. type LFCLKSRC_Register is record -- Clock source. - SRC : LFCLKSRC_SRC_Field := NRF51_SVD.CLOCK.Rc; + SRC : LFCLKSRC_SRC_Field := NRF_SVD.CLOCK.Rc; -- unspecified Reserved_2_31 : HAL.UInt30 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for LFCLKSRC_Register use record @@ -513,7 +488,7 @@ package NRF51_SVD.CLOCK is -- unspecified Reserved_7_31 : HAL.UInt25 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for CTIV_Register use record @@ -523,25 +498,23 @@ package NRF51_SVD.CLOCK is -- External Xtal frequency selection. type XTALFREQ_XTALFREQ_Field is - ( - -- 32MHz xtal is used as source for the HFCLK oscillator. - XTALFREQ_XTALFREQ_Field_32Mhz, + (-- 32MHz xtal is used as source for the HFCLK oscillator. + Val_32Mhz, -- 16MHz xtal is used as source for the HFCLK oscillator. - XTALFREQ_XTALFREQ_Field_16Mhz) + Val_16Mhz) with Size => 8; for XTALFREQ_XTALFREQ_Field use - (XTALFREQ_XTALFREQ_Field_32Mhz => 0, - XTALFREQ_XTALFREQ_Field_16Mhz => 255); + (Val_32Mhz => 0, + Val_16Mhz => 255); -- Crystal frequency. type XTALFREQ_Register is record -- External Xtal frequency selection. - XTALFREQ : XTALFREQ_XTALFREQ_Field := - NRF51_SVD.CLOCK.XTALFREQ_XTALFREQ_Field_16Mhz; + XTALFREQ : XTALFREQ_XTALFREQ_Field := NRF_SVD.CLOCK.Val_16Mhz; -- unspecified Reserved_8_31 : HAL.UInt24 := 16#FFFFFF#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for XTALFREQ_Register use record @@ -627,6 +600,6 @@ package NRF51_SVD.CLOCK is -- Clock control. CLOCK_Periph : aliased CLOCK_Peripheral - with Import, Address => System'To_Address (16#40000000#); + with Import, Address => CLOCK_Base; -end NRF51_SVD.CLOCK; +end NRF_SVD.CLOCK; diff --git a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-ecb.ads b/arch/ARM/Nordic/svd/nrf51/nrf_svd-ecb.ads similarity index 91% rename from arch/ARM/Nordic/svd/nrf51/nrf51_svd-ecb.ads rename to arch/ARM/Nordic/svd/nrf51/nrf_svd-ecb.ads index 665f86de7..4eb2d2548 100644 --- a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-ecb.ads +++ b/arch/ARM/Nordic/svd/nrf51/nrf_svd-ecb.ads @@ -36,7 +36,7 @@ pragma Style_Checks (Off); with HAL; with System; -package NRF51_SVD.ECB is +package NRF_SVD.ECB is pragma Preelaborate; --------------- @@ -45,8 +45,7 @@ package NRF51_SVD.ECB is -- Enable interrupt on ENDECB event. type INTENSET_ENDECB_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -57,8 +56,7 @@ package NRF51_SVD.ECB is -- Enable interrupt on ENDECB event. type INTENSET_ENDECB_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Endecb_Field_Reset, -- Enable interrupt on write. Set) @@ -69,8 +67,7 @@ package NRF51_SVD.ECB is -- Enable interrupt on ERRORECB event. type INTENSET_ERRORECB_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -81,8 +78,7 @@ package NRF51_SVD.ECB is -- Enable interrupt on ERRORECB event. type INTENSET_ERRORECB_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Errorecb_Field_Reset, -- Enable interrupt on write. Set) @@ -101,7 +97,7 @@ package NRF51_SVD.ECB is -- unspecified Reserved_2_31 : HAL.UInt30 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENSET_Register use record @@ -112,8 +108,7 @@ package NRF51_SVD.ECB is -- Disable interrupt on ENDECB event. type INTENCLR_ENDECB_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -124,8 +119,7 @@ package NRF51_SVD.ECB is -- Disable interrupt on ENDECB event. type INTENCLR_ENDECB_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Endecb_Field_Reset, -- Disable interrupt on write. Clear) @@ -136,8 +130,7 @@ package NRF51_SVD.ECB is -- Disable interrupt on ERRORECB event. type INTENCLR_ERRORECB_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -148,8 +141,7 @@ package NRF51_SVD.ECB is -- Disable interrupt on ERRORECB event. type INTENCLR_ERRORECB_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Errorecb_Field_Reset, -- Disable interrupt on write. Clear) @@ -168,7 +160,7 @@ package NRF51_SVD.ECB is -- unspecified Reserved_2_31 : HAL.UInt30 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENCLR_Register use record @@ -179,8 +171,7 @@ package NRF51_SVD.ECB is -- Peripheral power control. type POWER_POWER_Field is - ( - -- Module power disabled. + (-- Module power disabled. Disabled, -- Module power enabled. Enabled) @@ -192,11 +183,11 @@ package NRF51_SVD.ECB is -- Peripheral power control. type POWER_Register is record -- Peripheral power control. - POWER : POWER_POWER_Field := NRF51_SVD.ECB.Disabled; + POWER : POWER_POWER_Field := NRF_SVD.ECB.Disabled; -- unspecified Reserved_1_31 : HAL.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for POWER_Register use record @@ -245,6 +236,6 @@ package NRF51_SVD.ECB is -- AES ECB Mode Encryption. ECB_Periph : aliased ECB_Peripheral - with Import, Address => System'To_Address (16#4000E000#); + with Import, Address => ECB_Base; -end NRF51_SVD.ECB; +end NRF_SVD.ECB; diff --git a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-ficr.ads b/arch/ARM/Nordic/svd/nrf51/nrf_svd-ficr.ads similarity index 89% rename from arch/ARM/Nordic/svd/nrf51/nrf51_svd-ficr.ads rename to arch/ARM/Nordic/svd/nrf51/nrf_svd-ficr.ads index b0c1a6e72..3855b10c9 100644 --- a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-ficr.ads +++ b/arch/ARM/Nordic/svd/nrf51/nrf_svd-ficr.ads @@ -36,7 +36,7 @@ pragma Style_Checks (Off); with HAL; with System; -package NRF51_SVD.FICR is +package NRF_SVD.FICR is pragma Preelaborate; --------------- @@ -45,8 +45,7 @@ package NRF51_SVD.FICR is -- Pre-programmed factory code present. type PPFC_PPFC_Field is - ( - -- Present. + (-- Present. Present, -- Not present. Notpresent) @@ -62,7 +61,7 @@ package NRF51_SVD.FICR is -- unspecified Reserved_8_31 : HAL.UInt24; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for PPFC_Register use record @@ -74,8 +73,7 @@ package NRF51_SVD.FICR is -- Deprecated array of size of RAM block in bytes. This name is kept for -- backward compatinility purposes. Use SIZERAMBLOCKS instead. - type SIZERAMBLOCK_Registers is array (0 .. 3) of HAL.UInt32 - with Volatile; + type SIZERAMBLOCK_Registers is array (0 .. 3) of HAL.UInt32; subtype CONFIGID_HWID_Field is HAL.UInt16; subtype CONFIGID_FWID_Field is HAL.UInt16; @@ -87,7 +85,7 @@ package NRF51_SVD.FICR is -- Read-only. Firmware Identification Number pre-loaded into the flash. FWID : CONFIGID_FWID_Field; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for CONFIGID_Register use record @@ -98,25 +96,21 @@ package NRF51_SVD.FICR is -- Device identifier. -- Device identifier. - type DEVICEID_Registers is array (0 .. 1) of HAL.UInt32 - with Volatile; + type DEVICEID_Registers is array (0 .. 1) of HAL.UInt32; -- Encryption root. -- Encryption root. - type ER_Registers is array (0 .. 3) of HAL.UInt32 - with Volatile; + type ER_Registers is array (0 .. 3) of HAL.UInt32; -- Identity root. -- Identity root. - type IR_Registers is array (0 .. 3) of HAL.UInt32 - with Volatile; + type IR_Registers is array (0 .. 3) of HAL.UInt32; -- Device address type. type DEVICEADDRTYPE_DEVICEADDRTYPE_Field is - ( - -- Public address. + (-- Public address. Public, -- Random address. Random) @@ -132,7 +126,7 @@ package NRF51_SVD.FICR is -- unspecified Reserved_1_31 : HAL.UInt31; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for DEVICEADDRTYPE_Register use record @@ -143,13 +137,11 @@ package NRF51_SVD.FICR is -- Device address. -- Device address. - type DEVICEADDR_Registers is array (0 .. 1) of HAL.UInt32 - with Volatile; + type DEVICEADDR_Registers is array (0 .. 1) of HAL.UInt32; -- Override default values for NRF_1Mbit mode. type OVERRIDEEN_NRF_1MBIT_Field is - ( - -- Override the default values for NRF_1Mbit mode. + (-- Override the default values for NRF_1Mbit mode. Override, -- Do not override the default values for NRF_1Mbit mode. Notoverride) @@ -160,8 +152,7 @@ package NRF51_SVD.FICR is -- Override default values for BLE_1Mbit mode. type OVERRIDEEN_BLE_1MBIT_Field is - ( - -- Override the default values for BLE_1Mbit mode. + (-- Override the default values for BLE_1Mbit mode. Override, -- Do not override the default values for BLE_1Mbit mode. Notoverride) @@ -181,7 +172,7 @@ package NRF51_SVD.FICR is -- unspecified Reserved_4_31 : HAL.UInt28; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for OVERRIDEEN_Register use record @@ -194,22 +185,19 @@ package NRF51_SVD.FICR is -- Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit mode. -- Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit mode. - type NRF_1MBIT_Registers is array (0 .. 4) of HAL.UInt32 - with Volatile; + type NRF_1MBIT_Registers is array (0 .. 4) of HAL.UInt32; -- Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit mode. -- Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit mode. - type BLE_1MBIT_Registers is array (0 .. 4) of HAL.UInt32 - with Volatile; + type BLE_1MBIT_Registers is array (0 .. 4) of HAL.UInt32; ----------------- -- Peripherals -- ----------------- type FICR_Disc is - ( - S, + (S, Default); -- Factory Information Configuration. @@ -280,6 +268,6 @@ package NRF51_SVD.FICR is -- Factory Information Configuration. FICR_Periph : aliased FICR_Peripheral - with Import, Address => System'To_Address (16#10000000#); + with Import, Address => FICR_Base; -end NRF51_SVD.FICR; +end NRF_SVD.FICR; diff --git a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-gpio.ads b/arch/ARM/Nordic/svd/nrf51/nrf_svd-gpio.ads similarity index 88% rename from arch/ARM/Nordic/svd/nrf51/nrf51_svd-gpio.ads rename to arch/ARM/Nordic/svd/nrf51/nrf_svd-gpio.ads index 0a312782c..b66e84cbe 100644 --- a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-gpio.ads +++ b/arch/ARM/Nordic/svd/nrf51/nrf_svd-gpio.ads @@ -36,7 +36,7 @@ pragma Style_Checks (Off); with HAL; with System; -package NRF51_SVD.GPIO is +package NRF_SVD.GPIO is pragma Preelaborate; --------------- @@ -45,8 +45,7 @@ package NRF51_SVD.GPIO is -- Pin 0. type OUT_PIN0_Field is - ( - -- Pin driver is low. + (-- Pin driver is low. Low, -- Pin driver is high. High) @@ -72,7 +71,7 @@ package NRF51_SVD.GPIO is Arr : OUT_PIN_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for OUT_Register use record @@ -82,8 +81,7 @@ package NRF51_SVD.GPIO is -- Pin 0. type OUTSET_PIN0_Field is - ( - -- Pin driver is low. + (-- Pin driver is low. Low, -- Pin driver is high. High) @@ -94,8 +92,7 @@ package NRF51_SVD.GPIO is -- Pin 0. type OUTSET_PIN0_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Outset_Pin0_Field_Reset, -- Set pin driver high. Set) @@ -121,7 +118,7 @@ package NRF51_SVD.GPIO is Arr : OUTSET_PIN_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for OUTSET_Register use record @@ -131,8 +128,7 @@ package NRF51_SVD.GPIO is -- Pin 0. type OUTCLR_PIN0_Field is - ( - -- Pin driver is low. + (-- Pin driver is low. Low, -- Pin driver is high. High) @@ -143,8 +139,7 @@ package NRF51_SVD.GPIO is -- Pin 0. type OUTCLR_PIN0_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Outclr_Pin0_Field_Reset, -- Set pin driver low. Clear) @@ -170,7 +165,7 @@ package NRF51_SVD.GPIO is Arr : OUTCLR_PIN_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for OUTCLR_Register use record @@ -180,8 +175,7 @@ package NRF51_SVD.GPIO is -- Pin 0. type IN_PIN0_Field is - ( - -- Pin input is low. + (-- Pin input is low. Low, -- Pin input is high. High) @@ -207,7 +201,7 @@ package NRF51_SVD.GPIO is Arr : IN_PIN_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for IN_Register use record @@ -217,8 +211,7 @@ package NRF51_SVD.GPIO is -- Pin 0. type DIR_PIN0_Field is - ( - -- Pin set as input. + (-- Pin set as input. Input, -- Pin set as output. Output) @@ -244,7 +237,7 @@ package NRF51_SVD.GPIO is Arr : DIR_PIN_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for DIR_Register use record @@ -254,8 +247,7 @@ package NRF51_SVD.GPIO is -- Set as output pin 0. type DIRSET_PIN0_Field is - ( - -- Pin set as input. + (-- Pin set as input. Input, -- Pin set as output. Output) @@ -266,8 +258,7 @@ package NRF51_SVD.GPIO is -- Set as output pin 0. type DIRSET_PIN0_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Dirset_Pin0_Field_Reset, -- Set pin as output. Set) @@ -293,7 +284,7 @@ package NRF51_SVD.GPIO is Arr : DIRSET_PIN_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for DIRSET_Register use record @@ -303,8 +294,7 @@ package NRF51_SVD.GPIO is -- Set as input pin 0. type DIRCLR_PIN0_Field is - ( - -- Pin set as input. + (-- Pin set as input. Input, -- Pin set as output. Output) @@ -315,8 +305,7 @@ package NRF51_SVD.GPIO is -- Set as input pin 0. type DIRCLR_PIN0_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Dirclr_Pin0_Field_Reset, -- Set pin as input. Clear) @@ -342,7 +331,7 @@ package NRF51_SVD.GPIO is Arr : DIRCLR_PIN_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for DIRCLR_Register use record @@ -352,8 +341,7 @@ package NRF51_SVD.GPIO is -- Pin direction. type PIN_CNF_DIR_Field is - ( - -- Configure pin as an input pin. + (-- Configure pin as an input pin. Input, -- Configure pin as an output pin. Output) @@ -364,8 +352,7 @@ package NRF51_SVD.GPIO is -- Connect or disconnect input path. type PIN_CNF_INPUT_Field is - ( - -- Connect input pin. + (-- Connect input pin. Connect, -- Disconnect input pin. Disconnect) @@ -376,8 +363,7 @@ package NRF51_SVD.GPIO is -- Pull-up or -down configuration. type PIN_CNF_PULL_Field is - ( - -- No pull. + (-- No pull. Disabled, -- Pulldown on pin. Pulldown, @@ -391,8 +377,7 @@ package NRF51_SVD.GPIO is -- Drive configuration. type PIN_CNF_DRIVE_Field is - ( - -- Standard '0', Standard '1'. + (-- Standard '0', Standard '1'. S0S1, -- High '0', Standard '1'. H0S1, @@ -421,8 +406,7 @@ package NRF51_SVD.GPIO is -- Pin sensing mechanism. type PIN_CNF_SENSE_Field is - ( - -- Disabled. + (-- Disabled. Disabled, -- Wakeup on high level. High, @@ -437,23 +421,23 @@ package NRF51_SVD.GPIO is -- Configuration of GPIO pins. type PIN_CNF_Register is record -- Pin direction. - DIR : PIN_CNF_DIR_Field := NRF51_SVD.GPIO.Input; + DIR : PIN_CNF_DIR_Field := NRF_SVD.GPIO.Input; -- Connect or disconnect input path. - INPUT : PIN_CNF_INPUT_Field := NRF51_SVD.GPIO.Disconnect; + INPUT : PIN_CNF_INPUT_Field := NRF_SVD.GPIO.Disconnect; -- Pull-up or -down configuration. - PULL : PIN_CNF_PULL_Field := NRF51_SVD.GPIO.Disabled; + PULL : PIN_CNF_PULL_Field := NRF_SVD.GPIO.Disabled; -- unspecified Reserved_4_7 : HAL.UInt4 := 16#0#; -- Drive configuration. - DRIVE : PIN_CNF_DRIVE_Field := NRF51_SVD.GPIO.S0S1; + DRIVE : PIN_CNF_DRIVE_Field := NRF_SVD.GPIO.S0S1; -- unspecified Reserved_11_15 : HAL.UInt5 := 16#0#; -- Pin sensing mechanism. - SENSE : PIN_CNF_SENSE_Field := NRF51_SVD.GPIO.Disabled; + SENSE : PIN_CNF_SENSE_Field := NRF_SVD.GPIO.Disabled; -- unspecified Reserved_18_31 : HAL.UInt14 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for PIN_CNF_Register use record @@ -468,8 +452,7 @@ package NRF51_SVD.GPIO is end record; -- Configuration of GPIO pins. - type PIN_CNF_Registers is array (0 .. 31) of PIN_CNF_Register - with Volatile; + type PIN_CNF_Registers is array (0 .. 31) of PIN_CNF_Register; ----------------- -- Peripherals -- @@ -509,6 +492,6 @@ package NRF51_SVD.GPIO is -- General purpose input and output. GPIO_Periph : aliased GPIO_Peripheral - with Import, Address => System'To_Address (16#50000000#); + with Import, Address => GPIO_Base; -end NRF51_SVD.GPIO; +end NRF_SVD.GPIO; diff --git a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-gpiote.ads b/arch/ARM/Nordic/svd/nrf51/nrf_svd-gpiote.ads similarity index 88% rename from arch/ARM/Nordic/svd/nrf51/nrf51_svd-gpiote.ads rename to arch/ARM/Nordic/svd/nrf51/nrf_svd-gpiote.ads index 27b9f34c6..30fcb36b4 100644 --- a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-gpiote.ads +++ b/arch/ARM/Nordic/svd/nrf51/nrf_svd-gpiote.ads @@ -36,7 +36,7 @@ pragma Style_Checks (Off); with HAL; with System; -package NRF51_SVD.GPIOTE is +package NRF_SVD.GPIOTE is pragma Preelaborate; --------------- @@ -46,19 +46,16 @@ package NRF51_SVD.GPIOTE is -- Tasks asssociated with GPIOTE channels. -- Tasks asssociated with GPIOTE channels. - type TASKS_OUT_Registers is array (0 .. 3) of HAL.UInt32 - with Volatile; + type TASKS_OUT_Registers is array (0 .. 3) of HAL.UInt32; -- Tasks asssociated with GPIOTE channels. -- Tasks asssociated with GPIOTE channels. - type EVENTS_IN_Registers is array (0 .. 3) of HAL.UInt32 - with Volatile; + type EVENTS_IN_Registers is array (0 .. 3) of HAL.UInt32; -- Enable interrupt on IN[0] event. type INTENSET_IN0_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -69,8 +66,7 @@ package NRF51_SVD.GPIOTE is -- Enable interrupt on IN[0] event. type INTENSET_IN0_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_In0_Field_Reset, -- Enable interrupt on write. Set) @@ -105,8 +101,7 @@ package NRF51_SVD.GPIOTE is -- Enable interrupt on PORT event. type INTENSET_PORT_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -117,8 +112,7 @@ package NRF51_SVD.GPIOTE is -- Enable interrupt on PORT event. type INTENSET_PORT_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Port_Field_Reset, -- Enable interrupt on write. Set) @@ -136,7 +130,7 @@ package NRF51_SVD.GPIOTE is -- Enable interrupt on PORT event. PORT : INTENSET_PORT_Field_1 := Intenset_Port_Field_Reset; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENSET_Register use record @@ -147,8 +141,7 @@ package NRF51_SVD.GPIOTE is -- Disable interrupt on IN[0] event. type INTENCLR_IN0_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -159,8 +152,7 @@ package NRF51_SVD.GPIOTE is -- Disable interrupt on IN[0] event. type INTENCLR_IN0_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_In0_Field_Reset, -- Disable interrupt on write. Clear) @@ -195,8 +187,7 @@ package NRF51_SVD.GPIOTE is -- Disable interrupt on PORT event. type INTENCLR_PORT_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -207,8 +198,7 @@ package NRF51_SVD.GPIOTE is -- Disable interrupt on PORT event. type INTENCLR_PORT_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Port_Field_Reset, -- Disable interrupt on write. Clear) @@ -226,7 +216,7 @@ package NRF51_SVD.GPIOTE is -- Disable interrupt on PORT event. PORT : INTENCLR_PORT_Field_1 := Intenclr_Port_Field_Reset; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENCLR_Register use record @@ -237,8 +227,7 @@ package NRF51_SVD.GPIOTE is -- Mode type CONFIG_MODE_Field is - ( - -- Disabled. + (-- Disabled. Disabled, -- Channel configure in event mode. Event, @@ -255,8 +244,7 @@ package NRF51_SVD.GPIOTE is -- Effects on output when in Task mode, or events on input that generates -- an event. type CONFIG_POLARITY_Field is - ( - -- No task or event. + (-- No task or event. None, -- Low to high. Lotohi, @@ -274,8 +262,7 @@ package NRF51_SVD.GPIOTE is -- Initial value of the output when the GPIOTE channel is configured as a -- Task. type CONFIG_OUTINIT_Field is - ( - -- Initial low output when in task mode. + (-- Initial low output when in task mode. Low, -- Initial high output when in task mode. High) @@ -287,7 +274,7 @@ package NRF51_SVD.GPIOTE is -- Channel configuration registers. type CONFIG_Register is record -- Mode - MODE : CONFIG_MODE_Field := NRF51_SVD.GPIOTE.Disabled; + MODE : CONFIG_MODE_Field := NRF_SVD.GPIOTE.Disabled; -- unspecified Reserved_2_7 : HAL.UInt6 := 16#0#; -- Pin select. @@ -296,16 +283,16 @@ package NRF51_SVD.GPIOTE is Reserved_13_15 : HAL.UInt3 := 16#0#; -- Effects on output when in Task mode, or events on input that -- generates an event. - POLARITY : CONFIG_POLARITY_Field := NRF51_SVD.GPIOTE.None; + POLARITY : CONFIG_POLARITY_Field := NRF_SVD.GPIOTE.None; -- unspecified Reserved_18_19 : HAL.UInt2 := 16#0#; -- Initial value of the output when the GPIOTE channel is configured as -- a Task. - OUTINIT : CONFIG_OUTINIT_Field := NRF51_SVD.GPIOTE.Low; + OUTINIT : CONFIG_OUTINIT_Field := NRF_SVD.GPIOTE.Low; -- unspecified Reserved_21_31 : HAL.UInt11 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for CONFIG_Register use record @@ -320,13 +307,11 @@ package NRF51_SVD.GPIOTE is end record; -- Channel configuration registers. - type CONFIG_Registers is array (0 .. 3) of CONFIG_Register - with Volatile; + type CONFIG_Registers is array (0 .. 3) of CONFIG_Register; -- Peripheral power control. type POWER_POWER_Field is - ( - -- Module power disabled. + (-- Module power disabled. Disabled, -- Module power enabled. Enabled) @@ -338,11 +323,11 @@ package NRF51_SVD.GPIOTE is -- Peripheral power control. type POWER_Register is record -- Peripheral power control. - POWER : POWER_POWER_Field := NRF51_SVD.GPIOTE.Disabled; + POWER : POWER_POWER_Field := NRF_SVD.GPIOTE.Disabled; -- unspecified Reserved_1_31 : HAL.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for POWER_Register use record @@ -385,6 +370,6 @@ package NRF51_SVD.GPIOTE is -- GPIO tasks and events. GPIOTE_Periph : aliased GPIOTE_Peripheral - with Import, Address => System'To_Address (16#40006000#); + with Import, Address => GPIOTE_Base; -end NRF51_SVD.GPIOTE; +end NRF_SVD.GPIOTE; diff --git a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-lpcomp.ads b/arch/ARM/Nordic/svd/nrf51/nrf_svd-lpcomp.ads similarity index 87% rename from arch/ARM/Nordic/svd/nrf51/nrf51_svd-lpcomp.ads rename to arch/ARM/Nordic/svd/nrf51/nrf_svd-lpcomp.ads index 27521207d..2ca7efa39 100644 --- a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-lpcomp.ads +++ b/arch/ARM/Nordic/svd/nrf51/nrf_svd-lpcomp.ads @@ -36,7 +36,7 @@ pragma Style_Checks (Off); with HAL; with System; -package NRF51_SVD.LPCOMP is +package NRF_SVD.LPCOMP is pragma Preelaborate; --------------- @@ -45,8 +45,7 @@ package NRF51_SVD.LPCOMP is -- Shortcut between READY event and SAMPLE task. type SHORTS_READY_SAMPLE_Field is - ( - -- Shortcut disabled. + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) @@ -57,8 +56,7 @@ package NRF51_SVD.LPCOMP is -- Shortcut between RADY event and STOP task. type SHORTS_READY_STOP_Field is - ( - -- Shortcut disabled. + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) @@ -69,8 +67,7 @@ package NRF51_SVD.LPCOMP is -- Shortcut between DOWN event and STOP task. type SHORTS_DOWN_STOP_Field is - ( - -- Shortcut disabled. + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) @@ -81,8 +78,7 @@ package NRF51_SVD.LPCOMP is -- Shortcut between UP event and STOP task. type SHORTS_UP_STOP_Field is - ( - -- Shortcut disabled. + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) @@ -93,8 +89,7 @@ package NRF51_SVD.LPCOMP is -- Shortcut between CROSS event and STOP task. type SHORTS_CROSS_STOP_Field is - ( - -- Shortcut disabled. + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) @@ -106,19 +101,19 @@ package NRF51_SVD.LPCOMP is -- Shortcuts for the LPCOMP. type SHORTS_Register is record -- Shortcut between READY event and SAMPLE task. - READY_SAMPLE : SHORTS_READY_SAMPLE_Field := NRF51_SVD.LPCOMP.Disabled; + READY_SAMPLE : SHORTS_READY_SAMPLE_Field := NRF_SVD.LPCOMP.Disabled; -- Shortcut between RADY event and STOP task. - READY_STOP : SHORTS_READY_STOP_Field := NRF51_SVD.LPCOMP.Disabled; + READY_STOP : SHORTS_READY_STOP_Field := NRF_SVD.LPCOMP.Disabled; -- Shortcut between DOWN event and STOP task. - DOWN_STOP : SHORTS_DOWN_STOP_Field := NRF51_SVD.LPCOMP.Disabled; + DOWN_STOP : SHORTS_DOWN_STOP_Field := NRF_SVD.LPCOMP.Disabled; -- Shortcut between UP event and STOP task. - UP_STOP : SHORTS_UP_STOP_Field := NRF51_SVD.LPCOMP.Disabled; + UP_STOP : SHORTS_UP_STOP_Field := NRF_SVD.LPCOMP.Disabled; -- Shortcut between CROSS event and STOP task. - CROSS_STOP : SHORTS_CROSS_STOP_Field := NRF51_SVD.LPCOMP.Disabled; + CROSS_STOP : SHORTS_CROSS_STOP_Field := NRF_SVD.LPCOMP.Disabled; -- unspecified Reserved_5_31 : HAL.UInt27 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for SHORTS_Register use record @@ -132,8 +127,7 @@ package NRF51_SVD.LPCOMP is -- Enable interrupt on READY event. type INTENSET_READY_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -144,8 +138,7 @@ package NRF51_SVD.LPCOMP is -- Enable interrupt on READY event. type INTENSET_READY_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Ready_Field_Reset, -- Enable interrupt on write. Set) @@ -156,8 +149,7 @@ package NRF51_SVD.LPCOMP is -- Enable interrupt on DOWN event. type INTENSET_DOWN_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -168,8 +160,7 @@ package NRF51_SVD.LPCOMP is -- Enable interrupt on DOWN event. type INTENSET_DOWN_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Down_Field_Reset, -- Enable interrupt on write. Set) @@ -180,8 +171,7 @@ package NRF51_SVD.LPCOMP is -- Enable interrupt on UP event. type INTENSET_UP_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -192,8 +182,7 @@ package NRF51_SVD.LPCOMP is -- Enable interrupt on UP event. type INTENSET_UP_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Up_Field_Reset, -- Enable interrupt on write. Set) @@ -204,8 +193,7 @@ package NRF51_SVD.LPCOMP is -- Enable interrupt on CROSS event. type INTENSET_CROSS_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -216,8 +204,7 @@ package NRF51_SVD.LPCOMP is -- Enable interrupt on CROSS event. type INTENSET_CROSS_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Cross_Field_Reset, -- Enable interrupt on write. Set) @@ -239,7 +226,7 @@ package NRF51_SVD.LPCOMP is -- unspecified Reserved_4_31 : HAL.UInt28 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENSET_Register use record @@ -252,8 +239,7 @@ package NRF51_SVD.LPCOMP is -- Disable interrupt on READY event. type INTENCLR_READY_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -264,8 +250,7 @@ package NRF51_SVD.LPCOMP is -- Disable interrupt on READY event. type INTENCLR_READY_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Ready_Field_Reset, -- Disable interrupt on write. Clear) @@ -276,8 +261,7 @@ package NRF51_SVD.LPCOMP is -- Disable interrupt on DOWN event. type INTENCLR_DOWN_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -288,8 +272,7 @@ package NRF51_SVD.LPCOMP is -- Disable interrupt on DOWN event. type INTENCLR_DOWN_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Down_Field_Reset, -- Disable interrupt on write. Clear) @@ -300,8 +283,7 @@ package NRF51_SVD.LPCOMP is -- Disable interrupt on UP event. type INTENCLR_UP_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -312,8 +294,7 @@ package NRF51_SVD.LPCOMP is -- Disable interrupt on UP event. type INTENCLR_UP_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Up_Field_Reset, -- Disable interrupt on write. Clear) @@ -324,8 +305,7 @@ package NRF51_SVD.LPCOMP is -- Disable interrupt on CROSS event. type INTENCLR_CROSS_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -336,8 +316,7 @@ package NRF51_SVD.LPCOMP is -- Disable interrupt on CROSS event. type INTENCLR_CROSS_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Cross_Field_Reset, -- Disable interrupt on write. Clear) @@ -359,7 +338,7 @@ package NRF51_SVD.LPCOMP is -- unspecified Reserved_4_31 : HAL.UInt28 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENCLR_Register use record @@ -372,8 +351,7 @@ package NRF51_SVD.LPCOMP is -- Result of last compare. Decision point SAMPLE task. type RESULT_RESULT_Field is - ( - -- Input voltage is bellow the reference threshold. + (-- Input voltage is bellow the reference threshold. Bellow, -- Input voltage is above the reference threshold. Above) @@ -389,7 +367,7 @@ package NRF51_SVD.LPCOMP is -- unspecified Reserved_1_31 : HAL.UInt31; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for RESULT_Register use record @@ -399,8 +377,7 @@ package NRF51_SVD.LPCOMP is -- Enable or disable LPCOMP. type ENABLE_ENABLE_Field is - ( - -- Disabled LPCOMP. + (-- Disabled LPCOMP. Disabled, -- Enable LPCOMP. Enabled) @@ -412,11 +389,11 @@ package NRF51_SVD.LPCOMP is -- Enable the LPCOMP. type ENABLE_Register is record -- Enable or disable LPCOMP. - ENABLE : ENABLE_ENABLE_Field := NRF51_SVD.LPCOMP.Disabled; + ENABLE : ENABLE_ENABLE_Field := NRF_SVD.LPCOMP.Disabled; -- unspecified Reserved_2_31 : HAL.UInt30 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for ENABLE_Register use record @@ -426,8 +403,7 @@ package NRF51_SVD.LPCOMP is -- Analog input pin select. type PSEL_PSEL_Field is - ( - -- Use analog input 0 as analog input. + (-- Use analog input 0 as analog input. Analoginput0, -- Use analog input 1 as analog input. Analoginput1, @@ -457,11 +433,11 @@ package NRF51_SVD.LPCOMP is -- Input pin select. type PSEL_Register is record -- Analog input pin select. - PSEL : PSEL_PSEL_Field := NRF51_SVD.LPCOMP.Analoginput0; + PSEL : PSEL_PSEL_Field := NRF_SVD.LPCOMP.Analoginput0; -- unspecified Reserved_3_31 : HAL.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for PSEL_Register use record @@ -471,8 +447,7 @@ package NRF51_SVD.LPCOMP is -- Reference select. type REFSEL_REFSEL_Field is - ( - -- Use supply with a 1/8 prescaler as reference. + (-- Use supply with a 1/8 prescaler as reference. Supplyoneeighthprescaling, -- Use supply with a 2/8 prescaler as reference. Supplytwoeighthsprescaling, @@ -503,11 +478,11 @@ package NRF51_SVD.LPCOMP is type REFSEL_Register is record -- Reference select. REFSEL : REFSEL_REFSEL_Field := - NRF51_SVD.LPCOMP.Supplyoneeighthprescaling; + NRF_SVD.LPCOMP.Supplyoneeighthprescaling; -- unspecified Reserved_3_31 : HAL.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for REFSEL_Register use record @@ -517,8 +492,7 @@ package NRF51_SVD.LPCOMP is -- External analog reference pin selection. type EXTREFSEL_EXTREFSEL_Field is - ( - -- Use analog reference 0 as reference. + (-- Use analog reference 0 as reference. Analogreference0, -- Use analog reference 1 as reference. Analogreference1) @@ -531,11 +505,11 @@ package NRF51_SVD.LPCOMP is type EXTREFSEL_Register is record -- External analog reference pin selection. EXTREFSEL : EXTREFSEL_EXTREFSEL_Field := - NRF51_SVD.LPCOMP.Analogreference0; + NRF_SVD.LPCOMP.Analogreference0; -- unspecified Reserved_1_31 : HAL.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for EXTREFSEL_Register use record @@ -545,8 +519,7 @@ package NRF51_SVD.LPCOMP is -- Analog detect configuration. type ANADETECT_ANADETECT_Field is - ( - -- Generate ANADETEC on crossing, both upwards and downwards crossing. + (-- Generate ANADETEC on crossing, both upwards and downwards crossing. Cross, -- Generate ANADETEC on upwards crossing only. Up, @@ -561,11 +534,11 @@ package NRF51_SVD.LPCOMP is -- Analog detect configuration. type ANADETECT_Register is record -- Analog detect configuration. - ANADETECT : ANADETECT_ANADETECT_Field := NRF51_SVD.LPCOMP.Cross; + ANADETECT : ANADETECT_ANADETECT_Field := NRF_SVD.LPCOMP.Cross; -- unspecified Reserved_2_31 : HAL.UInt30 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for ANADETECT_Register use record @@ -575,8 +548,7 @@ package NRF51_SVD.LPCOMP is -- Peripheral power control. type POWER_POWER_Field is - ( - -- Module power disabled. + (-- Module power disabled. Disabled, -- Module power enabled. Enabled) @@ -588,11 +560,11 @@ package NRF51_SVD.LPCOMP is -- Peripheral power control. type POWER_Register is record -- Peripheral power control. - POWER : POWER_POWER_Field := NRF51_SVD.LPCOMP.Disabled; + POWER : POWER_POWER_Field := NRF_SVD.LPCOMP.Disabled; -- unspecified Reserved_1_31 : HAL.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for POWER_Register use record @@ -665,6 +637,6 @@ package NRF51_SVD.LPCOMP is -- Low power comparator. LPCOMP_Periph : aliased LPCOMP_Peripheral - with Import, Address => System'To_Address (16#40013000#); + with Import, Address => LPCOMP_Base; -end NRF51_SVD.LPCOMP; +end NRF_SVD.LPCOMP; diff --git a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-mpu.ads b/arch/ARM/Nordic/svd/nrf51/nrf_svd-mpu.ads similarity index 82% rename from arch/ARM/Nordic/svd/nrf51/nrf51_svd-mpu.ads rename to arch/ARM/Nordic/svd/nrf51/nrf_svd-mpu.ads index 69344349c..798a7ccc4 100644 --- a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-mpu.ads +++ b/arch/ARM/Nordic/svd/nrf51/nrf_svd-mpu.ads @@ -36,7 +36,7 @@ pragma Style_Checks (Off); with HAL; with System; -package NRF51_SVD.MPU is +package NRF_SVD.MPU is pragma Preelaborate; --------------- @@ -45,8 +45,7 @@ package NRF51_SVD.MPU is -- POWER_CLOCK region configuration. type PERR0_POWER_CLOCK_Field is - ( - -- Peripheral configured in region 1. + (-- Peripheral configured in region 1. Inregion1, -- Peripheral configured in region 0. Inregion0) @@ -57,8 +56,7 @@ package NRF51_SVD.MPU is -- RADIO region configuration. type PERR0_RADIO_Field is - ( - -- Peripheral configured in region 1. + (-- Peripheral configured in region 1. Inregion1, -- Peripheral configured in region 0. Inregion0) @@ -69,8 +67,7 @@ package NRF51_SVD.MPU is -- UART0 region configuration. type PERR0_UART0_Field is - ( - -- Peripheral configured in region 1. + (-- Peripheral configured in region 1. Inregion1, -- Peripheral configured in region 0. Inregion0) @@ -81,8 +78,7 @@ package NRF51_SVD.MPU is -- SPI0 and TWI0 region configuration. type PERR0_SPI0_TWI0_Field is - ( - -- Peripheral configured in region 1. + (-- Peripheral configured in region 1. Inregion1, -- Peripheral configured in region 0. Inregion0) @@ -93,8 +89,7 @@ package NRF51_SVD.MPU is -- SPI1 and TWI1 region configuration. type PERR0_SPI1_TWI1_Field is - ( - -- Peripheral configured in region 1. + (-- Peripheral configured in region 1. Inregion1, -- Peripheral configured in region 0. Inregion0) @@ -105,8 +100,7 @@ package NRF51_SVD.MPU is -- GPIOTE region configuration. type PERR0_GPIOTE_Field is - ( - -- Peripheral configured in region 1. + (-- Peripheral configured in region 1. Inregion1, -- Peripheral configured in region 0. Inregion0) @@ -117,8 +111,7 @@ package NRF51_SVD.MPU is -- ADC region configuration. type PERR0_ADC_Field is - ( - -- Peripheral configured in region 1. + (-- Peripheral configured in region 1. Inregion1, -- Peripheral configured in region 0. Inregion0) @@ -129,8 +122,7 @@ package NRF51_SVD.MPU is -- TIMER0 region configuration. type PERR0_TIMER0_Field is - ( - -- Peripheral configured in region 1. + (-- Peripheral configured in region 1. Inregion1, -- Peripheral configured in region 0. Inregion0) @@ -165,8 +157,7 @@ package NRF51_SVD.MPU is -- RTC0 region configuration. type PERR0_RTC0_Field is - ( - -- Peripheral configured in region 1. + (-- Peripheral configured in region 1. Inregion1, -- Peripheral configured in region 0. Inregion0) @@ -177,8 +168,7 @@ package NRF51_SVD.MPU is -- TEMP region configuration. type PERR0_TEMP_Field is - ( - -- Peripheral configured in region 1. + (-- Peripheral configured in region 1. Inregion1, -- Peripheral configured in region 0. Inregion0) @@ -189,8 +179,7 @@ package NRF51_SVD.MPU is -- RNG region configuration. type PERR0_RNG_Field is - ( - -- Peripheral configured in region 1. + (-- Peripheral configured in region 1. Inregion1, -- Peripheral configured in region 0. Inregion0) @@ -201,8 +190,7 @@ package NRF51_SVD.MPU is -- ECB region configuration. type PERR0_ECB_Field is - ( - -- Peripheral configured in region 1. + (-- Peripheral configured in region 1. Inregion1, -- Peripheral configured in region 0. Inregion0) @@ -213,8 +201,7 @@ package NRF51_SVD.MPU is -- CCM and AAR region configuration. type PERR0_CCM_AAR_Field is - ( - -- Peripheral configured in region 1. + (-- Peripheral configured in region 1. Inregion1, -- Peripheral configured in region 0. Inregion0) @@ -225,8 +212,7 @@ package NRF51_SVD.MPU is -- WDT region configuration. type PERR0_WDT_Field is - ( - -- Peripheral configured in region 1. + (-- Peripheral configured in region 1. Inregion1, -- Peripheral configured in region 0. Inregion0) @@ -237,8 +223,7 @@ package NRF51_SVD.MPU is -- RTC1 region configuration. type PERR0_RTC1_Field is - ( - -- Peripheral configured in region 1. + (-- Peripheral configured in region 1. Inregion1, -- Peripheral configured in region 0. Inregion0) @@ -249,8 +234,7 @@ package NRF51_SVD.MPU is -- QDEC region configuration. type PERR0_QDEC_Field is - ( - -- Peripheral configured in region 1. + (-- Peripheral configured in region 1. Inregion1, -- Peripheral configured in region 0. Inregion0) @@ -261,8 +245,7 @@ package NRF51_SVD.MPU is -- LPCOMP region configuration. type PERR0_LPCOMP_Field is - ( - -- Peripheral configured in region 1. + (-- Peripheral configured in region 1. Inregion1, -- Peripheral configured in region 0. Inregion0) @@ -273,8 +256,7 @@ package NRF51_SVD.MPU is -- NVMC region configuration. type PERR0_NVMC_Field is - ( - -- Peripheral configured in region 1. + (-- Peripheral configured in region 1. Inregion1, -- Peripheral configured in region 0. Inregion0) @@ -285,8 +267,7 @@ package NRF51_SVD.MPU is -- PPI region configuration. type PERR0_PPI_Field is - ( - -- Peripheral configured in region 1. + (-- Peripheral configured in region 1. Inregion1, -- Peripheral configured in region 0. Inregion0) @@ -298,49 +279,49 @@ package NRF51_SVD.MPU is -- Configuration of peripherals in mpu regions. type PERR0_Register is record -- POWER_CLOCK region configuration. - POWER_CLOCK : PERR0_POWER_CLOCK_Field := NRF51_SVD.MPU.Inregion1; + POWER_CLOCK : PERR0_POWER_CLOCK_Field := NRF_SVD.MPU.Inregion1; -- RADIO region configuration. - RADIO : PERR0_RADIO_Field := NRF51_SVD.MPU.Inregion1; + RADIO : PERR0_RADIO_Field := NRF_SVD.MPU.Inregion1; -- UART0 region configuration. - UART0 : PERR0_UART0_Field := NRF51_SVD.MPU.Inregion1; + UART0 : PERR0_UART0_Field := NRF_SVD.MPU.Inregion1; -- SPI0 and TWI0 region configuration. - SPI0_TWI0 : PERR0_SPI0_TWI0_Field := NRF51_SVD.MPU.Inregion1; + SPI0_TWI0 : PERR0_SPI0_TWI0_Field := NRF_SVD.MPU.Inregion1; -- SPI1 and TWI1 region configuration. - SPI1_TWI1 : PERR0_SPI1_TWI1_Field := NRF51_SVD.MPU.Inregion1; + SPI1_TWI1 : PERR0_SPI1_TWI1_Field := NRF_SVD.MPU.Inregion1; -- unspecified Reserved_5_5 : HAL.Bit := 16#0#; -- GPIOTE region configuration. - GPIOTE : PERR0_GPIOTE_Field := NRF51_SVD.MPU.Inregion1; + GPIOTE : PERR0_GPIOTE_Field := NRF_SVD.MPU.Inregion1; -- ADC region configuration. - ADC : PERR0_ADC_Field := NRF51_SVD.MPU.Inregion1; + ADC : PERR0_ADC_Field := NRF_SVD.MPU.Inregion1; -- TIMER0 region configuration. TIMER : PERR0_TIMER_Field := (As_Array => False, Val => 16#0#); -- RTC0 region configuration. - RTC0 : PERR0_RTC0_Field := NRF51_SVD.MPU.Inregion1; + RTC0 : PERR0_RTC0_Field := NRF_SVD.MPU.Inregion1; -- TEMP region configuration. - TEMP : PERR0_TEMP_Field := NRF51_SVD.MPU.Inregion1; + TEMP : PERR0_TEMP_Field := NRF_SVD.MPU.Inregion1; -- RNG region configuration. - RNG : PERR0_RNG_Field := NRF51_SVD.MPU.Inregion1; + RNG : PERR0_RNG_Field := NRF_SVD.MPU.Inregion1; -- ECB region configuration. - ECB : PERR0_ECB_Field := NRF51_SVD.MPU.Inregion1; + ECB : PERR0_ECB_Field := NRF_SVD.MPU.Inregion1; -- CCM and AAR region configuration. - CCM_AAR : PERR0_CCM_AAR_Field := NRF51_SVD.MPU.Inregion1; + CCM_AAR : PERR0_CCM_AAR_Field := NRF_SVD.MPU.Inregion1; -- WDT region configuration. - WDT : PERR0_WDT_Field := NRF51_SVD.MPU.Inregion1; + WDT : PERR0_WDT_Field := NRF_SVD.MPU.Inregion1; -- RTC1 region configuration. - RTC1 : PERR0_RTC1_Field := NRF51_SVD.MPU.Inregion1; + RTC1 : PERR0_RTC1_Field := NRF_SVD.MPU.Inregion1; -- QDEC region configuration. - QDEC : PERR0_QDEC_Field := NRF51_SVD.MPU.Inregion1; + QDEC : PERR0_QDEC_Field := NRF_SVD.MPU.Inregion1; -- LPCOMP region configuration. - LPCOMP : PERR0_LPCOMP_Field := NRF51_SVD.MPU.Inregion1; + LPCOMP : PERR0_LPCOMP_Field := NRF_SVD.MPU.Inregion1; -- unspecified Reserved_20_29 : HAL.UInt10 := 16#0#; -- NVMC region configuration. - NVMC : PERR0_NVMC_Field := NRF51_SVD.MPU.Inregion1; + NVMC : PERR0_NVMC_Field := NRF_SVD.MPU.Inregion1; -- PPI region configuration. - PPI : PERR0_PPI_Field := NRF51_SVD.MPU.Inregion1; + PPI : PERR0_PPI_Field := NRF_SVD.MPU.Inregion1; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for PERR0_Register use record @@ -369,8 +350,7 @@ package NRF51_SVD.MPU is -- Protection enable for region 0. type PROTENSET0_PROTREG0_Field is - ( - -- Protection disabled. + (-- Protection disabled. Disabled, -- Protection enabled. Enabled) @@ -381,8 +361,7 @@ package NRF51_SVD.MPU is -- Protection enable for region 0. type PROTENSET0_PROTREG0_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Protenset0_Protreg0_Field_Reset, -- Enable protection on write. Set) @@ -409,7 +388,7 @@ package NRF51_SVD.MPU is Arr : PROTENSET0_PROTREG_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for PROTENSET0_Register use record @@ -419,8 +398,7 @@ package NRF51_SVD.MPU is -- Protection enable for region 32. type PROTENSET1_PROTREG32_Field is - ( - -- Protection disabled. + (-- Protection disabled. Disabled, -- Protection enabled. Enabled) @@ -431,8 +409,7 @@ package NRF51_SVD.MPU is -- Protection enable for region 32. type PROTENSET1_PROTREG32_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Protenset1_Protreg32_Field_Reset, -- Enable protection on write. Set) @@ -459,7 +436,7 @@ package NRF51_SVD.MPU is Arr : PROTENSET1_PROTREG_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for PROTENSET1_Register use record @@ -469,8 +446,7 @@ package NRF51_SVD.MPU is -- Disable protection mechanism in debug mode. type DISABLEINDEBUG_DISABLEINDEBUG_Field is - ( - -- Protection enabled. + (-- Protection enabled. Enabled, -- Protection disabled. Disabled) @@ -483,11 +459,11 @@ package NRF51_SVD.MPU is type DISABLEINDEBUG_Register is record -- Disable protection mechanism in debug mode. DISABLEINDEBUG : DISABLEINDEBUG_DISABLEINDEBUG_Field := - NRF51_SVD.MPU.Disabled; + NRF_SVD.MPU.Disabled; -- unspecified Reserved_1_31 : HAL.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for DISABLEINDEBUG_Register use record @@ -497,22 +473,20 @@ package NRF51_SVD.MPU is -- Erase and write protection block size. type PROTBLOCKSIZE_PROTBLOCKSIZE_Field is - ( - -- Erase and write protection block size is 4k. - PROTBLOCKSIZE_PROTBLOCKSIZE_Field_4K) + (-- Erase and write protection block size is 4k. + Val_4K) with Size => 2; for PROTBLOCKSIZE_PROTBLOCKSIZE_Field use - (PROTBLOCKSIZE_PROTBLOCKSIZE_Field_4K => 0); + (Val_4K => 0); -- Erase and write protection block size. type PROTBLOCKSIZE_Register is record -- Erase and write protection block size. - PROTBLOCKSIZE : PROTBLOCKSIZE_PROTBLOCKSIZE_Field := - NRF51_SVD.MPU.PROTBLOCKSIZE_PROTBLOCKSIZE_Field_4K; + PROTBLOCKSIZE : PROTBLOCKSIZE_PROTBLOCKSIZE_Field := NRF_SVD.MPU.Val_4K; -- unspecified Reserved_2_31 : HAL.UInt30 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for PROTBLOCKSIZE_Register use record @@ -552,6 +526,6 @@ package NRF51_SVD.MPU is -- Memory Protection Unit. MPU_Periph : aliased MPU_Peripheral - with Import, Address => System'To_Address (16#40000000#); + with Import, Address => MPU_Base; -end NRF51_SVD.MPU; +end NRF_SVD.MPU; diff --git a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-nvmc.ads b/arch/ARM/Nordic/svd/nrf51/nrf_svd-nvmc.ads similarity index 89% rename from arch/ARM/Nordic/svd/nrf51/nrf51_svd-nvmc.ads rename to arch/ARM/Nordic/svd/nrf51/nrf_svd-nvmc.ads index 97f2c833f..f48469d93 100644 --- a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-nvmc.ads +++ b/arch/ARM/Nordic/svd/nrf51/nrf_svd-nvmc.ads @@ -36,7 +36,7 @@ pragma Style_Checks (Off); with HAL; with System; -package NRF51_SVD.NVMC is +package NRF_SVD.NVMC is pragma Preelaborate; --------------- @@ -45,8 +45,7 @@ package NRF51_SVD.NVMC is -- NVMC ready. type READY_READY_Field is - ( - -- NVMC is busy (on-going write or erase operation). + (-- NVMC is busy (on-going write or erase operation). Busy, -- NVMC is ready. Ready) @@ -62,7 +61,7 @@ package NRF51_SVD.NVMC is -- unspecified Reserved_1_31 : HAL.UInt31; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for READY_Register use record @@ -72,8 +71,7 @@ package NRF51_SVD.NVMC is -- Program write enable. type CONFIG_WEN_Field is - ( - -- Read only access. + (-- Read only access. Ren, -- Write enabled. Wen, @@ -88,11 +86,11 @@ package NRF51_SVD.NVMC is -- Configuration register. type CONFIG_Register is record -- Program write enable. - WEN : CONFIG_WEN_Field := NRF51_SVD.NVMC.Ren; + WEN : CONFIG_WEN_Field := NRF_SVD.NVMC.Ren; -- unspecified Reserved_2_31 : HAL.UInt30 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for CONFIG_Register use record @@ -102,8 +100,7 @@ package NRF51_SVD.NVMC is -- Starts the erasing of all user NVM (code region 0/1 and UICR registers). type ERASEALL_ERASEALL_Field is - ( - -- No operation. + (-- No operation. Nooperation, -- Start chip erase. Erase) @@ -116,11 +113,11 @@ package NRF51_SVD.NVMC is type ERASEALL_Register is record -- Starts the erasing of all user NVM (code region 0/1 and UICR -- registers). - ERASEALL : ERASEALL_ERASEALL_Field := NRF51_SVD.NVMC.Nooperation; + ERASEALL : ERASEALL_ERASEALL_Field := NRF_SVD.NVMC.Nooperation; -- unspecified Reserved_1_31 : HAL.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for ERASEALL_Register use record @@ -130,8 +127,7 @@ package NRF51_SVD.NVMC is -- It can only be used when all contents of code region 1 are erased. type ERASEUICR_ERASEUICR_Field is - ( - -- No operation. + (-- No operation. Nooperation, -- Start UICR erase. Erase) @@ -143,11 +139,11 @@ package NRF51_SVD.NVMC is -- Register for start erasing User Information Congfiguration Registers. type ERASEUICR_Register is record -- It can only be used when all contents of code region 1 are erased. - ERASEUICR : ERASEUICR_ERASEUICR_Field := NRF51_SVD.NVMC.Nooperation; + ERASEUICR : ERASEUICR_ERASEUICR_Field := NRF_SVD.NVMC.Nooperation; -- unspecified Reserved_1_31 : HAL.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for ERASEUICR_Register use record @@ -160,8 +156,7 @@ package NRF51_SVD.NVMC is ----------------- type NVMC_Disc is - ( - Age, + (Age, Cr1); -- Non Volatile Memory Controller. @@ -201,6 +196,6 @@ package NRF51_SVD.NVMC is -- Non Volatile Memory Controller. NVMC_Periph : aliased NVMC_Peripheral - with Import, Address => System'To_Address (16#4001E000#); + with Import, Address => NVMC_Base; -end NRF51_SVD.NVMC; +end NRF_SVD.NVMC; diff --git a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-power.ads b/arch/ARM/Nordic/svd/nrf51/nrf_svd-power.ads similarity index 84% rename from arch/ARM/Nordic/svd/nrf51/nrf51_svd-power.ads rename to arch/ARM/Nordic/svd/nrf51/nrf_svd-power.ads index 25e1f73c8..2c6de2ef1 100644 --- a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-power.ads +++ b/arch/ARM/Nordic/svd/nrf51/nrf_svd-power.ads @@ -36,7 +36,7 @@ pragma Style_Checks (Off); with HAL; with System; -package NRF51_SVD.POWER is +package NRF_SVD.POWER is pragma Preelaborate; --------------- @@ -45,8 +45,7 @@ package NRF51_SVD.POWER is -- Enable interrupt on POFWARN event. type INTENSET_POFWARN_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -57,8 +56,7 @@ package NRF51_SVD.POWER is -- Enable interrupt on POFWARN event. type INTENSET_POFWARN_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Pofwarn_Field_Reset, -- Enable interrupt on write. Set) @@ -77,7 +75,7 @@ package NRF51_SVD.POWER is -- unspecified Reserved_3_31 : HAL.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENSET_Register use record @@ -88,8 +86,7 @@ package NRF51_SVD.POWER is -- Disable interrupt on POFWARN event. type INTENCLR_POFWARN_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -100,8 +97,7 @@ package NRF51_SVD.POWER is -- Disable interrupt on POFWARN event. type INTENCLR_POFWARN_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Pofwarn_Field_Reset, -- Disable interrupt on write. Clear) @@ -120,7 +116,7 @@ package NRF51_SVD.POWER is -- unspecified Reserved_3_31 : HAL.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENCLR_Register use record @@ -131,8 +127,7 @@ package NRF51_SVD.POWER is -- Reset from pin-reset detected. type RESETREAS_RESETPIN_Field is - ( - -- Reset not detected. + (-- Reset not detected. Notdetected, -- Reset detected. Detected) @@ -143,8 +138,7 @@ package NRF51_SVD.POWER is -- Reset from watchdog detected. type RESETREAS_DOG_Field is - ( - -- Reset not detected. + (-- Reset not detected. Notdetected, -- Reset detected. Detected) @@ -155,8 +149,7 @@ package NRF51_SVD.POWER is -- Reset from AIRCR.SYSRESETREQ detected. type RESETREAS_SREQ_Field is - ( - -- Reset not detected. + (-- Reset not detected. Notdetected, -- Reset detected. Detected) @@ -167,8 +160,7 @@ package NRF51_SVD.POWER is -- Reset from CPU lock-up detected. type RESETREAS_LOCKUP_Field is - ( - -- Reset not detected. + (-- Reset not detected. Notdetected, -- Reset detected. Detected) @@ -180,8 +172,7 @@ package NRF51_SVD.POWER is -- Reset from wake-up from OFF mode detected by the use of DETECT signal -- from GPIO. type RESETREAS_OFF_Field is - ( - -- Reset not detected. + (-- Reset not detected. Notdetected, -- Reset detected. Detected) @@ -193,8 +184,7 @@ package NRF51_SVD.POWER is -- Reset from wake-up from OFF mode detected by the use of ANADETECT signal -- from LPCOMP. type RESETREAS_LPCOMP_Field is - ( - -- Reset not detected. + (-- Reset not detected. Notdetected, -- Reset detected. Detected) @@ -206,8 +196,7 @@ package NRF51_SVD.POWER is -- Reset from wake-up from OFF mode detected by entering into debug -- interface mode. type RESETREAS_DIF_Field is - ( - -- Reset not detected. + (-- Reset not detected. Notdetected, -- Reset detected. Detected) @@ -219,29 +208,28 @@ package NRF51_SVD.POWER is -- Reset reason. type RESETREAS_Register is record -- Reset from pin-reset detected. - RESETPIN : RESETREAS_RESETPIN_Field := - NRF51_SVD.POWER.Notdetected; + RESETPIN : RESETREAS_RESETPIN_Field := NRF_SVD.POWER.Notdetected; -- Reset from watchdog detected. - DOG : RESETREAS_DOG_Field := NRF51_SVD.POWER.Notdetected; + DOG : RESETREAS_DOG_Field := NRF_SVD.POWER.Notdetected; -- Reset from AIRCR.SYSRESETREQ detected. - SREQ : RESETREAS_SREQ_Field := NRF51_SVD.POWER.Notdetected; + SREQ : RESETREAS_SREQ_Field := NRF_SVD.POWER.Notdetected; -- Reset from CPU lock-up detected. - LOCKUP : RESETREAS_LOCKUP_Field := NRF51_SVD.POWER.Notdetected; + LOCKUP : RESETREAS_LOCKUP_Field := NRF_SVD.POWER.Notdetected; -- unspecified Reserved_4_15 : HAL.UInt12 := 16#0#; -- Reset from wake-up from OFF mode detected by the use of DETECT signal -- from GPIO. - OFF : RESETREAS_OFF_Field := NRF51_SVD.POWER.Notdetected; + OFF : RESETREAS_OFF_Field := NRF_SVD.POWER.Notdetected; -- Reset from wake-up from OFF mode detected by the use of ANADETECT -- signal from LPCOMP. - LPCOMP : RESETREAS_LPCOMP_Field := NRF51_SVD.POWER.Notdetected; + LPCOMP : RESETREAS_LPCOMP_Field := NRF_SVD.POWER.Notdetected; -- Reset from wake-up from OFF mode detected by entering into debug -- interface mode. - DIF : RESETREAS_DIF_Field := NRF51_SVD.POWER.Notdetected; + DIF : RESETREAS_DIF_Field := NRF_SVD.POWER.Notdetected; -- unspecified Reserved_19_31 : HAL.UInt13 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for RESETREAS_Register use record @@ -258,8 +246,7 @@ package NRF51_SVD.POWER is -- RAM block 0 status. type RAMSTATUS_RAMBLOCK0_Field is - ( - -- RAM block 0 is off or powering up. + (-- RAM block 0 is off or powering up. Off, -- RAM block 0 is on. On) @@ -270,8 +257,7 @@ package NRF51_SVD.POWER is -- RAM block 1 status. type RAMSTATUS_RAMBLOCK1_Field is - ( - -- RAM block 1 is off or powering up. + (-- RAM block 1 is off or powering up. Off, -- RAM block 1 is on. On) @@ -282,8 +268,7 @@ package NRF51_SVD.POWER is -- RAM block 2 status. type RAMSTATUS_RAMBLOCK2_Field is - ( - -- RAM block 2 is off or powering up. + (-- RAM block 2 is off or powering up. Off, -- RAM block 2 is on. On) @@ -294,8 +279,7 @@ package NRF51_SVD.POWER is -- RAM block 3 status. type RAMSTATUS_RAMBLOCK3_Field is - ( - -- RAM block 3 is off or powering up. + (-- RAM block 3 is off or powering up. Off, -- RAM block 3 is on. On) @@ -317,7 +301,7 @@ package NRF51_SVD.POWER is -- unspecified Reserved_4_31 : HAL.UInt28; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for RAMSTATUS_Register use record @@ -330,8 +314,7 @@ package NRF51_SVD.POWER is -- Enter system off mode. type SYSTEMOFF_SYSTEMOFF_Field is - ( - -- Reset value for the field + (-- Reset value for the field Systemoff_Systemoff_Field_Reset, -- Enter system off mode. Enter) @@ -348,7 +331,7 @@ package NRF51_SVD.POWER is -- unspecified Reserved_1_31 : HAL.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for SYSTEMOFF_Register use record @@ -358,8 +341,7 @@ package NRF51_SVD.POWER is -- Power failure comparator enable. type POFCON_POF_Field is - ( - -- Disabled. + (-- Disabled. Disabled, -- Enabled. Enabled) @@ -370,8 +352,7 @@ package NRF51_SVD.POWER is -- Set threshold level. type POFCON_THRESHOLD_Field is - ( - -- Set threshold to 2.1Volts. + (-- Set threshold to 2.1Volts. V21, -- Set threshold to 2.3Volts. V23, @@ -389,13 +370,13 @@ package NRF51_SVD.POWER is -- Power failure configuration. type POFCON_Register is record -- Power failure comparator enable. - POF : POFCON_POF_Field := NRF51_SVD.POWER.Disabled; + POF : POFCON_POF_Field := NRF_SVD.POWER.Disabled; -- Set threshold level. - THRESHOLD : POFCON_THRESHOLD_Field := NRF51_SVD.POWER.V21; + THRESHOLD : POFCON_THRESHOLD_Field := NRF_SVD.POWER.V21; -- unspecified Reserved_3_31 : HAL.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for POFCON_Register use record @@ -414,7 +395,7 @@ package NRF51_SVD.POWER is -- unspecified Reserved_8_31 : HAL.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for GPREGRET_Register use record @@ -424,8 +405,7 @@ package NRF51_SVD.POWER is -- RAM block 0 behaviour in ON mode. type RAMON_ONRAM0_Field is - ( - -- RAM block 0 OFF in ON mode. + (-- RAM block 0 OFF in ON mode. Ram0Off, -- RAM block 0 ON in ON mode. Ram0On) @@ -436,8 +416,7 @@ package NRF51_SVD.POWER is -- RAM block 1 behaviour in ON mode. type RAMON_ONRAM1_Field is - ( - -- RAM block 1 OFF in ON mode. + (-- RAM block 1 OFF in ON mode. Ram1Off, -- RAM block 1 ON in ON mode. Ram1On) @@ -448,8 +427,7 @@ package NRF51_SVD.POWER is -- RAM block 0 behaviour in OFF mode. type RAMON_OFFRAM0_Field is - ( - -- RAM block 0 OFF in OFF mode. + (-- RAM block 0 OFF in OFF mode. Ram0Off, -- RAM block 0 ON in OFF mode. Ram0On) @@ -460,8 +438,7 @@ package NRF51_SVD.POWER is -- RAM block 1 behaviour in OFF mode. type RAMON_OFFRAM1_Field is - ( - -- RAM block 1 OFF in OFF mode. + (-- RAM block 1 OFF in OFF mode. Ram1Off, -- RAM block 1 ON in OFF mode. Ram1On) @@ -473,19 +450,19 @@ package NRF51_SVD.POWER is -- Ram on/off. type RAMON_Register is record -- RAM block 0 behaviour in ON mode. - ONRAM0 : RAMON_ONRAM0_Field := NRF51_SVD.POWER.Ram0On; + ONRAM0 : RAMON_ONRAM0_Field := NRF_SVD.POWER.Ram0On; -- RAM block 1 behaviour in ON mode. - ONRAM1 : RAMON_ONRAM1_Field := NRF51_SVD.POWER.Ram1On; + ONRAM1 : RAMON_ONRAM1_Field := NRF_SVD.POWER.Ram1On; -- unspecified Reserved_2_15 : HAL.UInt14 := 16#0#; -- RAM block 0 behaviour in OFF mode. - OFFRAM0 : RAMON_OFFRAM0_Field := NRF51_SVD.POWER.Ram0Off; + OFFRAM0 : RAMON_OFFRAM0_Field := NRF_SVD.POWER.Ram0Off; -- RAM block 1 behaviour in OFF mode. - OFFRAM1 : RAMON_OFFRAM1_Field := NRF51_SVD.POWER.Ram1Off; + OFFRAM1 : RAMON_OFFRAM1_Field := NRF_SVD.POWER.Ram1Off; -- unspecified Reserved_18_31 : HAL.UInt14 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for RAMON_Register use record @@ -499,8 +476,7 @@ package NRF51_SVD.POWER is -- Enable or disable pin reset in debug interface mode. type RESET_RESET_Field is - ( - -- Pin reset in debug interface mode disabled. + (-- Pin reset in debug interface mode disabled. Disabled, -- Pin reset in debug interface mode enabled. Enabled) @@ -513,11 +489,11 @@ package NRF51_SVD.POWER is -- retained register. type RESET_Register is record -- Enable or disable pin reset in debug interface mode. - RESET : RESET_RESET_Field := NRF51_SVD.POWER.Disabled; + RESET : RESET_RESET_Field := NRF_SVD.POWER.Disabled; -- unspecified Reserved_1_31 : HAL.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for RESET_Register use record @@ -527,8 +503,7 @@ package NRF51_SVD.POWER is -- RAM block 2 behaviour in ON mode. type RAMONB_ONRAM2_Field is - ( - -- RAM block 2 OFF in ON mode. + (-- RAM block 2 OFF in ON mode. Ram2Off, -- RAM block 2 ON in ON mode. Ram2On) @@ -539,8 +514,7 @@ package NRF51_SVD.POWER is -- RAM block 3 behaviour in ON mode. type RAMONB_ONRAM3_Field is - ( - -- RAM block 33 OFF in ON mode. + (-- RAM block 33 OFF in ON mode. Ram3Off, -- RAM block 3 ON in ON mode. Ram3On) @@ -551,8 +525,7 @@ package NRF51_SVD.POWER is -- RAM block 2 behaviour in OFF mode. type RAMONB_OFFRAM2_Field is - ( - -- RAM block 2 OFF in OFF mode. + (-- RAM block 2 OFF in OFF mode. Ram2Off, -- RAM block 2 ON in OFF mode. Ram2On) @@ -563,8 +536,7 @@ package NRF51_SVD.POWER is -- RAM block 3 behaviour in OFF mode. type RAMONB_OFFRAM3_Field is - ( - -- RAM block 3 OFF in OFF mode. + (-- RAM block 3 OFF in OFF mode. Ram3Off, -- RAM block 3 ON in OFF mode. Ram3On) @@ -576,19 +548,19 @@ package NRF51_SVD.POWER is -- Ram on/off. type RAMONB_Register is record -- RAM block 2 behaviour in ON mode. - ONRAM2 : RAMONB_ONRAM2_Field := NRF51_SVD.POWER.Ram2On; + ONRAM2 : RAMONB_ONRAM2_Field := NRF_SVD.POWER.Ram2On; -- RAM block 3 behaviour in ON mode. - ONRAM3 : RAMONB_ONRAM3_Field := NRF51_SVD.POWER.Ram3On; + ONRAM3 : RAMONB_ONRAM3_Field := NRF_SVD.POWER.Ram3On; -- unspecified Reserved_2_15 : HAL.UInt14 := 16#0#; -- RAM block 2 behaviour in OFF mode. - OFFRAM2 : RAMONB_OFFRAM2_Field := NRF51_SVD.POWER.Ram2Off; + OFFRAM2 : RAMONB_OFFRAM2_Field := NRF_SVD.POWER.Ram2Off; -- RAM block 3 behaviour in OFF mode. - OFFRAM3 : RAMONB_OFFRAM3_Field := NRF51_SVD.POWER.Ram3Off; + OFFRAM3 : RAMONB_OFFRAM3_Field := NRF_SVD.POWER.Ram3Off; -- unspecified Reserved_18_31 : HAL.UInt14 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for RAMONB_Register use record @@ -602,8 +574,7 @@ package NRF51_SVD.POWER is -- Enable DCDC converter. type DCDCEN_DCDCEN_Field is - ( - -- DCDC converter disabled. + (-- DCDC converter disabled. Disabled, -- DCDC converter enabled. Enabled) @@ -615,11 +586,11 @@ package NRF51_SVD.POWER is -- DCDC converter enable configuration register. type DCDCEN_Register is record -- Enable DCDC converter. - DCDCEN : DCDCEN_DCDCEN_Field := NRF51_SVD.POWER.Disabled; + DCDCEN : DCDCEN_DCDCEN_Field := NRF_SVD.POWER.Disabled; -- unspecified Reserved_1_31 : HAL.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for DCDCEN_Register use record @@ -629,8 +600,7 @@ package NRF51_SVD.POWER is -- DCDC power-up force off. type DCDCFORCE_FORCEOFF_Field is - ( - -- No force. + (-- No force. Noforce, -- Force. Force) @@ -641,8 +611,7 @@ package NRF51_SVD.POWER is -- DCDC power-up force on. type DCDCFORCE_FORCEON_Field is - ( - -- No force. + (-- No force. Noforce, -- Force. Force) @@ -654,13 +623,13 @@ package NRF51_SVD.POWER is -- DCDC power-up force register. type DCDCFORCE_Register is record -- DCDC power-up force off. - FORCEOFF : DCDCFORCE_FORCEOFF_Field := NRF51_SVD.POWER.Noforce; + FORCEOFF : DCDCFORCE_FORCEOFF_Field := NRF_SVD.POWER.Noforce; -- DCDC power-up force on. - FORCEON : DCDCFORCE_FORCEON_Field := NRF51_SVD.POWER.Noforce; + FORCEON : DCDCFORCE_FORCEON_Field := NRF_SVD.POWER.Noforce; -- unspecified Reserved_2_31 : HAL.UInt30 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for DCDCFORCE_Register use record @@ -730,6 +699,6 @@ package NRF51_SVD.POWER is -- Power Control. POWER_Periph : aliased POWER_Peripheral - with Import, Address => System'To_Address (16#40000000#); + with Import, Address => POWER_Base; -end NRF51_SVD.POWER; +end NRF_SVD.POWER; diff --git a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-ppi.ads b/arch/ARM/Nordic/svd/nrf51/nrf_svd-ppi.ads similarity index 93% rename from arch/ARM/Nordic/svd/nrf51/nrf51_svd-ppi.ads rename to arch/ARM/Nordic/svd/nrf51/nrf_svd-ppi.ads index 1630c4ec8..b0e950587 100644 --- a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-ppi.ads +++ b/arch/ARM/Nordic/svd/nrf51/nrf_svd-ppi.ads @@ -36,7 +36,7 @@ pragma Style_Checks (Off); with HAL; with System; -package NRF51_SVD.PPI is +package NRF_SVD.PPI is pragma Preelaborate; --------------- @@ -54,7 +54,7 @@ package NRF51_SVD.PPI is -- Disable channel group. DIS : aliased HAL.UInt32; end record - with Volatile, Size => 64; + with Size => 64; for PPI_TASKS_CHG_Cluster use record EN at 16#0# range 0 .. 31; @@ -66,8 +66,7 @@ package NRF51_SVD.PPI is -- Enable PPI channel 0. type CHEN_CH0_Field is - ( - -- Channel disabled. + (-- Channel disabled. Disabled, -- Channel enabled. Enabled) @@ -102,8 +101,7 @@ package NRF51_SVD.PPI is -- Enable PPI channel 3. type CHEN_CH3_Field is - ( - -- Channel disabled + (-- Channel disabled Disabled, -- Channel enabled Enabled) @@ -114,8 +112,7 @@ package NRF51_SVD.PPI is -- Enable PPI channel 4. type CHEN_CH4_Field is - ( - -- Channel disabled. + (-- Channel disabled. Disabled, -- Channel enabled. Enabled) @@ -150,8 +147,7 @@ package NRF51_SVD.PPI is -- Enable PPI channel 20. type CHEN_CH20_Field is - ( - -- Channel disabled. + (-- Channel disabled. Disabled, -- Channel enabled. Enabled) @@ -189,7 +185,7 @@ package NRF51_SVD.PPI is -- Enable PPI channel 0. CH : CHEN_CH_Field := (As_Array => False, Val => 16#0#); -- Enable PPI channel 3. - CH3 : CHEN_CH3_Field := NRF51_SVD.PPI.Disabled; + CH3 : CHEN_CH3_Field := NRF_SVD.PPI.Disabled; -- Enable PPI channel 4. CH_1 : CHEN_CH_Field_1 := (As_Array => False, Val => 16#0#); -- unspecified @@ -197,7 +193,7 @@ package NRF51_SVD.PPI is -- Enable PPI channel 20. CH_2 : CHEN_CH_Field_2 := (As_Array => False, Val => 16#0#); end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for CHEN_Register use record @@ -210,8 +206,7 @@ package NRF51_SVD.PPI is -- Enable PPI channel 0. type CHENSET_CH0_Field is - ( - -- Channel disabled. + (-- Channel disabled. Disabled, -- Channel enabled. Enabled) @@ -222,8 +217,7 @@ package NRF51_SVD.PPI is -- Enable PPI channel 0. type CHENSET_CH0_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Chenset_Ch0_Field_Reset, -- Enable channel on write. Set) @@ -258,8 +252,7 @@ package NRF51_SVD.PPI is -- Enable PPI channel 20. type CHENSET_CH20_Field is - ( - -- Channel disabled. + (-- Channel disabled. Disabled, -- Channel enabled. Enabled) @@ -270,8 +263,7 @@ package NRF51_SVD.PPI is -- Enable PPI channel 20. type CHENSET_CH20_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Chenset_Ch20_Field_Reset, -- Enable channel on write. Set) @@ -314,7 +306,7 @@ package NRF51_SVD.PPI is CH_1 : CHENSET_CH_Field_1 := (As_Array => False, Val => 16#0#); end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for CHENSET_Register use record @@ -325,8 +317,7 @@ package NRF51_SVD.PPI is -- Disable PPI channel 0. type CHENCLR_CH0_Field is - ( - -- Channel disabled. + (-- Channel disabled. Disabled, -- Channel enabled. Enabled) @@ -337,8 +328,7 @@ package NRF51_SVD.PPI is -- Disable PPI channel 0. type CHENCLR_CH0_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Chenclr_Ch0_Field_Reset, -- Disable channel on write. Clear) @@ -373,8 +363,7 @@ package NRF51_SVD.PPI is -- Disable PPI channel 20. type CHENCLR_CH20_Field is - ( - -- Channel disabled. + (-- Channel disabled. Disabled, -- Channel enabled. Enabled) @@ -385,8 +374,7 @@ package NRF51_SVD.PPI is -- Disable PPI channel 20. type CHENCLR_CH20_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Chenclr_Ch20_Field_Reset, -- Disable channel on write. Clear) @@ -429,7 +417,7 @@ package NRF51_SVD.PPI is CH_1 : CHENCLR_CH_Field_1 := (As_Array => False, Val => 16#0#); end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for CHENCLR_Register use record @@ -449,7 +437,7 @@ package NRF51_SVD.PPI is -- Channel task end-point. TEP : aliased HAL.UInt32; end record - with Volatile, Size => 64; + with Size => 64; for PPI_CH_Cluster use record EEP at 16#0# range 0 .. 31; @@ -461,8 +449,7 @@ package NRF51_SVD.PPI is -- Include CH0 in channel group. type CHG_CH0_Field is - ( - -- Channel excluded. + (-- Channel excluded. Excluded, -- Channel included. Included) @@ -497,8 +484,7 @@ package NRF51_SVD.PPI is -- Include CH20 in channel group. type CHG_CH20_Field is - ( - -- Channel excluded. + (-- Channel excluded. Excluded, -- Channel included. Included) @@ -540,7 +526,7 @@ package NRF51_SVD.PPI is -- Include CH20 in channel group. CH_1 : CHG_CH_Field_1 := (As_Array => False, Val => 16#0#); end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for CHG_Register use record @@ -550,8 +536,7 @@ package NRF51_SVD.PPI is end record; -- Channel group configuration. - type CHG_Registers is array (0 .. 3) of CHG_Register - with Volatile; + type CHG_Registers is array (0 .. 3) of CHG_Register; ----------------- -- Peripherals -- @@ -585,6 +570,6 @@ package NRF51_SVD.PPI is -- PPI controller. PPI_Periph : aliased PPI_Peripheral - with Import, Address => System'To_Address (16#4001F000#); + with Import, Address => PPI_Base; -end NRF51_SVD.PPI; +end NRF_SVD.PPI; diff --git a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-qdec.ads b/arch/ARM/Nordic/svd/nrf51/nrf_svd-qdec.ads similarity index 83% rename from arch/ARM/Nordic/svd/nrf51/nrf51_svd-qdec.ads rename to arch/ARM/Nordic/svd/nrf51/nrf_svd-qdec.ads index 215152b3f..62bf54dd5 100644 --- a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-qdec.ads +++ b/arch/ARM/Nordic/svd/nrf51/nrf_svd-qdec.ads @@ -36,7 +36,7 @@ pragma Style_Checks (Off); with HAL; with System; -package NRF51_SVD.QDEC is +package NRF_SVD.QDEC is pragma Preelaborate; --------------- @@ -45,8 +45,7 @@ package NRF51_SVD.QDEC is -- Shortcut between REPORTRDY event and READCLRACC task. type SHORTS_REPORTRDY_READCLRACC_Field is - ( - -- Shortcut disabled. + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) @@ -57,8 +56,7 @@ package NRF51_SVD.QDEC is -- Shortcut between SAMPLERDY event and STOP task. type SHORTS_SAMPLERDY_STOP_Field is - ( - -- Shortcut disabled. + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) @@ -71,14 +69,14 @@ package NRF51_SVD.QDEC is type SHORTS_Register is record -- Shortcut between REPORTRDY event and READCLRACC task. REPORTRDY_READCLRACC : SHORTS_REPORTRDY_READCLRACC_Field := - NRF51_SVD.QDEC.Disabled; + NRF_SVD.QDEC.Disabled; -- Shortcut between SAMPLERDY event and STOP task. SAMPLERDY_STOP : SHORTS_SAMPLERDY_STOP_Field := - NRF51_SVD.QDEC.Disabled; + NRF_SVD.QDEC.Disabled; -- unspecified Reserved_2_31 : HAL.UInt30 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for SHORTS_Register use record @@ -89,8 +87,7 @@ package NRF51_SVD.QDEC is -- Enable interrupt on SAMPLERDY event. type INTENSET_SAMPLERDY_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -101,8 +98,7 @@ package NRF51_SVD.QDEC is -- Enable interrupt on SAMPLERDY event. type INTENSET_SAMPLERDY_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Samplerdy_Field_Reset, -- Enable interrupt on write. Set) @@ -113,8 +109,7 @@ package NRF51_SVD.QDEC is -- Enable interrupt on REPORTRDY event. type INTENSET_REPORTRDY_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -125,8 +120,7 @@ package NRF51_SVD.QDEC is -- Enable interrupt on REPORTRDY event. type INTENSET_REPORTRDY_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Reportrdy_Field_Reset, -- Enable interrupt on write. Set) @@ -137,8 +131,7 @@ package NRF51_SVD.QDEC is -- Enable interrupt on ACCOF event. type INTENSET_ACCOF_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -149,8 +142,7 @@ package NRF51_SVD.QDEC is -- Enable interrupt on ACCOF event. type INTENSET_ACCOF_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Accof_Field_Reset, -- Enable interrupt on write. Set) @@ -172,7 +164,7 @@ package NRF51_SVD.QDEC is -- unspecified Reserved_3_31 : HAL.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENSET_Register use record @@ -184,8 +176,7 @@ package NRF51_SVD.QDEC is -- Disable interrupt on SAMPLERDY event. type INTENCLR_SAMPLERDY_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -196,8 +187,7 @@ package NRF51_SVD.QDEC is -- Disable interrupt on SAMPLERDY event. type INTENCLR_SAMPLERDY_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Samplerdy_Field_Reset, -- Disable interrupt on write. Clear) @@ -208,8 +198,7 @@ package NRF51_SVD.QDEC is -- Disable interrupt on REPORTRDY event. type INTENCLR_REPORTRDY_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -220,8 +209,7 @@ package NRF51_SVD.QDEC is -- Disable interrupt on REPORTRDY event. type INTENCLR_REPORTRDY_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Reportrdy_Field_Reset, -- Disable interrupt on write. Clear) @@ -232,8 +220,7 @@ package NRF51_SVD.QDEC is -- Disable interrupt on ACCOF event. type INTENCLR_ACCOF_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -244,8 +231,7 @@ package NRF51_SVD.QDEC is -- Disable interrupt on ACCOF event. type INTENCLR_ACCOF_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Accof_Field_Reset, -- Disable interrupt on write. Clear) @@ -267,7 +253,7 @@ package NRF51_SVD.QDEC is -- unspecified Reserved_3_31 : HAL.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENCLR_Register use record @@ -279,8 +265,7 @@ package NRF51_SVD.QDEC is -- Enable or disable QDEC. type ENABLE_ENABLE_Field is - ( - -- Disabled QDEC. + (-- Disabled QDEC. Disabled, -- Enable QDEC. Enabled) @@ -292,11 +277,11 @@ package NRF51_SVD.QDEC is -- Enable the QDEC. type ENABLE_Register is record -- Enable or disable QDEC. - ENABLE : ENABLE_ENABLE_Field := NRF51_SVD.QDEC.Disabled; + ENABLE : ENABLE_ENABLE_Field := NRF_SVD.QDEC.Disabled; -- unspecified Reserved_1_31 : HAL.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for ENABLE_Register use record @@ -306,8 +291,7 @@ package NRF51_SVD.QDEC is -- LED output pin polarity. type LEDPOL_LEDPOL_Field is - ( - -- LED output is active low. + (-- LED output is active low. Activelow, -- LED output is active high. Activehigh) @@ -319,11 +303,11 @@ package NRF51_SVD.QDEC is -- LED output pin polarity. type LEDPOL_Register is record -- LED output pin polarity. - LEDPOL : LEDPOL_LEDPOL_Field := NRF51_SVD.QDEC.Activelow; + LEDPOL : LEDPOL_LEDPOL_Field := NRF_SVD.QDEC.Activelow; -- unspecified Reserved_1_31 : HAL.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for LEDPOL_Register use record @@ -333,43 +317,41 @@ package NRF51_SVD.QDEC is -- Sample period. type SAMPLEPER_SAMPLEPER_Field is - ( - -- 128us sample period. - SAMPLEPER_SAMPLEPER_Field_128US, + (-- 128us sample period. + Val_128US, -- 256us sample period. - SAMPLEPER_SAMPLEPER_Field_256US, + Val_256US, -- 512us sample period. - SAMPLEPER_SAMPLEPER_Field_512US, + Val_512US, -- 1024us sample period. - SAMPLEPER_SAMPLEPER_Field_1024US, + Val_1024US, -- 2048us sample period. - SAMPLEPER_SAMPLEPER_Field_2048US, + Val_2048US, -- 4096us sample period. - SAMPLEPER_SAMPLEPER_Field_4096US, + Val_4096US, -- 8192us sample period. - SAMPLEPER_SAMPLEPER_Field_8192US, + Val_8192US, -- 16384us sample period. - SAMPLEPER_SAMPLEPER_Field_16384US) + Val_16384US) with Size => 3; for SAMPLEPER_SAMPLEPER_Field use - (SAMPLEPER_SAMPLEPER_Field_128US => 0, - SAMPLEPER_SAMPLEPER_Field_256US => 1, - SAMPLEPER_SAMPLEPER_Field_512US => 2, - SAMPLEPER_SAMPLEPER_Field_1024US => 3, - SAMPLEPER_SAMPLEPER_Field_2048US => 4, - SAMPLEPER_SAMPLEPER_Field_4096US => 5, - SAMPLEPER_SAMPLEPER_Field_8192US => 6, - SAMPLEPER_SAMPLEPER_Field_16384US => 7); + (Val_128US => 0, + Val_256US => 1, + Val_512US => 2, + Val_1024US => 3, + Val_2048US => 4, + Val_4096US => 5, + Val_8192US => 6, + Val_16384US => 7); -- Sample period. type SAMPLEPER_Register is record -- Sample period. - SAMPLEPER : SAMPLEPER_SAMPLEPER_Field := - NRF51_SVD.QDEC.SAMPLEPER_SAMPLEPER_Field_128US; + SAMPLEPER : SAMPLEPER_SAMPLEPER_Field := NRF_SVD.QDEC.Val_128US; -- unspecified Reserved_3_31 : HAL.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for SAMPLEPER_Register use record @@ -379,43 +361,41 @@ package NRF51_SVD.QDEC is -- Number of samples to generate an EVENT_REPORTRDY. type REPORTPER_REPORTPER_Field is - ( - -- 10 samples per report. - REPORTPER_REPORTPER_Field_10Smpl, + (-- 10 samples per report. + Val_10Smpl, -- 40 samples per report. - REPORTPER_REPORTPER_Field_40Smpl, + Val_40Smpl, -- 80 samples per report. - REPORTPER_REPORTPER_Field_80Smpl, + Val_80Smpl, -- 120 samples per report. - REPORTPER_REPORTPER_Field_120Smpl, + Val_120Smpl, -- 160 samples per report. - REPORTPER_REPORTPER_Field_160Smpl, + Val_160Smpl, -- 200 samples per report. - REPORTPER_REPORTPER_Field_200Smpl, + Val_200Smpl, -- 240 samples per report. - REPORTPER_REPORTPER_Field_240Smpl, + Val_240Smpl, -- 280 samples per report. - REPORTPER_REPORTPER_Field_280Smpl) + Val_280Smpl) with Size => 3; for REPORTPER_REPORTPER_Field use - (REPORTPER_REPORTPER_Field_10Smpl => 0, - REPORTPER_REPORTPER_Field_40Smpl => 1, - REPORTPER_REPORTPER_Field_80Smpl => 2, - REPORTPER_REPORTPER_Field_120Smpl => 3, - REPORTPER_REPORTPER_Field_160Smpl => 4, - REPORTPER_REPORTPER_Field_200Smpl => 5, - REPORTPER_REPORTPER_Field_240Smpl => 6, - REPORTPER_REPORTPER_Field_280Smpl => 7); + (Val_10Smpl => 0, + Val_40Smpl => 1, + Val_80Smpl => 2, + Val_120Smpl => 3, + Val_160Smpl => 4, + Val_200Smpl => 5, + Val_240Smpl => 6, + Val_280Smpl => 7); -- Number of samples to generate an EVENT_REPORTRDY. type REPORTPER_Register is record -- Number of samples to generate an EVENT_REPORTRDY. - REPORTPER : REPORTPER_REPORTPER_Field := - NRF51_SVD.QDEC.REPORTPER_REPORTPER_Field_10Smpl; + REPORTPER : REPORTPER_REPORTPER_Field := NRF_SVD.QDEC.Val_10Smpl; -- unspecified Reserved_3_31 : HAL.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for REPORTPER_Register use record @@ -425,8 +405,7 @@ package NRF51_SVD.QDEC is -- Enable debounce input filters. type DBFEN_DBFEN_Field is - ( - -- Debounce input filters disabled. + (-- Debounce input filters disabled. Disabled, -- Debounce input filters enabled. Enabled) @@ -438,11 +417,11 @@ package NRF51_SVD.QDEC is -- Enable debouncer input filters. type DBFEN_Register is record -- Enable debounce input filters. - DBFEN : DBFEN_DBFEN_Field := NRF51_SVD.QDEC.Disabled; + DBFEN : DBFEN_DBFEN_Field := NRF_SVD.QDEC.Disabled; -- unspecified Reserved_1_31 : HAL.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for DBFEN_Register use record @@ -459,7 +438,7 @@ package NRF51_SVD.QDEC is -- unspecified Reserved_9_31 : HAL.UInt23 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for LEDPRE_Register use record @@ -476,7 +455,7 @@ package NRF51_SVD.QDEC is -- unspecified Reserved_4_31 : HAL.UInt28; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for ACCDBL_Register use record @@ -494,7 +473,7 @@ package NRF51_SVD.QDEC is -- unspecified Reserved_4_31 : HAL.UInt28; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for ACCDBLREAD_Register use record @@ -504,8 +483,7 @@ package NRF51_SVD.QDEC is -- Peripheral power control. type POWER_POWER_Field is - ( - -- Module power disabled. + (-- Module power disabled. Disabled, -- Module power enabled. Enabled) @@ -517,11 +495,11 @@ package NRF51_SVD.QDEC is -- Peripheral power control. type POWER_Register is record -- Peripheral power control. - POWER : POWER_POWER_Field := NRF51_SVD.QDEC.Disabled; + POWER : POWER_POWER_Field := NRF_SVD.QDEC.Disabled; -- unspecified Reserved_1_31 : HAL.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for POWER_Register use record @@ -619,6 +597,6 @@ package NRF51_SVD.QDEC is -- Rotary decoder. QDEC_Periph : aliased QDEC_Peripheral - with Import, Address => System'To_Address (16#40012000#); + with Import, Address => QDEC_Base; -end NRF51_SVD.QDEC; +end NRF_SVD.QDEC; diff --git a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-radio.ads b/arch/ARM/Nordic/svd/nrf51/nrf_svd-radio.ads similarity index 89% rename from arch/ARM/Nordic/svd/nrf51/nrf51_svd-radio.ads rename to arch/ARM/Nordic/svd/nrf51/nrf_svd-radio.ads index c75aecc19..ccdcb9c62 100644 --- a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-radio.ads +++ b/arch/ARM/Nordic/svd/nrf51/nrf_svd-radio.ads @@ -36,7 +36,7 @@ pragma Style_Checks (Off); with HAL; with System; -package NRF51_SVD.RADIO is +package NRF_SVD.RADIO is pragma Preelaborate; --------------- @@ -45,8 +45,7 @@ package NRF51_SVD.RADIO is -- Shortcut between READY event and START task. type SHORTS_READY_START_Field is - ( - -- Shortcut disabled. + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) @@ -57,8 +56,7 @@ package NRF51_SVD.RADIO is -- Shortcut between END event and DISABLE task. type SHORTS_END_DISABLE_Field is - ( - -- Shortcut disabled. + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) @@ -69,8 +67,7 @@ package NRF51_SVD.RADIO is -- Shortcut between DISABLED event and TXEN task. type SHORTS_DISABLED_TXEN_Field is - ( - -- Shortcut disabled. + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) @@ -81,8 +78,7 @@ package NRF51_SVD.RADIO is -- Shortcut between DISABLED event and RXEN task. type SHORTS_DISABLED_RXEN_Field is - ( - -- Shortcut disabled. + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) @@ -93,8 +89,7 @@ package NRF51_SVD.RADIO is -- Shortcut between ADDRESS event and RSSISTART task. type SHORTS_ADDRESS_RSSISTART_Field is - ( - -- Shortcut disabled. + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) @@ -105,8 +100,7 @@ package NRF51_SVD.RADIO is -- Shortcut between END event and START task. type SHORTS_END_START_Field is - ( - -- Shortcut disabled. + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) @@ -117,8 +111,7 @@ package NRF51_SVD.RADIO is -- Shortcut between ADDRESS event and BCSTART task. type SHORTS_ADDRESS_BCSTART_Field is - ( - -- Shortcut disabled. + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) @@ -129,8 +122,7 @@ package NRF51_SVD.RADIO is -- Shortcut between DISABLED event and RSSISTOP task. type SHORTS_DISABLED_RSSISTOP_Field is - ( - -- Shortcut disabled. + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) @@ -142,34 +134,32 @@ package NRF51_SVD.RADIO is -- Shortcuts for the radio. type SHORTS_Register is record -- Shortcut between READY event and START task. - READY_START : SHORTS_READY_START_Field := - NRF51_SVD.RADIO.Disabled; + READY_START : SHORTS_READY_START_Field := NRF_SVD.RADIO.Disabled; -- Shortcut between END event and DISABLE task. - END_DISABLE : SHORTS_END_DISABLE_Field := - NRF51_SVD.RADIO.Disabled; + END_DISABLE : SHORTS_END_DISABLE_Field := NRF_SVD.RADIO.Disabled; -- Shortcut between DISABLED event and TXEN task. DISABLED_TXEN : SHORTS_DISABLED_TXEN_Field := - NRF51_SVD.RADIO.Disabled; + NRF_SVD.RADIO.Disabled; -- Shortcut between DISABLED event and RXEN task. DISABLED_RXEN : SHORTS_DISABLED_RXEN_Field := - NRF51_SVD.RADIO.Disabled; + NRF_SVD.RADIO.Disabled; -- Shortcut between ADDRESS event and RSSISTART task. ADDRESS_RSSISTART : SHORTS_ADDRESS_RSSISTART_Field := - NRF51_SVD.RADIO.Disabled; + NRF_SVD.RADIO.Disabled; -- Shortcut between END event and START task. - END_START : SHORTS_END_START_Field := NRF51_SVD.RADIO.Disabled; + END_START : SHORTS_END_START_Field := NRF_SVD.RADIO.Disabled; -- Shortcut between ADDRESS event and BCSTART task. ADDRESS_BCSTART : SHORTS_ADDRESS_BCSTART_Field := - NRF51_SVD.RADIO.Disabled; + NRF_SVD.RADIO.Disabled; -- unspecified Reserved_7_7 : HAL.Bit := 16#0#; -- Shortcut between DISABLED event and RSSISTOP task. DISABLED_RSSISTOP : SHORTS_DISABLED_RSSISTOP_Field := - NRF51_SVD.RADIO.Disabled; + NRF_SVD.RADIO.Disabled; -- unspecified Reserved_9_31 : HAL.UInt23 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for SHORTS_Register use record @@ -187,8 +177,7 @@ package NRF51_SVD.RADIO is -- Enable interrupt on READY event. type INTENSET_READY_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -199,8 +188,7 @@ package NRF51_SVD.RADIO is -- Enable interrupt on READY event. type INTENSET_READY_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Ready_Field_Reset, -- Enable interrupt on write. Set) @@ -211,8 +199,7 @@ package NRF51_SVD.RADIO is -- Enable interrupt on ADDRESS event. type INTENSET_ADDRESS_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -223,8 +210,7 @@ package NRF51_SVD.RADIO is -- Enable interrupt on ADDRESS event. type INTENSET_ADDRESS_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Address_Field_Reset, -- Enable interrupt on write. Set) @@ -235,8 +221,7 @@ package NRF51_SVD.RADIO is -- Enable interrupt on PAYLOAD event. type INTENSET_PAYLOAD_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -247,8 +232,7 @@ package NRF51_SVD.RADIO is -- Enable interrupt on PAYLOAD event. type INTENSET_PAYLOAD_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Payload_Field_Reset, -- Enable interrupt on write. Set) @@ -259,8 +243,7 @@ package NRF51_SVD.RADIO is -- Enable interrupt on END event. type INTENSET_END_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -271,8 +254,7 @@ package NRF51_SVD.RADIO is -- Enable interrupt on END event. type INTENSET_END_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_End_Field_Reset, -- Enable interrupt on write. Set) @@ -283,8 +265,7 @@ package NRF51_SVD.RADIO is -- Enable interrupt on DISABLED event. type INTENSET_DISABLED_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -295,8 +276,7 @@ package NRF51_SVD.RADIO is -- Enable interrupt on DISABLED event. type INTENSET_DISABLED_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Disabled_Field_Reset, -- Enable interrupt on write. Set) @@ -307,8 +287,7 @@ package NRF51_SVD.RADIO is -- Enable interrupt on DEVMATCH event. type INTENSET_DEVMATCH_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -319,8 +298,7 @@ package NRF51_SVD.RADIO is -- Enable interrupt on DEVMATCH event. type INTENSET_DEVMATCH_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Devmatch_Field_Reset, -- Enable interrupt on write. Set) @@ -331,8 +309,7 @@ package NRF51_SVD.RADIO is -- Enable interrupt on DEVMISS event. type INTENSET_DEVMISS_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -343,8 +320,7 @@ package NRF51_SVD.RADIO is -- Enable interrupt on DEVMISS event. type INTENSET_DEVMISS_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Devmiss_Field_Reset, -- Enable interrupt on write. Set) @@ -355,8 +331,7 @@ package NRF51_SVD.RADIO is -- Enable interrupt on RSSIEND event. type INTENSET_RSSIEND_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -367,8 +342,7 @@ package NRF51_SVD.RADIO is -- Enable interrupt on RSSIEND event. type INTENSET_RSSIEND_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Rssiend_Field_Reset, -- Enable interrupt on write. Set) @@ -379,8 +353,7 @@ package NRF51_SVD.RADIO is -- Enable interrupt on BCMATCH event. type INTENSET_BCMATCH_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -391,8 +364,7 @@ package NRF51_SVD.RADIO is -- Enable interrupt on BCMATCH event. type INTENSET_BCMATCH_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Bcmatch_Field_Reset, -- Enable interrupt on write. Set) @@ -433,7 +405,7 @@ package NRF51_SVD.RADIO is -- unspecified Reserved_11_31 : HAL.UInt21 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENSET_Register use record @@ -452,8 +424,7 @@ package NRF51_SVD.RADIO is -- Disable interrupt on READY event. type INTENCLR_READY_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -464,8 +435,7 @@ package NRF51_SVD.RADIO is -- Disable interrupt on READY event. type INTENCLR_READY_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Ready_Field_Reset, -- Disable interrupt on write. Clear) @@ -476,8 +446,7 @@ package NRF51_SVD.RADIO is -- Disable interrupt on ADDRESS event. type INTENCLR_ADDRESS_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -488,8 +457,7 @@ package NRF51_SVD.RADIO is -- Disable interrupt on ADDRESS event. type INTENCLR_ADDRESS_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Address_Field_Reset, -- Disable interrupt on write. Clear) @@ -500,8 +468,7 @@ package NRF51_SVD.RADIO is -- Disable interrupt on PAYLOAD event. type INTENCLR_PAYLOAD_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -512,8 +479,7 @@ package NRF51_SVD.RADIO is -- Disable interrupt on PAYLOAD event. type INTENCLR_PAYLOAD_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Payload_Field_Reset, -- Disable interrupt on write. Clear) @@ -524,8 +490,7 @@ package NRF51_SVD.RADIO is -- Disable interrupt on END event. type INTENCLR_END_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -536,8 +501,7 @@ package NRF51_SVD.RADIO is -- Disable interrupt on END event. type INTENCLR_END_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_End_Field_Reset, -- Disable interrupt on write. Clear) @@ -548,8 +512,7 @@ package NRF51_SVD.RADIO is -- Disable interrupt on DISABLED event. type INTENCLR_DISABLED_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -560,8 +523,7 @@ package NRF51_SVD.RADIO is -- Disable interrupt on DISABLED event. type INTENCLR_DISABLED_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Disabled_Field_Reset, -- Disable interrupt on write. Clear) @@ -572,8 +534,7 @@ package NRF51_SVD.RADIO is -- Disable interrupt on DEVMATCH event. type INTENCLR_DEVMATCH_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -584,8 +545,7 @@ package NRF51_SVD.RADIO is -- Disable interrupt on DEVMATCH event. type INTENCLR_DEVMATCH_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Devmatch_Field_Reset, -- Disable interrupt on write. Clear) @@ -596,8 +556,7 @@ package NRF51_SVD.RADIO is -- Disable interrupt on DEVMISS event. type INTENCLR_DEVMISS_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -608,8 +567,7 @@ package NRF51_SVD.RADIO is -- Disable interrupt on DEVMISS event. type INTENCLR_DEVMISS_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Devmiss_Field_Reset, -- Disable interrupt on write. Clear) @@ -620,8 +578,7 @@ package NRF51_SVD.RADIO is -- Disable interrupt on RSSIEND event. type INTENCLR_RSSIEND_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -632,8 +589,7 @@ package NRF51_SVD.RADIO is -- Disable interrupt on RSSIEND event. type INTENCLR_RSSIEND_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Rssiend_Field_Reset, -- Disable interrupt on write. Clear) @@ -644,8 +600,7 @@ package NRF51_SVD.RADIO is -- Disable interrupt on BCMATCH event. type INTENCLR_BCMATCH_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -656,8 +611,7 @@ package NRF51_SVD.RADIO is -- Disable interrupt on BCMATCH event. type INTENCLR_BCMATCH_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Bcmatch_Field_Reset, -- Disable interrupt on write. Clear) @@ -698,7 +652,7 @@ package NRF51_SVD.RADIO is -- unspecified Reserved_11_31 : HAL.UInt21 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENCLR_Register use record @@ -717,8 +671,7 @@ package NRF51_SVD.RADIO is -- CRC status of received packet. type CRCSTATUS_CRCSTATUS_Field is - ( - -- Packet received with CRC error. + (-- Packet received with CRC error. Crcerror, -- Packet received with CRC ok. Crcok) @@ -734,7 +687,7 @@ package NRF51_SVD.RADIO is -- unspecified Reserved_1_31 : HAL.UInt31; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for CRCSTATUS_Register use record @@ -751,7 +704,7 @@ package NRF51_SVD.RADIO is -- unspecified Reserved_3_31 : HAL.UInt29; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for RXMATCH_Register use record @@ -768,7 +721,7 @@ package NRF51_SVD.RADIO is -- unspecified Reserved_24_31 : HAL.UInt8; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for RXCRC_Register use record @@ -786,7 +739,7 @@ package NRF51_SVD.RADIO is -- unspecified Reserved_3_31 : HAL.UInt29; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for DAI_Register use record @@ -804,7 +757,7 @@ package NRF51_SVD.RADIO is -- unspecified Reserved_7_31 : HAL.UInt25 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for FREQUENCY_Register use record @@ -814,9 +767,8 @@ package NRF51_SVD.RADIO is -- Radio output power. Decision point: TXEN task. type TXPOWER_TXPOWER_Field is - ( - -- 0dBm. - TXPOWER_TXPOWER_Field_0DBm, + (-- 0dBm. + Val_0DBm, -- +4dBm. Pos4DBm, -- -30dBm. @@ -833,7 +785,7 @@ package NRF51_SVD.RADIO is Neg4DBm) with Size => 8; for TXPOWER_TXPOWER_Field use - (TXPOWER_TXPOWER_Field_0DBm => 0, + (Val_0DBm => 0, Pos4DBm => 4, Neg30DBm => 216, Neg20DBm => 236, @@ -845,12 +797,11 @@ package NRF51_SVD.RADIO is -- Output power. type TXPOWER_Register is record -- Radio output power. Decision point: TXEN task. - TXPOWER : TXPOWER_TXPOWER_Field := - NRF51_SVD.RADIO.TXPOWER_TXPOWER_Field_0DBm; + TXPOWER : TXPOWER_TXPOWER_Field := NRF_SVD.RADIO.Val_0DBm; -- unspecified Reserved_8_31 : HAL.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for TXPOWER_Register use record @@ -861,8 +812,7 @@ package NRF51_SVD.RADIO is -- Radio data rate and modulation setting. Decision point: TXEN or RXEN -- task. type MODE_MODE_Field is - ( - -- 1Mbit/s Nordic propietary radio mode. + (-- 1Mbit/s Nordic propietary radio mode. Nrf_1Mbit, -- 2Mbit/s Nordic propietary radio mode. Nrf_2Mbit, @@ -881,11 +831,11 @@ package NRF51_SVD.RADIO is type MODE_Register is record -- Radio data rate and modulation setting. Decision point: TXEN or RXEN -- task. - MODE : MODE_MODE_Field := NRF51_SVD.RADIO.Nrf_1Mbit; + MODE : MODE_MODE_Field := NRF_SVD.RADIO.Nrf_1Mbit; -- unspecified Reserved_2_31 : HAL.UInt30 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for MODE_Register use record @@ -911,7 +861,7 @@ package NRF51_SVD.RADIO is -- unspecified Reserved_20_31 : HAL.UInt12 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for PCNF0_Register use record @@ -929,8 +879,7 @@ package NRF51_SVD.RADIO is -- On air endianness of packet length field. Decision point: START task. type PCNF1_ENDIAN_Field is - ( - -- Least significant bit on air first + (-- Least significant bit on air first Little, -- Most significant bit on air first Big) @@ -941,8 +890,7 @@ package NRF51_SVD.RADIO is -- Packet whitening enable. type PCNF1_WHITEEN_Field is - ( - -- Whitening disabled. + (-- Whitening disabled. Disabled, -- Whitening enabled. Enabled) @@ -962,13 +910,13 @@ package NRF51_SVD.RADIO is -- unspecified Reserved_19_23 : HAL.UInt5 := 16#0#; -- On air endianness of packet length field. Decision point: START task. - ENDIAN : PCNF1_ENDIAN_Field := NRF51_SVD.RADIO.Little; + ENDIAN : PCNF1_ENDIAN_Field := NRF_SVD.RADIO.Little; -- Packet whitening enable. - WHITEEN : PCNF1_WHITEEN_Field := NRF51_SVD.RADIO.Disabled; + WHITEEN : PCNF1_WHITEEN_Field := NRF_SVD.RADIO.Disabled; -- unspecified Reserved_26_31 : HAL.UInt6 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for PCNF1_Register use record @@ -1001,7 +949,7 @@ package NRF51_SVD.RADIO is Arr : PREFIX0_AP_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for PREFIX0_Register use record @@ -1029,7 +977,7 @@ package NRF51_SVD.RADIO is Arr : PREFIX1_AP_Field_Array; end case; end record - with Unchecked_Union, Size => 32, Volatile_Full_Access, + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for PREFIX1_Register use record @@ -1047,7 +995,7 @@ package NRF51_SVD.RADIO is -- unspecified Reserved_3_31 : HAL.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for TXADDRESS_Register use record @@ -1057,8 +1005,7 @@ package NRF51_SVD.RADIO is -- Enable reception on logical address 0. Decision point: START task. type RXADDRESSES_ADDR0_Field is - ( - -- Reception disabled. + (-- Reception disabled. Disabled, -- Reception enabled. Enabled) @@ -1100,7 +1047,7 @@ package NRF51_SVD.RADIO is -- unspecified Reserved_8_31 : HAL.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for RXADDRESSES_Register use record @@ -1110,8 +1057,7 @@ package NRF51_SVD.RADIO is -- CRC length. Decision point: START task. type CRCCNF_LEN_Field is - ( - -- CRC calculation disabled. + (-- CRC calculation disabled. Disabled, -- One byte long CRC. One, @@ -1129,11 +1075,10 @@ package NRF51_SVD.RADIO is -- Leave packet address field out of the CRC calculation. Decision point: -- START task. type CRCCNF_SKIPADDR_Field is - ( - -- Include packet address in CRC calculation. + (-- Include packet address in CRC calculation. Include, - -- Packet address is skipped in CRC calculation. The CRC calculation - -- will start at the first byte after the address. + -- Packet address is skipped in CRC calculation. The CRC calculation will +-- start at the first byte after the address. Skip) with Size => 1; for CRCCNF_SKIPADDR_Field use @@ -1143,16 +1088,16 @@ package NRF51_SVD.RADIO is -- CRC configuration. type CRCCNF_Register is record -- CRC length. Decision point: START task. - LEN : CRCCNF_LEN_Field := NRF51_SVD.RADIO.Disabled; + LEN : CRCCNF_LEN_Field := NRF_SVD.RADIO.Disabled; -- unspecified Reserved_2_7 : HAL.UInt6 := 16#0#; -- Leave packet address field out of the CRC calculation. Decision -- point: START task. - SKIPADDR : CRCCNF_SKIPADDR_Field := NRF51_SVD.RADIO.Include; + SKIPADDR : CRCCNF_SKIPADDR_Field := NRF_SVD.RADIO.Include; -- unspecified Reserved_9_31 : HAL.UInt23 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for CRCCNF_Register use record @@ -1171,7 +1116,7 @@ package NRF51_SVD.RADIO is -- unspecified Reserved_24_31 : HAL.UInt8 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for CRCPOLY_Register use record @@ -1188,7 +1133,7 @@ package NRF51_SVD.RADIO is -- unspecified Reserved_24_31 : HAL.UInt8 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for CRCINIT_Register use record @@ -1198,8 +1143,7 @@ package NRF51_SVD.RADIO is -- Constant carrier. Decision point: TXEN task. type TEST_CONSTCARRIER_Field is - ( - -- Constant carrier disabled. + (-- Constant carrier disabled. Disabled, -- Constant carrier enabled. Enabled) @@ -1210,8 +1154,7 @@ package NRF51_SVD.RADIO is -- PLL lock. Decision point: TXEN or RXEN task. type TEST_PLLLOCK_Field is - ( - -- PLL lock disabled. + (-- PLL lock disabled. Disabled, -- PLL lock enabled. Enabled) @@ -1223,13 +1166,13 @@ package NRF51_SVD.RADIO is -- Test features enable register. type TEST_Register is record -- Constant carrier. Decision point: TXEN task. - CONSTCARRIER : TEST_CONSTCARRIER_Field := NRF51_SVD.RADIO.Disabled; + CONSTCARRIER : TEST_CONSTCARRIER_Field := NRF_SVD.RADIO.Disabled; -- PLL lock. Decision point: TXEN or RXEN task. - PLLLOCK : TEST_PLLLOCK_Field := NRF51_SVD.RADIO.Disabled; + PLLLOCK : TEST_PLLLOCK_Field := NRF_SVD.RADIO.Disabled; -- unspecified Reserved_2_31 : HAL.UInt30 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for TEST_Register use record @@ -1247,7 +1190,7 @@ package NRF51_SVD.RADIO is -- unspecified Reserved_8_31 : HAL.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for TIFS_Register use record @@ -1265,7 +1208,7 @@ package NRF51_SVD.RADIO is -- unspecified Reserved_7_31 : HAL.UInt25; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for RSSISAMPLE_Register use record @@ -1275,8 +1218,7 @@ package NRF51_SVD.RADIO is -- Current radio state. type STATE_STATE_Field is - ( - -- Radio is in the Disabled state. + (-- Radio is in the Disabled state. Disabled, -- Radio is in the Rx Ramp Up state. Rxru, @@ -1313,7 +1255,7 @@ package NRF51_SVD.RADIO is -- unspecified Reserved_4_31 : HAL.UInt28; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for STATE_Register use record @@ -1331,7 +1273,7 @@ package NRF51_SVD.RADIO is -- unspecified Reserved_7_31 : HAL.UInt25 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for DATAWHITEIV_Register use record @@ -1342,8 +1284,7 @@ package NRF51_SVD.RADIO is -- Device address base segment. -- Device address base segment. - type DAB_Registers is array (0 .. 7) of HAL.UInt32 - with Volatile; + type DAB_Registers is array (0 .. 7) of HAL.UInt32; subtype DAP_DAP_Field is HAL.UInt16; @@ -1354,7 +1295,7 @@ package NRF51_SVD.RADIO is -- unspecified Reserved_16_31 : HAL.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for DAP_Register use record @@ -1363,13 +1304,11 @@ package NRF51_SVD.RADIO is end record; -- Device address prefix. - type DAP_Registers is array (0 .. 7) of DAP_Register - with Volatile; + type DAP_Registers is array (0 .. 7) of DAP_Register; -- Enable or disable device address matching using device address 0. type DACNF_ENA0_Field is - ( - -- Disabled. + (-- Disabled. Disabled, -- Enabled. Enabled) @@ -1435,7 +1374,7 @@ package NRF51_SVD.RADIO is -- unspecified Reserved_16_31 : HAL.UInt16 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for DACNF_Register use record @@ -1448,8 +1387,7 @@ package NRF51_SVD.RADIO is -- Enable or disable override of default trim values. type OVERRIDE4_ENABLE_Field is - ( - -- Override trim values disabled. + (-- Override trim values disabled. Disabled, -- Override trim values enabled. Enabled) @@ -1465,9 +1403,9 @@ package NRF51_SVD.RADIO is -- unspecified Reserved_28_30 : HAL.UInt3 := 16#0#; -- Enable or disable override of default trim values. - ENABLE : OVERRIDE4_ENABLE_Field := NRF51_SVD.RADIO.Disabled; + ENABLE : OVERRIDE4_ENABLE_Field := NRF_SVD.RADIO.Disabled; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for OVERRIDE4_Register use record @@ -1478,8 +1416,7 @@ package NRF51_SVD.RADIO is -- Peripheral power control. type POWER_POWER_Field is - ( - -- Module power disabled. + (-- Module power disabled. Disabled, -- Module power enabled. Enabled) @@ -1491,11 +1428,11 @@ package NRF51_SVD.RADIO is -- Peripheral power control. type POWER_Register is record -- Peripheral power control. - POWER : POWER_POWER_Field := NRF51_SVD.RADIO.Disabled; + POWER : POWER_POWER_Field := NRF_SVD.RADIO.Disabled; -- unspecified Reserved_1_31 : HAL.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for POWER_Register use record @@ -1683,6 +1620,6 @@ package NRF51_SVD.RADIO is -- The radio. RADIO_Periph : aliased RADIO_Peripheral - with Import, Address => System'To_Address (16#40001000#); + with Import, Address => RADIO_Base; -end NRF51_SVD.RADIO; +end NRF_SVD.RADIO; diff --git a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-rng.ads b/arch/ARM/Nordic/svd/nrf51/nrf_svd-rng.ads similarity index 89% rename from arch/ARM/Nordic/svd/nrf51/nrf51_svd-rng.ads rename to arch/ARM/Nordic/svd/nrf51/nrf_svd-rng.ads index c82ac0431..331f15206 100644 --- a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-rng.ads +++ b/arch/ARM/Nordic/svd/nrf51/nrf_svd-rng.ads @@ -36,7 +36,7 @@ pragma Style_Checks (Off); with HAL; with System; -package NRF51_SVD.RNG is +package NRF_SVD.RNG is pragma Preelaborate; --------------- @@ -45,8 +45,7 @@ package NRF51_SVD.RNG is -- Shortcut between VALRDY event and STOP task. type SHORTS_VALRDY_STOP_Field is - ( - -- Shortcut disabled. + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) @@ -58,11 +57,11 @@ package NRF51_SVD.RNG is -- Shortcuts for the RNG. type SHORTS_Register is record -- Shortcut between VALRDY event and STOP task. - VALRDY_STOP : SHORTS_VALRDY_STOP_Field := NRF51_SVD.RNG.Disabled; + VALRDY_STOP : SHORTS_VALRDY_STOP_Field := NRF_SVD.RNG.Disabled; -- unspecified Reserved_1_31 : HAL.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for SHORTS_Register use record @@ -72,8 +71,7 @@ package NRF51_SVD.RNG is -- Enable interrupt on VALRDY event. type INTENSET_VALRDY_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -84,8 +82,7 @@ package NRF51_SVD.RNG is -- Enable interrupt on VALRDY event. type INTENSET_VALRDY_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Valrdy_Field_Reset, -- Enable interrupt on write. Set) @@ -101,7 +98,7 @@ package NRF51_SVD.RNG is -- unspecified Reserved_1_31 : HAL.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENSET_Register use record @@ -111,8 +108,7 @@ package NRF51_SVD.RNG is -- Disable interrupt on VALRDY event. type INTENCLR_VALRDY_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -123,8 +119,7 @@ package NRF51_SVD.RNG is -- Disable interrupt on VALRDY event. type INTENCLR_VALRDY_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Valrdy_Field_Reset, -- Disable interrupt on write. Clear) @@ -140,7 +135,7 @@ package NRF51_SVD.RNG is -- unspecified Reserved_1_31 : HAL.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENCLR_Register use record @@ -150,8 +145,7 @@ package NRF51_SVD.RNG is -- Digital error correction enable. type CONFIG_DERCEN_Field is - ( - -- Digital error correction disabled. + (-- Digital error correction disabled. Disabled, -- Digital error correction enabled. Enabled) @@ -163,11 +157,11 @@ package NRF51_SVD.RNG is -- Configuration register. type CONFIG_Register is record -- Digital error correction enable. - DERCEN : CONFIG_DERCEN_Field := NRF51_SVD.RNG.Disabled; + DERCEN : CONFIG_DERCEN_Field := NRF_SVD.RNG.Disabled; -- unspecified Reserved_1_31 : HAL.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for CONFIG_Register use record @@ -184,7 +178,7 @@ package NRF51_SVD.RNG is -- unspecified Reserved_8_31 : HAL.UInt24; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for VALUE_Register use record @@ -194,8 +188,7 @@ package NRF51_SVD.RNG is -- Peripheral power control. type POWER_POWER_Field is - ( - -- Module power disabled. + (-- Module power disabled. Disabled, -- Module power enabled. Enabled) @@ -207,11 +200,11 @@ package NRF51_SVD.RNG is -- Peripheral power control. type POWER_Register is record -- Peripheral power control. - POWER : POWER_POWER_Field := NRF51_SVD.RNG.Disabled; + POWER : POWER_POWER_Field := NRF_SVD.RNG.Disabled; -- unspecified Reserved_1_31 : HAL.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for POWER_Register use record @@ -260,6 +253,6 @@ package NRF51_SVD.RNG is -- Random Number Generator. RNG_Periph : aliased RNG_Peripheral - with Import, Address => System'To_Address (16#4000D000#); + with Import, Address => RNG_Base; -end NRF51_SVD.RNG; +end NRF_SVD.RNG; diff --git a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-rtc.ads b/arch/ARM/Nordic/svd/nrf51/nrf_svd-rtc.ads similarity index 91% rename from arch/ARM/Nordic/svd/nrf51/nrf51_svd-rtc.ads rename to arch/ARM/Nordic/svd/nrf51/nrf_svd-rtc.ads index ec6c73564..41e3e0864 100644 --- a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-rtc.ads +++ b/arch/ARM/Nordic/svd/nrf51/nrf_svd-rtc.ads @@ -36,7 +36,7 @@ pragma Style_Checks (Off); with HAL; with System; -package NRF51_SVD.RTC is +package NRF_SVD.RTC is pragma Preelaborate; --------------- @@ -46,13 +46,11 @@ package NRF51_SVD.RTC is -- Compare event on CC[n] match. -- Compare event on CC[n] match. - type EVENTS_COMPARE_Registers is array (0 .. 3) of HAL.UInt32 - with Volatile; + type EVENTS_COMPARE_Registers is array (0 .. 3) of HAL.UInt32; -- Enable interrupt on TICK event. type INTENSET_TICK_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -63,8 +61,7 @@ package NRF51_SVD.RTC is -- Enable interrupt on TICK event. type INTENSET_TICK_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Tick_Field_Reset, -- Enable interrupt on write. Set) @@ -75,8 +72,7 @@ package NRF51_SVD.RTC is -- Enable interrupt on OVRFLW event. type INTENSET_OVRFLW_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -87,8 +83,7 @@ package NRF51_SVD.RTC is -- Enable interrupt on OVRFLW event. type INTENSET_OVRFLW_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Ovrflw_Field_Reset, -- Enable interrupt on write. Set) @@ -99,8 +94,7 @@ package NRF51_SVD.RTC is -- Enable interrupt on COMPARE[0] event. type INTENSET_COMPARE0_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -111,8 +105,7 @@ package NRF51_SVD.RTC is -- Enable interrupt on COMPARE[0] event. type INTENSET_COMPARE0_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Compare0_Field_Reset, -- Enable interrupt on write. Set) @@ -160,7 +153,7 @@ package NRF51_SVD.RTC is -- unspecified Reserved_20_31 : HAL.UInt12 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENSET_Register use record @@ -173,8 +166,7 @@ package NRF51_SVD.RTC is -- Disable interrupt on TICK event. type INTENCLR_TICK_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -185,8 +177,7 @@ package NRF51_SVD.RTC is -- Disable interrupt on TICK event. type INTENCLR_TICK_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Tick_Field_Reset, -- Disable interrupt on write. Clear) @@ -197,8 +188,7 @@ package NRF51_SVD.RTC is -- Disable interrupt on OVRFLW event. type INTENCLR_OVRFLW_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -209,8 +199,7 @@ package NRF51_SVD.RTC is -- Disable interrupt on OVRFLW event. type INTENCLR_OVRFLW_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Ovrflw_Field_Reset, -- Disable interrupt on write. Clear) @@ -221,8 +210,7 @@ package NRF51_SVD.RTC is -- Disable interrupt on COMPARE[0] event. type INTENCLR_COMPARE0_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -233,8 +221,7 @@ package NRF51_SVD.RTC is -- Disable interrupt on COMPARE[0] event. type INTENCLR_COMPARE0_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Compare0_Field_Reset, -- Disable interrupt on write. Clear) @@ -282,7 +269,7 @@ package NRF51_SVD.RTC is -- unspecified Reserved_20_31 : HAL.UInt12 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENCLR_Register use record @@ -295,8 +282,7 @@ package NRF51_SVD.RTC is -- TICK event enable. type EVTEN_TICK_Field is - ( - -- Event disabled. + (-- Event disabled. Disabled, -- Event enabled. Enabled) @@ -307,8 +293,7 @@ package NRF51_SVD.RTC is -- OVRFLW event enable. type EVTEN_OVRFLW_Field is - ( - -- Event disabled. + (-- Event disabled. Disabled, -- Event enabled. Enabled) @@ -319,8 +304,7 @@ package NRF51_SVD.RTC is -- COMPARE[0] event enable. type EVTEN_COMPARE0_Field is - ( - -- Event disabled. + (-- Event disabled. Disabled, -- Event enabled. Enabled) @@ -356,9 +340,9 @@ package NRF51_SVD.RTC is -- Configures event enable routing to PPI for each RTC event. type EVTEN_Register is record -- TICK event enable. - TICK : EVTEN_TICK_Field := NRF51_SVD.RTC.Disabled; + TICK : EVTEN_TICK_Field := NRF_SVD.RTC.Disabled; -- OVRFLW event enable. - OVRFLW : EVTEN_OVRFLW_Field := NRF51_SVD.RTC.Disabled; + OVRFLW : EVTEN_OVRFLW_Field := NRF_SVD.RTC.Disabled; -- unspecified Reserved_2_15 : HAL.UInt14 := 16#0#; -- COMPARE[0] event enable. @@ -367,7 +351,7 @@ package NRF51_SVD.RTC is -- unspecified Reserved_20_31 : HAL.UInt12 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for EVTEN_Register use record @@ -380,8 +364,7 @@ package NRF51_SVD.RTC is -- Enable routing to PPI of TICK event. type EVTENSET_TICK_Field is - ( - -- Event disabled. + (-- Event disabled. Disabled, -- Event enabled. Enabled) @@ -392,8 +375,7 @@ package NRF51_SVD.RTC is -- Enable routing to PPI of TICK event. type EVTENSET_TICK_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Evtenset_Tick_Field_Reset, -- Enable event on write. Set) @@ -404,8 +386,7 @@ package NRF51_SVD.RTC is -- Enable routing to PPI of OVRFLW event. type EVTENSET_OVRFLW_Field is - ( - -- Event disabled. + (-- Event disabled. Disabled, -- Event enabled. Enabled) @@ -416,8 +397,7 @@ package NRF51_SVD.RTC is -- Enable routing to PPI of OVRFLW event. type EVTENSET_OVRFLW_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Evtenset_Ovrflw_Field_Reset, -- Enable event on write. Set) @@ -428,8 +408,7 @@ package NRF51_SVD.RTC is -- Enable routing to PPI of COMPARE[0] event. type EVTENSET_COMPARE0_Field is - ( - -- Event disabled. + (-- Event disabled. Disabled, -- Event enabled. Enabled) @@ -440,8 +419,7 @@ package NRF51_SVD.RTC is -- Enable routing to PPI of COMPARE[0] event. type EVTENSET_COMPARE0_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Evtenset_Compare0_Field_Reset, -- Enable event on write. Set) @@ -490,7 +468,7 @@ package NRF51_SVD.RTC is -- unspecified Reserved_20_31 : HAL.UInt12 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for EVTENSET_Register use record @@ -503,8 +481,7 @@ package NRF51_SVD.RTC is -- Disable routing to PPI of TICK event. type EVTENCLR_TICK_Field is - ( - -- Event disabled. + (-- Event disabled. Disabled, -- Event enabled. Enabled) @@ -515,8 +492,7 @@ package NRF51_SVD.RTC is -- Disable routing to PPI of TICK event. type EVTENCLR_TICK_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Evtenclr_Tick_Field_Reset, -- Disable event on write. Clear) @@ -527,8 +503,7 @@ package NRF51_SVD.RTC is -- Disable routing to PPI of OVRFLW event. type EVTENCLR_OVRFLW_Field is - ( - -- Event disabled. + (-- Event disabled. Disabled, -- Event enabled. Enabled) @@ -539,8 +514,7 @@ package NRF51_SVD.RTC is -- Disable routing to PPI of OVRFLW event. type EVTENCLR_OVRFLW_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Evtenclr_Ovrflw_Field_Reset, -- Disable event on write. Clear) @@ -551,8 +525,7 @@ package NRF51_SVD.RTC is -- Disable routing to PPI of COMPARE[0] event. type EVTENCLR_COMPARE0_Field is - ( - -- Event disabled. + (-- Event disabled. Disabled, -- Event enabled. Enabled) @@ -563,8 +536,7 @@ package NRF51_SVD.RTC is -- Disable routing to PPI of COMPARE[0] event. type EVTENCLR_COMPARE0_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Evtenclr_Compare0_Field_Reset, -- Disable event on write. Clear) @@ -613,7 +585,7 @@ package NRF51_SVD.RTC is -- unspecified Reserved_20_31 : HAL.UInt12 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for EVTENCLR_Register use record @@ -633,7 +605,7 @@ package NRF51_SVD.RTC is -- unspecified Reserved_24_31 : HAL.UInt8; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for COUNTER_Register use record @@ -651,7 +623,7 @@ package NRF51_SVD.RTC is -- unspecified Reserved_12_31 : HAL.UInt20 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for PRESCALER_Register use record @@ -668,7 +640,7 @@ package NRF51_SVD.RTC is -- unspecified Reserved_24_31 : HAL.UInt8 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for CC_Register use record @@ -677,13 +649,11 @@ package NRF51_SVD.RTC is end record; -- Capture/compare registers. - type CC_Registers is array (0 .. 3) of CC_Register - with Volatile; + type CC_Registers is array (0 .. 3) of CC_Register; -- Peripheral power control. type POWER_POWER_Field is - ( - -- Module power disabled. + (-- Module power disabled. Disabled, -- Module power enabled. Enabled) @@ -695,11 +665,11 @@ package NRF51_SVD.RTC is -- Peripheral power control. type POWER_Register is record -- Peripheral power control. - POWER : POWER_POWER_Field := NRF51_SVD.RTC.Disabled; + POWER : POWER_POWER_Field := NRF_SVD.RTC.Disabled; -- unspecified Reserved_1_31 : HAL.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for POWER_Register use record @@ -772,10 +742,10 @@ package NRF51_SVD.RTC is -- Real time counter 0. RTC0_Periph : aliased RTC_Peripheral - with Import, Address => System'To_Address (16#4000B000#); + with Import, Address => RTC0_Base; -- Real time counter 1. RTC1_Periph : aliased RTC_Peripheral - with Import, Address => System'To_Address (16#40011000#); + with Import, Address => RTC1_Base; -end NRF51_SVD.RTC; +end NRF_SVD.RTC; diff --git a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-spi.ads b/arch/ARM/Nordic/svd/nrf51/nrf_svd-spi.ads similarity index 87% rename from arch/ARM/Nordic/svd/nrf51/nrf51_svd-spi.ads rename to arch/ARM/Nordic/svd/nrf51/nrf_svd-spi.ads index 00d99c995..49b75476c 100644 --- a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-spi.ads +++ b/arch/ARM/Nordic/svd/nrf51/nrf_svd-spi.ads @@ -36,7 +36,7 @@ pragma Style_Checks (Off); with HAL; with System; -package NRF51_SVD.SPI is +package NRF_SVD.SPI is pragma Preelaborate; --------------- @@ -45,8 +45,7 @@ package NRF51_SVD.SPI is -- Enable interrupt on READY event. type INTENSET_READY_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -57,8 +56,7 @@ package NRF51_SVD.SPI is -- Enable interrupt on READY event. type INTENSET_READY_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Ready_Field_Reset, -- Enable interrupt on write. Set) @@ -76,7 +74,7 @@ package NRF51_SVD.SPI is -- unspecified Reserved_3_31 : HAL.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENSET_Register use record @@ -87,8 +85,7 @@ package NRF51_SVD.SPI is -- Disable interrupt on READY event. type INTENCLR_READY_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -99,8 +96,7 @@ package NRF51_SVD.SPI is -- Disable interrupt on READY event. type INTENCLR_READY_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Ready_Field_Reset, -- Disable interrupt on write. Clear) @@ -118,7 +114,7 @@ package NRF51_SVD.SPI is -- unspecified Reserved_3_31 : HAL.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENCLR_Register use record @@ -129,8 +125,7 @@ package NRF51_SVD.SPI is -- Enable or disable SPI. type ENABLE_ENABLE_Field is - ( - -- Disabled SPI. + (-- Disabled SPI. Disabled, -- Enable SPI. Enabled) @@ -142,11 +137,11 @@ package NRF51_SVD.SPI is -- Enable SPI. type ENABLE_Register is record -- Enable or disable SPI. - ENABLE : ENABLE_ENABLE_Field := NRF51_SVD.SPI.Disabled; + ENABLE : ENABLE_ENABLE_Field := NRF_SVD.SPI.Disabled; -- unspecified Reserved_3_31 : HAL.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for ENABLE_Register use record @@ -164,7 +159,7 @@ package NRF51_SVD.SPI is -- unspecified Reserved_8_31 : HAL.UInt24; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for RXD_Register use record @@ -181,7 +176,7 @@ package NRF51_SVD.SPI is -- unspecified Reserved_8_31 : HAL.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for TXD_Register use record @@ -191,8 +186,7 @@ package NRF51_SVD.SPI is -- Bit order. type CONFIG_ORDER_Field is - ( - -- Most significant bit transmitted out first. + (-- Most significant bit transmitted out first. Msbfirst, -- Least significant bit transmitted out first. Lsbfirst) @@ -203,12 +197,9 @@ package NRF51_SVD.SPI is -- Serial clock (SCK) phase. type CONFIG_CPHA_Field is - ( - -- Sample on leading edge of the clock. Shift serial data on trailing - -- edge. + (-- Sample on leading edge of the clock. Shift serial data on trailing edge. Leading, - -- Sample on trailing edge of the clock. Shift serial data on leading - -- edge. + -- Sample on trailing edge of the clock. Shift serial data on leading edge. Trailing) with Size => 1; for CONFIG_CPHA_Field use @@ -217,8 +208,7 @@ package NRF51_SVD.SPI is -- Serial clock (SCK) polarity. type CONFIG_CPOL_Field is - ( - -- Active high. + (-- Active high. Activehigh, -- Active low. Activelow) @@ -230,15 +220,15 @@ package NRF51_SVD.SPI is -- Configuration register. type CONFIG_Register is record -- Bit order. - ORDER : CONFIG_ORDER_Field := NRF51_SVD.SPI.Msbfirst; + ORDER : CONFIG_ORDER_Field := NRF_SVD.SPI.Msbfirst; -- Serial clock (SCK) phase. - CPHA : CONFIG_CPHA_Field := NRF51_SVD.SPI.Leading; + CPHA : CONFIG_CPHA_Field := NRF_SVD.SPI.Leading; -- Serial clock (SCK) polarity. - CPOL : CONFIG_CPOL_Field := NRF51_SVD.SPI.Activehigh; + CPOL : CONFIG_CPOL_Field := NRF_SVD.SPI.Activehigh; -- unspecified Reserved_3_31 : HAL.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for CONFIG_Register use record @@ -250,8 +240,7 @@ package NRF51_SVD.SPI is -- Peripheral power control. type POWER_POWER_Field is - ( - -- Module power disabled. + (-- Module power disabled. Disabled, -- Module power enabled. Enabled) @@ -263,11 +252,11 @@ package NRF51_SVD.SPI is -- Peripheral power control. type POWER_Register is record -- Peripheral power control. - POWER : POWER_POWER_Field := NRF51_SVD.SPI.Disabled; + POWER : POWER_POWER_Field := NRF_SVD.SPI.Disabled; -- unspecified Reserved_1_31 : HAL.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for POWER_Register use record @@ -325,10 +314,10 @@ package NRF51_SVD.SPI is -- SPI master 0. SPI0_Periph : aliased SPI_Peripheral - with Import, Address => System'To_Address (16#40003000#); + with Import, Address => SPI0_Base; -- SPI master 1. SPI1_Periph : aliased SPI_Peripheral - with Import, Address => System'To_Address (16#40004000#); + with Import, Address => SPI1_Base; -end NRF51_SVD.SPI; +end NRF_SVD.SPI; diff --git a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-spim.ads b/arch/ARM/Nordic/svd/nrf51/nrf_svd-spim.ads similarity index 90% rename from arch/ARM/Nordic/svd/nrf51/nrf51_svd-spim.ads rename to arch/ARM/Nordic/svd/nrf51/nrf_svd-spim.ads index 00630cc46..6fe7386af 100644 --- a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-spim.ads +++ b/arch/ARM/Nordic/svd/nrf51/nrf_svd-spim.ads @@ -36,7 +36,7 @@ pragma Style_Checks (Off); with HAL; with System; -package NRF51_SVD.SPIM is +package NRF_SVD.SPIM is pragma Preelaborate; --------------- @@ -45,8 +45,7 @@ package NRF51_SVD.SPIM is -- Enable interrupt on STOPPED event. type INTENSET_STOPPED_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -57,8 +56,7 @@ package NRF51_SVD.SPIM is -- Enable interrupt on STOPPED event. type INTENSET_STOPPED_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Stopped_Field_Reset, -- Enable interrupt on write. Set) @@ -69,8 +67,7 @@ package NRF51_SVD.SPIM is -- Enable interrupt on ENDRX event. type INTENSET_ENDRX_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -81,8 +78,7 @@ package NRF51_SVD.SPIM is -- Enable interrupt on ENDRX event. type INTENSET_ENDRX_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Endrx_Field_Reset, -- Enable interrupt on write. Set) @@ -93,8 +89,7 @@ package NRF51_SVD.SPIM is -- Enable interrupt on ENDTX event. type INTENSET_ENDTX_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -105,8 +100,7 @@ package NRF51_SVD.SPIM is -- Enable interrupt on ENDTX event. type INTENSET_ENDTX_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Endtx_Field_Reset, -- Enable interrupt on write. Set) @@ -117,8 +111,7 @@ package NRF51_SVD.SPIM is -- Enable interrupt on STARTED event. type INTENSET_STARTED_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -129,8 +122,7 @@ package NRF51_SVD.SPIM is -- Enable interrupt on STARTED event. type INTENSET_STARTED_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Started_Field_Reset, -- Enable interrupt on write. Set) @@ -162,7 +154,7 @@ package NRF51_SVD.SPIM is -- unspecified Reserved_20_31 : HAL.UInt12 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENSET_Register use record @@ -179,8 +171,7 @@ package NRF51_SVD.SPIM is -- Disable interrupt on STOPPED event. type INTENCLR_STOPPED_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -191,8 +182,7 @@ package NRF51_SVD.SPIM is -- Disable interrupt on STOPPED event. type INTENCLR_STOPPED_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Stopped_Field_Reset, -- Disable interrupt on write. Clear) @@ -203,8 +193,7 @@ package NRF51_SVD.SPIM is -- Disable interrupt on ENDRX event. type INTENCLR_ENDRX_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -215,8 +204,7 @@ package NRF51_SVD.SPIM is -- Disable interrupt on ENDRX event. type INTENCLR_ENDRX_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Endrx_Field_Reset, -- Disable interrupt on write. Clear) @@ -227,8 +215,7 @@ package NRF51_SVD.SPIM is -- Disable interrupt on ENDTX event. type INTENCLR_ENDTX_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -239,8 +226,7 @@ package NRF51_SVD.SPIM is -- Disable interrupt on ENDTX event. type INTENCLR_ENDTX_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Endtx_Field_Reset, -- Disable interrupt on write. Clear) @@ -251,8 +237,7 @@ package NRF51_SVD.SPIM is -- Disable interrupt on STARTED event. type INTENCLR_STARTED_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -263,8 +248,7 @@ package NRF51_SVD.SPIM is -- Disable interrupt on STARTED event. type INTENCLR_STARTED_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Started_Field_Reset, -- Disable interrupt on write. Clear) @@ -296,7 +280,7 @@ package NRF51_SVD.SPIM is -- unspecified Reserved_20_31 : HAL.UInt12 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENCLR_Register use record @@ -313,8 +297,7 @@ package NRF51_SVD.SPIM is -- Enable or disable SPIM. type ENABLE_ENABLE_Field is - ( - -- Disabled SPIM. + (-- Disabled SPIM. Disabled, -- Enable SPIM. Enabled) @@ -326,11 +309,11 @@ package NRF51_SVD.SPIM is -- Enable SPIM. type ENABLE_Register is record -- Enable or disable SPIM. - ENABLE : ENABLE_ENABLE_Field := NRF51_SVD.SPIM.Disabled; + ENABLE : ENABLE_ENABLE_Field := NRF_SVD.SPIM.Disabled; -- unspecified Reserved_4_31 : HAL.UInt28 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for ENABLE_Register use record @@ -351,7 +334,7 @@ package NRF51_SVD.SPIM is -- Pin select for MISO. MISO : aliased HAL.UInt32; end record - with Volatile, Size => 96; + with Size => 96; for SPIM_PSEL_Cluster use record SCK at 16#0# range 0 .. 31; @@ -372,7 +355,7 @@ package NRF51_SVD.SPIM is -- unspecified Reserved_8_31 : HAL.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for MAXCNT_RXD_Register use record @@ -389,7 +372,7 @@ package NRF51_SVD.SPIM is -- unspecified Reserved_8_31 : HAL.UInt24; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for AMOUNT_RXD_Register use record @@ -406,7 +389,7 @@ package NRF51_SVD.SPIM is -- Number of bytes received in the last transaction. AMOUNT : aliased AMOUNT_RXD_Register; end record - with Volatile, Size => 96; + with Size => 96; for SPIM_RXD_Cluster use record PTR at 16#0# range 0 .. 31; @@ -427,7 +410,7 @@ package NRF51_SVD.SPIM is -- unspecified Reserved_8_31 : HAL.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for MAXCNT_TXD_Register use record @@ -444,7 +427,7 @@ package NRF51_SVD.SPIM is -- unspecified Reserved_8_31 : HAL.UInt24; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for AMOUNT_TXD_Register use record @@ -461,7 +444,7 @@ package NRF51_SVD.SPIM is -- Number of bytes sent in the last transaction. AMOUNT : aliased AMOUNT_TXD_Register; end record - with Volatile, Size => 96; + with Size => 96; for SPIM_TXD_Cluster use record PTR at 16#0# range 0 .. 31; @@ -471,8 +454,7 @@ package NRF51_SVD.SPIM is -- Bit order. type CONFIG_ORDER_Field is - ( - -- Most significant bit transmitted out first. + (-- Most significant bit transmitted out first. Msbfirst, -- Least significant bit transmitted out first. Lsbfirst) @@ -483,12 +465,9 @@ package NRF51_SVD.SPIM is -- Serial clock (SCK) phase. type CONFIG_CPHA_Field is - ( - -- Sample on leading edge of the clock. Shift serial data on trailing - -- edge. + (-- Sample on leading edge of the clock. Shift serial data on trailing edge. Leading, - -- Sample on trailing edge of the clock. Shift serial data on leading - -- edge. + -- Sample on trailing edge of the clock. Shift serial data on leading edge. Trailing) with Size => 1; for CONFIG_CPHA_Field use @@ -497,8 +476,7 @@ package NRF51_SVD.SPIM is -- Serial clock (SCK) polarity. type CONFIG_CPOL_Field is - ( - -- Active high. + (-- Active high. Activehigh, -- Active low. Activelow) @@ -510,15 +488,15 @@ package NRF51_SVD.SPIM is -- Configuration register. type CONFIG_Register is record -- Bit order. - ORDER : CONFIG_ORDER_Field := NRF51_SVD.SPIM.Msbfirst; + ORDER : CONFIG_ORDER_Field := NRF_SVD.SPIM.Msbfirst; -- Serial clock (SCK) phase. - CPHA : CONFIG_CPHA_Field := NRF51_SVD.SPIM.Leading; + CPHA : CONFIG_CPHA_Field := NRF_SVD.SPIM.Leading; -- Serial clock (SCK) polarity. - CPOL : CONFIG_CPOL_Field := NRF51_SVD.SPIM.Activehigh; + CPOL : CONFIG_CPOL_Field := NRF_SVD.SPIM.Activehigh; -- unspecified Reserved_3_31 : HAL.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for CONFIG_Register use record @@ -537,7 +515,7 @@ package NRF51_SVD.SPIM is -- unspecified Reserved_8_31 : HAL.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for ORC_Register use record @@ -547,8 +525,7 @@ package NRF51_SVD.SPIM is -- Peripheral power control. type POWER_POWER_Field is - ( - -- Module power disabled. + (-- Module power disabled. Disabled, -- Module power enabled. Enabled) @@ -560,11 +537,11 @@ package NRF51_SVD.SPIM is -- Peripheral power control. type POWER_Register is record -- Peripheral power control. - POWER : POWER_POWER_Field := NRF51_SVD.SPIM.Disabled; + POWER : POWER_POWER_Field := NRF_SVD.SPIM.Disabled; -- unspecified Reserved_1_31 : HAL.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for POWER_Register use record @@ -640,6 +617,6 @@ package NRF51_SVD.SPIM is -- SPI master with easyDMA 1. SPIM1_Periph : aliased SPIM_Peripheral - with Import, Address => System'To_Address (16#40004000#); + with Import, Address => SPIM1_Base; -end NRF51_SVD.SPIM; +end NRF_SVD.SPIM; diff --git a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-spis.ads b/arch/ARM/Nordic/svd/nrf51/nrf_svd-spis.ads similarity index 89% rename from arch/ARM/Nordic/svd/nrf51/nrf51_svd-spis.ads rename to arch/ARM/Nordic/svd/nrf51/nrf_svd-spis.ads index d19c8ddaa..b74c36710 100644 --- a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-spis.ads +++ b/arch/ARM/Nordic/svd/nrf51/nrf_svd-spis.ads @@ -36,7 +36,7 @@ pragma Style_Checks (Off); with HAL; with System; -package NRF51_SVD.SPIS is +package NRF_SVD.SPIS is pragma Preelaborate; --------------- @@ -45,8 +45,7 @@ package NRF51_SVD.SPIS is -- Shortcut between END event and the ACQUIRE task. type SHORTS_END_ACQUIRE_Field is - ( - -- Shortcut disabled. + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) @@ -60,11 +59,11 @@ package NRF51_SVD.SPIS is -- unspecified Reserved_0_1 : HAL.UInt2 := 16#0#; -- Shortcut between END event and the ACQUIRE task. - END_ACQUIRE : SHORTS_END_ACQUIRE_Field := NRF51_SVD.SPIS.Disabled; + END_ACQUIRE : SHORTS_END_ACQUIRE_Field := NRF_SVD.SPIS.Disabled; -- unspecified Reserved_3_31 : HAL.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for SHORTS_Register use record @@ -75,8 +74,7 @@ package NRF51_SVD.SPIS is -- Enable interrupt on END event. type INTENSET_END_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -87,8 +85,7 @@ package NRF51_SVD.SPIS is -- Enable interrupt on END event. type INTENSET_END_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_End_Field_Reset, -- Enable interrupt on write. Set) @@ -99,8 +96,7 @@ package NRF51_SVD.SPIS is -- Enable interrupt on ACQUIRED event. type INTENSET_ACQUIRED_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -111,8 +107,7 @@ package NRF51_SVD.SPIS is -- Enable interrupt on ACQUIRED event. type INTENSET_ACQUIRED_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Acquired_Field_Reset, -- Enable interrupt on write. Set) @@ -135,7 +130,7 @@ package NRF51_SVD.SPIS is -- unspecified Reserved_11_31 : HAL.UInt21 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENSET_Register use record @@ -148,8 +143,7 @@ package NRF51_SVD.SPIS is -- Disable interrupt on END event. type INTENCLR_END_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -160,8 +154,7 @@ package NRF51_SVD.SPIS is -- Disable interrupt on END event. type INTENCLR_END_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_End_Field_Reset, -- Disable interrupt on write. Clear) @@ -172,8 +165,7 @@ package NRF51_SVD.SPIS is -- Disable interrupt on ACQUIRED event. type INTENCLR_ACQUIRED_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -184,8 +176,7 @@ package NRF51_SVD.SPIS is -- Disable interrupt on ACQUIRED event. type INTENCLR_ACQUIRED_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Acquired_Field_Reset, -- Disable interrupt on write. Clear) @@ -208,7 +199,7 @@ package NRF51_SVD.SPIS is -- unspecified Reserved_11_31 : HAL.UInt21 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENCLR_Register use record @@ -221,15 +212,13 @@ package NRF51_SVD.SPIS is -- Semaphore status. type SEMSTAT_SEMSTAT_Field is - ( - -- Semaphore is free. + (-- Semaphore is free. Free, -- Semaphore is assigned to the CPU. Cpu, -- Semaphore is assigned to the SPIS. Spis, - -- Semaphore is assigned to the SPIS, but a handover to the CPU is - -- pending. + -- Semaphore is assigned to the SPIS, but a handover to the CPU is pending. Cpupending) with Size => 2; for SEMSTAT_SEMSTAT_Field use @@ -245,7 +234,7 @@ package NRF51_SVD.SPIS is -- unspecified Reserved_2_31 : HAL.UInt30; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for SEMSTAT_Register use record @@ -255,8 +244,7 @@ package NRF51_SVD.SPIS is -- TX buffer overread detected, and prevented. type STATUS_OVERREAD_Field is - ( - -- Error not present. + (-- Error not present. Notpresent, -- Error present. Present) @@ -267,8 +255,7 @@ package NRF51_SVD.SPIS is -- TX buffer overread detected, and prevented. type STATUS_OVERREAD_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Status_Overread_Field_Reset, -- Clear on write. Clear) @@ -279,8 +266,7 @@ package NRF51_SVD.SPIS is -- RX buffer overflow detected, and prevented. type STATUS_OVERFLOW_Field is - ( - -- Error not present. + (-- Error not present. Notpresent, -- Error present. Present) @@ -291,8 +277,7 @@ package NRF51_SVD.SPIS is -- RX buffer overflow detected, and prevented. type STATUS_OVERFLOW_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Status_Overflow_Field_Reset, -- Clear on write. Clear) @@ -310,7 +295,7 @@ package NRF51_SVD.SPIS is -- unspecified Reserved_2_31 : HAL.UInt30 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for STATUS_Register use record @@ -321,8 +306,7 @@ package NRF51_SVD.SPIS is -- Enable or disable SPIS. type ENABLE_ENABLE_Field is - ( - -- Disabled SPIS. + (-- Disabled SPIS. Disabled, -- Enable SPIS. Enabled) @@ -334,11 +318,11 @@ package NRF51_SVD.SPIS is -- Enable SPIS. type ENABLE_Register is record -- Enable or disable SPIS. - ENABLE : ENABLE_ENABLE_Field := NRF51_SVD.SPIS.Disabled; + ENABLE : ENABLE_ENABLE_Field := NRF_SVD.SPIS.Disabled; -- unspecified Reserved_3_31 : HAL.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for ENABLE_Register use record @@ -355,7 +339,7 @@ package NRF51_SVD.SPIS is -- unspecified Reserved_8_31 : HAL.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for MAXRX_Register use record @@ -372,7 +356,7 @@ package NRF51_SVD.SPIS is -- unspecified Reserved_8_31 : HAL.UInt24; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for AMOUNTRX_Register use record @@ -389,7 +373,7 @@ package NRF51_SVD.SPIS is -- unspecified Reserved_8_31 : HAL.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for MAXTX_Register use record @@ -406,7 +390,7 @@ package NRF51_SVD.SPIS is -- unspecified Reserved_8_31 : HAL.UInt24; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for AMOUNTTX_Register use record @@ -416,8 +400,7 @@ package NRF51_SVD.SPIS is -- Bit order. type CONFIG_ORDER_Field is - ( - -- Most significant bit transmitted out first. + (-- Most significant bit transmitted out first. Msbfirst, -- Least significant bit transmitted out first. Lsbfirst) @@ -428,12 +411,9 @@ package NRF51_SVD.SPIS is -- Serial clock (SCK) phase. type CONFIG_CPHA_Field is - ( - -- Sample on leading edge of the clock. Shift serial data on trailing - -- edge. + (-- Sample on leading edge of the clock. Shift serial data on trailing edge. Leading, - -- Sample on trailing edge of the clock. Shift serial data on leading - -- edge. + -- Sample on trailing edge of the clock. Shift serial data on leading edge. Trailing) with Size => 1; for CONFIG_CPHA_Field use @@ -442,8 +422,7 @@ package NRF51_SVD.SPIS is -- Serial clock (SCK) polarity. type CONFIG_CPOL_Field is - ( - -- Active high. + (-- Active high. Activehigh, -- Active low. Activelow) @@ -455,15 +434,15 @@ package NRF51_SVD.SPIS is -- Configuration register. type CONFIG_Register is record -- Bit order. - ORDER : CONFIG_ORDER_Field := NRF51_SVD.SPIS.Msbfirst; + ORDER : CONFIG_ORDER_Field := NRF_SVD.SPIS.Msbfirst; -- Serial clock (SCK) phase. - CPHA : CONFIG_CPHA_Field := NRF51_SVD.SPIS.Leading; + CPHA : CONFIG_CPHA_Field := NRF_SVD.SPIS.Leading; -- Serial clock (SCK) polarity. - CPOL : CONFIG_CPOL_Field := NRF51_SVD.SPIS.Activehigh; + CPOL : CONFIG_CPOL_Field := NRF_SVD.SPIS.Activehigh; -- unspecified Reserved_3_31 : HAL.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for CONFIG_Register use record @@ -482,7 +461,7 @@ package NRF51_SVD.SPIS is -- unspecified Reserved_8_31 : HAL.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for DEF_Register use record @@ -499,7 +478,7 @@ package NRF51_SVD.SPIS is -- unspecified Reserved_8_31 : HAL.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for ORC_Register use record @@ -509,8 +488,7 @@ package NRF51_SVD.SPIS is -- Peripheral power control. type POWER_POWER_Field is - ( - -- Module power disabled. + (-- Module power disabled. Disabled, -- Module power enabled. Enabled) @@ -522,11 +500,11 @@ package NRF51_SVD.SPIS is -- Peripheral power control. type POWER_Register is record -- Peripheral power control. - POWER : POWER_POWER_Field := NRF51_SVD.SPIS.Disabled; + POWER : POWER_POWER_Field := NRF_SVD.SPIS.Disabled; -- unspecified Reserved_1_31 : HAL.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for POWER_Register use record @@ -620,6 +598,6 @@ package NRF51_SVD.SPIS is -- SPI slave 1. SPIS1_Periph : aliased SPIS_Peripheral - with Import, Address => System'To_Address (16#40004000#); + with Import, Address => SPIS1_Base; -end NRF51_SVD.SPIS; +end NRF_SVD.SPIS; diff --git a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-temp.ads b/arch/ARM/Nordic/svd/nrf51/nrf_svd-temp.ads similarity index 91% rename from arch/ARM/Nordic/svd/nrf51/nrf51_svd-temp.ads rename to arch/ARM/Nordic/svd/nrf51/nrf_svd-temp.ads index df610dca0..ad18738f4 100644 --- a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-temp.ads +++ b/arch/ARM/Nordic/svd/nrf51/nrf_svd-temp.ads @@ -36,7 +36,7 @@ pragma Style_Checks (Off); with HAL; with System; -package NRF51_SVD.TEMP is +package NRF_SVD.TEMP is pragma Preelaborate; --------------- @@ -45,8 +45,7 @@ package NRF51_SVD.TEMP is -- Enable interrupt on DATARDY event. type INTENSET_DATARDY_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -57,8 +56,7 @@ package NRF51_SVD.TEMP is -- Enable interrupt on DATARDY event. type INTENSET_DATARDY_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Datardy_Field_Reset, -- Enable interrupt on write. Set) @@ -75,7 +73,7 @@ package NRF51_SVD.TEMP is -- unspecified Reserved_1_31 : HAL.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENSET_Register use record @@ -85,8 +83,7 @@ package NRF51_SVD.TEMP is -- Disable interrupt on DATARDY event. type INTENCLR_DATARDY_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -97,8 +94,7 @@ package NRF51_SVD.TEMP is -- Disable interrupt on DATARDY event. type INTENCLR_DATARDY_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Datardy_Field_Reset, -- Disable interrupt on write. Clear) @@ -115,7 +111,7 @@ package NRF51_SVD.TEMP is -- unspecified Reserved_1_31 : HAL.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENCLR_Register use record @@ -125,8 +121,7 @@ package NRF51_SVD.TEMP is -- Peripheral power control. type POWER_POWER_Field is - ( - -- Module power disabled. + (-- Module power disabled. Disabled, -- Module power enabled. Enabled) @@ -138,11 +133,11 @@ package NRF51_SVD.TEMP is -- Peripheral power control. type POWER_Register is record -- Peripheral power control. - POWER : POWER_POWER_Field := NRF51_SVD.TEMP.Disabled; + POWER : POWER_POWER_Field := NRF_SVD.TEMP.Disabled; -- unspecified Reserved_1_31 : HAL.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for POWER_Register use record @@ -185,6 +180,6 @@ package NRF51_SVD.TEMP is -- Temperature Sensor. TEMP_Periph : aliased TEMP_Peripheral - with Import, Address => System'To_Address (16#4000C000#); + with Import, Address => TEMP_Base; -end NRF51_SVD.TEMP; +end NRF_SVD.TEMP; diff --git a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-timer.ads b/arch/ARM/Nordic/svd/nrf51/nrf_svd-timer.ads similarity index 84% rename from arch/ARM/Nordic/svd/nrf51/nrf51_svd-timer.ads rename to arch/ARM/Nordic/svd/nrf51/nrf_svd-timer.ads index 6bcf783f8..d88bcbfe6 100644 --- a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-timer.ads +++ b/arch/ARM/Nordic/svd/nrf51/nrf_svd-timer.ads @@ -36,7 +36,7 @@ pragma Style_Checks (Off); with HAL; with System; -package NRF51_SVD.TIMER is +package NRF_SVD.TIMER is pragma Preelaborate; --------------- @@ -46,19 +46,16 @@ package NRF51_SVD.TIMER is -- Capture Timer value to CC[n] registers. -- Capture Timer value to CC[n] registers. - type TASKS_CAPTURE_Registers is array (0 .. 3) of HAL.UInt32 - with Volatile; + type TASKS_CAPTURE_Registers is array (0 .. 3) of HAL.UInt32; -- Compare event on CC[n] match. -- Compare event on CC[n] match. - type EVENTS_COMPARE_Registers is array (0 .. 3) of HAL.UInt32 - with Volatile; + type EVENTS_COMPARE_Registers is array (0 .. 3) of HAL.UInt32; -- Shortcut between CC[0] event and the CLEAR task. type SHORTS_COMPARE0_CLEAR_Field is - ( - -- Shortcut disabled. + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) @@ -69,8 +66,7 @@ package NRF51_SVD.TIMER is -- Shortcut between CC[1] event and the CLEAR task. type SHORTS_COMPARE1_CLEAR_Field is - ( - -- Shortcut disabled. + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) @@ -81,8 +77,7 @@ package NRF51_SVD.TIMER is -- Shortcut between CC[2] event and the CLEAR task. type SHORTS_COMPARE2_CLEAR_Field is - ( - -- Shortcut disabled. + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) @@ -93,8 +88,7 @@ package NRF51_SVD.TIMER is -- Shortcut between CC[3] event and the CLEAR task. type SHORTS_COMPARE3_CLEAR_Field is - ( - -- Shortcut disabled. + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) @@ -105,8 +99,7 @@ package NRF51_SVD.TIMER is -- Shortcut between CC[0] event and the STOP task. type SHORTS_COMPARE0_STOP_Field is - ( - -- Shortcut disabled. + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) @@ -117,8 +110,7 @@ package NRF51_SVD.TIMER is -- Shortcut between CC[1] event and the STOP task. type SHORTS_COMPARE1_STOP_Field is - ( - -- Shortcut disabled. + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) @@ -129,8 +121,7 @@ package NRF51_SVD.TIMER is -- Shortcut between CC[2] event and the STOP task. type SHORTS_COMPARE2_STOP_Field is - ( - -- Shortcut disabled. + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) @@ -141,8 +132,7 @@ package NRF51_SVD.TIMER is -- Shortcut between CC[3] event and the STOP task. type SHORTS_COMPARE3_STOP_Field is - ( - -- Shortcut disabled. + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) @@ -154,31 +144,27 @@ package NRF51_SVD.TIMER is -- Shortcuts for Timer. type SHORTS_Register is record -- Shortcut between CC[0] event and the CLEAR task. - COMPARE0_CLEAR : SHORTS_COMPARE0_CLEAR_Field := - NRF51_SVD.TIMER.Disabled; + COMPARE0_CLEAR : SHORTS_COMPARE0_CLEAR_Field := NRF_SVD.TIMER.Disabled; -- Shortcut between CC[1] event and the CLEAR task. - COMPARE1_CLEAR : SHORTS_COMPARE1_CLEAR_Field := - NRF51_SVD.TIMER.Disabled; + COMPARE1_CLEAR : SHORTS_COMPARE1_CLEAR_Field := NRF_SVD.TIMER.Disabled; -- Shortcut between CC[2] event and the CLEAR task. - COMPARE2_CLEAR : SHORTS_COMPARE2_CLEAR_Field := - NRF51_SVD.TIMER.Disabled; + COMPARE2_CLEAR : SHORTS_COMPARE2_CLEAR_Field := NRF_SVD.TIMER.Disabled; -- Shortcut between CC[3] event and the CLEAR task. - COMPARE3_CLEAR : SHORTS_COMPARE3_CLEAR_Field := - NRF51_SVD.TIMER.Disabled; + COMPARE3_CLEAR : SHORTS_COMPARE3_CLEAR_Field := NRF_SVD.TIMER.Disabled; -- unspecified Reserved_4_7 : HAL.UInt4 := 16#0#; -- Shortcut between CC[0] event and the STOP task. - COMPARE0_STOP : SHORTS_COMPARE0_STOP_Field := NRF51_SVD.TIMER.Disabled; + COMPARE0_STOP : SHORTS_COMPARE0_STOP_Field := NRF_SVD.TIMER.Disabled; -- Shortcut between CC[1] event and the STOP task. - COMPARE1_STOP : SHORTS_COMPARE1_STOP_Field := NRF51_SVD.TIMER.Disabled; + COMPARE1_STOP : SHORTS_COMPARE1_STOP_Field := NRF_SVD.TIMER.Disabled; -- Shortcut between CC[2] event and the STOP task. - COMPARE2_STOP : SHORTS_COMPARE2_STOP_Field := NRF51_SVD.TIMER.Disabled; + COMPARE2_STOP : SHORTS_COMPARE2_STOP_Field := NRF_SVD.TIMER.Disabled; -- Shortcut between CC[3] event and the STOP task. - COMPARE3_STOP : SHORTS_COMPARE3_STOP_Field := NRF51_SVD.TIMER.Disabled; + COMPARE3_STOP : SHORTS_COMPARE3_STOP_Field := NRF_SVD.TIMER.Disabled; -- unspecified Reserved_12_31 : HAL.UInt20 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for SHORTS_Register use record @@ -196,8 +182,7 @@ package NRF51_SVD.TIMER is -- Enable interrupt on COMPARE[0] type INTENSET_COMPARE0_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -208,8 +193,7 @@ package NRF51_SVD.TIMER is -- Enable interrupt on COMPARE[0] type INTENSET_COMPARE0_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Compare0_Field_Reset, -- Enable interrupt on write. Set) @@ -253,7 +237,7 @@ package NRF51_SVD.TIMER is -- unspecified Reserved_20_31 : HAL.UInt12 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENSET_Register use record @@ -264,8 +248,7 @@ package NRF51_SVD.TIMER is -- Disable interrupt on COMPARE[0] type INTENCLR_COMPARE0_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -276,8 +259,7 @@ package NRF51_SVD.TIMER is -- Disable interrupt on COMPARE[0] type INTENCLR_COMPARE0_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Compare0_Field_Reset, -- Disable interrupt on write. Clear) @@ -321,7 +303,7 @@ package NRF51_SVD.TIMER is -- unspecified Reserved_20_31 : HAL.UInt12 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENCLR_Register use record @@ -332,8 +314,7 @@ package NRF51_SVD.TIMER is -- Select Normal or Counter mode. type MODE_MODE_Field is - ( - -- Timer in Normal mode. + (-- Timer in Normal mode. Timer, -- Timer in Counter mode. Counter) @@ -345,11 +326,11 @@ package NRF51_SVD.TIMER is -- Timer Mode selection. type MODE_Register is record -- Select Normal or Counter mode. - MODE : MODE_MODE_Field := NRF51_SVD.TIMER.Timer; + MODE : MODE_MODE_Field := NRF_SVD.TIMER.Timer; -- unspecified Reserved_1_31 : HAL.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for MODE_Register use record @@ -360,32 +341,30 @@ package NRF51_SVD.TIMER is -- Sets timer behaviour ro be like the implementation of a timer with width -- as indicated. type BITMODE_BITMODE_Field is - ( - -- 16-bit timer behaviour. - BITMODE_BITMODE_Field_16Bit, + (-- 16-bit timer behaviour. + Val_16Bit, -- 8-bit timer behaviour. - BITMODE_BITMODE_Field_08Bit, + Val_08Bit, -- 24-bit timer behaviour. - BITMODE_BITMODE_Field_24Bit, + Val_24Bit, -- 32-bit timer behaviour. - BITMODE_BITMODE_Field_32Bit) + Val_32Bit) with Size => 2; for BITMODE_BITMODE_Field use - (BITMODE_BITMODE_Field_16Bit => 0, - BITMODE_BITMODE_Field_08Bit => 1, - BITMODE_BITMODE_Field_24Bit => 2, - BITMODE_BITMODE_Field_32Bit => 3); + (Val_16Bit => 0, + Val_08Bit => 1, + Val_24Bit => 2, + Val_32Bit => 3); -- Sets timer behaviour. type BITMODE_Register is record -- Sets timer behaviour ro be like the implementation of a timer with -- width as indicated. - BITMODE : BITMODE_BITMODE_Field := - NRF51_SVD.TIMER.BITMODE_BITMODE_Field_16Bit; + BITMODE : BITMODE_BITMODE_Field := NRF_SVD.TIMER.Val_16Bit; -- unspecified Reserved_2_31 : HAL.UInt30 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for BITMODE_Register use record @@ -403,7 +382,7 @@ package NRF51_SVD.TIMER is -- unspecified Reserved_4_31 : HAL.UInt28 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for PRESCALER_Register use record @@ -414,13 +393,11 @@ package NRF51_SVD.TIMER is -- Capture/compare registers. -- Capture/compare registers. - type CC_Registers is array (0 .. 3) of HAL.UInt32 - with Volatile; + type CC_Registers is array (0 .. 3) of HAL.UInt32; -- Peripheral power control. type POWER_POWER_Field is - ( - -- Module power disabled. + (-- Module power disabled. Disabled, -- Module power enabled. Enabled) @@ -432,11 +409,11 @@ package NRF51_SVD.TIMER is -- Peripheral power control. type POWER_Register is record -- Peripheral power control. - POWER : POWER_POWER_Field := NRF51_SVD.TIMER.Disabled; + POWER : POWER_POWER_Field := NRF_SVD.TIMER.Disabled; -- unspecified Reserved_1_31 : HAL.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for POWER_Register use record @@ -504,14 +481,14 @@ package NRF51_SVD.TIMER is -- Timer 0. TIMER0_Periph : aliased TIMER_Peripheral - with Import, Address => System'To_Address (16#40008000#); + with Import, Address => TIMER0_Base; -- Timer 1. TIMER1_Periph : aliased TIMER_Peripheral - with Import, Address => System'To_Address (16#40009000#); + with Import, Address => TIMER1_Base; -- Timer 2. TIMER2_Periph : aliased TIMER_Peripheral - with Import, Address => System'To_Address (16#4000A000#); + with Import, Address => TIMER2_Base; -end NRF51_SVD.TIMER; +end NRF_SVD.TIMER; diff --git a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-twi.ads b/arch/ARM/Nordic/svd/nrf51/nrf_svd-twi.ads similarity index 90% rename from arch/ARM/Nordic/svd/nrf51/nrf51_svd-twi.ads rename to arch/ARM/Nordic/svd/nrf51/nrf_svd-twi.ads index ed768c2d6..d1cae6a39 100644 --- a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-twi.ads +++ b/arch/ARM/Nordic/svd/nrf51/nrf_svd-twi.ads @@ -36,7 +36,7 @@ pragma Style_Checks (Off); with HAL; with System; -package NRF51_SVD.TWI is +package NRF_SVD.TWI is pragma Preelaborate; --------------- @@ -45,8 +45,7 @@ package NRF51_SVD.TWI is -- Shortcut between BB event and the SUSPEND task. type SHORTS_BB_SUSPEND_Field is - ( - -- Shortcut disabled. + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) @@ -57,8 +56,7 @@ package NRF51_SVD.TWI is -- Shortcut between BB event and the STOP task. type SHORTS_BB_STOP_Field is - ( - -- Shortcut disabled. + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) @@ -70,13 +68,13 @@ package NRF51_SVD.TWI is -- Shortcuts for TWI. type SHORTS_Register is record -- Shortcut between BB event and the SUSPEND task. - BB_SUSPEND : SHORTS_BB_SUSPEND_Field := NRF51_SVD.TWI.Disabled; + BB_SUSPEND : SHORTS_BB_SUSPEND_Field := NRF_SVD.TWI.Disabled; -- Shortcut between BB event and the STOP task. - BB_STOP : SHORTS_BB_STOP_Field := NRF51_SVD.TWI.Disabled; + BB_STOP : SHORTS_BB_STOP_Field := NRF_SVD.TWI.Disabled; -- unspecified Reserved_2_31 : HAL.UInt30 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for SHORTS_Register use record @@ -87,8 +85,7 @@ package NRF51_SVD.TWI is -- Enable interrupt on STOPPED event. type INTENSET_STOPPED_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -99,8 +96,7 @@ package NRF51_SVD.TWI is -- Enable interrupt on STOPPED event. type INTENSET_STOPPED_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Stopped_Field_Reset, -- Enable interrupt on write. Set) @@ -111,8 +107,7 @@ package NRF51_SVD.TWI is -- Enable interrupt on READY event. type INTENSET_RXDREADY_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -123,8 +118,7 @@ package NRF51_SVD.TWI is -- Enable interrupt on READY event. type INTENSET_RXDREADY_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Rxdready_Field_Reset, -- Enable interrupt on write. Set) @@ -135,8 +129,7 @@ package NRF51_SVD.TWI is -- Enable interrupt on TXDSENT event. type INTENSET_TXDSENT_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -147,8 +140,7 @@ package NRF51_SVD.TWI is -- Enable interrupt on TXDSENT event. type INTENSET_TXDSENT_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Txdsent_Field_Reset, -- Enable interrupt on write. Set) @@ -159,8 +151,7 @@ package NRF51_SVD.TWI is -- Enable interrupt on ERROR event. type INTENSET_ERROR_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -171,8 +162,7 @@ package NRF51_SVD.TWI is -- Enable interrupt on ERROR event. type INTENSET_ERROR_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Error_Field_Reset, -- Enable interrupt on write. Set) @@ -183,8 +173,7 @@ package NRF51_SVD.TWI is -- Enable interrupt on BB event. type INTENSET_BB_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -195,8 +184,7 @@ package NRF51_SVD.TWI is -- Enable interrupt on BB event. type INTENSET_BB_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Bb_Field_Reset, -- Enable interrupt on write. Set) @@ -207,8 +195,7 @@ package NRF51_SVD.TWI is -- Enable interrupt on SUSPENDED event. type INTENSET_SUSPENDED_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -219,8 +206,7 @@ package NRF51_SVD.TWI is -- Enable interrupt on SUSPENDED event. type INTENSET_SUSPENDED_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Suspended_Field_Reset, -- Enable interrupt on write. Set) @@ -260,7 +246,7 @@ package NRF51_SVD.TWI is -- unspecified Reserved_19_31 : HAL.UInt13 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENSET_Register use record @@ -280,8 +266,7 @@ package NRF51_SVD.TWI is -- Disable interrupt on STOPPED event. type INTENCLR_STOPPED_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -292,8 +277,7 @@ package NRF51_SVD.TWI is -- Disable interrupt on STOPPED event. type INTENCLR_STOPPED_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Stopped_Field_Reset, -- Disable interrupt on write. Clear) @@ -304,8 +288,7 @@ package NRF51_SVD.TWI is -- Disable interrupt on RXDREADY event. type INTENCLR_RXDREADY_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -316,8 +299,7 @@ package NRF51_SVD.TWI is -- Disable interrupt on RXDREADY event. type INTENCLR_RXDREADY_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Rxdready_Field_Reset, -- Disable interrupt on write. Clear) @@ -328,8 +310,7 @@ package NRF51_SVD.TWI is -- Disable interrupt on TXDSENT event. type INTENCLR_TXDSENT_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -340,8 +321,7 @@ package NRF51_SVD.TWI is -- Disable interrupt on TXDSENT event. type INTENCLR_TXDSENT_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Txdsent_Field_Reset, -- Disable interrupt on write. Clear) @@ -352,8 +332,7 @@ package NRF51_SVD.TWI is -- Disable interrupt on ERROR event. type INTENCLR_ERROR_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -364,8 +343,7 @@ package NRF51_SVD.TWI is -- Disable interrupt on ERROR event. type INTENCLR_ERROR_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Error_Field_Reset, -- Disable interrupt on write. Clear) @@ -376,8 +354,7 @@ package NRF51_SVD.TWI is -- Disable interrupt on BB event. type INTENCLR_BB_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -388,8 +365,7 @@ package NRF51_SVD.TWI is -- Disable interrupt on BB event. type INTENCLR_BB_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Bb_Field_Reset, -- Disable interrupt on write. Clear) @@ -400,8 +376,7 @@ package NRF51_SVD.TWI is -- Disable interrupt on SUSPENDED event. type INTENCLR_SUSPENDED_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -412,8 +387,7 @@ package NRF51_SVD.TWI is -- Disable interrupt on SUSPENDED event. type INTENCLR_SUSPENDED_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Suspended_Field_Reset, -- Disable interrupt on write. Clear) @@ -453,7 +427,7 @@ package NRF51_SVD.TWI is -- unspecified Reserved_19_31 : HAL.UInt13 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENCLR_Register use record @@ -474,8 +448,7 @@ package NRF51_SVD.TWI is -- Byte received in RXD register before read of the last received byte -- (data loss). type ERRORSRC_OVERRUN_Field is - ( - -- Error not present. + (-- Error not present. Notpresent, -- Error present. Present) @@ -487,8 +460,7 @@ package NRF51_SVD.TWI is -- Byte received in RXD register before read of the last received byte -- (data loss). type ERRORSRC_OVERRUN_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Errorsrc_Overrun_Field_Reset, -- Clear error on write. Clear) @@ -499,8 +471,7 @@ package NRF51_SVD.TWI is -- NACK received after sending the address. type ERRORSRC_ANACK_Field is - ( - -- Error not present. + (-- Error not present. Notpresent, -- Error present. Present) @@ -511,8 +482,7 @@ package NRF51_SVD.TWI is -- NACK received after sending the address. type ERRORSRC_ANACK_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Errorsrc_Anack_Field_Reset, -- Clear error on write. Clear) @@ -523,8 +493,7 @@ package NRF51_SVD.TWI is -- NACK received after sending a data byte. type ERRORSRC_DNACK_Field is - ( - -- Error not present. + (-- Error not present. Notpresent, -- Error present. Present) @@ -535,8 +504,7 @@ package NRF51_SVD.TWI is -- NACK received after sending a data byte. type ERRORSRC_DNACK_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Errorsrc_Dnack_Field_Reset, -- Clear error on write. Clear) @@ -558,7 +526,7 @@ package NRF51_SVD.TWI is -- unspecified Reserved_3_31 : HAL.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for ERRORSRC_Register use record @@ -570,8 +538,7 @@ package NRF51_SVD.TWI is -- Enable or disable W2M type ENABLE_ENABLE_Field is - ( - -- Disabled. + (-- Disabled. Disabled, -- Enabled. Enabled) @@ -583,11 +550,11 @@ package NRF51_SVD.TWI is -- Enable two-wire master. type ENABLE_Register is record -- Enable or disable W2M - ENABLE : ENABLE_ENABLE_Field := NRF51_SVD.TWI.Disabled; + ENABLE : ENABLE_ENABLE_Field := NRF_SVD.TWI.Disabled; -- unspecified Reserved_3_31 : HAL.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for ENABLE_Register use record @@ -605,7 +572,7 @@ package NRF51_SVD.TWI is -- unspecified Reserved_8_31 : HAL.UInt24; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for RXD_Register use record @@ -622,7 +589,7 @@ package NRF51_SVD.TWI is -- unspecified Reserved_8_31 : HAL.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for TXD_Register use record @@ -639,7 +606,7 @@ package NRF51_SVD.TWI is -- unspecified Reserved_7_31 : HAL.UInt25 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for ADDRESS_Register use record @@ -649,8 +616,7 @@ package NRF51_SVD.TWI is -- Peripheral power control. type POWER_POWER_Field is - ( - -- Module power disabled. + (-- Module power disabled. Disabled, -- Module power enabled. Enabled) @@ -662,11 +628,11 @@ package NRF51_SVD.TWI is -- Peripheral power control. type POWER_Register is record -- Peripheral power control. - POWER : POWER_POWER_Field := NRF51_SVD.TWI.Disabled; + POWER : POWER_POWER_Field := NRF_SVD.TWI.Disabled; -- unspecified Reserved_1_31 : HAL.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for POWER_Register use record @@ -757,10 +723,10 @@ package NRF51_SVD.TWI is -- Two-wire interface master 0. TWI0_Periph : aliased TWI_Peripheral - with Import, Address => System'To_Address (16#40003000#); + with Import, Address => TWI0_Base; -- Two-wire interface master 1. TWI1_Periph : aliased TWI_Peripheral - with Import, Address => System'To_Address (16#40004000#); + with Import, Address => TWI1_Base; -end NRF51_SVD.TWI; +end NRF_SVD.TWI; diff --git a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-uart.ads b/arch/ARM/Nordic/svd/nrf51/nrf_svd-uart.ads similarity index 90% rename from arch/ARM/Nordic/svd/nrf51/nrf51_svd-uart.ads rename to arch/ARM/Nordic/svd/nrf51/nrf_svd-uart.ads index c6414411d..8a3129400 100644 --- a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-uart.ads +++ b/arch/ARM/Nordic/svd/nrf51/nrf_svd-uart.ads @@ -36,7 +36,7 @@ pragma Style_Checks (Off); with HAL; with System; -package NRF51_SVD.UART is +package NRF_SVD.UART is pragma Preelaborate; --------------- @@ -45,8 +45,7 @@ package NRF51_SVD.UART is -- Shortcut between CTS event and STARTRX task. type SHORTS_CTS_STARTRX_Field is - ( - -- Shortcut disabled. + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) @@ -57,8 +56,7 @@ package NRF51_SVD.UART is -- Shortcut between NCTS event and STOPRX task. type SHORTS_NCTS_STOPRX_Field is - ( - -- Shortcut disabled. + (-- Shortcut disabled. Disabled, -- Shortcut enabled. Enabled) @@ -72,13 +70,13 @@ package NRF51_SVD.UART is -- unspecified Reserved_0_2 : HAL.UInt3 := 16#0#; -- Shortcut between CTS event and STARTRX task. - CTS_STARTRX : SHORTS_CTS_STARTRX_Field := NRF51_SVD.UART.Disabled; + CTS_STARTRX : SHORTS_CTS_STARTRX_Field := NRF_SVD.UART.Disabled; -- Shortcut between NCTS event and STOPRX task. - NCTS_STOPRX : SHORTS_NCTS_STOPRX_Field := NRF51_SVD.UART.Disabled; + NCTS_STOPRX : SHORTS_NCTS_STOPRX_Field := NRF_SVD.UART.Disabled; -- unspecified Reserved_5_31 : HAL.UInt27 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for SHORTS_Register use record @@ -90,8 +88,7 @@ package NRF51_SVD.UART is -- Enable interrupt on CTS event. type INTENSET_CTS_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -102,8 +99,7 @@ package NRF51_SVD.UART is -- Enable interrupt on CTS event. type INTENSET_CTS_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Cts_Field_Reset, -- Enable interrupt on write. Set) @@ -114,8 +110,7 @@ package NRF51_SVD.UART is -- Enable interrupt on NCTS event. type INTENSET_NCTS_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -126,8 +121,7 @@ package NRF51_SVD.UART is -- Enable interrupt on NCTS event. type INTENSET_NCTS_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Ncts_Field_Reset, -- Enable interrupt on write. Set) @@ -138,8 +132,7 @@ package NRF51_SVD.UART is -- Enable interrupt on RXRDY event. type INTENSET_RXDRDY_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -150,8 +143,7 @@ package NRF51_SVD.UART is -- Enable interrupt on RXRDY event. type INTENSET_RXDRDY_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Rxdrdy_Field_Reset, -- Enable interrupt on write. Set) @@ -162,8 +154,7 @@ package NRF51_SVD.UART is -- Enable interrupt on TXRDY event. type INTENSET_TXDRDY_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -174,8 +165,7 @@ package NRF51_SVD.UART is -- Enable interrupt on TXRDY event. type INTENSET_TXDRDY_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Txdrdy_Field_Reset, -- Enable interrupt on write. Set) @@ -186,8 +176,7 @@ package NRF51_SVD.UART is -- Enable interrupt on ERROR event. type INTENSET_ERROR_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -198,8 +187,7 @@ package NRF51_SVD.UART is -- Enable interrupt on ERROR event. type INTENSET_ERROR_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Error_Field_Reset, -- Enable interrupt on write. Set) @@ -210,8 +198,7 @@ package NRF51_SVD.UART is -- Enable interrupt on RXTO event. type INTENSET_RXTO_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -222,8 +209,7 @@ package NRF51_SVD.UART is -- Enable interrupt on RXTO event. type INTENSET_RXTO_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Rxto_Field_Reset, -- Enable interrupt on write. Set) @@ -255,7 +241,7 @@ package NRF51_SVD.UART is -- unspecified Reserved_18_31 : HAL.UInt14 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENSET_Register use record @@ -273,8 +259,7 @@ package NRF51_SVD.UART is -- Disable interrupt on CTS event. type INTENCLR_CTS_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -285,8 +270,7 @@ package NRF51_SVD.UART is -- Disable interrupt on CTS event. type INTENCLR_CTS_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Cts_Field_Reset, -- Disable interrupt on write. Clear) @@ -297,8 +281,7 @@ package NRF51_SVD.UART is -- Disable interrupt on NCTS event. type INTENCLR_NCTS_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -309,8 +292,7 @@ package NRF51_SVD.UART is -- Disable interrupt on NCTS event. type INTENCLR_NCTS_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Ncts_Field_Reset, -- Disable interrupt on write. Clear) @@ -321,8 +303,7 @@ package NRF51_SVD.UART is -- Disable interrupt on RXRDY event. type INTENCLR_RXDRDY_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -333,8 +314,7 @@ package NRF51_SVD.UART is -- Disable interrupt on RXRDY event. type INTENCLR_RXDRDY_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Rxdrdy_Field_Reset, -- Disable interrupt on write. Clear) @@ -345,8 +325,7 @@ package NRF51_SVD.UART is -- Disable interrupt on TXRDY event. type INTENCLR_TXDRDY_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -357,8 +336,7 @@ package NRF51_SVD.UART is -- Disable interrupt on TXRDY event. type INTENCLR_TXDRDY_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Txdrdy_Field_Reset, -- Disable interrupt on write. Clear) @@ -369,8 +347,7 @@ package NRF51_SVD.UART is -- Disable interrupt on ERROR event. type INTENCLR_ERROR_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -381,8 +358,7 @@ package NRF51_SVD.UART is -- Disable interrupt on ERROR event. type INTENCLR_ERROR_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Error_Field_Reset, -- Disable interrupt on write. Clear) @@ -393,8 +369,7 @@ package NRF51_SVD.UART is -- Disable interrupt on RXTO event. type INTENCLR_RXTO_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -405,8 +380,7 @@ package NRF51_SVD.UART is -- Disable interrupt on RXTO event. type INTENCLR_RXTO_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Rxto_Field_Reset, -- Disable interrupt on write. Clear) @@ -438,7 +412,7 @@ package NRF51_SVD.UART is -- unspecified Reserved_18_31 : HAL.UInt14 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENCLR_Register use record @@ -457,8 +431,7 @@ package NRF51_SVD.UART is -- A start bit is received while the previous data still lies in RXD. (Data -- loss). type ERRORSRC_OVERRUN_Field is - ( - -- Error not present. + (-- Error not present. Notpresent, -- Error present. Present) @@ -470,8 +443,7 @@ package NRF51_SVD.UART is -- A start bit is received while the previous data still lies in RXD. (Data -- loss). type ERRORSRC_OVERRUN_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Errorsrc_Overrun_Field_Reset, -- Clear error on write. Clear) @@ -483,8 +455,7 @@ package NRF51_SVD.UART is -- A character with bad parity is received. Only checked if HW parity -- control is enabled. type ERRORSRC_PARITY_Field is - ( - -- Error not present. + (-- Error not present. Notpresent, -- Error present. Present) @@ -496,8 +467,7 @@ package NRF51_SVD.UART is -- A character with bad parity is received. Only checked if HW parity -- control is enabled. type ERRORSRC_PARITY_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Errorsrc_Parity_Field_Reset, -- Clear error on write. Clear) @@ -509,8 +479,7 @@ package NRF51_SVD.UART is -- A valid stop bit is not detected on the serial data input after all bits -- in a character have been received. type ERRORSRC_FRAMING_Field is - ( - -- Error not present. + (-- Error not present. Notpresent, -- Error present. Present) @@ -522,8 +491,7 @@ package NRF51_SVD.UART is -- A valid stop bit is not detected on the serial data input after all bits -- in a character have been received. type ERRORSRC_FRAMING_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Errorsrc_Framing_Field_Reset, -- Clear error on write. Clear) @@ -534,8 +502,7 @@ package NRF51_SVD.UART is -- The serial data input is '0' for longer than the length of a data frame. type ERRORSRC_BREAK_Field is - ( - -- Error not present. + (-- Error not present. Notpresent, -- Error present. Present) @@ -546,8 +513,7 @@ package NRF51_SVD.UART is -- The serial data input is '0' for longer than the length of a data frame. type ERRORSRC_BREAK_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Errorsrc_Break_Field_Reset, -- Clear error on write. Clear) @@ -575,7 +541,7 @@ package NRF51_SVD.UART is -- unspecified Reserved_4_31 : HAL.UInt28 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for ERRORSRC_Register use record @@ -588,8 +554,7 @@ package NRF51_SVD.UART is -- Enable or disable UART and acquire IOs. type ENABLE_ENABLE_Field is - ( - -- UART disabled. + (-- UART disabled. Disabled, -- UART enabled. Enabled) @@ -601,11 +566,11 @@ package NRF51_SVD.UART is -- Enable UART and acquire IOs. type ENABLE_Register is record -- Enable or disable UART and acquire IOs. - ENABLE : ENABLE_ENABLE_Field := NRF51_SVD.UART.Disabled; + ENABLE : ENABLE_ENABLE_Field := NRF_SVD.UART.Disabled; -- unspecified Reserved_3_31 : HAL.UInt29 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for ENABLE_Register use record @@ -625,7 +590,7 @@ package NRF51_SVD.UART is -- unspecified Reserved_8_31 : HAL.UInt24; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for RXD_Register use record @@ -642,7 +607,7 @@ package NRF51_SVD.UART is -- unspecified Reserved_8_31 : HAL.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for TXD_Register use record @@ -652,8 +617,7 @@ package NRF51_SVD.UART is -- Hardware flow control. type CONFIG_HWFC_Field is - ( - -- Hardware flow control disabled. + (-- Hardware flow control disabled. Disabled, -- Hardware flow control enabled. Enabled) @@ -664,8 +628,7 @@ package NRF51_SVD.UART is -- Include parity bit. type CONFIG_PARITY_Field is - ( - -- Parity bit excluded. + (-- Parity bit excluded. Excluded, -- Parity bit included. Included) @@ -677,13 +640,13 @@ package NRF51_SVD.UART is -- Configuration of parity and hardware flow control register. type CONFIG_Register is record -- Hardware flow control. - HWFC : CONFIG_HWFC_Field := NRF51_SVD.UART.Disabled; + HWFC : CONFIG_HWFC_Field := NRF_SVD.UART.Disabled; -- Include parity bit. - PARITY : CONFIG_PARITY_Field := NRF51_SVD.UART.Excluded; + PARITY : CONFIG_PARITY_Field := NRF_SVD.UART.Excluded; -- unspecified Reserved_4_31 : HAL.UInt28 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for CONFIG_Register use record @@ -694,8 +657,7 @@ package NRF51_SVD.UART is -- Peripheral power control. type POWER_POWER_Field is - ( - -- Module power disabled. + (-- Module power disabled. Disabled, -- Module power enabled. Enabled) @@ -707,11 +669,11 @@ package NRF51_SVD.UART is -- Peripheral power control. type POWER_Register is record -- Peripheral power control. - POWER : POWER_POWER_Field := NRF51_SVD.UART.Disabled; + POWER : POWER_POWER_Field := NRF_SVD.UART.Disabled; -- unspecified Reserved_1_31 : HAL.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for POWER_Register use record @@ -810,6 +772,6 @@ package NRF51_SVD.UART is -- Universal Asynchronous Receiver/Transmitter. UART0_Periph : aliased UART_Peripheral - with Import, Address => System'To_Address (16#40002000#); + with Import, Address => UART0_Base; -end NRF51_SVD.UART; +end NRF_SVD.UART; diff --git a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-uicr.ads b/arch/ARM/Nordic/svd/nrf51/nrf_svd-uicr.ads similarity index 85% rename from arch/ARM/Nordic/svd/nrf51/nrf51_svd-uicr.ads rename to arch/ARM/Nordic/svd/nrf51/nrf_svd-uicr.ads index 2a22f6954..a8393f1e2 100644 --- a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-uicr.ads +++ b/arch/ARM/Nordic/svd/nrf51/nrf_svd-uicr.ads @@ -36,7 +36,7 @@ pragma Style_Checks (Off); with HAL; with System; -package NRF51_SVD.UICR is +package NRF_SVD.UICR is pragma Preelaborate; --------------- @@ -46,8 +46,7 @@ package NRF51_SVD.UICR is -- Readback protect region 0. Will be ignored if pre-programmed factory -- code is present on the chip. type RBPCONF_PR0_Field is - ( - -- Enabled. + (-- Enabled. Enabled, -- Disabled. Disabled) @@ -58,8 +57,7 @@ package NRF51_SVD.UICR is -- Readback protect all code in the device. type RBPCONF_PALL_Field is - ( - -- Enabled. + (-- Enabled. Enabled, -- Disabled. Disabled) @@ -72,13 +70,13 @@ package NRF51_SVD.UICR is type RBPCONF_Register is record -- Readback protect region 0. Will be ignored if pre-programmed factory -- code is present on the chip. - PR0 : RBPCONF_PR0_Field := NRF51_SVD.UICR.Disabled; + PR0 : RBPCONF_PR0_Field := NRF_SVD.UICR.Disabled; -- Readback protect all code in the device. - PALL : RBPCONF_PALL_Field := NRF51_SVD.UICR.Disabled; + PALL : RBPCONF_PALL_Field := NRF_SVD.UICR.Disabled; -- unspecified Reserved_16_31 : HAL.UInt16 := 16#FFFF#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for RBPCONF_Register use record @@ -89,25 +87,23 @@ package NRF51_SVD.UICR is -- Reset value for CLOCK XTALFREQ register. type XTALFREQ_XTALFREQ_Field is - ( - -- 32MHz Xtal is used. - XTALFREQ_XTALFREQ_Field_32Mhz, + (-- 32MHz Xtal is used. + Val_32Mhz, -- 16MHz Xtal is used. - XTALFREQ_XTALFREQ_Field_16Mhz) + Val_16Mhz) with Size => 8; for XTALFREQ_XTALFREQ_Field use - (XTALFREQ_XTALFREQ_Field_32Mhz => 0, - XTALFREQ_XTALFREQ_Field_16Mhz => 255); + (Val_32Mhz => 0, + Val_16Mhz => 255); -- Reset value for CLOCK XTALFREQ register. type XTALFREQ_Register is record -- Reset value for CLOCK XTALFREQ register. - XTALFREQ : XTALFREQ_XTALFREQ_Field := - NRF51_SVD.UICR.XTALFREQ_XTALFREQ_Field_16Mhz; + XTALFREQ : XTALFREQ_XTALFREQ_Field := NRF_SVD.UICR.Val_16Mhz; -- unspecified Reserved_8_31 : HAL.UInt24 := 16#FFFFFF#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for XTALFREQ_Register use record @@ -125,7 +121,7 @@ package NRF51_SVD.UICR is -- unspecified Reserved_16_31 : HAL.UInt16; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for FWID_Register use record @@ -136,28 +132,24 @@ package NRF51_SVD.UICR is -- Reserved for Nordic firmware design. -- Reserved for Nordic firmware design. - type NRFFW_Registers is array (0 .. 14) of HAL.UInt32 - with Volatile; + type NRFFW_Registers is array (0 .. 14) of HAL.UInt32; -- Reserved for Nordic hardware design. -- Reserved for Nordic hardware design. - type NRFHW_Registers is array (0 .. 11) of HAL.UInt32 - with Volatile; + type NRFHW_Registers is array (0 .. 11) of HAL.UInt32; -- Reserved for customer. -- Reserved for customer. - type CUSTOMER_Registers is array (0 .. 31) of HAL.UInt32 - with Volatile; + type CUSTOMER_Registers is array (0 .. 31) of HAL.UInt32; ----------------- -- Peripherals -- ----------------- type UICR_Disc is - ( - Mode_1, + (Mode_1, Mode_2); -- User Information Configuration. @@ -200,6 +192,6 @@ package NRF51_SVD.UICR is -- User Information Configuration. UICR_Periph : aliased UICR_Peripheral - with Import, Address => System'To_Address (16#10001000#); + with Import, Address => UICR_Base; -end NRF51_SVD.UICR; +end NRF_SVD.UICR; diff --git a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-wdt.ads b/arch/ARM/Nordic/svd/nrf51/nrf_svd-wdt.ads similarity index 85% rename from arch/ARM/Nordic/svd/nrf51/nrf51_svd-wdt.ads rename to arch/ARM/Nordic/svd/nrf51/nrf_svd-wdt.ads index 46f441d61..e63f6a76e 100644 --- a/arch/ARM/Nordic/svd/nrf51/nrf51_svd-wdt.ads +++ b/arch/ARM/Nordic/svd/nrf51/nrf_svd-wdt.ads @@ -36,7 +36,7 @@ pragma Style_Checks (Off); with HAL; with System; -package NRF51_SVD.WDT is +package NRF_SVD.WDT is pragma Preelaborate; --------------- @@ -45,8 +45,7 @@ package NRF51_SVD.WDT is -- Enable interrupt on TIMEOUT event. type INTENSET_TIMEOUT_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -57,8 +56,7 @@ package NRF51_SVD.WDT is -- Enable interrupt on TIMEOUT event. type INTENSET_TIMEOUT_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenset_Timeout_Field_Reset, -- Enable interrupt on write. Set) @@ -75,7 +73,7 @@ package NRF51_SVD.WDT is -- unspecified Reserved_1_31 : HAL.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENSET_Register use record @@ -85,8 +83,7 @@ package NRF51_SVD.WDT is -- Disable interrupt on TIMEOUT event. type INTENCLR_TIMEOUT_Field is - ( - -- Interrupt disabled. + (-- Interrupt disabled. Disabled, -- Interrupt enabled. Enabled) @@ -97,8 +94,7 @@ package NRF51_SVD.WDT is -- Disable interrupt on TIMEOUT event. type INTENCLR_TIMEOUT_Field_1 is - ( - -- Reset value for the field + (-- Reset value for the field Intenclr_Timeout_Field_Reset, -- Disable interrupt on write. Clear) @@ -115,7 +111,7 @@ package NRF51_SVD.WDT is -- unspecified Reserved_1_31 : HAL.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for INTENCLR_Register use record @@ -125,8 +121,7 @@ package NRF51_SVD.WDT is -- Watchdog running status. type RUNSTATUS_RUNSTATUS_Field is - ( - -- Watchdog timer is not running. + (-- Watchdog timer is not running. Notrunning, -- Watchdog timer is running. Running) @@ -142,7 +137,7 @@ package NRF51_SVD.WDT is -- unspecified Reserved_1_31 : HAL.UInt31; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for RUNSTATUS_Register use record @@ -152,8 +147,7 @@ package NRF51_SVD.WDT is -- Request status for RR[0]. type REQSTATUS_RR0_Field is - ( - -- RR[0] register is not enabled or has already requested reload. + (-- RR[0] register is not enabled or has already requested reload. Disabledorrequested, -- RR[0] register is enabled and has not jet requested. Enabledandunrequested) @@ -164,8 +158,7 @@ package NRF51_SVD.WDT is -- Request status for RR[1]. type REQSTATUS_RR1_Field is - ( - -- RR[1] register is not enabled or has already requested reload. + (-- RR[1] register is not enabled or has already requested reload. Disabledorrequested, -- RR[1] register is enabled and has not jet requested. Enabledandunrequested) @@ -176,8 +169,7 @@ package NRF51_SVD.WDT is -- Request status for RR[2]. type REQSTATUS_RR2_Field is - ( - -- RR[2] register is not enabled or has already requested reload. + (-- RR[2] register is not enabled or has already requested reload. Disabledorrequested, -- RR[2] register is enabled and has not jet requested. Enabledandunrequested) @@ -188,8 +180,7 @@ package NRF51_SVD.WDT is -- Request status for RR[3]. type REQSTATUS_RR3_Field is - ( - -- RR[3] register is not enabled or has already requested reload. + (-- RR[3] register is not enabled or has already requested reload. Disabledorrequested, -- RR[3] register is enabled and has not jet requested. Enabledandunrequested) @@ -200,8 +191,7 @@ package NRF51_SVD.WDT is -- Request status for RR[4]. type REQSTATUS_RR4_Field is - ( - -- RR[4] register is not enabled or has already requested reload. + (-- RR[4] register is not enabled or has already requested reload. Disabledorrequested, -- RR[4] register is enabled and has not jet requested. Enabledandunrequested) @@ -212,8 +202,7 @@ package NRF51_SVD.WDT is -- Request status for RR[5]. type REQSTATUS_RR5_Field is - ( - -- RR[5] register is not enabled or has already requested reload. + (-- RR[5] register is not enabled or has already requested reload. Disabledorrequested, -- RR[5] register is enabled and has not jet requested. Enabledandunrequested) @@ -224,8 +213,7 @@ package NRF51_SVD.WDT is -- Request status for RR[6]. type REQSTATUS_RR6_Field is - ( - -- RR[6] register is not enabled or has already requested reload. + (-- RR[6] register is not enabled or has already requested reload. Disabledorrequested, -- RR[6] register is enabled and has not jet requested. Enabledandunrequested) @@ -236,8 +224,7 @@ package NRF51_SVD.WDT is -- Request status for RR[7]. type REQSTATUS_RR7_Field is - ( - -- RR[7] register is not enabled or has already requested reload. + (-- RR[7] register is not enabled or has already requested reload. Disabledorrequested, -- RR[7] register is enabled and has not jet requested. Enabledandunrequested) @@ -267,7 +254,7 @@ package NRF51_SVD.WDT is -- unspecified Reserved_8_31 : HAL.UInt24; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for REQSTATUS_Register use record @@ -284,8 +271,7 @@ package NRF51_SVD.WDT is -- Enable or disable RR[0] register. type RREN_RR0_Field is - ( - -- RR[0] register is disabled. + (-- RR[0] register is disabled. Disabled, -- RR[0] register is enabled. Enabled) @@ -296,8 +282,7 @@ package NRF51_SVD.WDT is -- Enable or disable RR[1] register. type RREN_RR1_Field is - ( - -- RR[1] register is disabled. + (-- RR[1] register is disabled. Disabled, -- RR[1] register is enabled. Enabled) @@ -308,8 +293,7 @@ package NRF51_SVD.WDT is -- Enable or disable RR[2] register. type RREN_RR2_Field is - ( - -- RR[2] register is disabled. + (-- RR[2] register is disabled. Disabled, -- RR[2] register is enabled. Enabled) @@ -320,8 +304,7 @@ package NRF51_SVD.WDT is -- Enable or disable RR[3] register. type RREN_RR3_Field is - ( - -- RR[3] register is disabled. + (-- RR[3] register is disabled. Disabled, -- RR[3] register is enabled. Enabled) @@ -332,8 +315,7 @@ package NRF51_SVD.WDT is -- Enable or disable RR[4] register. type RREN_RR4_Field is - ( - -- RR[4] register is disabled. + (-- RR[4] register is disabled. Disabled, -- RR[4] register is enabled. Enabled) @@ -344,8 +326,7 @@ package NRF51_SVD.WDT is -- Enable or disable RR[5] register. type RREN_RR5_Field is - ( - -- RR[5] register is disabled. + (-- RR[5] register is disabled. Disabled, -- RR[5] register is enabled. Enabled) @@ -356,8 +337,7 @@ package NRF51_SVD.WDT is -- Enable or disable RR[6] register. type RREN_RR6_Field is - ( - -- RR[6] register is disabled. + (-- RR[6] register is disabled. Disabled, -- RR[6] register is enabled. Enabled) @@ -368,8 +348,7 @@ package NRF51_SVD.WDT is -- Enable or disable RR[7] register. type RREN_RR7_Field is - ( - -- RR[7] register is disabled. + (-- RR[7] register is disabled. Disabled, -- RR[7] register is enabled. Enabled) @@ -381,25 +360,25 @@ package NRF51_SVD.WDT is -- Reload request enable. type RREN_Register is record -- Enable or disable RR[0] register. - RR0 : RREN_RR0_Field := NRF51_SVD.WDT.Enabled; + RR0 : RREN_RR0_Field := NRF_SVD.WDT.Enabled; -- Enable or disable RR[1] register. - RR1 : RREN_RR1_Field := NRF51_SVD.WDT.Disabled; + RR1 : RREN_RR1_Field := NRF_SVD.WDT.Disabled; -- Enable or disable RR[2] register. - RR2 : RREN_RR2_Field := NRF51_SVD.WDT.Disabled; + RR2 : RREN_RR2_Field := NRF_SVD.WDT.Disabled; -- Enable or disable RR[3] register. - RR3 : RREN_RR3_Field := NRF51_SVD.WDT.Disabled; + RR3 : RREN_RR3_Field := NRF_SVD.WDT.Disabled; -- Enable or disable RR[4] register. - RR4 : RREN_RR4_Field := NRF51_SVD.WDT.Disabled; + RR4 : RREN_RR4_Field := NRF_SVD.WDT.Disabled; -- Enable or disable RR[5] register. - RR5 : RREN_RR5_Field := NRF51_SVD.WDT.Disabled; + RR5 : RREN_RR5_Field := NRF_SVD.WDT.Disabled; -- Enable or disable RR[6] register. - RR6 : RREN_RR6_Field := NRF51_SVD.WDT.Disabled; + RR6 : RREN_RR6_Field := NRF_SVD.WDT.Disabled; -- Enable or disable RR[7] register. - RR7 : RREN_RR7_Field := NRF51_SVD.WDT.Disabled; + RR7 : RREN_RR7_Field := NRF_SVD.WDT.Disabled; -- unspecified Reserved_8_31 : HAL.UInt24 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for RREN_Register use record @@ -416,8 +395,7 @@ package NRF51_SVD.WDT is -- Configure the watchdog to pause or not while the CPU is sleeping. type CONFIG_SLEEP_Field is - ( - -- Pause watchdog while the CPU is asleep. + (-- Pause watchdog while the CPU is asleep. Pause, -- Do not pause watchdog while the CPU is asleep. Run) @@ -429,8 +407,7 @@ package NRF51_SVD.WDT is -- Configure the watchdog to pause or not while the CPU is halted by the -- debugger. type CONFIG_HALT_Field is - ( - -- Pause watchdog while the CPU is halted by the debugger. + (-- Pause watchdog while the CPU is halted by the debugger. Pause, -- Do not pause watchdog while the CPU is halted by the debugger. Run) @@ -442,16 +419,16 @@ package NRF51_SVD.WDT is -- Configuration register. type CONFIG_Register is record -- Configure the watchdog to pause or not while the CPU is sleeping. - SLEEP : CONFIG_SLEEP_Field := NRF51_SVD.WDT.Run; + SLEEP : CONFIG_SLEEP_Field := NRF_SVD.WDT.Run; -- unspecified Reserved_1_2 : HAL.UInt2 := 16#0#; -- Configure the watchdog to pause or not while the CPU is halted by the -- debugger. - HALT : CONFIG_HALT_Field := NRF51_SVD.WDT.Pause; + HALT : CONFIG_HALT_Field := NRF_SVD.WDT.Pause; -- unspecified Reserved_4_31 : HAL.UInt28 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for CONFIG_Register use record @@ -464,13 +441,11 @@ package NRF51_SVD.WDT is -- Reload requests registers. -- Reload requests registers. - type RR_Registers is array (0 .. 7) of HAL.UInt32 - with Volatile; + type RR_Registers is array (0 .. 7) of HAL.UInt32; -- Peripheral power control. type POWER_POWER_Field is - ( - -- Module power disabled. + (-- Module power disabled. Disabled, -- Module power enabled. Enabled) @@ -482,11 +457,11 @@ package NRF51_SVD.WDT is -- Peripheral power control. type POWER_Register is record -- Peripheral power control. - POWER : POWER_POWER_Field := NRF51_SVD.WDT.Disabled; + POWER : POWER_POWER_Field := NRF_SVD.WDT.Disabled; -- unspecified Reserved_1_31 : HAL.UInt31 := 16#0#; end record - with Volatile_Full_Access, Size => 32, + with Volatile_Full_Access, Object_Size => 32, Bit_Order => System.Low_Order_First; for POWER_Register use record @@ -541,6 +516,6 @@ package NRF51_SVD.WDT is -- Watchdog Timer. WDT_Periph : aliased WDT_Peripheral - with Import, Address => System'To_Address (16#40010000#); + with Import, Address => WDT_Base; -end NRF51_SVD.WDT; +end NRF_SVD.WDT; diff --git a/arch/ARM/Nordic/svd/nrf51/nrf_svd.ads b/arch/ARM/Nordic/svd/nrf51/nrf_svd.ads new file mode 100644 index 000000000..7e689a118 --- /dev/null +++ b/arch/ARM/Nordic/svd/nrf51/nrf_svd.ads @@ -0,0 +1,81 @@ +-- Copyright (c) 2013, Nordic Semiconductor ASA +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- * Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- * Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- +-- * Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from +-- this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + +-- This spec has been automatically generated from nrf51.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with System; + +-- nRF51 reference description for radio MCU with ARM 32-bit Cortex-M0 +-- Microcontroller at 16MHz CPU clock +package NRF_SVD is + pragma Preelaborate; + + -------------------- + -- Base addresses -- + -------------------- + + POWER_Base : constant System.Address := System'To_Address (16#40000000#); + CLOCK_Base : constant System.Address := System'To_Address (16#40000000#); + MPU_Base : constant System.Address := System'To_Address (16#40000000#); + AMLI_Base : constant System.Address := System'To_Address (16#40000000#); + RADIO_Base : constant System.Address := System'To_Address (16#40001000#); + UART0_Base : constant System.Address := System'To_Address (16#40002000#); + SPI0_Base : constant System.Address := System'To_Address (16#40003000#); + TWI0_Base : constant System.Address := System'To_Address (16#40003000#); + SPI1_Base : constant System.Address := System'To_Address (16#40004000#); + TWI1_Base : constant System.Address := System'To_Address (16#40004000#); + SPIS1_Base : constant System.Address := System'To_Address (16#40004000#); + SPIM1_Base : constant System.Address := System'To_Address (16#40004000#); + GPIOTE_Base : constant System.Address := System'To_Address (16#40006000#); + ADC_Base : constant System.Address := System'To_Address (16#40007000#); + TIMER0_Base : constant System.Address := System'To_Address (16#40008000#); + TIMER1_Base : constant System.Address := System'To_Address (16#40009000#); + TIMER2_Base : constant System.Address := System'To_Address (16#4000A000#); + RTC0_Base : constant System.Address := System'To_Address (16#4000B000#); + TEMP_Base : constant System.Address := System'To_Address (16#4000C000#); + RNG_Base : constant System.Address := System'To_Address (16#4000D000#); + ECB_Base : constant System.Address := System'To_Address (16#4000E000#); + AAR_Base : constant System.Address := System'To_Address (16#4000F000#); + CCM_Base : constant System.Address := System'To_Address (16#4000F000#); + WDT_Base : constant System.Address := System'To_Address (16#40010000#); + RTC1_Base : constant System.Address := System'To_Address (16#40011000#); + QDEC_Base : constant System.Address := System'To_Address (16#40012000#); + LPCOMP_Base : constant System.Address := System'To_Address (16#40013000#); + SWI_Base : constant System.Address := System'To_Address (16#40014000#); + NVMC_Base : constant System.Address := System'To_Address (16#4001E000#); + PPI_Base : constant System.Address := System'To_Address (16#4001F000#); + FICR_Base : constant System.Address := System'To_Address (16#10000000#); + UICR_Base : constant System.Address := System'To_Address (16#10001000#); + GPIO_Base : constant System.Address := System'To_Address (16#50000000#); + +end NRF_SVD; diff --git a/arch/ARM/Nordic/svd/nrf52/nrf_svd-aar.ads b/arch/ARM/Nordic/svd/nrf52/nrf_svd-aar.ads new file mode 100644 index 000000000..345d790e8 --- /dev/null +++ b/arch/ARM/Nordic/svd/nrf52/nrf_svd-aar.ads @@ -0,0 +1,349 @@ +-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- 2. Redistributions in binary form, except as embedded into a Nordic +-- Semiconductor ASA integrated circuit in a product or a software update for +-- such product, must reproduce the above copyright notice, this list of +-- conditions and the following disclaimer in the documentation and/or other +-- materials provided with the distribution. +-- +-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from this +-- software without specific prior written permission. +-- +-- 4. This software, with or without modification, must only be used with a +-- Nordic Semiconductor ASA integrated circuit. +-- +-- 5. Any software provided in binary form under this license must not be reverse +-- engineered, decompiled, modified and/or disassembled. +-- +-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +-- OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + +-- This spec has been automatically generated from nrf52.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package NRF_SVD.AAR is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Write '1' to Enable interrupt for END event + type INTENSET_END_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_END_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for END event + type INTENSET_END_Field_1 is + (-- Reset value for the field + Intenset_End_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_END_Field_1 use + (Intenset_End_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for RESOLVED event + type INTENSET_RESOLVED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_RESOLVED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for RESOLVED event + type INTENSET_RESOLVED_Field_1 is + (-- Reset value for the field + Intenset_Resolved_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_RESOLVED_Field_1 use + (Intenset_Resolved_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for NOTRESOLVED event + type INTENSET_NOTRESOLVED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_NOTRESOLVED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for NOTRESOLVED event + type INTENSET_NOTRESOLVED_Field_1 is + (-- Reset value for the field + Intenset_Notresolved_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_NOTRESOLVED_Field_1 use + (Intenset_Notresolved_Field_Reset => 0, + Set => 1); + + -- Enable interrupt + type INTENSET_Register is record + -- Write '1' to Enable interrupt for END event + END_k : INTENSET_END_Field_1 := Intenset_End_Field_Reset; + -- Write '1' to Enable interrupt for RESOLVED event + RESOLVED : INTENSET_RESOLVED_Field_1 := + Intenset_Resolved_Field_Reset; + -- Write '1' to Enable interrupt for NOTRESOLVED event + NOTRESOLVED : INTENSET_NOTRESOLVED_Field_1 := + Intenset_Notresolved_Field_Reset; + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENSET_Register use record + END_k at 0 range 0 .. 0; + RESOLVED at 0 range 1 .. 1; + NOTRESOLVED at 0 range 2 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + -- Write '1' to Disable interrupt for END event + type INTENCLR_END_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_END_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for END event + type INTENCLR_END_Field_1 is + (-- Reset value for the field + Intenclr_End_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_END_Field_1 use + (Intenclr_End_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for RESOLVED event + type INTENCLR_RESOLVED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_RESOLVED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for RESOLVED event + type INTENCLR_RESOLVED_Field_1 is + (-- Reset value for the field + Intenclr_Resolved_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_RESOLVED_Field_1 use + (Intenclr_Resolved_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for NOTRESOLVED event + type INTENCLR_NOTRESOLVED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_NOTRESOLVED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for NOTRESOLVED event + type INTENCLR_NOTRESOLVED_Field_1 is + (-- Reset value for the field + Intenclr_Notresolved_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_NOTRESOLVED_Field_1 use + (Intenclr_Notresolved_Field_Reset => 0, + Clear => 1); + + -- Disable interrupt + type INTENCLR_Register is record + -- Write '1' to Disable interrupt for END event + END_k : INTENCLR_END_Field_1 := Intenclr_End_Field_Reset; + -- Write '1' to Disable interrupt for RESOLVED event + RESOLVED : INTENCLR_RESOLVED_Field_1 := + Intenclr_Resolved_Field_Reset; + -- Write '1' to Disable interrupt for NOTRESOLVED event + NOTRESOLVED : INTENCLR_NOTRESOLVED_Field_1 := + Intenclr_Notresolved_Field_Reset; + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENCLR_Register use record + END_k at 0 range 0 .. 0; + RESOLVED at 0 range 1 .. 1; + NOTRESOLVED at 0 range 2 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + subtype STATUS_STATUS_Field is HAL.UInt4; + + -- Resolution status + type STATUS_Register is record + -- Read-only. The IRK that was used last time an address was resolved + STATUS : STATUS_STATUS_Field; + -- unspecified + Reserved_4_31 : HAL.UInt28; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for STATUS_Register use record + STATUS at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- Enable or disable AAR + type ENABLE_ENABLE_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 2; + for ENABLE_ENABLE_Field use + (Disabled => 0, + Enabled => 3); + + -- Enable AAR + type ENABLE_Register is record + -- Enable or disable AAR + ENABLE : ENABLE_ENABLE_Field := NRF_SVD.AAR.Disabled; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ENABLE_Register use record + ENABLE at 0 range 0 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + subtype NIRK_NIRK_Field is HAL.UInt5; + + -- Number of IRKs + type NIRK_Register is record + -- Number of Identity root keys available in the IRK data structure + NIRK : NIRK_NIRK_Field := 16#1#; + -- unspecified + Reserved_5_31 : HAL.UInt27 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for NIRK_Register use record + NIRK at 0 range 0 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Accelerated Address Resolver + type AAR_Peripheral is record + -- Start resolving addresses based on IRKs specified in the IRK data + -- structure + TASKS_START : aliased HAL.UInt32; + -- Stop resolving addresses + TASKS_STOP : aliased HAL.UInt32; + -- Address resolution procedure complete + EVENTS_END : aliased HAL.UInt32; + -- Address resolved + EVENTS_RESOLVED : aliased HAL.UInt32; + -- Address not resolved + EVENTS_NOTRESOLVED : aliased HAL.UInt32; + -- Enable interrupt + INTENSET : aliased INTENSET_Register; + -- Disable interrupt + INTENCLR : aliased INTENCLR_Register; + -- Resolution status + STATUS : aliased STATUS_Register; + -- Enable AAR + ENABLE : aliased ENABLE_Register; + -- Number of IRKs + NIRK : aliased NIRK_Register; + -- Pointer to IRK data structure + IRKPTR : aliased HAL.UInt32; + -- Pointer to the resolvable address + ADDRPTR : aliased HAL.UInt32; + -- Pointer to data area used for temporary storage + SCRATCHPTR : aliased HAL.UInt32; + end record + with Volatile; + + for AAR_Peripheral use record + TASKS_START at 16#0# range 0 .. 31; + TASKS_STOP at 16#8# range 0 .. 31; + EVENTS_END at 16#100# range 0 .. 31; + EVENTS_RESOLVED at 16#104# range 0 .. 31; + EVENTS_NOTRESOLVED at 16#108# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + STATUS at 16#400# range 0 .. 31; + ENABLE at 16#500# range 0 .. 31; + NIRK at 16#504# range 0 .. 31; + IRKPTR at 16#508# range 0 .. 31; + ADDRPTR at 16#510# range 0 .. 31; + SCRATCHPTR at 16#514# range 0 .. 31; + end record; + + -- Accelerated Address Resolver + AAR_Periph : aliased AAR_Peripheral + with Import, Address => AAR_Base; + +end NRF_SVD.AAR; diff --git a/arch/ARM/Nordic/svd/nrf52/nrf_svd-bprot.ads b/arch/ARM/Nordic/svd/nrf52/nrf_svd-bprot.ads new file mode 100644 index 000000000..f824aac09 --- /dev/null +++ b/arch/ARM/Nordic/svd/nrf52/nrf_svd-bprot.ads @@ -0,0 +1,268 @@ +-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- 2. Redistributions in binary form, except as embedded into a Nordic +-- Semiconductor ASA integrated circuit in a product or a software update for +-- such product, must reproduce the above copyright notice, this list of +-- conditions and the following disclaimer in the documentation and/or other +-- materials provided with the distribution. +-- +-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from this +-- software without specific prior written permission. +-- +-- 4. This software, with or without modification, must only be used with a +-- Nordic Semiconductor ASA integrated circuit. +-- +-- 5. Any software provided in binary form under this license must not be reverse +-- engineered, decompiled, modified and/or disassembled. +-- +-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +-- OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + +-- This spec has been automatically generated from nrf52.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package NRF_SVD.BPROT is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Enable protection for region 0. Write '0' has no effect. + type CONFIG0_REGION0_Field is + (-- Protection disabled + Disabled, + -- Protection enable + Enabled) + with Size => 1; + for CONFIG0_REGION0_Field use + (Disabled => 0, + Enabled => 1); + + -- CONFIG0_REGION array + type CONFIG0_REGION_Field_Array is array (0 .. 31) + of CONFIG0_REGION0_Field + with Component_Size => 1, Size => 32; + + -- Block protect configuration register 0 + type CONFIG0_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- REGION as a value + Val : HAL.UInt32; + when True => + -- REGION as an array + Arr : CONFIG0_REGION_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CONFIG0_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- Enable protection for region 32. Write '0' has no effect. + type CONFIG1_REGION32_Field is + (-- Protection disabled + Disabled, + -- Protection enabled + Enabled) + with Size => 1; + for CONFIG1_REGION32_Field use + (Disabled => 0, + Enabled => 1); + + -- CONFIG1_REGION array + type CONFIG1_REGION_Field_Array is array (32 .. 63) + of CONFIG1_REGION32_Field + with Component_Size => 1, Size => 32; + + -- Block protect configuration register 1 + type CONFIG1_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- REGION as a value + Val : HAL.UInt32; + when True => + -- REGION as an array + Arr : CONFIG1_REGION_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CONFIG1_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- Disable the protection mechanism for NVM regions while in debug + -- interface mode. This register will only disable the protection mechanism + -- if the device is in debug interface mode. + type DISABLEINDEBUG_DISABLEINDEBUG_Field is + (-- Enable in debug + Enabled, + -- Disable in debug + Disabled) + with Size => 1; + for DISABLEINDEBUG_DISABLEINDEBUG_Field use + (Enabled => 0, + Disabled => 1); + + -- Disable protection mechanism in debug interface mode + type DISABLEINDEBUG_Register is record + -- Disable the protection mechanism for NVM regions while in debug + -- interface mode. This register will only disable the protection + -- mechanism if the device is in debug interface mode. + DISABLEINDEBUG : DISABLEINDEBUG_DISABLEINDEBUG_Field := + NRF_SVD.BPROT.Disabled; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DISABLEINDEBUG_Register use record + DISABLEINDEBUG at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Enable protection for region 64. Write '0' has no effect. + type CONFIG2_REGION64_Field is + (-- Protection disabled + Disabled, + -- Protection enabled + Enabled) + with Size => 1; + for CONFIG2_REGION64_Field use + (Disabled => 0, + Enabled => 1); + + -- CONFIG2_REGION array + type CONFIG2_REGION_Field_Array is array (64 .. 95) + of CONFIG2_REGION64_Field + with Component_Size => 1, Size => 32; + + -- Block protect configuration register 2 + type CONFIG2_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- REGION as a value + Val : HAL.UInt32; + when True => + -- REGION as an array + Arr : CONFIG2_REGION_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CONFIG2_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- Enable protection for region 96. Write '0' has no effect. + type CONFIG3_REGION96_Field is + (-- Protection disabled + Disabled, + -- Protection enabled + Enabled) + with Size => 1; + for CONFIG3_REGION96_Field use + (Disabled => 0, + Enabled => 1); + + -- CONFIG3_REGION array + type CONFIG3_REGION_Field_Array is array (96 .. 127) + of CONFIG3_REGION96_Field + with Component_Size => 1, Size => 32; + + -- Block protect configuration register 3 + type CONFIG3_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- REGION as a value + Val : HAL.UInt32; + when True => + -- REGION as an array + Arr : CONFIG3_REGION_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CONFIG3_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Block Protect + type BPROT_Peripheral is record + -- Block protect configuration register 0 + CONFIG0 : aliased CONFIG0_Register; + -- Block protect configuration register 1 + CONFIG1 : aliased CONFIG1_Register; + -- Disable protection mechanism in debug interface mode + DISABLEINDEBUG : aliased DISABLEINDEBUG_Register; + -- Unspecified + UNUSED0 : aliased HAL.UInt32; + -- Block protect configuration register 2 + CONFIG2 : aliased CONFIG2_Register; + -- Block protect configuration register 3 + CONFIG3 : aliased CONFIG3_Register; + end record + with Volatile; + + for BPROT_Peripheral use record + CONFIG0 at 16#600# range 0 .. 31; + CONFIG1 at 16#604# range 0 .. 31; + DISABLEINDEBUG at 16#608# range 0 .. 31; + UNUSED0 at 16#60C# range 0 .. 31; + CONFIG2 at 16#610# range 0 .. 31; + CONFIG3 at 16#614# range 0 .. 31; + end record; + + -- Block Protect + BPROT_Periph : aliased BPROT_Peripheral + with Import, Address => BPROT_Base; + +end NRF_SVD.BPROT; diff --git a/arch/ARM/Nordic/svd/nrf52/nrf_svd-ccm.ads b/arch/ARM/Nordic/svd/nrf52/nrf_svd-ccm.ads new file mode 100644 index 000000000..6e499cb65 --- /dev/null +++ b/arch/ARM/Nordic/svd/nrf52/nrf_svd-ccm.ads @@ -0,0 +1,439 @@ +-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- 2. Redistributions in binary form, except as embedded into a Nordic +-- Semiconductor ASA integrated circuit in a product or a software update for +-- such product, must reproduce the above copyright notice, this list of +-- conditions and the following disclaimer in the documentation and/or other +-- materials provided with the distribution. +-- +-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from this +-- software without specific prior written permission. +-- +-- 4. This software, with or without modification, must only be used with a +-- Nordic Semiconductor ASA integrated circuit. +-- +-- 5. Any software provided in binary form under this license must not be reverse +-- engineered, decompiled, modified and/or disassembled. +-- +-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +-- OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + +-- This spec has been automatically generated from nrf52.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package NRF_SVD.CCM is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Shortcut between ENDKSGEN event and CRYPT task + type SHORTS_ENDKSGEN_CRYPT_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_ENDKSGEN_CRYPT_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut register + type SHORTS_Register is record + -- Shortcut between ENDKSGEN event and CRYPT task + ENDKSGEN_CRYPT : SHORTS_ENDKSGEN_CRYPT_Field := NRF_SVD.CCM.Disabled; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SHORTS_Register use record + ENDKSGEN_CRYPT at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Write '1' to Enable interrupt for ENDKSGEN event + type INTENSET_ENDKSGEN_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_ENDKSGEN_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for ENDKSGEN event + type INTENSET_ENDKSGEN_Field_1 is + (-- Reset value for the field + Intenset_Endksgen_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_ENDKSGEN_Field_1 use + (Intenset_Endksgen_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for ENDCRYPT event + type INTENSET_ENDCRYPT_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_ENDCRYPT_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for ENDCRYPT event + type INTENSET_ENDCRYPT_Field_1 is + (-- Reset value for the field + Intenset_Endcrypt_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_ENDCRYPT_Field_1 use + (Intenset_Endcrypt_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for ERROR event + type INTENSET_ERROR_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_ERROR_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for ERROR event + type INTENSET_ERROR_Field_1 is + (-- Reset value for the field + Intenset_Error_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_ERROR_Field_1 use + (Intenset_Error_Field_Reset => 0, + Set => 1); + + -- Enable interrupt + type INTENSET_Register is record + -- Write '1' to Enable interrupt for ENDKSGEN event + ENDKSGEN : INTENSET_ENDKSGEN_Field_1 := + Intenset_Endksgen_Field_Reset; + -- Write '1' to Enable interrupt for ENDCRYPT event + ENDCRYPT : INTENSET_ENDCRYPT_Field_1 := + Intenset_Endcrypt_Field_Reset; + -- Write '1' to Enable interrupt for ERROR event + ERROR : INTENSET_ERROR_Field_1 := Intenset_Error_Field_Reset; + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENSET_Register use record + ENDKSGEN at 0 range 0 .. 0; + ENDCRYPT at 0 range 1 .. 1; + ERROR at 0 range 2 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + -- Write '1' to Disable interrupt for ENDKSGEN event + type INTENCLR_ENDKSGEN_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_ENDKSGEN_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for ENDKSGEN event + type INTENCLR_ENDKSGEN_Field_1 is + (-- Reset value for the field + Intenclr_Endksgen_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_ENDKSGEN_Field_1 use + (Intenclr_Endksgen_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for ENDCRYPT event + type INTENCLR_ENDCRYPT_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_ENDCRYPT_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for ENDCRYPT event + type INTENCLR_ENDCRYPT_Field_1 is + (-- Reset value for the field + Intenclr_Endcrypt_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_ENDCRYPT_Field_1 use + (Intenclr_Endcrypt_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for ERROR event + type INTENCLR_ERROR_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_ERROR_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for ERROR event + type INTENCLR_ERROR_Field_1 is + (-- Reset value for the field + Intenclr_Error_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_ERROR_Field_1 use + (Intenclr_Error_Field_Reset => 0, + Clear => 1); + + -- Disable interrupt + type INTENCLR_Register is record + -- Write '1' to Disable interrupt for ENDKSGEN event + ENDKSGEN : INTENCLR_ENDKSGEN_Field_1 := + Intenclr_Endksgen_Field_Reset; + -- Write '1' to Disable interrupt for ENDCRYPT event + ENDCRYPT : INTENCLR_ENDCRYPT_Field_1 := + Intenclr_Endcrypt_Field_Reset; + -- Write '1' to Disable interrupt for ERROR event + ERROR : INTENCLR_ERROR_Field_1 := Intenclr_Error_Field_Reset; + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENCLR_Register use record + ENDKSGEN at 0 range 0 .. 0; + ENDCRYPT at 0 range 1 .. 1; + ERROR at 0 range 2 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + -- The result of the MIC check performed during the previous decryption + -- operation + type MICSTATUS_MICSTATUS_Field is + (-- MIC check failed + Checkfailed, + -- MIC check passed + Checkpassed) + with Size => 1; + for MICSTATUS_MICSTATUS_Field use + (Checkfailed => 0, + Checkpassed => 1); + + -- MIC check result + type MICSTATUS_Register is record + -- Read-only. The result of the MIC check performed during the previous + -- decryption operation + MICSTATUS : MICSTATUS_MICSTATUS_Field; + -- unspecified + Reserved_1_31 : HAL.UInt31; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MICSTATUS_Register use record + MICSTATUS at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Enable or disable CCM + type ENABLE_ENABLE_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 2; + for ENABLE_ENABLE_Field use + (Disabled => 0, + Enabled => 2); + + -- Enable + type ENABLE_Register is record + -- Enable or disable CCM + ENABLE : ENABLE_ENABLE_Field := NRF_SVD.CCM.Disabled; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ENABLE_Register use record + ENABLE at 0 range 0 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + -- The mode of operation to be used + type MODE_MODE_Field is + (-- AES CCM packet encryption mode + Encryption, + -- AES CCM packet decryption mode + Decryption) + with Size => 1; + for MODE_MODE_Field use + (Encryption => 0, + Decryption => 1); + + -- Data rate that the CCM shall run in synch with + type MODE_DATARATE_Field is + (-- In synch with 1 Mbit data rate + Val_1Mbit, + -- In synch with 2 Mbit data rate + Val_2Mbit) + with Size => 1; + for MODE_DATARATE_Field use + (Val_1Mbit => 0, + Val_2Mbit => 1); + + -- Packet length configuration + type MODE_LENGTH_Field is + (-- Default length. Effective length of LENGTH field is 5-bit + Default, + -- Extended length. Effective length of LENGTH field is 8-bit + Extended) + with Size => 1; + for MODE_LENGTH_Field use + (Default => 0, + Extended => 1); + + -- Operation mode + type MODE_Register is record + -- The mode of operation to be used + MODE : MODE_MODE_Field := NRF_SVD.CCM.Decryption; + -- unspecified + Reserved_1_15 : HAL.UInt15 := 16#0#; + -- Data rate that the CCM shall run in synch with + DATARATE : MODE_DATARATE_Field := NRF_SVD.CCM.Val_1Mbit; + -- unspecified + Reserved_17_23 : HAL.UInt7 := 16#0#; + -- Packet length configuration + LENGTH : MODE_LENGTH_Field := NRF_SVD.CCM.Default; + -- unspecified + Reserved_25_31 : HAL.UInt7 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MODE_Register use record + MODE at 0 range 0 .. 0; + Reserved_1_15 at 0 range 1 .. 15; + DATARATE at 0 range 16 .. 16; + Reserved_17_23 at 0 range 17 .. 23; + LENGTH at 0 range 24 .. 24; + Reserved_25_31 at 0 range 25 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- AES CCM Mode Encryption + type CCM_Peripheral is record + -- Start generation of key-stream. This operation will stop by itself + -- when completed. + TASKS_KSGEN : aliased HAL.UInt32; + -- Start encryption/decryption. This operation will stop by itself when + -- completed. + TASKS_CRYPT : aliased HAL.UInt32; + -- Stop encryption/decryption + TASKS_STOP : aliased HAL.UInt32; + -- Key-stream generation complete + EVENTS_ENDKSGEN : aliased HAL.UInt32; + -- Encrypt/decrypt complete + EVENTS_ENDCRYPT : aliased HAL.UInt32; + -- CCM error event + EVENTS_ERROR : aliased HAL.UInt32; + -- Shortcut register + SHORTS : aliased SHORTS_Register; + -- Enable interrupt + INTENSET : aliased INTENSET_Register; + -- Disable interrupt + INTENCLR : aliased INTENCLR_Register; + -- MIC check result + MICSTATUS : aliased MICSTATUS_Register; + -- Enable + ENABLE : aliased ENABLE_Register; + -- Operation mode + MODE : aliased MODE_Register; + -- Pointer to data structure holding AES key and NONCE vector + CNFPTR : aliased HAL.UInt32; + -- Input pointer + INPTR : aliased HAL.UInt32; + -- Output pointer + OUTPTR : aliased HAL.UInt32; + -- Pointer to data area used for temporary storage + SCRATCHPTR : aliased HAL.UInt32; + end record + with Volatile; + + for CCM_Peripheral use record + TASKS_KSGEN at 16#0# range 0 .. 31; + TASKS_CRYPT at 16#4# range 0 .. 31; + TASKS_STOP at 16#8# range 0 .. 31; + EVENTS_ENDKSGEN at 16#100# range 0 .. 31; + EVENTS_ENDCRYPT at 16#104# range 0 .. 31; + EVENTS_ERROR at 16#108# range 0 .. 31; + SHORTS at 16#200# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + MICSTATUS at 16#400# range 0 .. 31; + ENABLE at 16#500# range 0 .. 31; + MODE at 16#504# range 0 .. 31; + CNFPTR at 16#508# range 0 .. 31; + INPTR at 16#50C# range 0 .. 31; + OUTPTR at 16#510# range 0 .. 31; + SCRATCHPTR at 16#514# range 0 .. 31; + end record; + + -- AES CCM Mode Encryption + CCM_Periph : aliased CCM_Peripheral + with Import, Address => CCM_Base; + +end NRF_SVD.CCM; diff --git a/arch/ARM/Nordic/svd/nrf52/nrf_svd-clock.ads b/arch/ARM/Nordic/svd/nrf52/nrf_svd-clock.ads new file mode 100644 index 000000000..2a0e8877e --- /dev/null +++ b/arch/ARM/Nordic/svd/nrf52/nrf_svd-clock.ads @@ -0,0 +1,674 @@ +-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- 2. Redistributions in binary form, except as embedded into a Nordic +-- Semiconductor ASA integrated circuit in a product or a software update for +-- such product, must reproduce the above copyright notice, this list of +-- conditions and the following disclaimer in the documentation and/or other +-- materials provided with the distribution. +-- +-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from this +-- software without specific prior written permission. +-- +-- 4. This software, with or without modification, must only be used with a +-- Nordic Semiconductor ASA integrated circuit. +-- +-- 5. Any software provided in binary form under this license must not be reverse +-- engineered, decompiled, modified and/or disassembled. +-- +-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +-- OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + +-- This spec has been automatically generated from nrf52.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package NRF_SVD.CLOCK is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Write '1' to Enable interrupt for HFCLKSTARTED event + type INTENSET_HFCLKSTARTED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_HFCLKSTARTED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for HFCLKSTARTED event + type INTENSET_HFCLKSTARTED_Field_1 is + (-- Reset value for the field + Intenset_Hfclkstarted_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_HFCLKSTARTED_Field_1 use + (Intenset_Hfclkstarted_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for LFCLKSTARTED event + type INTENSET_LFCLKSTARTED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_LFCLKSTARTED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for LFCLKSTARTED event + type INTENSET_LFCLKSTARTED_Field_1 is + (-- Reset value for the field + Intenset_Lfclkstarted_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_LFCLKSTARTED_Field_1 use + (Intenset_Lfclkstarted_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for DONE event + type INTENSET_DONE_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_DONE_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for DONE event + type INTENSET_DONE_Field_1 is + (-- Reset value for the field + Intenset_Done_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_DONE_Field_1 use + (Intenset_Done_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for CTTO event + type INTENSET_CTTO_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_CTTO_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for CTTO event + type INTENSET_CTTO_Field_1 is + (-- Reset value for the field + Intenset_Ctto_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_CTTO_Field_1 use + (Intenset_Ctto_Field_Reset => 0, + Set => 1); + + -- Enable interrupt + type INTENSET_Register is record + -- Write '1' to Enable interrupt for HFCLKSTARTED event + HFCLKSTARTED : INTENSET_HFCLKSTARTED_Field_1 := + Intenset_Hfclkstarted_Field_Reset; + -- Write '1' to Enable interrupt for LFCLKSTARTED event + LFCLKSTARTED : INTENSET_LFCLKSTARTED_Field_1 := + Intenset_Lfclkstarted_Field_Reset; + -- unspecified + Reserved_2_2 : HAL.Bit := 16#0#; + -- Write '1' to Enable interrupt for DONE event + DONE : INTENSET_DONE_Field_1 := Intenset_Done_Field_Reset; + -- Write '1' to Enable interrupt for CTTO event + CTTO : INTENSET_CTTO_Field_1 := Intenset_Ctto_Field_Reset; + -- unspecified + Reserved_5_31 : HAL.UInt27 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENSET_Register use record + HFCLKSTARTED at 0 range 0 .. 0; + LFCLKSTARTED at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + DONE at 0 range 3 .. 3; + CTTO at 0 range 4 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + -- Write '1' to Disable interrupt for HFCLKSTARTED event + type INTENCLR_HFCLKSTARTED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_HFCLKSTARTED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for HFCLKSTARTED event + type INTENCLR_HFCLKSTARTED_Field_1 is + (-- Reset value for the field + Intenclr_Hfclkstarted_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_HFCLKSTARTED_Field_1 use + (Intenclr_Hfclkstarted_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for LFCLKSTARTED event + type INTENCLR_LFCLKSTARTED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_LFCLKSTARTED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for LFCLKSTARTED event + type INTENCLR_LFCLKSTARTED_Field_1 is + (-- Reset value for the field + Intenclr_Lfclkstarted_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_LFCLKSTARTED_Field_1 use + (Intenclr_Lfclkstarted_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for DONE event + type INTENCLR_DONE_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_DONE_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for DONE event + type INTENCLR_DONE_Field_1 is + (-- Reset value for the field + Intenclr_Done_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_DONE_Field_1 use + (Intenclr_Done_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for CTTO event + type INTENCLR_CTTO_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_CTTO_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for CTTO event + type INTENCLR_CTTO_Field_1 is + (-- Reset value for the field + Intenclr_Ctto_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_CTTO_Field_1 use + (Intenclr_Ctto_Field_Reset => 0, + Clear => 1); + + -- Disable interrupt + type INTENCLR_Register is record + -- Write '1' to Disable interrupt for HFCLKSTARTED event + HFCLKSTARTED : INTENCLR_HFCLKSTARTED_Field_1 := + Intenclr_Hfclkstarted_Field_Reset; + -- Write '1' to Disable interrupt for LFCLKSTARTED event + LFCLKSTARTED : INTENCLR_LFCLKSTARTED_Field_1 := + Intenclr_Lfclkstarted_Field_Reset; + -- unspecified + Reserved_2_2 : HAL.Bit := 16#0#; + -- Write '1' to Disable interrupt for DONE event + DONE : INTENCLR_DONE_Field_1 := Intenclr_Done_Field_Reset; + -- Write '1' to Disable interrupt for CTTO event + CTTO : INTENCLR_CTTO_Field_1 := Intenclr_Ctto_Field_Reset; + -- unspecified + Reserved_5_31 : HAL.UInt27 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENCLR_Register use record + HFCLKSTARTED at 0 range 0 .. 0; + LFCLKSTARTED at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + DONE at 0 range 3 .. 3; + CTTO at 0 range 4 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + -- HFCLKSTART task triggered or not + type HFCLKRUN_STATUS_Field is + (-- Task not triggered + Nottriggered, + -- Task triggered + Triggered) + with Size => 1; + for HFCLKRUN_STATUS_Field use + (Nottriggered => 0, + Triggered => 1); + + -- Status indicating that HFCLKSTART task has been triggered + type HFCLKRUN_Register is record + -- Read-only. HFCLKSTART task triggered or not + STATUS : HFCLKRUN_STATUS_Field; + -- unspecified + Reserved_1_31 : HAL.UInt31; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for HFCLKRUN_Register use record + STATUS at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Source of HFCLK + type HFCLKSTAT_SRC_Field is + (-- 64 MHz internal oscillator (HFINT) + Rc, + -- 64 MHz crystal oscillator (HFXO) + Xtal) + with Size => 1; + for HFCLKSTAT_SRC_Field use + (Rc => 0, + Xtal => 1); + + -- HFCLK state + type HFCLKSTAT_STATE_Field is + (-- HFCLK not running + Notrunning, + -- HFCLK running + Running) + with Size => 1; + for HFCLKSTAT_STATE_Field use + (Notrunning => 0, + Running => 1); + + -- HFCLK status + type HFCLKSTAT_Register is record + -- Read-only. Source of HFCLK + SRC : HFCLKSTAT_SRC_Field; + -- unspecified + Reserved_1_15 : HAL.UInt15; + -- Read-only. HFCLK state + STATE : HFCLKSTAT_STATE_Field; + -- unspecified + Reserved_17_31 : HAL.UInt15; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for HFCLKSTAT_Register use record + SRC at 0 range 0 .. 0; + Reserved_1_15 at 0 range 1 .. 15; + STATE at 0 range 16 .. 16; + Reserved_17_31 at 0 range 17 .. 31; + end record; + + -- LFCLKSTART task triggered or not + type LFCLKRUN_STATUS_Field is + (-- Task not triggered + Nottriggered, + -- Task triggered + Triggered) + with Size => 1; + for LFCLKRUN_STATUS_Field use + (Nottriggered => 0, + Triggered => 1); + + -- Status indicating that LFCLKSTART task has been triggered + type LFCLKRUN_Register is record + -- Read-only. LFCLKSTART task triggered or not + STATUS : LFCLKRUN_STATUS_Field; + -- unspecified + Reserved_1_31 : HAL.UInt31; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for LFCLKRUN_Register use record + STATUS at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Source of LFCLK + type LFCLKSTAT_SRC_Field is + (-- 32.768 kHz RC oscillator + Rc, + -- 32.768 kHz crystal oscillator + Xtal, + -- 32.768 kHz synthesized from HFCLK + Synth) + with Size => 2; + for LFCLKSTAT_SRC_Field use + (Rc => 0, + Xtal => 1, + Synth => 2); + + -- LFCLK state + type LFCLKSTAT_STATE_Field is + (-- LFCLK not running + Notrunning, + -- LFCLK running + Running) + with Size => 1; + for LFCLKSTAT_STATE_Field use + (Notrunning => 0, + Running => 1); + + -- LFCLK status + type LFCLKSTAT_Register is record + -- Read-only. Source of LFCLK + SRC : LFCLKSTAT_SRC_Field; + -- unspecified + Reserved_2_15 : HAL.UInt14; + -- Read-only. LFCLK state + STATE : LFCLKSTAT_STATE_Field; + -- unspecified + Reserved_17_31 : HAL.UInt15; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for LFCLKSTAT_Register use record + SRC at 0 range 0 .. 1; + Reserved_2_15 at 0 range 2 .. 15; + STATE at 0 range 16 .. 16; + Reserved_17_31 at 0 range 17 .. 31; + end record; + + -- Clock source + type LFCLKSRCCOPY_SRC_Field is + (-- 32.768 kHz RC oscillator + Rc, + -- 32.768 kHz crystal oscillator + Xtal, + -- 32.768 kHz synthesized from HFCLK + Synth) + with Size => 2; + for LFCLKSRCCOPY_SRC_Field use + (Rc => 0, + Xtal => 1, + Synth => 2); + + -- Copy of LFCLKSRC register, set when LFCLKSTART task was triggered + type LFCLKSRCCOPY_Register is record + -- Read-only. Clock source + SRC : LFCLKSRCCOPY_SRC_Field; + -- unspecified + Reserved_2_31 : HAL.UInt30; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for LFCLKSRCCOPY_Register use record + SRC at 0 range 0 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + -- Clock source + type LFCLKSRC_SRC_Field is + (-- 32.768 kHz RC oscillator + Rc, + -- 32.768 kHz crystal oscillator + Xtal, + -- 32.768 kHz synthesized from HFCLK + Synth) + with Size => 2; + for LFCLKSRC_SRC_Field use + (Rc => 0, + Xtal => 1, + Synth => 2); + + -- Enable or disable bypass of LFCLK crystal oscillator with external clock + -- source + type LFCLKSRC_BYPASS_Field is + (-- Disable (use with Xtal or low-swing external source) + Disabled, + -- Enable (use with rail-to-rail external source) + Enabled) + with Size => 1; + for LFCLKSRC_BYPASS_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable external source for LFCLK + type LFCLKSRC_EXTERNAL_Field is + (-- Disable external source (use with Xtal) + Disabled, + -- Enable use of external source instead of Xtal (SRC needs to be set to Xtal) + Enabled) + with Size => 1; + for LFCLKSRC_EXTERNAL_Field use + (Disabled => 0, + Enabled => 1); + + -- Clock source for the LFCLK + type LFCLKSRC_Register is record + -- Clock source + SRC : LFCLKSRC_SRC_Field := NRF_SVD.CLOCK.Rc; + -- unspecified + Reserved_2_15 : HAL.UInt14 := 16#0#; + -- Enable or disable bypass of LFCLK crystal oscillator with external + -- clock source + BYPASS : LFCLKSRC_BYPASS_Field := NRF_SVD.CLOCK.Disabled; + -- Enable or disable external source for LFCLK + EXTERNAL : LFCLKSRC_EXTERNAL_Field := NRF_SVD.CLOCK.Disabled; + -- unspecified + Reserved_18_31 : HAL.UInt14 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for LFCLKSRC_Register use record + SRC at 0 range 0 .. 1; + Reserved_2_15 at 0 range 2 .. 15; + BYPASS at 0 range 16 .. 16; + EXTERNAL at 0 range 17 .. 17; + Reserved_18_31 at 0 range 18 .. 31; + end record; + + subtype CTIV_CTIV_Field is HAL.UInt7; + + -- Calibration timer interval + type CTIV_Register is record + -- Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 + -- seconds to 31.75 seconds. + CTIV : CTIV_CTIV_Field := 16#0#; + -- unspecified + Reserved_7_31 : HAL.UInt25 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CTIV_Register use record + CTIV at 0 range 0 .. 6; + Reserved_7_31 at 0 range 7 .. 31; + end record; + + -- Speed of Trace Port clock. Note that the TRACECLK pin will output this + -- clock divided by two. + type TRACECONFIG_TRACEPORTSPEED_Field is + (-- 32 MHz Trace Port clock (TRACECLK = 16 MHz) + Val_32Mhz, + -- 16 MHz Trace Port clock (TRACECLK = 8 MHz) + Val_16Mhz, + -- 8 MHz Trace Port clock (TRACECLK = 4 MHz) + Val_8Mhz, + -- 4 MHz Trace Port clock (TRACECLK = 2 MHz) + Val_4Mhz) + with Size => 2; + for TRACECONFIG_TRACEPORTSPEED_Field use + (Val_32Mhz => 0, + Val_16Mhz => 1, + Val_8Mhz => 2, + Val_4Mhz => 3); + + -- Pin multiplexing of trace signals. + type TRACECONFIG_TRACEMUX_Field is + (-- GPIOs multiplexed onto all trace-pins + Gpio, + -- SWO multiplexed onto P0.18, GPIO multiplexed onto other trace pins + Serial, + -- TRACECLK and TRACEDATA multiplexed onto P0.20, P0.18, P0.16, P0.15 and +-- P0.14. + Parallel) + with Size => 2; + for TRACECONFIG_TRACEMUX_Field use + (Gpio => 0, + Serial => 1, + Parallel => 2); + + -- Clocking options for the Trace Port debug interface + type TRACECONFIG_Register is record + -- Speed of Trace Port clock. Note that the TRACECLK pin will output + -- this clock divided by two. + TRACEPORTSPEED : TRACECONFIG_TRACEPORTSPEED_Field := + NRF_SVD.CLOCK.Val_32Mhz; + -- unspecified + Reserved_2_15 : HAL.UInt14 := 16#0#; + -- Pin multiplexing of trace signals. + TRACEMUX : TRACECONFIG_TRACEMUX_Field := NRF_SVD.CLOCK.Gpio; + -- unspecified + Reserved_18_31 : HAL.UInt14 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRACECONFIG_Register use record + TRACEPORTSPEED at 0 range 0 .. 1; + Reserved_2_15 at 0 range 2 .. 15; + TRACEMUX at 0 range 16 .. 17; + Reserved_18_31 at 0 range 18 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Clock control + type CLOCK_Peripheral is record + -- Start HFCLK crystal oscillator + TASKS_HFCLKSTART : aliased HAL.UInt32; + -- Stop HFCLK crystal oscillator + TASKS_HFCLKSTOP : aliased HAL.UInt32; + -- Start LFCLK source + TASKS_LFCLKSTART : aliased HAL.UInt32; + -- Stop LFCLK source + TASKS_LFCLKSTOP : aliased HAL.UInt32; + -- Start calibration of LFRC oscillator + TASKS_CAL : aliased HAL.UInt32; + -- Start calibration timer + TASKS_CTSTART : aliased HAL.UInt32; + -- Stop calibration timer + TASKS_CTSTOP : aliased HAL.UInt32; + -- HFCLK oscillator started + EVENTS_HFCLKSTARTED : aliased HAL.UInt32; + -- LFCLK started + EVENTS_LFCLKSTARTED : aliased HAL.UInt32; + -- Calibration of LFCLK RC oscillator complete event + EVENTS_DONE : aliased HAL.UInt32; + -- Calibration timer timeout + EVENTS_CTTO : aliased HAL.UInt32; + -- Enable interrupt + INTENSET : aliased INTENSET_Register; + -- Disable interrupt + INTENCLR : aliased INTENCLR_Register; + -- Status indicating that HFCLKSTART task has been triggered + HFCLKRUN : aliased HFCLKRUN_Register; + -- HFCLK status + HFCLKSTAT : aliased HFCLKSTAT_Register; + -- Status indicating that LFCLKSTART task has been triggered + LFCLKRUN : aliased LFCLKRUN_Register; + -- LFCLK status + LFCLKSTAT : aliased LFCLKSTAT_Register; + -- Copy of LFCLKSRC register, set when LFCLKSTART task was triggered + LFCLKSRCCOPY : aliased LFCLKSRCCOPY_Register; + -- Clock source for the LFCLK + LFCLKSRC : aliased LFCLKSRC_Register; + -- Calibration timer interval + CTIV : aliased CTIV_Register; + -- Clocking options for the Trace Port debug interface + TRACECONFIG : aliased TRACECONFIG_Register; + end record + with Volatile; + + for CLOCK_Peripheral use record + TASKS_HFCLKSTART at 16#0# range 0 .. 31; + TASKS_HFCLKSTOP at 16#4# range 0 .. 31; + TASKS_LFCLKSTART at 16#8# range 0 .. 31; + TASKS_LFCLKSTOP at 16#C# range 0 .. 31; + TASKS_CAL at 16#10# range 0 .. 31; + TASKS_CTSTART at 16#14# range 0 .. 31; + TASKS_CTSTOP at 16#18# range 0 .. 31; + EVENTS_HFCLKSTARTED at 16#100# range 0 .. 31; + EVENTS_LFCLKSTARTED at 16#104# range 0 .. 31; + EVENTS_DONE at 16#10C# range 0 .. 31; + EVENTS_CTTO at 16#110# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + HFCLKRUN at 16#408# range 0 .. 31; + HFCLKSTAT at 16#40C# range 0 .. 31; + LFCLKRUN at 16#414# range 0 .. 31; + LFCLKSTAT at 16#418# range 0 .. 31; + LFCLKSRCCOPY at 16#41C# range 0 .. 31; + LFCLKSRC at 16#518# range 0 .. 31; + CTIV at 16#538# range 0 .. 31; + TRACECONFIG at 16#55C# range 0 .. 31; + end record; + + -- Clock control + CLOCK_Periph : aliased CLOCK_Peripheral + with Import, Address => CLOCK_Base; + +end NRF_SVD.CLOCK; diff --git a/arch/ARM/Nordic/svd/nrf52/nrf_svd-comp.ads b/arch/ARM/Nordic/svd/nrf52/nrf_svd-comp.ads new file mode 100644 index 000000000..dc0251302 --- /dev/null +++ b/arch/ARM/Nordic/svd/nrf52/nrf_svd-comp.ads @@ -0,0 +1,809 @@ +-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- 2. Redistributions in binary form, except as embedded into a Nordic +-- Semiconductor ASA integrated circuit in a product or a software update for +-- such product, must reproduce the above copyright notice, this list of +-- conditions and the following disclaimer in the documentation and/or other +-- materials provided with the distribution. +-- +-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from this +-- software without specific prior written permission. +-- +-- 4. This software, with or without modification, must only be used with a +-- Nordic Semiconductor ASA integrated circuit. +-- +-- 5. Any software provided in binary form under this license must not be reverse +-- engineered, decompiled, modified and/or disassembled. +-- +-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +-- OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + +-- This spec has been automatically generated from nrf52.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package NRF_SVD.COMP is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Shortcut between READY event and SAMPLE task + type SHORTS_READY_SAMPLE_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_READY_SAMPLE_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut between READY event and STOP task + type SHORTS_READY_STOP_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_READY_STOP_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut between DOWN event and STOP task + type SHORTS_DOWN_STOP_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_DOWN_STOP_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut between UP event and STOP task + type SHORTS_UP_STOP_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_UP_STOP_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut between CROSS event and STOP task + type SHORTS_CROSS_STOP_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_CROSS_STOP_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut register + type SHORTS_Register is record + -- Shortcut between READY event and SAMPLE task + READY_SAMPLE : SHORTS_READY_SAMPLE_Field := NRF_SVD.COMP.Disabled; + -- Shortcut between READY event and STOP task + READY_STOP : SHORTS_READY_STOP_Field := NRF_SVD.COMP.Disabled; + -- Shortcut between DOWN event and STOP task + DOWN_STOP : SHORTS_DOWN_STOP_Field := NRF_SVD.COMP.Disabled; + -- Shortcut between UP event and STOP task + UP_STOP : SHORTS_UP_STOP_Field := NRF_SVD.COMP.Disabled; + -- Shortcut between CROSS event and STOP task + CROSS_STOP : SHORTS_CROSS_STOP_Field := NRF_SVD.COMP.Disabled; + -- unspecified + Reserved_5_31 : HAL.UInt27 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SHORTS_Register use record + READY_SAMPLE at 0 range 0 .. 0; + READY_STOP at 0 range 1 .. 1; + DOWN_STOP at 0 range 2 .. 2; + UP_STOP at 0 range 3 .. 3; + CROSS_STOP at 0 range 4 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + -- Enable or disable interrupt for READY event + type INTEN_READY_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_READY_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for DOWN event + type INTEN_DOWN_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_DOWN_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for UP event + type INTEN_UP_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_UP_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for CROSS event + type INTEN_CROSS_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_CROSS_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt + type INTEN_Register is record + -- Enable or disable interrupt for READY event + READY : INTEN_READY_Field := NRF_SVD.COMP.Disabled; + -- Enable or disable interrupt for DOWN event + DOWN : INTEN_DOWN_Field := NRF_SVD.COMP.Disabled; + -- Enable or disable interrupt for UP event + UP : INTEN_UP_Field := NRF_SVD.COMP.Disabled; + -- Enable or disable interrupt for CROSS event + CROSS : INTEN_CROSS_Field := NRF_SVD.COMP.Disabled; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTEN_Register use record + READY at 0 range 0 .. 0; + DOWN at 0 range 1 .. 1; + UP at 0 range 2 .. 2; + CROSS at 0 range 3 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- Write '1' to Enable interrupt for READY event + type INTENSET_READY_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_READY_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for READY event + type INTENSET_READY_Field_1 is + (-- Reset value for the field + Intenset_Ready_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_READY_Field_1 use + (Intenset_Ready_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for DOWN event + type INTENSET_DOWN_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_DOWN_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for DOWN event + type INTENSET_DOWN_Field_1 is + (-- Reset value for the field + Intenset_Down_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_DOWN_Field_1 use + (Intenset_Down_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for UP event + type INTENSET_UP_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_UP_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for UP event + type INTENSET_UP_Field_1 is + (-- Reset value for the field + Intenset_Up_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_UP_Field_1 use + (Intenset_Up_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for CROSS event + type INTENSET_CROSS_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_CROSS_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for CROSS event + type INTENSET_CROSS_Field_1 is + (-- Reset value for the field + Intenset_Cross_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_CROSS_Field_1 use + (Intenset_Cross_Field_Reset => 0, + Set => 1); + + -- Enable interrupt + type INTENSET_Register is record + -- Write '1' to Enable interrupt for READY event + READY : INTENSET_READY_Field_1 := Intenset_Ready_Field_Reset; + -- Write '1' to Enable interrupt for DOWN event + DOWN : INTENSET_DOWN_Field_1 := Intenset_Down_Field_Reset; + -- Write '1' to Enable interrupt for UP event + UP : INTENSET_UP_Field_1 := Intenset_Up_Field_Reset; + -- Write '1' to Enable interrupt for CROSS event + CROSS : INTENSET_CROSS_Field_1 := Intenset_Cross_Field_Reset; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENSET_Register use record + READY at 0 range 0 .. 0; + DOWN at 0 range 1 .. 1; + UP at 0 range 2 .. 2; + CROSS at 0 range 3 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- Write '1' to Disable interrupt for READY event + type INTENCLR_READY_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_READY_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for READY event + type INTENCLR_READY_Field_1 is + (-- Reset value for the field + Intenclr_Ready_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_READY_Field_1 use + (Intenclr_Ready_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for DOWN event + type INTENCLR_DOWN_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_DOWN_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for DOWN event + type INTENCLR_DOWN_Field_1 is + (-- Reset value for the field + Intenclr_Down_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_DOWN_Field_1 use + (Intenclr_Down_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for UP event + type INTENCLR_UP_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_UP_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for UP event + type INTENCLR_UP_Field_1 is + (-- Reset value for the field + Intenclr_Up_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_UP_Field_1 use + (Intenclr_Up_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for CROSS event + type INTENCLR_CROSS_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_CROSS_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for CROSS event + type INTENCLR_CROSS_Field_1 is + (-- Reset value for the field + Intenclr_Cross_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_CROSS_Field_1 use + (Intenclr_Cross_Field_Reset => 0, + Clear => 1); + + -- Disable interrupt + type INTENCLR_Register is record + -- Write '1' to Disable interrupt for READY event + READY : INTENCLR_READY_Field_1 := Intenclr_Ready_Field_Reset; + -- Write '1' to Disable interrupt for DOWN event + DOWN : INTENCLR_DOWN_Field_1 := Intenclr_Down_Field_Reset; + -- Write '1' to Disable interrupt for UP event + UP : INTENCLR_UP_Field_1 := Intenclr_Up_Field_Reset; + -- Write '1' to Disable interrupt for CROSS event + CROSS : INTENCLR_CROSS_Field_1 := Intenclr_Cross_Field_Reset; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENCLR_Register use record + READY at 0 range 0 .. 0; + DOWN at 0 range 1 .. 1; + UP at 0 range 2 .. 2; + CROSS at 0 range 3 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- Result of last compare. Decision point SAMPLE task. + type RESULT_RESULT_Field is + (-- Input voltage is below the threshold (VIN+ < VIN-) + Below, + -- Input voltage is above the threshold (VIN+ > VIN-) + Above) + with Size => 1; + for RESULT_RESULT_Field use + (Below => 0, + Above => 1); + + -- Compare result + type RESULT_Register is record + -- Read-only. Result of last compare. Decision point SAMPLE task. + RESULT : RESULT_RESULT_Field; + -- unspecified + Reserved_1_31 : HAL.UInt31; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RESULT_Register use record + RESULT at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Enable or disable COMP + type ENABLE_ENABLE_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 2; + for ENABLE_ENABLE_Field use + (Disabled => 0, + Enabled => 2); + + -- COMP enable + type ENABLE_Register is record + -- Enable or disable COMP + ENABLE : ENABLE_ENABLE_Field := NRF_SVD.COMP.Disabled; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ENABLE_Register use record + ENABLE at 0 range 0 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + -- Analog pin select + type PSEL_PSEL_Field is + (-- AIN0 selected as analog input + Analoginput0, + -- AIN1 selected as analog input + Analoginput1, + -- AIN2 selected as analog input + Analoginput2, + -- AIN3 selected as analog input + Analoginput3, + -- AIN4 selected as analog input + Analoginput4, + -- AIN5 selected as analog input + Analoginput5, + -- AIN6 selected as analog input + Analoginput6, + -- AIN7 selected as analog input + Analoginput7) + with Size => 3; + for PSEL_PSEL_Field use + (Analoginput0 => 0, + Analoginput1 => 1, + Analoginput2 => 2, + Analoginput3 => 3, + Analoginput4 => 4, + Analoginput5 => 5, + Analoginput6 => 6, + Analoginput7 => 7); + + -- Pin select + type PSEL_Register is record + -- Analog pin select + PSEL : PSEL_PSEL_Field := NRF_SVD.COMP.Analoginput0; + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PSEL_Register use record + PSEL at 0 range 0 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + -- Reference select + type REFSEL_REFSEL_Field is + (-- VREF = internal 1.2 V reference (VDD >= 1.7 V) + Int1V2, + -- VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V) + Int1V8, + -- VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V) + Int2V4, + -- VREF = VDD + Vdd, + -- VREF = AREF (VDD >= VREF >= AREFMIN) + Aref) + with Size => 3; + for REFSEL_REFSEL_Field use + (Int1V2 => 0, + Int1V8 => 1, + Int2V4 => 2, + Vdd => 4, + Aref => 7); + + -- Reference source select for single-ended mode + type REFSEL_Register is record + -- Reference select + REFSEL : REFSEL_REFSEL_Field := NRF_SVD.COMP.Vdd; + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for REFSEL_Register use record + REFSEL at 0 range 0 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + -- External analog reference select + type EXTREFSEL_EXTREFSEL_Field is + (-- Use AIN0 as external analog reference + Analogreference0, + -- Use AIN1 as external analog reference + Analogreference1, + -- Use AIN2 as external analog reference + Analogreference2, + -- Use AIN3 as external analog reference + Analogreference3, + -- Use AIN4 as external analog reference + Analogreference4, + -- Use AIN5 as external analog reference + Analogreference5, + -- Use AIN6 as external analog reference + Analogreference6, + -- Use AIN7 as external analog reference + Analogreference7) + with Size => 3; + for EXTREFSEL_EXTREFSEL_Field use + (Analogreference0 => 0, + Analogreference1 => 1, + Analogreference2 => 2, + Analogreference3 => 3, + Analogreference4 => 4, + Analogreference5 => 5, + Analogreference6 => 6, + Analogreference7 => 7); + + -- External reference select + type EXTREFSEL_Register is record + -- External analog reference select + EXTREFSEL : EXTREFSEL_EXTREFSEL_Field := + NRF_SVD.COMP.Analogreference0; + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EXTREFSEL_Register use record + EXTREFSEL at 0 range 0 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + subtype TH_THDOWN_Field is HAL.UInt6; + subtype TH_THUP_Field is HAL.UInt6; + + -- Threshold configuration for hysteresis unit + type TH_Register is record + -- VDOWN = (THDOWN+1)/64*VREF + THDOWN : TH_THDOWN_Field := 16#0#; + -- unspecified + Reserved_6_7 : HAL.UInt2 := 16#0#; + -- VUP = (THUP+1)/64*VREF + THUP : TH_THUP_Field := 16#0#; + -- unspecified + Reserved_14_31 : HAL.UInt18 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TH_Register use record + THDOWN at 0 range 0 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + THUP at 0 range 8 .. 13; + Reserved_14_31 at 0 range 14 .. 31; + end record; + + -- Speed and power modes + type MODE_SP_Field is + (-- Low-power mode + Low, + -- Normal mode + Normal, + -- High-speed mode + High) + with Size => 2; + for MODE_SP_Field use + (Low => 0, + Normal => 1, + High => 2); + + -- Main operation modes + type MODE_MAIN_Field is + (-- Single-ended mode + Se, + -- Differential mode + Diff) + with Size => 1; + for MODE_MAIN_Field use + (Se => 0, + Diff => 1); + + -- Mode configuration + type MODE_Register is record + -- Speed and power modes + SP : MODE_SP_Field := NRF_SVD.COMP.Low; + -- unspecified + Reserved_2_7 : HAL.UInt6 := 16#0#; + -- Main operation modes + MAIN : MODE_MAIN_Field := NRF_SVD.COMP.Se; + -- unspecified + Reserved_9_31 : HAL.UInt23 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MODE_Register use record + SP at 0 range 0 .. 1; + Reserved_2_7 at 0 range 2 .. 7; + MAIN at 0 range 8 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + -- Comparator hysteresis + type HYST_HYST_Field is + (-- Comparator hysteresis disabled + Nohyst, + -- Comparator hysteresis enabled + Hyst50MV) + with Size => 1; + for HYST_HYST_Field use + (Nohyst => 0, + Hyst50MV => 1); + + -- Comparator hysteresis enable + type HYST_Register is record + -- Comparator hysteresis + HYST : HYST_HYST_Field := NRF_SVD.COMP.Nohyst; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for HYST_Register use record + HYST at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Comparator hysteresis + type ISOURCE_ISOURCE_Field is + (-- Current source disabled + Off, + -- Current source enabled (+/- 2.5 uA) + Ien2MA5, + -- Current source enabled (+/- 5 uA) + Ien5MA, + -- Current source enabled (+/- 10 uA) + Ien10MA) + with Size => 2; + for ISOURCE_ISOURCE_Field use + (Off => 0, + Ien2MA5 => 1, + Ien5MA => 2, + Ien10MA => 3); + + -- Current source select on analog input + type ISOURCE_Register is record + -- Comparator hysteresis + ISOURCE : ISOURCE_ISOURCE_Field := NRF_SVD.COMP.Off; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ISOURCE_Register use record + ISOURCE at 0 range 0 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Comparator + type COMP_Peripheral is record + -- Start comparator + TASKS_START : aliased HAL.UInt32; + -- Stop comparator + TASKS_STOP : aliased HAL.UInt32; + -- Sample comparator value + TASKS_SAMPLE : aliased HAL.UInt32; + -- COMP is ready and output is valid + EVENTS_READY : aliased HAL.UInt32; + -- Downward crossing + EVENTS_DOWN : aliased HAL.UInt32; + -- Upward crossing + EVENTS_UP : aliased HAL.UInt32; + -- Downward or upward crossing + EVENTS_CROSS : aliased HAL.UInt32; + -- Shortcut register + SHORTS : aliased SHORTS_Register; + -- Enable or disable interrupt + INTEN : aliased INTEN_Register; + -- Enable interrupt + INTENSET : aliased INTENSET_Register; + -- Disable interrupt + INTENCLR : aliased INTENCLR_Register; + -- Compare result + RESULT : aliased RESULT_Register; + -- COMP enable + ENABLE : aliased ENABLE_Register; + -- Pin select + PSEL : aliased PSEL_Register; + -- Reference source select for single-ended mode + REFSEL : aliased REFSEL_Register; + -- External reference select + EXTREFSEL : aliased EXTREFSEL_Register; + -- Threshold configuration for hysteresis unit + TH : aliased TH_Register; + -- Mode configuration + MODE : aliased MODE_Register; + -- Comparator hysteresis enable + HYST : aliased HYST_Register; + -- Current source select on analog input + ISOURCE : aliased ISOURCE_Register; + end record + with Volatile; + + for COMP_Peripheral use record + TASKS_START at 16#0# range 0 .. 31; + TASKS_STOP at 16#4# range 0 .. 31; + TASKS_SAMPLE at 16#8# range 0 .. 31; + EVENTS_READY at 16#100# range 0 .. 31; + EVENTS_DOWN at 16#104# range 0 .. 31; + EVENTS_UP at 16#108# range 0 .. 31; + EVENTS_CROSS at 16#10C# range 0 .. 31; + SHORTS at 16#200# range 0 .. 31; + INTEN at 16#300# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + RESULT at 16#400# range 0 .. 31; + ENABLE at 16#500# range 0 .. 31; + PSEL at 16#504# range 0 .. 31; + REFSEL at 16#508# range 0 .. 31; + EXTREFSEL at 16#50C# range 0 .. 31; + TH at 16#530# range 0 .. 31; + MODE at 16#534# range 0 .. 31; + HYST at 16#538# range 0 .. 31; + ISOURCE at 16#53C# range 0 .. 31; + end record; + + -- Comparator + COMP_Periph : aliased COMP_Peripheral + with Import, Address => COMP_Base; + +end NRF_SVD.COMP; diff --git a/arch/ARM/Nordic/svd/nrf52/nrf_svd-ecb.ads b/arch/ARM/Nordic/svd/nrf52/nrf_svd-ecb.ads new file mode 100644 index 000000000..de2cdc07c --- /dev/null +++ b/arch/ARM/Nordic/svd/nrf52/nrf_svd-ecb.ads @@ -0,0 +1,219 @@ +-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- 2. Redistributions in binary form, except as embedded into a Nordic +-- Semiconductor ASA integrated circuit in a product or a software update for +-- such product, must reproduce the above copyright notice, this list of +-- conditions and the following disclaimer in the documentation and/or other +-- materials provided with the distribution. +-- +-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from this +-- software without specific prior written permission. +-- +-- 4. This software, with or without modification, must only be used with a +-- Nordic Semiconductor ASA integrated circuit. +-- +-- 5. Any software provided in binary form under this license must not be reverse +-- engineered, decompiled, modified and/or disassembled. +-- +-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +-- OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + +-- This spec has been automatically generated from nrf52.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package NRF_SVD.ECB is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Write '1' to Enable interrupt for ENDECB event + type INTENSET_ENDECB_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_ENDECB_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for ENDECB event + type INTENSET_ENDECB_Field_1 is + (-- Reset value for the field + Intenset_Endecb_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_ENDECB_Field_1 use + (Intenset_Endecb_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for ERRORECB event + type INTENSET_ERRORECB_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_ERRORECB_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for ERRORECB event + type INTENSET_ERRORECB_Field_1 is + (-- Reset value for the field + Intenset_Errorecb_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_ERRORECB_Field_1 use + (Intenset_Errorecb_Field_Reset => 0, + Set => 1); + + -- Enable interrupt + type INTENSET_Register is record + -- Write '1' to Enable interrupt for ENDECB event + ENDECB : INTENSET_ENDECB_Field_1 := Intenset_Endecb_Field_Reset; + -- Write '1' to Enable interrupt for ERRORECB event + ERRORECB : INTENSET_ERRORECB_Field_1 := + Intenset_Errorecb_Field_Reset; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENSET_Register use record + ENDECB at 0 range 0 .. 0; + ERRORECB at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + -- Write '1' to Disable interrupt for ENDECB event + type INTENCLR_ENDECB_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_ENDECB_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for ENDECB event + type INTENCLR_ENDECB_Field_1 is + (-- Reset value for the field + Intenclr_Endecb_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_ENDECB_Field_1 use + (Intenclr_Endecb_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for ERRORECB event + type INTENCLR_ERRORECB_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_ERRORECB_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for ERRORECB event + type INTENCLR_ERRORECB_Field_1 is + (-- Reset value for the field + Intenclr_Errorecb_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_ERRORECB_Field_1 use + (Intenclr_Errorecb_Field_Reset => 0, + Clear => 1); + + -- Disable interrupt + type INTENCLR_Register is record + -- Write '1' to Disable interrupt for ENDECB event + ENDECB : INTENCLR_ENDECB_Field_1 := Intenclr_Endecb_Field_Reset; + -- Write '1' to Disable interrupt for ERRORECB event + ERRORECB : INTENCLR_ERRORECB_Field_1 := + Intenclr_Errorecb_Field_Reset; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENCLR_Register use record + ENDECB at 0 range 0 .. 0; + ERRORECB at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- AES ECB Mode Encryption + type ECB_Peripheral is record + -- Start ECB block encrypt + TASKS_STARTECB : aliased HAL.UInt32; + -- Abort a possible executing ECB operation + TASKS_STOPECB : aliased HAL.UInt32; + -- ECB block encrypt complete + EVENTS_ENDECB : aliased HAL.UInt32; + -- ECB block encrypt aborted because of a STOPECB task or due to an + -- error + EVENTS_ERRORECB : aliased HAL.UInt32; + -- Enable interrupt + INTENSET : aliased INTENSET_Register; + -- Disable interrupt + INTENCLR : aliased INTENCLR_Register; + -- ECB block encrypt memory pointers + ECBDATAPTR : aliased HAL.UInt32; + end record + with Volatile; + + for ECB_Peripheral use record + TASKS_STARTECB at 16#0# range 0 .. 31; + TASKS_STOPECB at 16#4# range 0 .. 31; + EVENTS_ENDECB at 16#100# range 0 .. 31; + EVENTS_ERRORECB at 16#104# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + ECBDATAPTR at 16#504# range 0 .. 31; + end record; + + -- AES ECB Mode Encryption + ECB_Periph : aliased ECB_Peripheral + with Import, Address => ECB_Base; + +end NRF_SVD.ECB; diff --git a/arch/ARM/Nordic/svd/nrf52/nrf_svd-egu.ads b/arch/ARM/Nordic/svd/nrf52/nrf_svd-egu.ads new file mode 100644 index 000000000..08229ec51 --- /dev/null +++ b/arch/ARM/Nordic/svd/nrf52/nrf_svd-egu.ads @@ -0,0 +1,298 @@ +-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- 2. Redistributions in binary form, except as embedded into a Nordic +-- Semiconductor ASA integrated circuit in a product or a software update for +-- such product, must reproduce the above copyright notice, this list of +-- conditions and the following disclaimer in the documentation and/or other +-- materials provided with the distribution. +-- +-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from this +-- software without specific prior written permission. +-- +-- 4. This software, with or without modification, must only be used with a +-- Nordic Semiconductor ASA integrated circuit. +-- +-- 5. Any software provided in binary form under this license must not be reverse +-- engineered, decompiled, modified and/or disassembled. +-- +-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +-- OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + +-- This spec has been automatically generated from nrf52.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package NRF_SVD.EGU is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Description collection[0]: Trigger 0 for triggering the corresponding TRIGGERED[0] event + + -- Description collection[0]: Trigger 0 for triggering the corresponding + -- TRIGGERED[0] event + type TASKS_TRIGGER_Registers is array (0 .. 15) of HAL.UInt32; + + -- Description collection[0]: Event number 0 generated by triggering the corresponding TRIGGER[0] task + + -- Description collection[0]: Event number 0 generated by triggering the + -- corresponding TRIGGER[0] task + type EVENTS_TRIGGERED_Registers is array (0 .. 15) of HAL.UInt32; + + -- Enable or disable interrupt for TRIGGERED[0] event + type INTEN_TRIGGERED0_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_TRIGGERED0_Field use + (Disabled => 0, + Enabled => 1); + + -- INTEN_TRIGGERED array + type INTEN_TRIGGERED_Field_Array is array (0 .. 15) + of INTEN_TRIGGERED0_Field + with Component_Size => 1, Size => 16; + + -- Type definition for INTEN_TRIGGERED + type INTEN_TRIGGERED_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- TRIGGERED as a value + Val : HAL.UInt16; + when True => + -- TRIGGERED as an array + Arr : INTEN_TRIGGERED_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for INTEN_TRIGGERED_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Enable or disable interrupt + type INTEN_Register is record + -- Enable or disable interrupt for TRIGGERED[0] event + TRIGGERED : INTEN_TRIGGERED_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTEN_Register use record + TRIGGERED at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- Write '1' to Enable interrupt for TRIGGERED[0] event + type INTENSET_TRIGGERED0_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_TRIGGERED0_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for TRIGGERED[0] event + type INTENSET_TRIGGERED0_Field_1 is + (-- Reset value for the field + Intenset_Triggered0_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_TRIGGERED0_Field_1 use + (Intenset_Triggered0_Field_Reset => 0, + Set => 1); + + -- INTENSET_TRIGGERED array + type INTENSET_TRIGGERED_Field_Array is array (0 .. 15) + of INTENSET_TRIGGERED0_Field_1 + with Component_Size => 1, Size => 16; + + -- Type definition for INTENSET_TRIGGERED + type INTENSET_TRIGGERED_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- TRIGGERED as a value + Val : HAL.UInt16; + when True => + -- TRIGGERED as an array + Arr : INTENSET_TRIGGERED_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for INTENSET_TRIGGERED_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Enable interrupt + type INTENSET_Register is record + -- Write '1' to Enable interrupt for TRIGGERED[0] event + TRIGGERED : INTENSET_TRIGGERED_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENSET_Register use record + TRIGGERED at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- Write '1' to Disable interrupt for TRIGGERED[0] event + type INTENCLR_TRIGGERED0_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_TRIGGERED0_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for TRIGGERED[0] event + type INTENCLR_TRIGGERED0_Field_1 is + (-- Reset value for the field + Intenclr_Triggered0_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_TRIGGERED0_Field_1 use + (Intenclr_Triggered0_Field_Reset => 0, + Clear => 1); + + -- INTENCLR_TRIGGERED array + type INTENCLR_TRIGGERED_Field_Array is array (0 .. 15) + of INTENCLR_TRIGGERED0_Field_1 + with Component_Size => 1, Size => 16; + + -- Type definition for INTENCLR_TRIGGERED + type INTENCLR_TRIGGERED_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- TRIGGERED as a value + Val : HAL.UInt16; + when True => + -- TRIGGERED as an array + Arr : INTENCLR_TRIGGERED_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for INTENCLR_TRIGGERED_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Disable interrupt + type INTENCLR_Register is record + -- Write '1' to Disable interrupt for TRIGGERED[0] event + TRIGGERED : INTENCLR_TRIGGERED_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENCLR_Register use record + TRIGGERED at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Event Generator Unit 0 + type EGU_Peripheral is record + -- Description collection[0]: Trigger 0 for triggering the corresponding + -- TRIGGERED[0] event + TASKS_TRIGGER : aliased TASKS_TRIGGER_Registers; + -- Description collection[0]: Event number 0 generated by triggering the + -- corresponding TRIGGER[0] task + EVENTS_TRIGGERED : aliased EVENTS_TRIGGERED_Registers; + -- Enable or disable interrupt + INTEN : aliased INTEN_Register; + -- Enable interrupt + INTENSET : aliased INTENSET_Register; + -- Disable interrupt + INTENCLR : aliased INTENCLR_Register; + end record + with Volatile; + + for EGU_Peripheral use record + TASKS_TRIGGER at 16#0# range 0 .. 511; + EVENTS_TRIGGERED at 16#100# range 0 .. 511; + INTEN at 16#300# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + end record; + + -- Event Generator Unit 0 + EGU0_Periph : aliased EGU_Peripheral + with Import, Address => EGU0_Base; + + -- Event Generator Unit 1 + EGU1_Periph : aliased EGU_Peripheral + with Import, Address => EGU1_Base; + + -- Event Generator Unit 2 + EGU2_Periph : aliased EGU_Peripheral + with Import, Address => EGU2_Base; + + -- Event Generator Unit 3 + EGU3_Periph : aliased EGU_Peripheral + with Import, Address => EGU3_Base; + + -- Event Generator Unit 4 + EGU4_Periph : aliased EGU_Peripheral + with Import, Address => EGU4_Base; + + -- Event Generator Unit 5 + EGU5_Periph : aliased EGU_Peripheral + with Import, Address => EGU5_Base; + +end NRF_SVD.EGU; diff --git a/arch/ARM/Nordic/svd/nrf52/nrf_svd-ficr.ads b/arch/ARM/Nordic/svd/nrf52/nrf_svd-ficr.ads new file mode 100644 index 000000000..ed8209073 --- /dev/null +++ b/arch/ARM/Nordic/svd/nrf52/nrf_svd-ficr.ads @@ -0,0 +1,460 @@ +-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- 2. Redistributions in binary form, except as embedded into a Nordic +-- Semiconductor ASA integrated circuit in a product or a software update for +-- such product, must reproduce the above copyright notice, this list of +-- conditions and the following disclaimer in the documentation and/or other +-- materials provided with the distribution. +-- +-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from this +-- software without specific prior written permission. +-- +-- 4. This software, with or without modification, must only be used with a +-- Nordic Semiconductor ASA integrated circuit. +-- +-- 5. Any software provided in binary form under this license must not be reverse +-- engineered, decompiled, modified and/or disassembled. +-- +-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +-- OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + +-- This spec has been automatically generated from nrf52.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package NRF_SVD.FICR is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Description collection[0]: Device identifier + + -- Description collection[0]: Device identifier + type DEVICEID_Registers is array (0 .. 1) of HAL.UInt32; + + -- Description collection[0]: Encryption Root, word 0 + + -- Description collection[0]: Encryption Root, word 0 + type ER_Registers is array (0 .. 3) of HAL.UInt32; + + -- Description collection[0]: Identity Root, word 0 + + -- Description collection[0]: Identity Root, word 0 + type IR_Registers is array (0 .. 3) of HAL.UInt32; + + -- Device address type + type DEVICEADDRTYPE_DEVICEADDRTYPE_Field is + (-- Public address + Public, + -- Random address + Random) + with Size => 1; + for DEVICEADDRTYPE_DEVICEADDRTYPE_Field use + (Public => 0, + Random => 1); + + -- Device address type + type DEVICEADDRTYPE_Register is record + -- Read-only. Device address type + DEVICEADDRTYPE : DEVICEADDRTYPE_DEVICEADDRTYPE_Field; + -- unspecified + Reserved_1_31 : HAL.UInt31; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DEVICEADDRTYPE_Register use record + DEVICEADDRTYPE at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Description collection[0]: Device address 0 + + -- Description collection[0]: Device address 0 + type DEVICEADDR_Registers is array (0 .. 1) of HAL.UInt32; + + ------------------------------ + -- INFO cluster's Registers -- + ------------------------------ + + -- Description collection[0]: Unspecified + + -- Description collection[0]: Unspecified + type UNUSED0_INFO_Registers is array (0 .. 2) of HAL.UInt32; + + -- Device info + type INFO_Cluster is record + -- Part code + PART : aliased HAL.UInt32; + -- Part Variant, Hardware version and Production configuration + VARIANT : aliased HAL.UInt32; + -- Package option + PACKAGE_k : aliased HAL.UInt32; + -- RAM variant + RAM : aliased HAL.UInt32; + -- Flash variant + FLASH : aliased HAL.UInt32; + -- Description collection[0]: Unspecified + UNUSED0 : aliased UNUSED0_INFO_Registers; + end record + with Size => 256; + + for INFO_Cluster use record + PART at 16#0# range 0 .. 31; + VARIANT at 16#4# range 0 .. 31; + PACKAGE_k at 16#8# range 0 .. 31; + RAM at 16#C# range 0 .. 31; + FLASH at 16#10# range 0 .. 31; + UNUSED0 at 16#14# range 0 .. 95; + end record; + + ------------------------------ + -- TEMP cluster's Registers -- + ------------------------------ + + subtype A_A_Field is HAL.UInt12; + + -- Slope definition A0. + type A_Register is record + -- Read-only. A (slope definition) register. + A : A_A_Field; + -- unspecified + Reserved_12_31 : HAL.UInt20; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for A_Register use record + A at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype B_B_Field is HAL.UInt14; + + -- y-intercept B0. + type B_Register is record + -- Read-only. B (y-intercept) + B : B_B_Field; + -- unspecified + Reserved_14_31 : HAL.UInt18; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for B_Register use record + B at 0 range 0 .. 13; + Reserved_14_31 at 0 range 14 .. 31; + end record; + + subtype T_T_Field is HAL.UInt8; + + -- Segment end T0. + type T_Register is record + -- Read-only. T (segment end)register. + T : T_T_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for T_Register use record + T at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- Registers storing factory TEMP module linearization coefficients + type TEMP_Cluster is record + -- Slope definition A0. + A0 : aliased A_Register; + -- Slope definition A1. + A1 : aliased A_Register; + -- Slope definition A2. + A2 : aliased A_Register; + -- Slope definition A3. + A3 : aliased A_Register; + -- Slope definition A4. + A4 : aliased A_Register; + -- Slope definition A5. + A5 : aliased A_Register; + -- y-intercept B0. + B0 : aliased B_Register; + -- y-intercept B1. + B1 : aliased B_Register; + -- y-intercept B2. + B2 : aliased B_Register; + -- y-intercept B3. + B3 : aliased B_Register; + -- y-intercept B4. + B4 : aliased B_Register; + -- y-intercept B5. + B5 : aliased B_Register; + -- Segment end T0. + T0 : aliased T_Register; + -- Segment end T1. + T1 : aliased T_Register; + -- Segment end T2. + T2 : aliased T_Register; + -- Segment end T3. + T3 : aliased T_Register; + -- Segment end T4. + T4 : aliased T_Register; + end record + with Size => 544; + + for TEMP_Cluster use record + A0 at 16#0# range 0 .. 31; + A1 at 16#4# range 0 .. 31; + A2 at 16#8# range 0 .. 31; + A3 at 16#C# range 0 .. 31; + A4 at 16#10# range 0 .. 31; + A5 at 16#14# range 0 .. 31; + B0 at 16#18# range 0 .. 31; + B1 at 16#1C# range 0 .. 31; + B2 at 16#20# range 0 .. 31; + B3 at 16#24# range 0 .. 31; + B4 at 16#28# range 0 .. 31; + B5 at 16#2C# range 0 .. 31; + T0 at 16#30# range 0 .. 31; + T1 at 16#34# range 0 .. 31; + T2 at 16#38# range 0 .. 31; + T3 at 16#3C# range 0 .. 31; + T4 at 16#40# range 0 .. 31; + end record; + + ----------------------------- + -- NFC cluster's Registers -- + ----------------------------- + + subtype TAGHEADER0_NFC_MFGID_Field is HAL.UInt8; + -- TAGHEADER0_NFC_UD array element + subtype TAGHEADER0_NFC_UD_Element is HAL.UInt8; + + -- TAGHEADER0_NFC_UD array + type TAGHEADER0_NFC_UD_Field_Array is array (1 .. 3) + of TAGHEADER0_NFC_UD_Element + with Component_Size => 8, Size => 24; + + -- Type definition for TAGHEADER0_NFC_UD + type TAGHEADER0_NFC_UD_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- UD as a value + Val : HAL.UInt24; + when True => + -- UD as an array + Arr : TAGHEADER0_NFC_UD_Field_Array; + end case; + end record + with Unchecked_Union, Size => 24; + + for TAGHEADER0_NFC_UD_Field use record + Val at 0 range 0 .. 23; + Arr at 0 range 0 .. 23; + end record; + + -- Default header for NFC Tag. Software can read these values to populate + -- NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + type TAGHEADER0_NFC_Register is record + -- Read-only. Default Manufacturer ID: Nordic Semiconductor ASA has ICM + -- 0x5F + MFGID : TAGHEADER0_NFC_MFGID_Field; + -- Read-only. Unique identifier byte 1 + UD : TAGHEADER0_NFC_UD_Field; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TAGHEADER0_NFC_Register use record + MFGID at 0 range 0 .. 7; + UD at 0 range 8 .. 31; + end record; + + -- TAGHEADER1_NFC_UD array element + subtype TAGHEADER1_NFC_UD_Element is HAL.UInt8; + + -- TAGHEADER1_NFC_UD array + type TAGHEADER1_NFC_UD_Field_Array is array (4 .. 7) + of TAGHEADER1_NFC_UD_Element + with Component_Size => 8, Size => 32; + + -- Default header for NFC Tag. Software can read these values to populate + -- NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + type TAGHEADER1_NFC_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- UD as a value + Val : HAL.UInt32; + when True => + -- UD as an array + Arr : TAGHEADER1_NFC_UD_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TAGHEADER1_NFC_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- TAGHEADER2_NFC_UD array element + subtype TAGHEADER2_NFC_UD_Element is HAL.UInt8; + + -- TAGHEADER2_NFC_UD array + type TAGHEADER2_NFC_UD_Field_Array is array (8 .. 11) + of TAGHEADER2_NFC_UD_Element + with Component_Size => 8, Size => 32; + + -- Default header for NFC Tag. Software can read these values to populate + -- NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + type TAGHEADER2_NFC_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- UD as a value + Val : HAL.UInt32; + when True => + -- UD as an array + Arr : TAGHEADER2_NFC_UD_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TAGHEADER2_NFC_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- TAGHEADER3_NFC_UD array element + subtype TAGHEADER3_NFC_UD_Element is HAL.UInt8; + + -- TAGHEADER3_NFC_UD array + type TAGHEADER3_NFC_UD_Field_Array is array (12 .. 15) + of TAGHEADER3_NFC_UD_Element + with Component_Size => 8, Size => 32; + + -- Default header for NFC Tag. Software can read these values to populate + -- NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + type TAGHEADER3_NFC_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- UD as a value + Val : HAL.UInt32; + when True => + -- UD as an array + Arr : TAGHEADER3_NFC_UD_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TAGHEADER3_NFC_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- Unspecified + type NFC_Cluster is record + -- Default header for NFC Tag. Software can read these values to + -- populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + TAGHEADER0 : aliased TAGHEADER0_NFC_Register; + -- Default header for NFC Tag. Software can read these values to + -- populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + TAGHEADER1 : aliased TAGHEADER1_NFC_Register; + -- Default header for NFC Tag. Software can read these values to + -- populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + TAGHEADER2 : aliased TAGHEADER2_NFC_Register; + -- Default header for NFC Tag. Software can read these values to + -- populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. + TAGHEADER3 : aliased TAGHEADER3_NFC_Register; + end record + with Size => 128; + + for NFC_Cluster use record + TAGHEADER0 at 16#0# range 0 .. 31; + TAGHEADER1 at 16#4# range 0 .. 31; + TAGHEADER2 at 16#8# range 0 .. 31; + TAGHEADER3 at 16#C# range 0 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Factory Information Configuration Registers + type FICR_Peripheral is record + -- Code memory page size + CODEPAGESIZE : aliased HAL.UInt32; + -- Code memory size + CODESIZE : aliased HAL.UInt32; + -- Description collection[0]: Device identifier + DEVICEID : aliased DEVICEID_Registers; + -- Description collection[0]: Encryption Root, word 0 + ER : aliased ER_Registers; + -- Description collection[0]: Identity Root, word 0 + IR : aliased IR_Registers; + -- Device address type + DEVICEADDRTYPE : aliased DEVICEADDRTYPE_Register; + -- Description collection[0]: Device address 0 + DEVICEADDR : aliased DEVICEADDR_Registers; + -- Device info + INFO : aliased INFO_Cluster; + -- Registers storing factory TEMP module linearization coefficients + TEMP : aliased TEMP_Cluster; + -- Unspecified + NFC : aliased NFC_Cluster; + end record + with Volatile; + + for FICR_Peripheral use record + CODEPAGESIZE at 16#10# range 0 .. 31; + CODESIZE at 16#14# range 0 .. 31; + DEVICEID at 16#60# range 0 .. 63; + ER at 16#80# range 0 .. 127; + IR at 16#90# range 0 .. 127; + DEVICEADDRTYPE at 16#A0# range 0 .. 31; + DEVICEADDR at 16#A4# range 0 .. 63; + INFO at 16#100# range 0 .. 255; + TEMP at 16#404# range 0 .. 543; + NFC at 16#450# range 0 .. 127; + end record; + + -- Factory Information Configuration Registers + FICR_Periph : aliased FICR_Peripheral + with Import, Address => FICR_Base; + +end NRF_SVD.FICR; diff --git a/arch/ARM/Nordic/svd/nrf52/nrf_svd-fpu.ads b/arch/ARM/Nordic/svd/nrf52/nrf_svd-fpu.ads new file mode 100644 index 000000000..3a28eaed1 --- /dev/null +++ b/arch/ARM/Nordic/svd/nrf52/nrf_svd-fpu.ads @@ -0,0 +1,73 @@ +-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- 2. Redistributions in binary form, except as embedded into a Nordic +-- Semiconductor ASA integrated circuit in a product or a software update for +-- such product, must reproduce the above copyright notice, this list of +-- conditions and the following disclaimer in the documentation and/or other +-- materials provided with the distribution. +-- +-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from this +-- software without specific prior written permission. +-- +-- 4. This software, with or without modification, must only be used with a +-- Nordic Semiconductor ASA integrated circuit. +-- +-- 5. Any software provided in binary form under this license must not be reverse +-- engineered, decompiled, modified and/or disassembled. +-- +-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +-- OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + +-- This spec has been automatically generated from nrf52.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; + +package NRF_SVD.FPU is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + ----------------- + -- Peripherals -- + ----------------- + + -- FPU + type FPU_Peripheral is record + -- Unused. + UNUSED : aliased HAL.UInt32; + end record + with Volatile; + + for FPU_Peripheral use record + UNUSED at 0 range 0 .. 31; + end record; + + -- FPU + FPU_Periph : aliased FPU_Peripheral + with Import, Address => FPU_Base; + +end NRF_SVD.FPU; diff --git a/arch/ARM/Nordic/svd/nrf52/nrf_svd-gpio.ads b/arch/ARM/Nordic/svd/nrf52/nrf_svd-gpio.ads new file mode 100644 index 000000000..6ea98ecc1 --- /dev/null +++ b/arch/ARM/Nordic/svd/nrf52/nrf_svd-gpio.ads @@ -0,0 +1,577 @@ +-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- 2. Redistributions in binary form, except as embedded into a Nordic +-- Semiconductor ASA integrated circuit in a product or a software update for +-- such product, must reproduce the above copyright notice, this list of +-- conditions and the following disclaimer in the documentation and/or other +-- materials provided with the distribution. +-- +-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from this +-- software without specific prior written permission. +-- +-- 4. This software, with or without modification, must only be used with a +-- Nordic Semiconductor ASA integrated circuit. +-- +-- 5. Any software provided in binary form under this license must not be reverse +-- engineered, decompiled, modified and/or disassembled. +-- +-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +-- OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + +-- This spec has been automatically generated from nrf52.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package NRF_SVD.GPIO is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Pin 0 + type OUT_PIN0_Field is + (-- Pin driver is low + Low, + -- Pin driver is high + High) + with Size => 1; + for OUT_PIN0_Field use + (Low => 0, + High => 1); + + -- OUT_PIN array + type OUT_PIN_Field_Array is array (0 .. 31) of OUT_PIN0_Field + with Component_Size => 1, Size => 32; + + -- Write GPIO port + type OUT_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PIN as a value + Val : HAL.UInt32; + when True => + -- PIN as an array + Arr : OUT_PIN_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for OUT_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- Pin 0 + type OUTSET_PIN0_Field is + (-- Read: pin driver is low + Low, + -- Read: pin driver is high + High) + with Size => 1; + for OUTSET_PIN0_Field use + (Low => 0, + High => 1); + + -- Pin 0 + type OUTSET_PIN0_Field_1 is + (-- Reset value for the field + Outset_Pin0_Field_Reset, + -- Write: writing a '1' sets the pin high; writing a '0' has no effect + Set) + with Size => 1; + for OUTSET_PIN0_Field_1 use + (Outset_Pin0_Field_Reset => 0, + Set => 1); + + -- OUTSET_PIN array + type OUTSET_PIN_Field_Array is array (0 .. 31) of OUTSET_PIN0_Field_1 + with Component_Size => 1, Size => 32; + + -- Set individual bits in GPIO port + type OUTSET_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PIN as a value + Val : HAL.UInt32; + when True => + -- PIN as an array + Arr : OUTSET_PIN_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for OUTSET_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- Pin 0 + type OUTCLR_PIN0_Field is + (-- Read: pin driver is low + Low, + -- Read: pin driver is high + High) + with Size => 1; + for OUTCLR_PIN0_Field use + (Low => 0, + High => 1); + + -- Pin 0 + type OUTCLR_PIN0_Field_1 is + (-- Reset value for the field + Outclr_Pin0_Field_Reset, + -- Write: writing a '1' sets the pin low; writing a '0' has no effect + Clear) + with Size => 1; + for OUTCLR_PIN0_Field_1 use + (Outclr_Pin0_Field_Reset => 0, + Clear => 1); + + -- OUTCLR_PIN array + type OUTCLR_PIN_Field_Array is array (0 .. 31) of OUTCLR_PIN0_Field_1 + with Component_Size => 1, Size => 32; + + -- Clear individual bits in GPIO port + type OUTCLR_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PIN as a value + Val : HAL.UInt32; + when True => + -- PIN as an array + Arr : OUTCLR_PIN_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for OUTCLR_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- Pin 0 + type IN_PIN0_Field is + (-- Pin input is low + Low, + -- Pin input is high + High) + with Size => 1; + for IN_PIN0_Field use + (Low => 0, + High => 1); + + -- IN_PIN array + type IN_PIN_Field_Array is array (0 .. 31) of IN_PIN0_Field + with Component_Size => 1, Size => 32; + + -- Read GPIO port + type IN_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PIN as a value + Val : HAL.UInt32; + when True => + -- PIN as an array + Arr : IN_PIN_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IN_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- Pin 0 + type DIR_PIN0_Field is + (-- Pin set as input + Input, + -- Pin set as output + Output) + with Size => 1; + for DIR_PIN0_Field use + (Input => 0, + Output => 1); + + -- DIR_PIN array + type DIR_PIN_Field_Array is array (0 .. 31) of DIR_PIN0_Field + with Component_Size => 1, Size => 32; + + -- Direction of GPIO pins + type DIR_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PIN as a value + Val : HAL.UInt32; + when True => + -- PIN as an array + Arr : DIR_PIN_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DIR_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- Set as output pin 0 + type DIRSET_PIN0_Field is + (-- Read: pin set as input + Input, + -- Read: pin set as output + Output) + with Size => 1; + for DIRSET_PIN0_Field use + (Input => 0, + Output => 1); + + -- Set as output pin 0 + type DIRSET_PIN0_Field_1 is + (-- Reset value for the field + Dirset_Pin0_Field_Reset, + -- Write: writing a '1' sets pin to output; writing a '0' has no effect + Set) + with Size => 1; + for DIRSET_PIN0_Field_1 use + (Dirset_Pin0_Field_Reset => 0, + Set => 1); + + -- DIRSET_PIN array + type DIRSET_PIN_Field_Array is array (0 .. 31) of DIRSET_PIN0_Field_1 + with Component_Size => 1, Size => 32; + + -- DIR set register + type DIRSET_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PIN as a value + Val : HAL.UInt32; + when True => + -- PIN as an array + Arr : DIRSET_PIN_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DIRSET_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- Set as input pin 0 + type DIRCLR_PIN0_Field is + (-- Read: pin set as input + Input, + -- Read: pin set as output + Output) + with Size => 1; + for DIRCLR_PIN0_Field use + (Input => 0, + Output => 1); + + -- Set as input pin 0 + type DIRCLR_PIN0_Field_1 is + (-- Reset value for the field + Dirclr_Pin0_Field_Reset, + -- Write: writing a '1' sets pin to input; writing a '0' has no effect + Clear) + with Size => 1; + for DIRCLR_PIN0_Field_1 use + (Dirclr_Pin0_Field_Reset => 0, + Clear => 1); + + -- DIRCLR_PIN array + type DIRCLR_PIN_Field_Array is array (0 .. 31) of DIRCLR_PIN0_Field_1 + with Component_Size => 1, Size => 32; + + -- DIR clear register + type DIRCLR_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PIN as a value + Val : HAL.UInt32; + when True => + -- PIN as an array + Arr : DIRCLR_PIN_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DIRCLR_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. + -- Write '1' to clear. + type LATCH_PIN0_Field is + (-- Criteria has not been met + Notlatched, + -- Criteria has been met + Latched) + with Size => 1; + for LATCH_PIN0_Field use + (Notlatched => 0, + Latched => 1); + + -- LATCH_PIN array + type LATCH_PIN_Field_Array is array (0 .. 31) of LATCH_PIN0_Field + with Component_Size => 1, Size => 32; + + -- Latch register indicating what GPIO pins that have met the criteria set + -- in the PIN_CNF[n].SENSE registers + type LATCH_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PIN as a value + Val : HAL.UInt32; + when True => + -- PIN as an array + Arr : LATCH_PIN_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for LATCH_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- Select between default DETECT signal behaviour and LDETECT mode + type DETECTMODE_DETECTMODE_Field is + (-- DETECT directly connected to PIN DETECT signals + Default, + -- Use the latched LDETECT behaviour + Ldetect) + with Size => 1; + for DETECTMODE_DETECTMODE_Field use + (Default => 0, + Ldetect => 1); + + -- Select between default DETECT signal behaviour and LDETECT mode + type DETECTMODE_Register is record + -- Select between default DETECT signal behaviour and LDETECT mode + DETECTMODE : DETECTMODE_DETECTMODE_Field := NRF_SVD.GPIO.Default; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DETECTMODE_Register use record + DETECTMODE at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Pin direction. Same physical register as DIR register + type PIN_CNF_DIR_Field is + (-- Configure pin as an input pin + Input, + -- Configure pin as an output pin + Output) + with Size => 1; + for PIN_CNF_DIR_Field use + (Input => 0, + Output => 1); + + -- Connect or disconnect input buffer + type PIN_CNF_INPUT_Field is + (-- Connect input buffer + Connect, + -- Disconnect input buffer + Disconnect) + with Size => 1; + for PIN_CNF_INPUT_Field use + (Connect => 0, + Disconnect => 1); + + -- Pull configuration + type PIN_CNF_PULL_Field is + (-- No pull + Disabled, + -- Pull down on pin + Pulldown, + -- Pull up on pin + Pullup) + with Size => 2; + for PIN_CNF_PULL_Field use + (Disabled => 0, + Pulldown => 1, + Pullup => 3); + + -- Drive configuration + type PIN_CNF_DRIVE_Field is + (-- Standard '0', standard '1' + S0S1, + -- High drive '0', standard '1' + H0S1, + -- Standard '0', high drive '1' + S0H1, + -- High drive '0', high 'drive '1'' + H0H1, + -- Disconnect '0' standard '1' (normally used for wired-or connections) + D0S1, + -- Disconnect '0', high drive '1' (normally used for wired-or connections) + D0H1, + -- Standard '0'. disconnect '1' (normally used for wired-and connections) + S0D1, + -- High drive '0', disconnect '1' (normally used for wired-and connections) + H0D1) + with Size => 3; + for PIN_CNF_DRIVE_Field use + (S0S1 => 0, + H0S1 => 1, + S0H1 => 2, + H0H1 => 3, + D0S1 => 4, + D0H1 => 5, + S0D1 => 6, + H0D1 => 7); + + -- Pin sensing mechanism + type PIN_CNF_SENSE_Field is + (-- Disabled + Disabled, + -- Sense for high level + High, + -- Sense for low level + Low) + with Size => 2; + for PIN_CNF_SENSE_Field use + (Disabled => 0, + High => 2, + Low => 3); + + -- Description collection[0]: Configuration of GPIO pins + type PIN_CNF_Register is record + -- Pin direction. Same physical register as DIR register + DIR : PIN_CNF_DIR_Field := NRF_SVD.GPIO.Input; + -- Connect or disconnect input buffer + INPUT : PIN_CNF_INPUT_Field := NRF_SVD.GPIO.Disconnect; + -- Pull configuration + PULL : PIN_CNF_PULL_Field := NRF_SVD.GPIO.Disabled; + -- unspecified + Reserved_4_7 : HAL.UInt4 := 16#0#; + -- Drive configuration + DRIVE : PIN_CNF_DRIVE_Field := NRF_SVD.GPIO.S0S1; + -- unspecified + Reserved_11_15 : HAL.UInt5 := 16#0#; + -- Pin sensing mechanism + SENSE : PIN_CNF_SENSE_Field := NRF_SVD.GPIO.Disabled; + -- unspecified + Reserved_18_31 : HAL.UInt14 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PIN_CNF_Register use record + DIR at 0 range 0 .. 0; + INPUT at 0 range 1 .. 1; + PULL at 0 range 2 .. 3; + Reserved_4_7 at 0 range 4 .. 7; + DRIVE at 0 range 8 .. 10; + Reserved_11_15 at 0 range 11 .. 15; + SENSE at 0 range 16 .. 17; + Reserved_18_31 at 0 range 18 .. 31; + end record; + + -- Description collection[0]: Configuration of GPIO pins + type PIN_CNF_Registers is array (0 .. 31) of PIN_CNF_Register; + + ----------------- + -- Peripherals -- + ----------------- + + -- GPIO Port 1 + type GPIO_Peripheral is record + -- Write GPIO port + OUT_k : aliased OUT_Register; + -- Set individual bits in GPIO port + OUTSET : aliased OUTSET_Register; + -- Clear individual bits in GPIO port + OUTCLR : aliased OUTCLR_Register; + -- Read GPIO port + IN_k : aliased IN_Register; + -- Direction of GPIO pins + DIR : aliased DIR_Register; + -- DIR set register + DIRSET : aliased DIRSET_Register; + -- DIR clear register + DIRCLR : aliased DIRCLR_Register; + -- Latch register indicating what GPIO pins that have met the criteria + -- set in the PIN_CNF[n].SENSE registers + LATCH : aliased LATCH_Register; + -- Select between default DETECT signal behaviour and LDETECT mode + DETECTMODE : aliased DETECTMODE_Register; + -- Description collection[0]: Configuration of GPIO pins + PIN_CNF : aliased PIN_CNF_Registers; + end record + with Volatile; + + for GPIO_Peripheral use record + OUT_k at 16#504# range 0 .. 31; + OUTSET at 16#508# range 0 .. 31; + OUTCLR at 16#50C# range 0 .. 31; + IN_k at 16#510# range 0 .. 31; + DIR at 16#514# range 0 .. 31; + DIRSET at 16#518# range 0 .. 31; + DIRCLR at 16#51C# range 0 .. 31; + LATCH at 16#520# range 0 .. 31; + DETECTMODE at 16#524# range 0 .. 31; + PIN_CNF at 16#700# range 0 .. 1023; + end record; + + -- GPIO Port 1 + GPIO_Periph : aliased GPIO_Peripheral + with Import, Address => P0_Base; + +end NRF_SVD.GPIO; diff --git a/arch/ARM/Nordic/svd/nrf52/nrf_svd-gpiote.ads b/arch/ARM/Nordic/svd/nrf52/nrf_svd-gpiote.ads new file mode 100644 index 000000000..ea5844e5f --- /dev/null +++ b/arch/ARM/Nordic/svd/nrf52/nrf_svd-gpiote.ads @@ -0,0 +1,390 @@ +-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- 2. Redistributions in binary form, except as embedded into a Nordic +-- Semiconductor ASA integrated circuit in a product or a software update for +-- such product, must reproduce the above copyright notice, this list of +-- conditions and the following disclaimer in the documentation and/or other +-- materials provided with the distribution. +-- +-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from this +-- software without specific prior written permission. +-- +-- 4. This software, with or without modification, must only be used with a +-- Nordic Semiconductor ASA integrated circuit. +-- +-- 5. Any software provided in binary form under this license must not be reverse +-- engineered, decompiled, modified and/or disassembled. +-- +-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +-- OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + +-- This spec has been automatically generated from nrf52.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package NRF_SVD.GPIOTE is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Description collection[0]: Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY. + + -- Description collection[0]: Task for writing to pin specified in + -- CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY. + type TASKS_OUT_Registers is array (0 .. 7) of HAL.UInt32; + + -- Description collection[0]: Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it high. + + -- Description collection[0]: Task for writing to pin specified in + -- CONFIG[0].PSEL. Action on pin is to set it high. + type TASKS_SET_Registers is array (0 .. 7) of HAL.UInt32; + + -- Description collection[0]: Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it low. + + -- Description collection[0]: Task for writing to pin specified in + -- CONFIG[0].PSEL. Action on pin is to set it low. + type TASKS_CLR_Registers is array (0 .. 7) of HAL.UInt32; + + -- Description collection[0]: Event generated from pin specified in CONFIG[0].PSEL + + -- Description collection[0]: Event generated from pin specified in + -- CONFIG[0].PSEL + type EVENTS_IN_Registers is array (0 .. 7) of HAL.UInt32; + + -- Write '1' to Enable interrupt for IN[0] event + type INTENSET_IN0_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_IN0_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for IN[0] event + type INTENSET_IN0_Field_1 is + (-- Reset value for the field + Intenset_In0_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_IN0_Field_1 use + (Intenset_In0_Field_Reset => 0, + Set => 1); + + -- INTENSET_IN array + type INTENSET_IN_Field_Array is array (0 .. 7) of INTENSET_IN0_Field_1 + with Component_Size => 1, Size => 8; + + -- Type definition for INTENSET_IN + type INTENSET_IN_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- IN as a value + Val : HAL.UInt8; + when True => + -- IN as an array + Arr : INTENSET_IN_Field_Array; + end case; + end record + with Unchecked_Union, Size => 8; + + for INTENSET_IN_Field use record + Val at 0 range 0 .. 7; + Arr at 0 range 0 .. 7; + end record; + + -- Write '1' to Enable interrupt for PORT event + type INTENSET_PORT_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_PORT_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for PORT event + type INTENSET_PORT_Field_1 is + (-- Reset value for the field + Intenset_Port_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_PORT_Field_1 use + (Intenset_Port_Field_Reset => 0, + Set => 1); + + -- Enable interrupt + type INTENSET_Register is record + -- Write '1' to Enable interrupt for IN[0] event + IN_k : INTENSET_IN_Field := (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_8_30 : HAL.UInt23 := 16#0#; + -- Write '1' to Enable interrupt for PORT event + PORT : INTENSET_PORT_Field_1 := Intenset_Port_Field_Reset; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENSET_Register use record + IN_k at 0 range 0 .. 7; + Reserved_8_30 at 0 range 8 .. 30; + PORT at 0 range 31 .. 31; + end record; + + -- Write '1' to Disable interrupt for IN[0] event + type INTENCLR_IN0_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_IN0_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for IN[0] event + type INTENCLR_IN0_Field_1 is + (-- Reset value for the field + Intenclr_In0_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_IN0_Field_1 use + (Intenclr_In0_Field_Reset => 0, + Clear => 1); + + -- INTENCLR_IN array + type INTENCLR_IN_Field_Array is array (0 .. 7) of INTENCLR_IN0_Field_1 + with Component_Size => 1, Size => 8; + + -- Type definition for INTENCLR_IN + type INTENCLR_IN_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- IN as a value + Val : HAL.UInt8; + when True => + -- IN as an array + Arr : INTENCLR_IN_Field_Array; + end case; + end record + with Unchecked_Union, Size => 8; + + for INTENCLR_IN_Field use record + Val at 0 range 0 .. 7; + Arr at 0 range 0 .. 7; + end record; + + -- Write '1' to Disable interrupt for PORT event + type INTENCLR_PORT_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_PORT_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for PORT event + type INTENCLR_PORT_Field_1 is + (-- Reset value for the field + Intenclr_Port_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_PORT_Field_1 use + (Intenclr_Port_Field_Reset => 0, + Clear => 1); + + -- Disable interrupt + type INTENCLR_Register is record + -- Write '1' to Disable interrupt for IN[0] event + IN_k : INTENCLR_IN_Field := (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_8_30 : HAL.UInt23 := 16#0#; + -- Write '1' to Disable interrupt for PORT event + PORT : INTENCLR_PORT_Field_1 := Intenclr_Port_Field_Reset; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENCLR_Register use record + IN_k at 0 range 0 .. 7; + Reserved_8_30 at 0 range 8 .. 30; + PORT at 0 range 31 .. 31; + end record; + + -- Mode + type CONFIG_MODE_Field is + (-- Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. + Disabled, + -- Event mode + Event, + -- Task mode + Task_k) + with Size => 2; + for CONFIG_MODE_Field use + (Disabled => 0, + Event => 1, + Task_k => 3); + + subtype CONFIG_PSEL_Field is HAL.UInt5; + + -- When In task mode: Operation to be performed on output when OUT[n] task + -- is triggered. When In event mode: Operation on input that shall trigger + -- IN[n] event. + type CONFIG_POLARITY_Field is + (-- Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event +-- generated on pin activity. + None, + -- Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when +-- rising edge on pin. + Lotohi, + -- Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event +-- when falling edge on pin. + Hitolo, + -- Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any +-- change on pin. + Toggle) + with Size => 2; + for CONFIG_POLARITY_Field use + (None => 0, + Lotohi => 1, + Hitolo => 2, + Toggle => 3); + + -- When in task mode: Initial value of the output when the GPIOTE channel + -- is configured. When in event mode: No effect. + type CONFIG_OUTINIT_Field is + (-- Task mode: Initial value of pin before task triggering is low + Low, + -- Task mode: Initial value of pin before task triggering is high + High) + with Size => 1; + for CONFIG_OUTINIT_Field use + (Low => 0, + High => 1); + + -- Description collection[0]: Configuration for OUT[n], SET[n] and CLR[n] + -- tasks and IN[n] event + type CONFIG_Register is record + -- Mode + MODE : CONFIG_MODE_Field := NRF_SVD.GPIOTE.Disabled; + -- unspecified + Reserved_2_7 : HAL.UInt6 := 16#0#; + -- GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] + -- event + PSEL : CONFIG_PSEL_Field := 16#0#; + -- unspecified + Reserved_13_15 : HAL.UInt3 := 16#0#; + -- When In task mode: Operation to be performed on output when OUT[n] + -- task is triggered. When In event mode: Operation on input that shall + -- trigger IN[n] event. + POLARITY : CONFIG_POLARITY_Field := NRF_SVD.GPIOTE.None; + -- unspecified + Reserved_18_19 : HAL.UInt2 := 16#0#; + -- When in task mode: Initial value of the output when the GPIOTE + -- channel is configured. When in event mode: No effect. + OUTINIT : CONFIG_OUTINIT_Field := NRF_SVD.GPIOTE.Low; + -- unspecified + Reserved_21_31 : HAL.UInt11 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CONFIG_Register use record + MODE at 0 range 0 .. 1; + Reserved_2_7 at 0 range 2 .. 7; + PSEL at 0 range 8 .. 12; + Reserved_13_15 at 0 range 13 .. 15; + POLARITY at 0 range 16 .. 17; + Reserved_18_19 at 0 range 18 .. 19; + OUTINIT at 0 range 20 .. 20; + Reserved_21_31 at 0 range 21 .. 31; + end record; + + -- Description collection[0]: Configuration for OUT[n], SET[n] and CLR[n] + -- tasks and IN[n] event + type CONFIG_Registers is array (0 .. 7) of CONFIG_Register; + + ----------------- + -- Peripherals -- + ----------------- + + -- GPIO Tasks and Events + type GPIOTE_Peripheral is record + -- Description collection[0]: Task for writing to pin specified in + -- CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY. + TASKS_OUT : aliased TASKS_OUT_Registers; + -- Description collection[0]: Task for writing to pin specified in + -- CONFIG[0].PSEL. Action on pin is to set it high. + TASKS_SET : aliased TASKS_SET_Registers; + -- Description collection[0]: Task for writing to pin specified in + -- CONFIG[0].PSEL. Action on pin is to set it low. + TASKS_CLR : aliased TASKS_CLR_Registers; + -- Description collection[0]: Event generated from pin specified in + -- CONFIG[0].PSEL + EVENTS_IN : aliased EVENTS_IN_Registers; + -- Event generated from multiple input GPIO pins with SENSE mechanism + -- enabled + EVENTS_PORT : aliased HAL.UInt32; + -- Enable interrupt + INTENSET : aliased INTENSET_Register; + -- Disable interrupt + INTENCLR : aliased INTENCLR_Register; + -- Description collection[0]: Configuration for OUT[n], SET[n] and + -- CLR[n] tasks and IN[n] event + CONFIG : aliased CONFIG_Registers; + end record + with Volatile; + + for GPIOTE_Peripheral use record + TASKS_OUT at 16#0# range 0 .. 255; + TASKS_SET at 16#30# range 0 .. 255; + TASKS_CLR at 16#60# range 0 .. 255; + EVENTS_IN at 16#100# range 0 .. 255; + EVENTS_PORT at 16#17C# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + CONFIG at 16#510# range 0 .. 255; + end record; + + -- GPIO Tasks and Events + GPIOTE_Periph : aliased GPIOTE_Peripheral + with Import, Address => GPIOTE_Base; + +end NRF_SVD.GPIOTE; diff --git a/arch/ARM/Nordic/svd/nrf52/nrf_svd-i2s.ads b/arch/ARM/Nordic/svd/nrf52/nrf_svd-i2s.ads new file mode 100644 index 000000000..f7f57617b --- /dev/null +++ b/arch/ARM/Nordic/svd/nrf52/nrf_svd-i2s.ads @@ -0,0 +1,949 @@ +-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- 2. Redistributions in binary form, except as embedded into a Nordic +-- Semiconductor ASA integrated circuit in a product or a software update for +-- such product, must reproduce the above copyright notice, this list of +-- conditions and the following disclaimer in the documentation and/or other +-- materials provided with the distribution. +-- +-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from this +-- software without specific prior written permission. +-- +-- 4. This software, with or without modification, must only be used with a +-- Nordic Semiconductor ASA integrated circuit. +-- +-- 5. Any software provided in binary form under this license must not be reverse +-- engineered, decompiled, modified and/or disassembled. +-- +-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +-- OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + +-- This spec has been automatically generated from nrf52.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package NRF_SVD.I2S is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Enable or disable interrupt for RXPTRUPD event + type INTEN_RXPTRUPD_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_RXPTRUPD_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for STOPPED event + type INTEN_STOPPED_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_STOPPED_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for TXPTRUPD event + type INTEN_TXPTRUPD_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_TXPTRUPD_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt + type INTEN_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#0#; + -- Enable or disable interrupt for RXPTRUPD event + RXPTRUPD : INTEN_RXPTRUPD_Field := NRF_SVD.I2S.Disabled; + -- Enable or disable interrupt for STOPPED event + STOPPED : INTEN_STOPPED_Field := NRF_SVD.I2S.Disabled; + -- unspecified + Reserved_3_4 : HAL.UInt2 := 16#0#; + -- Enable or disable interrupt for TXPTRUPD event + TXPTRUPD : INTEN_TXPTRUPD_Field := NRF_SVD.I2S.Disabled; + -- unspecified + Reserved_6_31 : HAL.UInt26 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTEN_Register use record + Reserved_0_0 at 0 range 0 .. 0; + RXPTRUPD at 0 range 1 .. 1; + STOPPED at 0 range 2 .. 2; + Reserved_3_4 at 0 range 3 .. 4; + TXPTRUPD at 0 range 5 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + -- Write '1' to Enable interrupt for RXPTRUPD event + type INTENSET_RXPTRUPD_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_RXPTRUPD_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for RXPTRUPD event + type INTENSET_RXPTRUPD_Field_1 is + (-- Reset value for the field + Intenset_Rxptrupd_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_RXPTRUPD_Field_1 use + (Intenset_Rxptrupd_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for STOPPED event + type INTENSET_STOPPED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_STOPPED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for STOPPED event + type INTENSET_STOPPED_Field_1 is + (-- Reset value for the field + Intenset_Stopped_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_STOPPED_Field_1 use + (Intenset_Stopped_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for TXPTRUPD event + type INTENSET_TXPTRUPD_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_TXPTRUPD_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for TXPTRUPD event + type INTENSET_TXPTRUPD_Field_1 is + (-- Reset value for the field + Intenset_Txptrupd_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_TXPTRUPD_Field_1 use + (Intenset_Txptrupd_Field_Reset => 0, + Set => 1); + + -- Enable interrupt + type INTENSET_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#0#; + -- Write '1' to Enable interrupt for RXPTRUPD event + RXPTRUPD : INTENSET_RXPTRUPD_Field_1 := + Intenset_Rxptrupd_Field_Reset; + -- Write '1' to Enable interrupt for STOPPED event + STOPPED : INTENSET_STOPPED_Field_1 := + Intenset_Stopped_Field_Reset; + -- unspecified + Reserved_3_4 : HAL.UInt2 := 16#0#; + -- Write '1' to Enable interrupt for TXPTRUPD event + TXPTRUPD : INTENSET_TXPTRUPD_Field_1 := + Intenset_Txptrupd_Field_Reset; + -- unspecified + Reserved_6_31 : HAL.UInt26 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENSET_Register use record + Reserved_0_0 at 0 range 0 .. 0; + RXPTRUPD at 0 range 1 .. 1; + STOPPED at 0 range 2 .. 2; + Reserved_3_4 at 0 range 3 .. 4; + TXPTRUPD at 0 range 5 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + -- Write '1' to Disable interrupt for RXPTRUPD event + type INTENCLR_RXPTRUPD_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_RXPTRUPD_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for RXPTRUPD event + type INTENCLR_RXPTRUPD_Field_1 is + (-- Reset value for the field + Intenclr_Rxptrupd_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_RXPTRUPD_Field_1 use + (Intenclr_Rxptrupd_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for STOPPED event + type INTENCLR_STOPPED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_STOPPED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for STOPPED event + type INTENCLR_STOPPED_Field_1 is + (-- Reset value for the field + Intenclr_Stopped_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_STOPPED_Field_1 use + (Intenclr_Stopped_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for TXPTRUPD event + type INTENCLR_TXPTRUPD_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_TXPTRUPD_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for TXPTRUPD event + type INTENCLR_TXPTRUPD_Field_1 is + (-- Reset value for the field + Intenclr_Txptrupd_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_TXPTRUPD_Field_1 use + (Intenclr_Txptrupd_Field_Reset => 0, + Clear => 1); + + -- Disable interrupt + type INTENCLR_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#0#; + -- Write '1' to Disable interrupt for RXPTRUPD event + RXPTRUPD : INTENCLR_RXPTRUPD_Field_1 := + Intenclr_Rxptrupd_Field_Reset; + -- Write '1' to Disable interrupt for STOPPED event + STOPPED : INTENCLR_STOPPED_Field_1 := + Intenclr_Stopped_Field_Reset; + -- unspecified + Reserved_3_4 : HAL.UInt2 := 16#0#; + -- Write '1' to Disable interrupt for TXPTRUPD event + TXPTRUPD : INTENCLR_TXPTRUPD_Field_1 := + Intenclr_Txptrupd_Field_Reset; + -- unspecified + Reserved_6_31 : HAL.UInt26 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENCLR_Register use record + Reserved_0_0 at 0 range 0 .. 0; + RXPTRUPD at 0 range 1 .. 1; + STOPPED at 0 range 2 .. 2; + Reserved_3_4 at 0 range 3 .. 4; + TXPTRUPD at 0 range 5 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + -- Enable I2S module. + type ENABLE_ENABLE_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for ENABLE_ENABLE_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable I2S module. + type ENABLE_Register is record + -- Enable I2S module. + ENABLE : ENABLE_ENABLE_Field := NRF_SVD.I2S.Disabled; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ENABLE_Register use record + ENABLE at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -------------------------------- + -- CONFIG cluster's Registers -- + -------------------------------- + + -- I2S mode. + type MODE_MODE_Field is + (-- Master mode. SCK and LRCK generated from internal master clcok (MCK) and +-- output on pins defined by PSEL.xxx. + Master, + -- Slave mode. SCK and LRCK generated by external master and received on pins +-- defined by PSEL.xxx + Slave) + with Size => 1; + for MODE_MODE_Field use + (Master => 0, + Slave => 1); + + -- I2S mode. + type MODE_CONFIG_Register is record + -- I2S mode. + MODE : MODE_MODE_Field := NRF_SVD.I2S.Master; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MODE_CONFIG_Register use record + MODE at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Reception (RX) enable. + type RXEN_RXEN_Field is + (-- Reception disabled and now data will be written to the RXD.PTR address. + Disabled, + -- Reception enabled. + Enabled) + with Size => 1; + for RXEN_RXEN_Field use + (Disabled => 0, + Enabled => 1); + + -- Reception (RX) enable. + type RXEN_CONFIG_Register is record + -- Reception (RX) enable. + RXEN : RXEN_RXEN_Field := NRF_SVD.I2S.Disabled; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RXEN_CONFIG_Register use record + RXEN at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Transmission (TX) enable. + type TXEN_TXEN_Field is + (-- Transmission disabled and now data will be read from the RXD.TXD address. + Disabled, + -- Transmission enabled. + Enabled) + with Size => 1; + for TXEN_TXEN_Field use + (Disabled => 0, + Enabled => 1); + + -- Transmission (TX) enable. + type TXEN_CONFIG_Register is record + -- Transmission (TX) enable. + TXEN : TXEN_TXEN_Field := NRF_SVD.I2S.Enabled; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TXEN_CONFIG_Register use record + TXEN at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Master clock generator enable. + type MCKEN_MCKEN_Field is + (-- Master clock generator disabled and PSEL.MCK not connected(available as +-- GPIO). + Disabled, + -- Master clock generator running and MCK output on PSEL.MCK. + Enabled) + with Size => 1; + for MCKEN_MCKEN_Field use + (Disabled => 0, + Enabled => 1); + + -- Master clock generator enable. + type MCKEN_CONFIG_Register is record + -- Master clock generator enable. + MCKEN : MCKEN_MCKEN_Field := NRF_SVD.I2S.Enabled; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MCKEN_CONFIG_Register use record + MCKEN at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- MCK / LRCK ratio. + type RATIO_RATIO_Field is + (-- LRCK = MCK / 32 + Val_32X, + -- LRCK = MCK / 48 + Val_48X, + -- LRCK = MCK / 64 + Val_64X, + -- LRCK = MCK / 96 + Val_96X, + -- LRCK = MCK / 128 + Val_128X, + -- LRCK = MCK / 192 + Val_192X, + -- LRCK = MCK / 256 + Val_256X, + -- LRCK = MCK / 384 + Val_384X, + -- LRCK = MCK / 512 + Val_512X) + with Size => 4; + for RATIO_RATIO_Field use + (Val_32X => 0, + Val_48X => 1, + Val_64X => 2, + Val_96X => 3, + Val_128X => 4, + Val_192X => 5, + Val_256X => 6, + Val_384X => 7, + Val_512X => 8); + + -- MCK / LRCK ratio. + type RATIO_CONFIG_Register is record + -- MCK / LRCK ratio. + RATIO : RATIO_RATIO_Field := NRF_SVD.I2S.Val_256X; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RATIO_CONFIG_Register use record + RATIO at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- Sample width. + type SWIDTH_SWIDTH_Field is + (-- 8 bit. + Val_8Bit, + -- 16 bit. + Val_16Bit, + -- 24 bit. + Val_24Bit) + with Size => 2; + for SWIDTH_SWIDTH_Field use + (Val_8Bit => 0, + Val_16Bit => 1, + Val_24Bit => 2); + + -- Sample width. + type SWIDTH_CONFIG_Register is record + -- Sample width. + SWIDTH : SWIDTH_SWIDTH_Field := NRF_SVD.I2S.Val_16Bit; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SWIDTH_CONFIG_Register use record + SWIDTH at 0 range 0 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + -- Alignment of sample within a frame. + type ALIGN_ALIGN_Field is + (-- Left-aligned. + Left, + -- Right-aligned. + Right) + with Size => 1; + for ALIGN_ALIGN_Field use + (Left => 0, + Right => 1); + + -- Alignment of sample within a frame. + type ALIGN_CONFIG_Register is record + -- Alignment of sample within a frame. + ALIGN : ALIGN_ALIGN_Field := NRF_SVD.I2S.Left; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ALIGN_CONFIG_Register use record + ALIGN at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Frame format. + type FORMAT_FORMAT_Field is + (-- Original I2S format. + I2S, + -- Alternate (left- or right-aligned) format. + Aligned) + with Size => 1; + for FORMAT_FORMAT_Field use + (I2S => 0, + Aligned => 1); + + -- Frame format. + type FORMAT_CONFIG_Register is record + -- Frame format. + FORMAT : FORMAT_FORMAT_Field := NRF_SVD.I2S.I2S; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FORMAT_CONFIG_Register use record + FORMAT at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Enable channels. + type CHANNELS_CHANNELS_Field is + (-- Stereo. + Stereo, + -- Left only. + Left, + -- Right only. + Right) + with Size => 2; + for CHANNELS_CHANNELS_Field use + (Stereo => 0, + Left => 1, + Right => 2); + + -- Enable channels. + type CHANNELS_CONFIG_Register is record + -- Enable channels. + CHANNELS : CHANNELS_CHANNELS_Field := NRF_SVD.I2S.Stereo; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CHANNELS_CONFIG_Register use record + CHANNELS at 0 range 0 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + -- Unspecified + type CONFIG_Cluster is record + -- I2S mode. + MODE : aliased MODE_CONFIG_Register; + -- Reception (RX) enable. + RXEN : aliased RXEN_CONFIG_Register; + -- Transmission (TX) enable. + TXEN : aliased TXEN_CONFIG_Register; + -- Master clock generator enable. + MCKEN : aliased MCKEN_CONFIG_Register; + -- Master clock generator frequency. + MCKFREQ : aliased HAL.UInt32; + -- MCK / LRCK ratio. + RATIO : aliased RATIO_CONFIG_Register; + -- Sample width. + SWIDTH : aliased SWIDTH_CONFIG_Register; + -- Alignment of sample within a frame. + ALIGN : aliased ALIGN_CONFIG_Register; + -- Frame format. + FORMAT : aliased FORMAT_CONFIG_Register; + -- Enable channels. + CHANNELS : aliased CHANNELS_CONFIG_Register; + end record + with Size => 320; + + for CONFIG_Cluster use record + MODE at 16#0# range 0 .. 31; + RXEN at 16#4# range 0 .. 31; + TXEN at 16#8# range 0 .. 31; + MCKEN at 16#C# range 0 .. 31; + MCKFREQ at 16#10# range 0 .. 31; + RATIO at 16#14# range 0 .. 31; + SWIDTH at 16#18# range 0 .. 31; + ALIGN at 16#1C# range 0 .. 31; + FORMAT at 16#20# range 0 .. 31; + CHANNELS at 16#24# range 0 .. 31; + end record; + + ----------------------------- + -- RXD cluster's Registers -- + ----------------------------- + + -- Unspecified + type RXD_Cluster is record + -- Receive buffer RAM start address. + PTR : aliased HAL.UInt32; + end record + with Size => 32; + + for RXD_Cluster use record + PTR at 0 range 0 .. 31; + end record; + + ----------------------------- + -- TXD cluster's Registers -- + ----------------------------- + + -- Unspecified + type TXD_Cluster is record + -- Transmit buffer RAM start address. + PTR : aliased HAL.UInt32; + end record + with Size => 32; + + for TXD_Cluster use record + PTR at 0 range 0 .. 31; + end record; + + ------------------------------- + -- RXTXD cluster's Registers -- + ------------------------------- + + subtype MAXCNT_RXTXD_MAXCNT_Field is HAL.UInt14; + + -- Size of RXD and TXD buffers. + type MAXCNT_RXTXD_Register is record + -- Size of RXD and TXD buffers in number of 32 bit words. + MAXCNT : MAXCNT_RXTXD_MAXCNT_Field := 16#0#; + -- unspecified + Reserved_14_31 : HAL.UInt18 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MAXCNT_RXTXD_Register use record + MAXCNT at 0 range 0 .. 13; + Reserved_14_31 at 0 range 14 .. 31; + end record; + + -- Unspecified + type RXTXD_Cluster is record + -- Size of RXD and TXD buffers. + MAXCNT : aliased MAXCNT_RXTXD_Register; + end record + with Size => 32; + + for RXTXD_Cluster use record + MAXCNT at 0 range 0 .. 31; + end record; + + ------------------------------ + -- PSEL cluster's Registers -- + ------------------------------ + + subtype MCK_PSEL_PIN_Field is HAL.UInt5; + + -- Connection + type MCK_CONNECT_Field is + (-- Connect + Connected, + -- Disconnect + Disconnected) + with Size => 1; + for MCK_CONNECT_Field use + (Connected => 0, + Disconnected => 1); + + -- Pin select for MCK signal. + type MCK_PSEL_Register is record + -- Pin number + PIN : MCK_PSEL_PIN_Field := 16#1F#; + -- unspecified + Reserved_5_30 : HAL.UInt26 := 16#3FFFFFF#; + -- Connection + CONNECT : MCK_CONNECT_Field := NRF_SVD.I2S.Disconnected; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MCK_PSEL_Register use record + PIN at 0 range 0 .. 4; + Reserved_5_30 at 0 range 5 .. 30; + CONNECT at 0 range 31 .. 31; + end record; + + subtype SCK_PSEL_PIN_Field is HAL.UInt5; + + -- Connection + type SCK_CONNECT_Field is + (-- Connect + Connected, + -- Disconnect + Disconnected) + with Size => 1; + for SCK_CONNECT_Field use + (Connected => 0, + Disconnected => 1); + + -- Pin select for SCK signal. + type SCK_PSEL_Register is record + -- Pin number + PIN : SCK_PSEL_PIN_Field := 16#1F#; + -- unspecified + Reserved_5_30 : HAL.UInt26 := 16#3FFFFFF#; + -- Connection + CONNECT : SCK_CONNECT_Field := NRF_SVD.I2S.Disconnected; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SCK_PSEL_Register use record + PIN at 0 range 0 .. 4; + Reserved_5_30 at 0 range 5 .. 30; + CONNECT at 0 range 31 .. 31; + end record; + + subtype LRCK_PSEL_PIN_Field is HAL.UInt5; + + -- Connection + type LRCK_CONNECT_Field is + (-- Connect + Connected, + -- Disconnect + Disconnected) + with Size => 1; + for LRCK_CONNECT_Field use + (Connected => 0, + Disconnected => 1); + + -- Pin select for LRCK signal. + type LRCK_PSEL_Register is record + -- Pin number + PIN : LRCK_PSEL_PIN_Field := 16#1F#; + -- unspecified + Reserved_5_30 : HAL.UInt26 := 16#3FFFFFF#; + -- Connection + CONNECT : LRCK_CONNECT_Field := NRF_SVD.I2S.Disconnected; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for LRCK_PSEL_Register use record + PIN at 0 range 0 .. 4; + Reserved_5_30 at 0 range 5 .. 30; + CONNECT at 0 range 31 .. 31; + end record; + + subtype SDIN_PSEL_PIN_Field is HAL.UInt5; + + -- Connection + type SDIN_CONNECT_Field is + (-- Connect + Connected, + -- Disconnect + Disconnected) + with Size => 1; + for SDIN_CONNECT_Field use + (Connected => 0, + Disconnected => 1); + + -- Pin select for SDIN signal. + type SDIN_PSEL_Register is record + -- Pin number + PIN : SDIN_PSEL_PIN_Field := 16#1F#; + -- unspecified + Reserved_5_30 : HAL.UInt26 := 16#3FFFFFF#; + -- Connection + CONNECT : SDIN_CONNECT_Field := NRF_SVD.I2S.Disconnected; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SDIN_PSEL_Register use record + PIN at 0 range 0 .. 4; + Reserved_5_30 at 0 range 5 .. 30; + CONNECT at 0 range 31 .. 31; + end record; + + subtype SDOUT_PSEL_PIN_Field is HAL.UInt5; + + -- Connection + type SDOUT_CONNECT_Field is + (-- Connect + Connected, + -- Disconnect + Disconnected) + with Size => 1; + for SDOUT_CONNECT_Field use + (Connected => 0, + Disconnected => 1); + + -- Pin select for SDOUT signal. + type SDOUT_PSEL_Register is record + -- Pin number + PIN : SDOUT_PSEL_PIN_Field := 16#1F#; + -- unspecified + Reserved_5_30 : HAL.UInt26 := 16#3FFFFFF#; + -- Connection + CONNECT : SDOUT_CONNECT_Field := NRF_SVD.I2S.Disconnected; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SDOUT_PSEL_Register use record + PIN at 0 range 0 .. 4; + Reserved_5_30 at 0 range 5 .. 30; + CONNECT at 0 range 31 .. 31; + end record; + + -- Unspecified + type PSEL_Cluster is record + -- Pin select for MCK signal. + MCK : aliased MCK_PSEL_Register; + -- Pin select for SCK signal. + SCK : aliased SCK_PSEL_Register; + -- Pin select for LRCK signal. + LRCK : aliased LRCK_PSEL_Register; + -- Pin select for SDIN signal. + SDIN : aliased SDIN_PSEL_Register; + -- Pin select for SDOUT signal. + SDOUT : aliased SDOUT_PSEL_Register; + end record + with Size => 160; + + for PSEL_Cluster use record + MCK at 16#0# range 0 .. 31; + SCK at 16#4# range 0 .. 31; + LRCK at 16#8# range 0 .. 31; + SDIN at 16#C# range 0 .. 31; + SDOUT at 16#10# range 0 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Inter-IC Sound + type I2S_Peripheral is record + -- Starts continuous I2S transfer. Also starts MCK generator when this + -- is enabled. + TASKS_START : aliased HAL.UInt32; + -- Stops I2S transfer. Also stops MCK generator. Triggering this task + -- will cause the {event:STOPPED} event to be generated. + TASKS_STOP : aliased HAL.UInt32; + -- The RXD.PTR register has been copied to internal double-buffers. When + -- the I2S module is started and RX is enabled, this event will be + -- generated for every RXTXD.MAXCNT words that are received on the SDIN + -- pin. + EVENTS_RXPTRUPD : aliased HAL.UInt32; + -- I2S transfer stopped. + EVENTS_STOPPED : aliased HAL.UInt32; + -- The TDX.PTR register has been copied to internal double-buffers. When + -- the I2S module is started and TX is enabled, this event will be + -- generated for every RXTXD.MAXCNT words that are sent on the SDOUT + -- pin. + EVENTS_TXPTRUPD : aliased HAL.UInt32; + -- Enable or disable interrupt + INTEN : aliased INTEN_Register; + -- Enable interrupt + INTENSET : aliased INTENSET_Register; + -- Disable interrupt + INTENCLR : aliased INTENCLR_Register; + -- Enable I2S module. + ENABLE : aliased ENABLE_Register; + -- Unspecified + CONFIG : aliased CONFIG_Cluster; + -- Unspecified + RXD : aliased RXD_Cluster; + -- Unspecified + TXD : aliased TXD_Cluster; + -- Unspecified + RXTXD : aliased RXTXD_Cluster; + -- Unspecified + PSEL : aliased PSEL_Cluster; + end record + with Volatile; + + for I2S_Peripheral use record + TASKS_START at 16#0# range 0 .. 31; + TASKS_STOP at 16#4# range 0 .. 31; + EVENTS_RXPTRUPD at 16#104# range 0 .. 31; + EVENTS_STOPPED at 16#108# range 0 .. 31; + EVENTS_TXPTRUPD at 16#114# range 0 .. 31; + INTEN at 16#300# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + ENABLE at 16#500# range 0 .. 31; + CONFIG at 16#504# range 0 .. 319; + RXD at 16#538# range 0 .. 31; + TXD at 16#540# range 0 .. 31; + RXTXD at 16#550# range 0 .. 31; + PSEL at 16#560# range 0 .. 159; + end record; + + -- Inter-IC Sound + I2S_Periph : aliased I2S_Peripheral + with Import, Address => I2S_Base; + +end NRF_SVD.I2S; diff --git a/arch/ARM/Nordic/svd/nrf52/nrf_svd-lpcomp.ads b/arch/ARM/Nordic/svd/nrf52/nrf_svd-lpcomp.ads new file mode 100644 index 000000000..3d2c21603 --- /dev/null +++ b/arch/ARM/Nordic/svd/nrf52/nrf_svd-lpcomp.ads @@ -0,0 +1,674 @@ +-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- 2. Redistributions in binary form, except as embedded into a Nordic +-- Semiconductor ASA integrated circuit in a product or a software update for +-- such product, must reproduce the above copyright notice, this list of +-- conditions and the following disclaimer in the documentation and/or other +-- materials provided with the distribution. +-- +-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from this +-- software without specific prior written permission. +-- +-- 4. This software, with or without modification, must only be used with a +-- Nordic Semiconductor ASA integrated circuit. +-- +-- 5. Any software provided in binary form under this license must not be reverse +-- engineered, decompiled, modified and/or disassembled. +-- +-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +-- OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + +-- This spec has been automatically generated from nrf52.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package NRF_SVD.LPCOMP is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Shortcut between READY event and SAMPLE task + type SHORTS_READY_SAMPLE_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_READY_SAMPLE_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut between READY event and STOP task + type SHORTS_READY_STOP_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_READY_STOP_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut between DOWN event and STOP task + type SHORTS_DOWN_STOP_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_DOWN_STOP_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut between UP event and STOP task + type SHORTS_UP_STOP_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_UP_STOP_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut between CROSS event and STOP task + type SHORTS_CROSS_STOP_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_CROSS_STOP_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut register + type SHORTS_Register is record + -- Shortcut between READY event and SAMPLE task + READY_SAMPLE : SHORTS_READY_SAMPLE_Field := NRF_SVD.LPCOMP.Disabled; + -- Shortcut between READY event and STOP task + READY_STOP : SHORTS_READY_STOP_Field := NRF_SVD.LPCOMP.Disabled; + -- Shortcut between DOWN event and STOP task + DOWN_STOP : SHORTS_DOWN_STOP_Field := NRF_SVD.LPCOMP.Disabled; + -- Shortcut between UP event and STOP task + UP_STOP : SHORTS_UP_STOP_Field := NRF_SVD.LPCOMP.Disabled; + -- Shortcut between CROSS event and STOP task + CROSS_STOP : SHORTS_CROSS_STOP_Field := NRF_SVD.LPCOMP.Disabled; + -- unspecified + Reserved_5_31 : HAL.UInt27 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SHORTS_Register use record + READY_SAMPLE at 0 range 0 .. 0; + READY_STOP at 0 range 1 .. 1; + DOWN_STOP at 0 range 2 .. 2; + UP_STOP at 0 range 3 .. 3; + CROSS_STOP at 0 range 4 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + -- Write '1' to Enable interrupt for READY event + type INTENSET_READY_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_READY_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for READY event + type INTENSET_READY_Field_1 is + (-- Reset value for the field + Intenset_Ready_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_READY_Field_1 use + (Intenset_Ready_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for DOWN event + type INTENSET_DOWN_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_DOWN_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for DOWN event + type INTENSET_DOWN_Field_1 is + (-- Reset value for the field + Intenset_Down_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_DOWN_Field_1 use + (Intenset_Down_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for UP event + type INTENSET_UP_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_UP_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for UP event + type INTENSET_UP_Field_1 is + (-- Reset value for the field + Intenset_Up_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_UP_Field_1 use + (Intenset_Up_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for CROSS event + type INTENSET_CROSS_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_CROSS_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for CROSS event + type INTENSET_CROSS_Field_1 is + (-- Reset value for the field + Intenset_Cross_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_CROSS_Field_1 use + (Intenset_Cross_Field_Reset => 0, + Set => 1); + + -- Enable interrupt + type INTENSET_Register is record + -- Write '1' to Enable interrupt for READY event + READY : INTENSET_READY_Field_1 := Intenset_Ready_Field_Reset; + -- Write '1' to Enable interrupt for DOWN event + DOWN : INTENSET_DOWN_Field_1 := Intenset_Down_Field_Reset; + -- Write '1' to Enable interrupt for UP event + UP : INTENSET_UP_Field_1 := Intenset_Up_Field_Reset; + -- Write '1' to Enable interrupt for CROSS event + CROSS : INTENSET_CROSS_Field_1 := Intenset_Cross_Field_Reset; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENSET_Register use record + READY at 0 range 0 .. 0; + DOWN at 0 range 1 .. 1; + UP at 0 range 2 .. 2; + CROSS at 0 range 3 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- Write '1' to Disable interrupt for READY event + type INTENCLR_READY_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_READY_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for READY event + type INTENCLR_READY_Field_1 is + (-- Reset value for the field + Intenclr_Ready_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_READY_Field_1 use + (Intenclr_Ready_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for DOWN event + type INTENCLR_DOWN_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_DOWN_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for DOWN event + type INTENCLR_DOWN_Field_1 is + (-- Reset value for the field + Intenclr_Down_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_DOWN_Field_1 use + (Intenclr_Down_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for UP event + type INTENCLR_UP_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_UP_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for UP event + type INTENCLR_UP_Field_1 is + (-- Reset value for the field + Intenclr_Up_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_UP_Field_1 use + (Intenclr_Up_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for CROSS event + type INTENCLR_CROSS_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_CROSS_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for CROSS event + type INTENCLR_CROSS_Field_1 is + (-- Reset value for the field + Intenclr_Cross_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_CROSS_Field_1 use + (Intenclr_Cross_Field_Reset => 0, + Clear => 1); + + -- Disable interrupt + type INTENCLR_Register is record + -- Write '1' to Disable interrupt for READY event + READY : INTENCLR_READY_Field_1 := Intenclr_Ready_Field_Reset; + -- Write '1' to Disable interrupt for DOWN event + DOWN : INTENCLR_DOWN_Field_1 := Intenclr_Down_Field_Reset; + -- Write '1' to Disable interrupt for UP event + UP : INTENCLR_UP_Field_1 := Intenclr_Up_Field_Reset; + -- Write '1' to Disable interrupt for CROSS event + CROSS : INTENCLR_CROSS_Field_1 := Intenclr_Cross_Field_Reset; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENCLR_Register use record + READY at 0 range 0 .. 0; + DOWN at 0 range 1 .. 1; + UP at 0 range 2 .. 2; + CROSS at 0 range 3 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- Result of last compare. Decision point SAMPLE task. + type RESULT_RESULT_Field is + (-- Input voltage is below the reference threshold (VIN+ < VIN-). + Below, + -- Input voltage is above the reference threshold (VIN+ > VIN-). + Above) + with Size => 1; + for RESULT_RESULT_Field use + (Below => 0, + Above => 1); + + -- Compare result + type RESULT_Register is record + -- Read-only. Result of last compare. Decision point SAMPLE task. + RESULT : RESULT_RESULT_Field; + -- unspecified + Reserved_1_31 : HAL.UInt31; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RESULT_Register use record + RESULT at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Enable or disable LPCOMP + type ENABLE_ENABLE_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 2; + for ENABLE_ENABLE_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable LPCOMP + type ENABLE_Register is record + -- Enable or disable LPCOMP + ENABLE : ENABLE_ENABLE_Field := NRF_SVD.LPCOMP.Disabled; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ENABLE_Register use record + ENABLE at 0 range 0 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + -- Analog pin select + type PSEL_PSEL_Field is + (-- AIN0 selected as analog input + Analoginput0, + -- AIN1 selected as analog input + Analoginput1, + -- AIN2 selected as analog input + Analoginput2, + -- AIN3 selected as analog input + Analoginput3, + -- AIN4 selected as analog input + Analoginput4, + -- AIN5 selected as analog input + Analoginput5, + -- AIN6 selected as analog input + Analoginput6, + -- AIN7 selected as analog input + Analoginput7) + with Size => 3; + for PSEL_PSEL_Field use + (Analoginput0 => 0, + Analoginput1 => 1, + Analoginput2 => 2, + Analoginput3 => 3, + Analoginput4 => 4, + Analoginput5 => 5, + Analoginput6 => 6, + Analoginput7 => 7); + + -- Input pin select + type PSEL_Register is record + -- Analog pin select + PSEL : PSEL_PSEL_Field := NRF_SVD.LPCOMP.Analoginput0; + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PSEL_Register use record + PSEL at 0 range 0 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + -- Reference select + type REFSEL_REFSEL_Field is + (-- VDD * 1/8 selected as reference + Ref1_8Vdd, + -- VDD * 2/8 selected as reference + Ref2_8Vdd, + -- VDD * 3/8 selected as reference + Ref3_8Vdd, + -- VDD * 4/8 selected as reference + Ref4_8Vdd, + -- VDD * 5/8 selected as reference + Ref5_8Vdd, + -- VDD * 6/8 selected as reference + Ref6_8Vdd, + -- VDD * 7/8 selected as reference + Ref7_8Vdd, + -- External analog reference selected + Aref, + -- VDD * 1/16 selected as reference + Ref1_16Vdd, + -- VDD * 3/16 selected as reference + Ref3_16Vdd, + -- VDD * 5/16 selected as reference + Ref5_16Vdd, + -- VDD * 7/16 selected as reference + Ref7_16Vdd, + -- VDD * 9/16 selected as reference + Ref9_16Vdd, + -- VDD * 11/16 selected as reference + Ref11_16Vdd, + -- VDD * 13/16 selected as reference + Ref13_16Vdd, + -- VDD * 15/16 selected as reference + Ref15_16Vdd) + with Size => 4; + for REFSEL_REFSEL_Field use + (Ref1_8Vdd => 0, + Ref2_8Vdd => 1, + Ref3_8Vdd => 2, + Ref4_8Vdd => 3, + Ref5_8Vdd => 4, + Ref6_8Vdd => 5, + Ref7_8Vdd => 6, + Aref => 7, + Ref1_16Vdd => 8, + Ref3_16Vdd => 9, + Ref5_16Vdd => 10, + Ref7_16Vdd => 11, + Ref9_16Vdd => 12, + Ref11_16Vdd => 13, + Ref13_16Vdd => 14, + Ref15_16Vdd => 15); + + -- Reference select + type REFSEL_Register is record + -- Reference select + REFSEL : REFSEL_REFSEL_Field := NRF_SVD.LPCOMP.Ref5_8Vdd; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for REFSEL_Register use record + REFSEL at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- External analog reference select + type EXTREFSEL_EXTREFSEL_Field is + (-- Use AIN0 as external analog reference + Analogreference0, + -- Use AIN1 as external analog reference + Analogreference1) + with Size => 1; + for EXTREFSEL_EXTREFSEL_Field use + (Analogreference0 => 0, + Analogreference1 => 1); + + -- External reference select + type EXTREFSEL_Register is record + -- External analog reference select + EXTREFSEL : EXTREFSEL_EXTREFSEL_Field := + NRF_SVD.LPCOMP.Analogreference0; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EXTREFSEL_Register use record + EXTREFSEL at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Analog detect configuration + type ANADETECT_ANADETECT_Field is + (-- Generate ANADETECT on crossing, both upward crossing and downward crossing + Cross, + -- Generate ANADETECT on upward crossing only + Up, + -- Generate ANADETECT on downward crossing only + Down) + with Size => 2; + for ANADETECT_ANADETECT_Field use + (Cross => 0, + Up => 1, + Down => 2); + + -- Analog detect configuration + type ANADETECT_Register is record + -- Analog detect configuration + ANADETECT : ANADETECT_ANADETECT_Field := NRF_SVD.LPCOMP.Cross; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ANADETECT_Register use record + ANADETECT at 0 range 0 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + -- Comparator hysteresis enable + type HYST_HYST_Field is + (-- Comparator hysteresis disabled + Nohyst, + -- Comparator hysteresis disabled (typ. 50 mV) + Hyst50MV) + with Size => 1; + for HYST_HYST_Field use + (Nohyst => 0, + Hyst50MV => 1); + + -- Comparator hysteresis enable + type HYST_Register is record + -- Comparator hysteresis enable + HYST : HYST_HYST_Field := NRF_SVD.LPCOMP.Nohyst; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for HYST_Register use record + HYST at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Low Power Comparator + type LPCOMP_Peripheral is record + -- Start comparator + TASKS_START : aliased HAL.UInt32; + -- Stop comparator + TASKS_STOP : aliased HAL.UInt32; + -- Sample comparator value + TASKS_SAMPLE : aliased HAL.UInt32; + -- LPCOMP is ready and output is valid + EVENTS_READY : aliased HAL.UInt32; + -- Downward crossing + EVENTS_DOWN : aliased HAL.UInt32; + -- Upward crossing + EVENTS_UP : aliased HAL.UInt32; + -- Downward or upward crossing + EVENTS_CROSS : aliased HAL.UInt32; + -- Shortcut register + SHORTS : aliased SHORTS_Register; + -- Enable interrupt + INTENSET : aliased INTENSET_Register; + -- Disable interrupt + INTENCLR : aliased INTENCLR_Register; + -- Compare result + RESULT : aliased RESULT_Register; + -- Enable LPCOMP + ENABLE : aliased ENABLE_Register; + -- Input pin select + PSEL : aliased PSEL_Register; + -- Reference select + REFSEL : aliased REFSEL_Register; + -- External reference select + EXTREFSEL : aliased EXTREFSEL_Register; + -- Analog detect configuration + ANADETECT : aliased ANADETECT_Register; + -- Comparator hysteresis enable + HYST : aliased HYST_Register; + end record + with Volatile; + + for LPCOMP_Peripheral use record + TASKS_START at 16#0# range 0 .. 31; + TASKS_STOP at 16#4# range 0 .. 31; + TASKS_SAMPLE at 16#8# range 0 .. 31; + EVENTS_READY at 16#100# range 0 .. 31; + EVENTS_DOWN at 16#104# range 0 .. 31; + EVENTS_UP at 16#108# range 0 .. 31; + EVENTS_CROSS at 16#10C# range 0 .. 31; + SHORTS at 16#200# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + RESULT at 16#400# range 0 .. 31; + ENABLE at 16#500# range 0 .. 31; + PSEL at 16#504# range 0 .. 31; + REFSEL at 16#508# range 0 .. 31; + EXTREFSEL at 16#50C# range 0 .. 31; + ANADETECT at 16#520# range 0 .. 31; + HYST at 16#538# range 0 .. 31; + end record; + + -- Low Power Comparator + LPCOMP_Periph : aliased LPCOMP_Peripheral + with Import, Address => LPCOMP_Base; + +end NRF_SVD.LPCOMP; diff --git a/arch/ARM/Nordic/svd/nrf52/nrf_svd-mwu.ads b/arch/ARM/Nordic/svd/nrf52/nrf_svd-mwu.ads new file mode 100644 index 000000000..a4d59e38b --- /dev/null +++ b/arch/ARM/Nordic/svd/nrf52/nrf_svd-mwu.ads @@ -0,0 +1,2848 @@ +-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- 2. Redistributions in binary form, except as embedded into a Nordic +-- Semiconductor ASA integrated circuit in a product or a software update for +-- such product, must reproduce the above copyright notice, this list of +-- conditions and the following disclaimer in the documentation and/or other +-- materials provided with the distribution. +-- +-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from this +-- software without specific prior written permission. +-- +-- 4. This software, with or without modification, must only be used with a +-- Nordic Semiconductor ASA integrated circuit. +-- +-- 5. Any software provided in binary form under this license must not be reverse +-- engineered, decompiled, modified and/or disassembled. +-- +-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +-- OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + +-- This spec has been automatically generated from nrf52.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package NRF_SVD.MWU is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + --------------------------------------- + -- EVENTS_REGION cluster's Registers -- + --------------------------------------- + + -- Unspecified + type EVENTS_REGION_Cluster is record + -- Description cluster[0]: Write access to region 0 detected + WA : aliased HAL.UInt32; + -- Description cluster[0]: Read access to region 0 detected + RA : aliased HAL.UInt32; + end record + with Size => 64; + + for EVENTS_REGION_Cluster use record + WA at 16#0# range 0 .. 31; + RA at 16#4# range 0 .. 31; + end record; + + -- Unspecified + type EVENTS_REGION_Clusters is array (0 .. 3) of EVENTS_REGION_Cluster; + + ---------------------------------------- + -- EVENTS_PREGION cluster's Registers -- + ---------------------------------------- + + -- Unspecified + type EVENTS_PREGION_Cluster is record + -- Description cluster[0]: Write access to peripheral region 0 detected + WA : aliased HAL.UInt32; + -- Description cluster[0]: Read access to peripheral region 0 detected + RA : aliased HAL.UInt32; + end record + with Size => 64; + + for EVENTS_PREGION_Cluster use record + WA at 16#0# range 0 .. 31; + RA at 16#4# range 0 .. 31; + end record; + + -- Unspecified + type EVENTS_PREGION_Clusters is array (0 .. 1) of EVENTS_PREGION_Cluster; + + -- Enable or disable interrupt for REGION[0].WA event + type INTEN_REGION0WA_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_REGION0WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for REGION[0].RA event + type INTEN_REGION0RA_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_REGION0RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for REGION[1].WA event + type INTEN_REGION1WA_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_REGION1WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for REGION[1].RA event + type INTEN_REGION1RA_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_REGION1RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for REGION[2].WA event + type INTEN_REGION2WA_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_REGION2WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for REGION[2].RA event + type INTEN_REGION2RA_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_REGION2RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for REGION[3].WA event + type INTEN_REGION3WA_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_REGION3WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for REGION[3].RA event + type INTEN_REGION3RA_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_REGION3RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for PREGION[0].WA event + type INTEN_PREGION0WA_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_PREGION0WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for PREGION[0].RA event + type INTEN_PREGION0RA_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_PREGION0RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for PREGION[1].WA event + type INTEN_PREGION1WA_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_PREGION1WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for PREGION[1].RA event + type INTEN_PREGION1RA_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_PREGION1RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt + type INTEN_Register is record + -- Enable or disable interrupt for REGION[0].WA event + REGION0WA : INTEN_REGION0WA_Field := NRF_SVD.MWU.Disabled; + -- Enable or disable interrupt for REGION[0].RA event + REGION0RA : INTEN_REGION0RA_Field := NRF_SVD.MWU.Disabled; + -- Enable or disable interrupt for REGION[1].WA event + REGION1WA : INTEN_REGION1WA_Field := NRF_SVD.MWU.Disabled; + -- Enable or disable interrupt for REGION[1].RA event + REGION1RA : INTEN_REGION1RA_Field := NRF_SVD.MWU.Disabled; + -- Enable or disable interrupt for REGION[2].WA event + REGION2WA : INTEN_REGION2WA_Field := NRF_SVD.MWU.Disabled; + -- Enable or disable interrupt for REGION[2].RA event + REGION2RA : INTEN_REGION2RA_Field := NRF_SVD.MWU.Disabled; + -- Enable or disable interrupt for REGION[3].WA event + REGION3WA : INTEN_REGION3WA_Field := NRF_SVD.MWU.Disabled; + -- Enable or disable interrupt for REGION[3].RA event + REGION3RA : INTEN_REGION3RA_Field := NRF_SVD.MWU.Disabled; + -- unspecified + Reserved_8_23 : HAL.UInt16 := 16#0#; + -- Enable or disable interrupt for PREGION[0].WA event + PREGION0WA : INTEN_PREGION0WA_Field := NRF_SVD.MWU.Disabled; + -- Enable or disable interrupt for PREGION[0].RA event + PREGION0RA : INTEN_PREGION0RA_Field := NRF_SVD.MWU.Disabled; + -- Enable or disable interrupt for PREGION[1].WA event + PREGION1WA : INTEN_PREGION1WA_Field := NRF_SVD.MWU.Disabled; + -- Enable or disable interrupt for PREGION[1].RA event + PREGION1RA : INTEN_PREGION1RA_Field := NRF_SVD.MWU.Disabled; + -- unspecified + Reserved_28_31 : HAL.UInt4 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTEN_Register use record + REGION0WA at 0 range 0 .. 0; + REGION0RA at 0 range 1 .. 1; + REGION1WA at 0 range 2 .. 2; + REGION1RA at 0 range 3 .. 3; + REGION2WA at 0 range 4 .. 4; + REGION2RA at 0 range 5 .. 5; + REGION3WA at 0 range 6 .. 6; + REGION3RA at 0 range 7 .. 7; + Reserved_8_23 at 0 range 8 .. 23; + PREGION0WA at 0 range 24 .. 24; + PREGION0RA at 0 range 25 .. 25; + PREGION1WA at 0 range 26 .. 26; + PREGION1RA at 0 range 27 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + -- Write '1' to Enable interrupt for REGION[0].WA event + type INTENSET_REGION0WA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_REGION0WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for REGION[0].WA event + type INTENSET_REGION0WA_Field_1 is + (-- Reset value for the field + Intenset_Region0Wa_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_REGION0WA_Field_1 use + (Intenset_Region0Wa_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for REGION[0].RA event + type INTENSET_REGION0RA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_REGION0RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for REGION[0].RA event + type INTENSET_REGION0RA_Field_1 is + (-- Reset value for the field + Intenset_Region0Ra_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_REGION0RA_Field_1 use + (Intenset_Region0Ra_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for REGION[1].WA event + type INTENSET_REGION1WA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_REGION1WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for REGION[1].WA event + type INTENSET_REGION1WA_Field_1 is + (-- Reset value for the field + Intenset_Region1Wa_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_REGION1WA_Field_1 use + (Intenset_Region1Wa_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for REGION[1].RA event + type INTENSET_REGION1RA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_REGION1RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for REGION[1].RA event + type INTENSET_REGION1RA_Field_1 is + (-- Reset value for the field + Intenset_Region1Ra_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_REGION1RA_Field_1 use + (Intenset_Region1Ra_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for REGION[2].WA event + type INTENSET_REGION2WA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_REGION2WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for REGION[2].WA event + type INTENSET_REGION2WA_Field_1 is + (-- Reset value for the field + Intenset_Region2Wa_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_REGION2WA_Field_1 use + (Intenset_Region2Wa_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for REGION[2].RA event + type INTENSET_REGION2RA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_REGION2RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for REGION[2].RA event + type INTENSET_REGION2RA_Field_1 is + (-- Reset value for the field + Intenset_Region2Ra_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_REGION2RA_Field_1 use + (Intenset_Region2Ra_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for REGION[3].WA event + type INTENSET_REGION3WA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_REGION3WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for REGION[3].WA event + type INTENSET_REGION3WA_Field_1 is + (-- Reset value for the field + Intenset_Region3Wa_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_REGION3WA_Field_1 use + (Intenset_Region3Wa_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for REGION[3].RA event + type INTENSET_REGION3RA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_REGION3RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for REGION[3].RA event + type INTENSET_REGION3RA_Field_1 is + (-- Reset value for the field + Intenset_Region3Ra_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_REGION3RA_Field_1 use + (Intenset_Region3Ra_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for PREGION[0].WA event + type INTENSET_PREGION0WA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_PREGION0WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for PREGION[0].WA event + type INTENSET_PREGION0WA_Field_1 is + (-- Reset value for the field + Intenset_Pregion0Wa_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_PREGION0WA_Field_1 use + (Intenset_Pregion0Wa_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for PREGION[0].RA event + type INTENSET_PREGION0RA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_PREGION0RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for PREGION[0].RA event + type INTENSET_PREGION0RA_Field_1 is + (-- Reset value for the field + Intenset_Pregion0Ra_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_PREGION0RA_Field_1 use + (Intenset_Pregion0Ra_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for PREGION[1].WA event + type INTENSET_PREGION1WA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_PREGION1WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for PREGION[1].WA event + type INTENSET_PREGION1WA_Field_1 is + (-- Reset value for the field + Intenset_Pregion1Wa_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_PREGION1WA_Field_1 use + (Intenset_Pregion1Wa_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for PREGION[1].RA event + type INTENSET_PREGION1RA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_PREGION1RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for PREGION[1].RA event + type INTENSET_PREGION1RA_Field_1 is + (-- Reset value for the field + Intenset_Pregion1Ra_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_PREGION1RA_Field_1 use + (Intenset_Pregion1Ra_Field_Reset => 0, + Set => 1); + + -- Enable interrupt + type INTENSET_Register is record + -- Write '1' to Enable interrupt for REGION[0].WA event + REGION0WA : INTENSET_REGION0WA_Field_1 := + Intenset_Region0Wa_Field_Reset; + -- Write '1' to Enable interrupt for REGION[0].RA event + REGION0RA : INTENSET_REGION0RA_Field_1 := + Intenset_Region0Ra_Field_Reset; + -- Write '1' to Enable interrupt for REGION[1].WA event + REGION1WA : INTENSET_REGION1WA_Field_1 := + Intenset_Region1Wa_Field_Reset; + -- Write '1' to Enable interrupt for REGION[1].RA event + REGION1RA : INTENSET_REGION1RA_Field_1 := + Intenset_Region1Ra_Field_Reset; + -- Write '1' to Enable interrupt for REGION[2].WA event + REGION2WA : INTENSET_REGION2WA_Field_1 := + Intenset_Region2Wa_Field_Reset; + -- Write '1' to Enable interrupt for REGION[2].RA event + REGION2RA : INTENSET_REGION2RA_Field_1 := + Intenset_Region2Ra_Field_Reset; + -- Write '1' to Enable interrupt for REGION[3].WA event + REGION3WA : INTENSET_REGION3WA_Field_1 := + Intenset_Region3Wa_Field_Reset; + -- Write '1' to Enable interrupt for REGION[3].RA event + REGION3RA : INTENSET_REGION3RA_Field_1 := + Intenset_Region3Ra_Field_Reset; + -- unspecified + Reserved_8_23 : HAL.UInt16 := 16#0#; + -- Write '1' to Enable interrupt for PREGION[0].WA event + PREGION0WA : INTENSET_PREGION0WA_Field_1 := + Intenset_Pregion0Wa_Field_Reset; + -- Write '1' to Enable interrupt for PREGION[0].RA event + PREGION0RA : INTENSET_PREGION0RA_Field_1 := + Intenset_Pregion0Ra_Field_Reset; + -- Write '1' to Enable interrupt for PREGION[1].WA event + PREGION1WA : INTENSET_PREGION1WA_Field_1 := + Intenset_Pregion1Wa_Field_Reset; + -- Write '1' to Enable interrupt for PREGION[1].RA event + PREGION1RA : INTENSET_PREGION1RA_Field_1 := + Intenset_Pregion1Ra_Field_Reset; + -- unspecified + Reserved_28_31 : HAL.UInt4 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENSET_Register use record + REGION0WA at 0 range 0 .. 0; + REGION0RA at 0 range 1 .. 1; + REGION1WA at 0 range 2 .. 2; + REGION1RA at 0 range 3 .. 3; + REGION2WA at 0 range 4 .. 4; + REGION2RA at 0 range 5 .. 5; + REGION3WA at 0 range 6 .. 6; + REGION3RA at 0 range 7 .. 7; + Reserved_8_23 at 0 range 8 .. 23; + PREGION0WA at 0 range 24 .. 24; + PREGION0RA at 0 range 25 .. 25; + PREGION1WA at 0 range 26 .. 26; + PREGION1RA at 0 range 27 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + -- Write '1' to Disable interrupt for REGION[0].WA event + type INTENCLR_REGION0WA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_REGION0WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for REGION[0].WA event + type INTENCLR_REGION0WA_Field_1 is + (-- Reset value for the field + Intenclr_Region0Wa_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_REGION0WA_Field_1 use + (Intenclr_Region0Wa_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for REGION[0].RA event + type INTENCLR_REGION0RA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_REGION0RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for REGION[0].RA event + type INTENCLR_REGION0RA_Field_1 is + (-- Reset value for the field + Intenclr_Region0Ra_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_REGION0RA_Field_1 use + (Intenclr_Region0Ra_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for REGION[1].WA event + type INTENCLR_REGION1WA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_REGION1WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for REGION[1].WA event + type INTENCLR_REGION1WA_Field_1 is + (-- Reset value for the field + Intenclr_Region1Wa_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_REGION1WA_Field_1 use + (Intenclr_Region1Wa_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for REGION[1].RA event + type INTENCLR_REGION1RA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_REGION1RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for REGION[1].RA event + type INTENCLR_REGION1RA_Field_1 is + (-- Reset value for the field + Intenclr_Region1Ra_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_REGION1RA_Field_1 use + (Intenclr_Region1Ra_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for REGION[2].WA event + type INTENCLR_REGION2WA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_REGION2WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for REGION[2].WA event + type INTENCLR_REGION2WA_Field_1 is + (-- Reset value for the field + Intenclr_Region2Wa_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_REGION2WA_Field_1 use + (Intenclr_Region2Wa_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for REGION[2].RA event + type INTENCLR_REGION2RA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_REGION2RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for REGION[2].RA event + type INTENCLR_REGION2RA_Field_1 is + (-- Reset value for the field + Intenclr_Region2Ra_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_REGION2RA_Field_1 use + (Intenclr_Region2Ra_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for REGION[3].WA event + type INTENCLR_REGION3WA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_REGION3WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for REGION[3].WA event + type INTENCLR_REGION3WA_Field_1 is + (-- Reset value for the field + Intenclr_Region3Wa_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_REGION3WA_Field_1 use + (Intenclr_Region3Wa_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for REGION[3].RA event + type INTENCLR_REGION3RA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_REGION3RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for REGION[3].RA event + type INTENCLR_REGION3RA_Field_1 is + (-- Reset value for the field + Intenclr_Region3Ra_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_REGION3RA_Field_1 use + (Intenclr_Region3Ra_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for PREGION[0].WA event + type INTENCLR_PREGION0WA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_PREGION0WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for PREGION[0].WA event + type INTENCLR_PREGION0WA_Field_1 is + (-- Reset value for the field + Intenclr_Pregion0Wa_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_PREGION0WA_Field_1 use + (Intenclr_Pregion0Wa_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for PREGION[0].RA event + type INTENCLR_PREGION0RA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_PREGION0RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for PREGION[0].RA event + type INTENCLR_PREGION0RA_Field_1 is + (-- Reset value for the field + Intenclr_Pregion0Ra_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_PREGION0RA_Field_1 use + (Intenclr_Pregion0Ra_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for PREGION[1].WA event + type INTENCLR_PREGION1WA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_PREGION1WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for PREGION[1].WA event + type INTENCLR_PREGION1WA_Field_1 is + (-- Reset value for the field + Intenclr_Pregion1Wa_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_PREGION1WA_Field_1 use + (Intenclr_Pregion1Wa_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for PREGION[1].RA event + type INTENCLR_PREGION1RA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_PREGION1RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for PREGION[1].RA event + type INTENCLR_PREGION1RA_Field_1 is + (-- Reset value for the field + Intenclr_Pregion1Ra_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_PREGION1RA_Field_1 use + (Intenclr_Pregion1Ra_Field_Reset => 0, + Clear => 1); + + -- Disable interrupt + type INTENCLR_Register is record + -- Write '1' to Disable interrupt for REGION[0].WA event + REGION0WA : INTENCLR_REGION0WA_Field_1 := + Intenclr_Region0Wa_Field_Reset; + -- Write '1' to Disable interrupt for REGION[0].RA event + REGION0RA : INTENCLR_REGION0RA_Field_1 := + Intenclr_Region0Ra_Field_Reset; + -- Write '1' to Disable interrupt for REGION[1].WA event + REGION1WA : INTENCLR_REGION1WA_Field_1 := + Intenclr_Region1Wa_Field_Reset; + -- Write '1' to Disable interrupt for REGION[1].RA event + REGION1RA : INTENCLR_REGION1RA_Field_1 := + Intenclr_Region1Ra_Field_Reset; + -- Write '1' to Disable interrupt for REGION[2].WA event + REGION2WA : INTENCLR_REGION2WA_Field_1 := + Intenclr_Region2Wa_Field_Reset; + -- Write '1' to Disable interrupt for REGION[2].RA event + REGION2RA : INTENCLR_REGION2RA_Field_1 := + Intenclr_Region2Ra_Field_Reset; + -- Write '1' to Disable interrupt for REGION[3].WA event + REGION3WA : INTENCLR_REGION3WA_Field_1 := + Intenclr_Region3Wa_Field_Reset; + -- Write '1' to Disable interrupt for REGION[3].RA event + REGION3RA : INTENCLR_REGION3RA_Field_1 := + Intenclr_Region3Ra_Field_Reset; + -- unspecified + Reserved_8_23 : HAL.UInt16 := 16#0#; + -- Write '1' to Disable interrupt for PREGION[0].WA event + PREGION0WA : INTENCLR_PREGION0WA_Field_1 := + Intenclr_Pregion0Wa_Field_Reset; + -- Write '1' to Disable interrupt for PREGION[0].RA event + PREGION0RA : INTENCLR_PREGION0RA_Field_1 := + Intenclr_Pregion0Ra_Field_Reset; + -- Write '1' to Disable interrupt for PREGION[1].WA event + PREGION1WA : INTENCLR_PREGION1WA_Field_1 := + Intenclr_Pregion1Wa_Field_Reset; + -- Write '1' to Disable interrupt for PREGION[1].RA event + PREGION1RA : INTENCLR_PREGION1RA_Field_1 := + Intenclr_Pregion1Ra_Field_Reset; + -- unspecified + Reserved_28_31 : HAL.UInt4 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENCLR_Register use record + REGION0WA at 0 range 0 .. 0; + REGION0RA at 0 range 1 .. 1; + REGION1WA at 0 range 2 .. 2; + REGION1RA at 0 range 3 .. 3; + REGION2WA at 0 range 4 .. 4; + REGION2RA at 0 range 5 .. 5; + REGION3WA at 0 range 6 .. 6; + REGION3RA at 0 range 7 .. 7; + Reserved_8_23 at 0 range 8 .. 23; + PREGION0WA at 0 range 24 .. 24; + PREGION0RA at 0 range 25 .. 25; + PREGION1WA at 0 range 26 .. 26; + PREGION1RA at 0 range 27 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + -- Enable or disable non-maskable interrupt for REGION[0].WA event + type NMIEN_REGION0WA_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for NMIEN_REGION0WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable non-maskable interrupt for REGION[0].RA event + type NMIEN_REGION0RA_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for NMIEN_REGION0RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable non-maskable interrupt for REGION[1].WA event + type NMIEN_REGION1WA_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for NMIEN_REGION1WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable non-maskable interrupt for REGION[1].RA event + type NMIEN_REGION1RA_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for NMIEN_REGION1RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable non-maskable interrupt for REGION[2].WA event + type NMIEN_REGION2WA_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for NMIEN_REGION2WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable non-maskable interrupt for REGION[2].RA event + type NMIEN_REGION2RA_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for NMIEN_REGION2RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable non-maskable interrupt for REGION[3].WA event + type NMIEN_REGION3WA_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for NMIEN_REGION3WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable non-maskable interrupt for REGION[3].RA event + type NMIEN_REGION3RA_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for NMIEN_REGION3RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable non-maskable interrupt for PREGION[0].WA event + type NMIEN_PREGION0WA_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for NMIEN_PREGION0WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable non-maskable interrupt for PREGION[0].RA event + type NMIEN_PREGION0RA_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for NMIEN_PREGION0RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable non-maskable interrupt for PREGION[1].WA event + type NMIEN_PREGION1WA_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for NMIEN_PREGION1WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable non-maskable interrupt for PREGION[1].RA event + type NMIEN_PREGION1RA_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for NMIEN_PREGION1RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable non-maskable interrupt + type NMIEN_Register is record + -- Enable or disable non-maskable interrupt for REGION[0].WA event + REGION0WA : NMIEN_REGION0WA_Field := NRF_SVD.MWU.Disabled; + -- Enable or disable non-maskable interrupt for REGION[0].RA event + REGION0RA : NMIEN_REGION0RA_Field := NRF_SVD.MWU.Disabled; + -- Enable or disable non-maskable interrupt for REGION[1].WA event + REGION1WA : NMIEN_REGION1WA_Field := NRF_SVD.MWU.Disabled; + -- Enable or disable non-maskable interrupt for REGION[1].RA event + REGION1RA : NMIEN_REGION1RA_Field := NRF_SVD.MWU.Disabled; + -- Enable or disable non-maskable interrupt for REGION[2].WA event + REGION2WA : NMIEN_REGION2WA_Field := NRF_SVD.MWU.Disabled; + -- Enable or disable non-maskable interrupt for REGION[2].RA event + REGION2RA : NMIEN_REGION2RA_Field := NRF_SVD.MWU.Disabled; + -- Enable or disable non-maskable interrupt for REGION[3].WA event + REGION3WA : NMIEN_REGION3WA_Field := NRF_SVD.MWU.Disabled; + -- Enable or disable non-maskable interrupt for REGION[3].RA event + REGION3RA : NMIEN_REGION3RA_Field := NRF_SVD.MWU.Disabled; + -- unspecified + Reserved_8_23 : HAL.UInt16 := 16#0#; + -- Enable or disable non-maskable interrupt for PREGION[0].WA event + PREGION0WA : NMIEN_PREGION0WA_Field := NRF_SVD.MWU.Disabled; + -- Enable or disable non-maskable interrupt for PREGION[0].RA event + PREGION0RA : NMIEN_PREGION0RA_Field := NRF_SVD.MWU.Disabled; + -- Enable or disable non-maskable interrupt for PREGION[1].WA event + PREGION1WA : NMIEN_PREGION1WA_Field := NRF_SVD.MWU.Disabled; + -- Enable or disable non-maskable interrupt for PREGION[1].RA event + PREGION1RA : NMIEN_PREGION1RA_Field := NRF_SVD.MWU.Disabled; + -- unspecified + Reserved_28_31 : HAL.UInt4 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for NMIEN_Register use record + REGION0WA at 0 range 0 .. 0; + REGION0RA at 0 range 1 .. 1; + REGION1WA at 0 range 2 .. 2; + REGION1RA at 0 range 3 .. 3; + REGION2WA at 0 range 4 .. 4; + REGION2RA at 0 range 5 .. 5; + REGION3WA at 0 range 6 .. 6; + REGION3RA at 0 range 7 .. 7; + Reserved_8_23 at 0 range 8 .. 23; + PREGION0WA at 0 range 24 .. 24; + PREGION0RA at 0 range 25 .. 25; + PREGION1WA at 0 range 26 .. 26; + PREGION1RA at 0 range 27 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + -- Write '1' to Enable non-maskable interrupt for REGION[0].WA event + type NMIENSET_REGION0WA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for NMIENSET_REGION0WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable non-maskable interrupt for REGION[0].WA event + type NMIENSET_REGION0WA_Field_1 is + (-- Reset value for the field + Nmienset_Region0Wa_Field_Reset, + -- Enable + Set) + with Size => 1; + for NMIENSET_REGION0WA_Field_1 use + (Nmienset_Region0Wa_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable non-maskable interrupt for REGION[0].RA event + type NMIENSET_REGION0RA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for NMIENSET_REGION0RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable non-maskable interrupt for REGION[0].RA event + type NMIENSET_REGION0RA_Field_1 is + (-- Reset value for the field + Nmienset_Region0Ra_Field_Reset, + -- Enable + Set) + with Size => 1; + for NMIENSET_REGION0RA_Field_1 use + (Nmienset_Region0Ra_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable non-maskable interrupt for REGION[1].WA event + type NMIENSET_REGION1WA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for NMIENSET_REGION1WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable non-maskable interrupt for REGION[1].WA event + type NMIENSET_REGION1WA_Field_1 is + (-- Reset value for the field + Nmienset_Region1Wa_Field_Reset, + -- Enable + Set) + with Size => 1; + for NMIENSET_REGION1WA_Field_1 use + (Nmienset_Region1Wa_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable non-maskable interrupt for REGION[1].RA event + type NMIENSET_REGION1RA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for NMIENSET_REGION1RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable non-maskable interrupt for REGION[1].RA event + type NMIENSET_REGION1RA_Field_1 is + (-- Reset value for the field + Nmienset_Region1Ra_Field_Reset, + -- Enable + Set) + with Size => 1; + for NMIENSET_REGION1RA_Field_1 use + (Nmienset_Region1Ra_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable non-maskable interrupt for REGION[2].WA event + type NMIENSET_REGION2WA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for NMIENSET_REGION2WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable non-maskable interrupt for REGION[2].WA event + type NMIENSET_REGION2WA_Field_1 is + (-- Reset value for the field + Nmienset_Region2Wa_Field_Reset, + -- Enable + Set) + with Size => 1; + for NMIENSET_REGION2WA_Field_1 use + (Nmienset_Region2Wa_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable non-maskable interrupt for REGION[2].RA event + type NMIENSET_REGION2RA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for NMIENSET_REGION2RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable non-maskable interrupt for REGION[2].RA event + type NMIENSET_REGION2RA_Field_1 is + (-- Reset value for the field + Nmienset_Region2Ra_Field_Reset, + -- Enable + Set) + with Size => 1; + for NMIENSET_REGION2RA_Field_1 use + (Nmienset_Region2Ra_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable non-maskable interrupt for REGION[3].WA event + type NMIENSET_REGION3WA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for NMIENSET_REGION3WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable non-maskable interrupt for REGION[3].WA event + type NMIENSET_REGION3WA_Field_1 is + (-- Reset value for the field + Nmienset_Region3Wa_Field_Reset, + -- Enable + Set) + with Size => 1; + for NMIENSET_REGION3WA_Field_1 use + (Nmienset_Region3Wa_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable non-maskable interrupt for REGION[3].RA event + type NMIENSET_REGION3RA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for NMIENSET_REGION3RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable non-maskable interrupt for REGION[3].RA event + type NMIENSET_REGION3RA_Field_1 is + (-- Reset value for the field + Nmienset_Region3Ra_Field_Reset, + -- Enable + Set) + with Size => 1; + for NMIENSET_REGION3RA_Field_1 use + (Nmienset_Region3Ra_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable non-maskable interrupt for PREGION[0].WA event + type NMIENSET_PREGION0WA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for NMIENSET_PREGION0WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable non-maskable interrupt for PREGION[0].WA event + type NMIENSET_PREGION0WA_Field_1 is + (-- Reset value for the field + Nmienset_Pregion0Wa_Field_Reset, + -- Enable + Set) + with Size => 1; + for NMIENSET_PREGION0WA_Field_1 use + (Nmienset_Pregion0Wa_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable non-maskable interrupt for PREGION[0].RA event + type NMIENSET_PREGION0RA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for NMIENSET_PREGION0RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable non-maskable interrupt for PREGION[0].RA event + type NMIENSET_PREGION0RA_Field_1 is + (-- Reset value for the field + Nmienset_Pregion0Ra_Field_Reset, + -- Enable + Set) + with Size => 1; + for NMIENSET_PREGION0RA_Field_1 use + (Nmienset_Pregion0Ra_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable non-maskable interrupt for PREGION[1].WA event + type NMIENSET_PREGION1WA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for NMIENSET_PREGION1WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable non-maskable interrupt for PREGION[1].WA event + type NMIENSET_PREGION1WA_Field_1 is + (-- Reset value for the field + Nmienset_Pregion1Wa_Field_Reset, + -- Enable + Set) + with Size => 1; + for NMIENSET_PREGION1WA_Field_1 use + (Nmienset_Pregion1Wa_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable non-maskable interrupt for PREGION[1].RA event + type NMIENSET_PREGION1RA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for NMIENSET_PREGION1RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable non-maskable interrupt for PREGION[1].RA event + type NMIENSET_PREGION1RA_Field_1 is + (-- Reset value for the field + Nmienset_Pregion1Ra_Field_Reset, + -- Enable + Set) + with Size => 1; + for NMIENSET_PREGION1RA_Field_1 use + (Nmienset_Pregion1Ra_Field_Reset => 0, + Set => 1); + + -- Enable non-maskable interrupt + type NMIENSET_Register is record + -- Write '1' to Enable non-maskable interrupt for REGION[0].WA event + REGION0WA : NMIENSET_REGION0WA_Field_1 := + Nmienset_Region0Wa_Field_Reset; + -- Write '1' to Enable non-maskable interrupt for REGION[0].RA event + REGION0RA : NMIENSET_REGION0RA_Field_1 := + Nmienset_Region0Ra_Field_Reset; + -- Write '1' to Enable non-maskable interrupt for REGION[1].WA event + REGION1WA : NMIENSET_REGION1WA_Field_1 := + Nmienset_Region1Wa_Field_Reset; + -- Write '1' to Enable non-maskable interrupt for REGION[1].RA event + REGION1RA : NMIENSET_REGION1RA_Field_1 := + Nmienset_Region1Ra_Field_Reset; + -- Write '1' to Enable non-maskable interrupt for REGION[2].WA event + REGION2WA : NMIENSET_REGION2WA_Field_1 := + Nmienset_Region2Wa_Field_Reset; + -- Write '1' to Enable non-maskable interrupt for REGION[2].RA event + REGION2RA : NMIENSET_REGION2RA_Field_1 := + Nmienset_Region2Ra_Field_Reset; + -- Write '1' to Enable non-maskable interrupt for REGION[3].WA event + REGION3WA : NMIENSET_REGION3WA_Field_1 := + Nmienset_Region3Wa_Field_Reset; + -- Write '1' to Enable non-maskable interrupt for REGION[3].RA event + REGION3RA : NMIENSET_REGION3RA_Field_1 := + Nmienset_Region3Ra_Field_Reset; + -- unspecified + Reserved_8_23 : HAL.UInt16 := 16#0#; + -- Write '1' to Enable non-maskable interrupt for PREGION[0].WA event + PREGION0WA : NMIENSET_PREGION0WA_Field_1 := + Nmienset_Pregion0Wa_Field_Reset; + -- Write '1' to Enable non-maskable interrupt for PREGION[0].RA event + PREGION0RA : NMIENSET_PREGION0RA_Field_1 := + Nmienset_Pregion0Ra_Field_Reset; + -- Write '1' to Enable non-maskable interrupt for PREGION[1].WA event + PREGION1WA : NMIENSET_PREGION1WA_Field_1 := + Nmienset_Pregion1Wa_Field_Reset; + -- Write '1' to Enable non-maskable interrupt for PREGION[1].RA event + PREGION1RA : NMIENSET_PREGION1RA_Field_1 := + Nmienset_Pregion1Ra_Field_Reset; + -- unspecified + Reserved_28_31 : HAL.UInt4 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for NMIENSET_Register use record + REGION0WA at 0 range 0 .. 0; + REGION0RA at 0 range 1 .. 1; + REGION1WA at 0 range 2 .. 2; + REGION1RA at 0 range 3 .. 3; + REGION2WA at 0 range 4 .. 4; + REGION2RA at 0 range 5 .. 5; + REGION3WA at 0 range 6 .. 6; + REGION3RA at 0 range 7 .. 7; + Reserved_8_23 at 0 range 8 .. 23; + PREGION0WA at 0 range 24 .. 24; + PREGION0RA at 0 range 25 .. 25; + PREGION1WA at 0 range 26 .. 26; + PREGION1RA at 0 range 27 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + -- Write '1' to Disable non-maskable interrupt for REGION[0].WA event + type NMIENCLR_REGION0WA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for NMIENCLR_REGION0WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable non-maskable interrupt for REGION[0].WA event + type NMIENCLR_REGION0WA_Field_1 is + (-- Reset value for the field + Nmienclr_Region0Wa_Field_Reset, + -- Disable + Clear) + with Size => 1; + for NMIENCLR_REGION0WA_Field_1 use + (Nmienclr_Region0Wa_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable non-maskable interrupt for REGION[0].RA event + type NMIENCLR_REGION0RA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for NMIENCLR_REGION0RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable non-maskable interrupt for REGION[0].RA event + type NMIENCLR_REGION0RA_Field_1 is + (-- Reset value for the field + Nmienclr_Region0Ra_Field_Reset, + -- Disable + Clear) + with Size => 1; + for NMIENCLR_REGION0RA_Field_1 use + (Nmienclr_Region0Ra_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable non-maskable interrupt for REGION[1].WA event + type NMIENCLR_REGION1WA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for NMIENCLR_REGION1WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable non-maskable interrupt for REGION[1].WA event + type NMIENCLR_REGION1WA_Field_1 is + (-- Reset value for the field + Nmienclr_Region1Wa_Field_Reset, + -- Disable + Clear) + with Size => 1; + for NMIENCLR_REGION1WA_Field_1 use + (Nmienclr_Region1Wa_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable non-maskable interrupt for REGION[1].RA event + type NMIENCLR_REGION1RA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for NMIENCLR_REGION1RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable non-maskable interrupt for REGION[1].RA event + type NMIENCLR_REGION1RA_Field_1 is + (-- Reset value for the field + Nmienclr_Region1Ra_Field_Reset, + -- Disable + Clear) + with Size => 1; + for NMIENCLR_REGION1RA_Field_1 use + (Nmienclr_Region1Ra_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable non-maskable interrupt for REGION[2].WA event + type NMIENCLR_REGION2WA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for NMIENCLR_REGION2WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable non-maskable interrupt for REGION[2].WA event + type NMIENCLR_REGION2WA_Field_1 is + (-- Reset value for the field + Nmienclr_Region2Wa_Field_Reset, + -- Disable + Clear) + with Size => 1; + for NMIENCLR_REGION2WA_Field_1 use + (Nmienclr_Region2Wa_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable non-maskable interrupt for REGION[2].RA event + type NMIENCLR_REGION2RA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for NMIENCLR_REGION2RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable non-maskable interrupt for REGION[2].RA event + type NMIENCLR_REGION2RA_Field_1 is + (-- Reset value for the field + Nmienclr_Region2Ra_Field_Reset, + -- Disable + Clear) + with Size => 1; + for NMIENCLR_REGION2RA_Field_1 use + (Nmienclr_Region2Ra_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable non-maskable interrupt for REGION[3].WA event + type NMIENCLR_REGION3WA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for NMIENCLR_REGION3WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable non-maskable interrupt for REGION[3].WA event + type NMIENCLR_REGION3WA_Field_1 is + (-- Reset value for the field + Nmienclr_Region3Wa_Field_Reset, + -- Disable + Clear) + with Size => 1; + for NMIENCLR_REGION3WA_Field_1 use + (Nmienclr_Region3Wa_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable non-maskable interrupt for REGION[3].RA event + type NMIENCLR_REGION3RA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for NMIENCLR_REGION3RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable non-maskable interrupt for REGION[3].RA event + type NMIENCLR_REGION3RA_Field_1 is + (-- Reset value for the field + Nmienclr_Region3Ra_Field_Reset, + -- Disable + Clear) + with Size => 1; + for NMIENCLR_REGION3RA_Field_1 use + (Nmienclr_Region3Ra_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable non-maskable interrupt for PREGION[0].WA event + type NMIENCLR_PREGION0WA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for NMIENCLR_PREGION0WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable non-maskable interrupt for PREGION[0].WA event + type NMIENCLR_PREGION0WA_Field_1 is + (-- Reset value for the field + Nmienclr_Pregion0Wa_Field_Reset, + -- Disable + Clear) + with Size => 1; + for NMIENCLR_PREGION0WA_Field_1 use + (Nmienclr_Pregion0Wa_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable non-maskable interrupt for PREGION[0].RA event + type NMIENCLR_PREGION0RA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for NMIENCLR_PREGION0RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable non-maskable interrupt for PREGION[0].RA event + type NMIENCLR_PREGION0RA_Field_1 is + (-- Reset value for the field + Nmienclr_Pregion0Ra_Field_Reset, + -- Disable + Clear) + with Size => 1; + for NMIENCLR_PREGION0RA_Field_1 use + (Nmienclr_Pregion0Ra_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable non-maskable interrupt for PREGION[1].WA event + type NMIENCLR_PREGION1WA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for NMIENCLR_PREGION1WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable non-maskable interrupt for PREGION[1].WA event + type NMIENCLR_PREGION1WA_Field_1 is + (-- Reset value for the field + Nmienclr_Pregion1Wa_Field_Reset, + -- Disable + Clear) + with Size => 1; + for NMIENCLR_PREGION1WA_Field_1 use + (Nmienclr_Pregion1Wa_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable non-maskable interrupt for PREGION[1].RA event + type NMIENCLR_PREGION1RA_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for NMIENCLR_PREGION1RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable non-maskable interrupt for PREGION[1].RA event + type NMIENCLR_PREGION1RA_Field_1 is + (-- Reset value for the field + Nmienclr_Pregion1Ra_Field_Reset, + -- Disable + Clear) + with Size => 1; + for NMIENCLR_PREGION1RA_Field_1 use + (Nmienclr_Pregion1Ra_Field_Reset => 0, + Clear => 1); + + -- Disable non-maskable interrupt + type NMIENCLR_Register is record + -- Write '1' to Disable non-maskable interrupt for REGION[0].WA event + REGION0WA : NMIENCLR_REGION0WA_Field_1 := + Nmienclr_Region0Wa_Field_Reset; + -- Write '1' to Disable non-maskable interrupt for REGION[0].RA event + REGION0RA : NMIENCLR_REGION0RA_Field_1 := + Nmienclr_Region0Ra_Field_Reset; + -- Write '1' to Disable non-maskable interrupt for REGION[1].WA event + REGION1WA : NMIENCLR_REGION1WA_Field_1 := + Nmienclr_Region1Wa_Field_Reset; + -- Write '1' to Disable non-maskable interrupt for REGION[1].RA event + REGION1RA : NMIENCLR_REGION1RA_Field_1 := + Nmienclr_Region1Ra_Field_Reset; + -- Write '1' to Disable non-maskable interrupt for REGION[2].WA event + REGION2WA : NMIENCLR_REGION2WA_Field_1 := + Nmienclr_Region2Wa_Field_Reset; + -- Write '1' to Disable non-maskable interrupt for REGION[2].RA event + REGION2RA : NMIENCLR_REGION2RA_Field_1 := + Nmienclr_Region2Ra_Field_Reset; + -- Write '1' to Disable non-maskable interrupt for REGION[3].WA event + REGION3WA : NMIENCLR_REGION3WA_Field_1 := + Nmienclr_Region3Wa_Field_Reset; + -- Write '1' to Disable non-maskable interrupt for REGION[3].RA event + REGION3RA : NMIENCLR_REGION3RA_Field_1 := + Nmienclr_Region3Ra_Field_Reset; + -- unspecified + Reserved_8_23 : HAL.UInt16 := 16#0#; + -- Write '1' to Disable non-maskable interrupt for PREGION[0].WA event + PREGION0WA : NMIENCLR_PREGION0WA_Field_1 := + Nmienclr_Pregion0Wa_Field_Reset; + -- Write '1' to Disable non-maskable interrupt for PREGION[0].RA event + PREGION0RA : NMIENCLR_PREGION0RA_Field_1 := + Nmienclr_Pregion0Ra_Field_Reset; + -- Write '1' to Disable non-maskable interrupt for PREGION[1].WA event + PREGION1WA : NMIENCLR_PREGION1WA_Field_1 := + Nmienclr_Pregion1Wa_Field_Reset; + -- Write '1' to Disable non-maskable interrupt for PREGION[1].RA event + PREGION1RA : NMIENCLR_PREGION1RA_Field_1 := + Nmienclr_Pregion1Ra_Field_Reset; + -- unspecified + Reserved_28_31 : HAL.UInt4 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for NMIENCLR_Register use record + REGION0WA at 0 range 0 .. 0; + REGION0RA at 0 range 1 .. 1; + REGION1WA at 0 range 2 .. 2; + REGION1RA at 0 range 3 .. 3; + REGION2WA at 0 range 4 .. 4; + REGION2RA at 0 range 5 .. 5; + REGION3WA at 0 range 6 .. 6; + REGION3RA at 0 range 7 .. 7; + Reserved_8_23 at 0 range 8 .. 23; + PREGION0WA at 0 range 24 .. 24; + PREGION0RA at 0 range 25 .. 25; + PREGION1WA at 0 range 26 .. 26; + PREGION1RA at 0 range 27 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + ----------------------------------- + -- PERREGION cluster's Registers -- + ----------------------------------- + + -- Subregion 0 in region 0 (write '1' to clear) + type SUBSTATWA_SR0_Field is + (-- No write access occurred in this subregion + Noaccess, + -- Write access(es) occurred in this subregion + Access_k) + with Size => 1; + for SUBSTATWA_SR0_Field use + (Noaccess => 0, + Access_k => 1); + + -- SUBSTATWA_PERREGION_SR array + type SUBSTATWA_PERREGION_SR_Field_Array is array (0 .. 31) + of SUBSTATWA_SR0_Field + with Component_Size => 1, Size => 32; + + -- Description cluster[0]: Source of event/interrupt in region 0, write + -- access detected while corresponding subregion was enabled for watching + type SUBSTATWA_PERREGION_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SR as a value + Val : HAL.UInt32; + when True => + -- SR as an array + Arr : SUBSTATWA_PERREGION_SR_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SUBSTATWA_PERREGION_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- Subregion 0 in region 0 (write '1' to clear) + type SUBSTATRA_SR0_Field is + (-- No read access occurred in this subregion + Noaccess, + -- Read access(es) occurred in this subregion + Access_k) + with Size => 1; + for SUBSTATRA_SR0_Field use + (Noaccess => 0, + Access_k => 1); + + -- SUBSTATRA_PERREGION_SR array + type SUBSTATRA_PERREGION_SR_Field_Array is array (0 .. 31) + of SUBSTATRA_SR0_Field + with Component_Size => 1, Size => 32; + + -- Description cluster[0]: Source of event/interrupt in region 0, read + -- access detected while corresponding subregion was enabled for watching + type SUBSTATRA_PERREGION_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SR as a value + Val : HAL.UInt32; + when True => + -- SR as an array + Arr : SUBSTATRA_PERREGION_SR_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SUBSTATRA_PERREGION_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- Unspecified + type PERREGION_Cluster is record + -- Description cluster[0]: Source of event/interrupt in region 0, write + -- access detected while corresponding subregion was enabled for + -- watching + SUBSTATWA : aliased SUBSTATWA_PERREGION_Register; + -- Description cluster[0]: Source of event/interrupt in region 0, read + -- access detected while corresponding subregion was enabled for + -- watching + SUBSTATRA : aliased SUBSTATRA_PERREGION_Register; + end record + with Size => 64; + + for PERREGION_Cluster use record + SUBSTATWA at 16#0# range 0 .. 31; + SUBSTATRA at 16#4# range 0 .. 31; + end record; + + -- Unspecified + type PERREGION_Clusters is array (0 .. 1) of PERREGION_Cluster; + + -- Enable/disable write access watch in region[0] + type REGIONEN_RGN0WA_Field is + (-- Disable write access watch in this region + Disable, + -- Enable write access watch in this region + Enable) + with Size => 1; + for REGIONEN_RGN0WA_Field use + (Disable => 0, + Enable => 1); + + -- Enable/disable read access watch in region[0] + type REGIONEN_RGN0RA_Field is + (-- Disable read access watch in this region + Disable, + -- Enable read access watch in this region + Enable) + with Size => 1; + for REGIONEN_RGN0RA_Field use + (Disable => 0, + Enable => 1); + + -- Enable/disable write access watch in region[1] + type REGIONEN_RGN1WA_Field is + (-- Disable write access watch in this region + Disable, + -- Enable write access watch in this region + Enable) + with Size => 1; + for REGIONEN_RGN1WA_Field use + (Disable => 0, + Enable => 1); + + -- Enable/disable read access watch in region[1] + type REGIONEN_RGN1RA_Field is + (-- Disable read access watch in this region + Disable, + -- Enable read access watch in this region + Enable) + with Size => 1; + for REGIONEN_RGN1RA_Field use + (Disable => 0, + Enable => 1); + + -- Enable/disable write access watch in region[2] + type REGIONEN_RGN2WA_Field is + (-- Disable write access watch in this region + Disable, + -- Enable write access watch in this region + Enable) + with Size => 1; + for REGIONEN_RGN2WA_Field use + (Disable => 0, + Enable => 1); + + -- Enable/disable read access watch in region[2] + type REGIONEN_RGN2RA_Field is + (-- Disable read access watch in this region + Disable, + -- Enable read access watch in this region + Enable) + with Size => 1; + for REGIONEN_RGN2RA_Field use + (Disable => 0, + Enable => 1); + + -- Enable/disable write access watch in region[3] + type REGIONEN_RGN3WA_Field is + (-- Disable write access watch in this region + Disable, + -- Enable write access watch in this region + Enable) + with Size => 1; + for REGIONEN_RGN3WA_Field use + (Disable => 0, + Enable => 1); + + -- Enable/disable read access watch in region[3] + type REGIONEN_RGN3RA_Field is + (-- Disable read access watch in this region + Disable, + -- Enable read access watch in this region + Enable) + with Size => 1; + for REGIONEN_RGN3RA_Field use + (Disable => 0, + Enable => 1); + + -- Enable/disable write access watch in PREGION[0] + type REGIONEN_PRGN0WA_Field is + (-- Disable write access watch in this PREGION + Disable, + -- Enable write access watch in this PREGION + Enable) + with Size => 1; + for REGIONEN_PRGN0WA_Field use + (Disable => 0, + Enable => 1); + + -- Enable/disable read access watch in PREGION[0] + type REGIONEN_PRGN0RA_Field is + (-- Disable read access watch in this PREGION + Disable, + -- Enable read access watch in this PREGION + Enable) + with Size => 1; + for REGIONEN_PRGN0RA_Field use + (Disable => 0, + Enable => 1); + + -- Enable/disable write access watch in PREGION[1] + type REGIONEN_PRGN1WA_Field is + (-- Disable write access watch in this PREGION + Disable, + -- Enable write access watch in this PREGION + Enable) + with Size => 1; + for REGIONEN_PRGN1WA_Field use + (Disable => 0, + Enable => 1); + + -- Enable/disable read access watch in PREGION[1] + type REGIONEN_PRGN1RA_Field is + (-- Disable read access watch in this PREGION + Disable, + -- Enable read access watch in this PREGION + Enable) + with Size => 1; + for REGIONEN_PRGN1RA_Field use + (Disable => 0, + Enable => 1); + + -- Enable/disable regions watch + type REGIONEN_Register is record + -- Enable/disable write access watch in region[0] + RGN0WA : REGIONEN_RGN0WA_Field := NRF_SVD.MWU.Disable; + -- Enable/disable read access watch in region[0] + RGN0RA : REGIONEN_RGN0RA_Field := NRF_SVD.MWU.Disable; + -- Enable/disable write access watch in region[1] + RGN1WA : REGIONEN_RGN1WA_Field := NRF_SVD.MWU.Disable; + -- Enable/disable read access watch in region[1] + RGN1RA : REGIONEN_RGN1RA_Field := NRF_SVD.MWU.Disable; + -- Enable/disable write access watch in region[2] + RGN2WA : REGIONEN_RGN2WA_Field := NRF_SVD.MWU.Disable; + -- Enable/disable read access watch in region[2] + RGN2RA : REGIONEN_RGN2RA_Field := NRF_SVD.MWU.Disable; + -- Enable/disable write access watch in region[3] + RGN3WA : REGIONEN_RGN3WA_Field := NRF_SVD.MWU.Disable; + -- Enable/disable read access watch in region[3] + RGN3RA : REGIONEN_RGN3RA_Field := NRF_SVD.MWU.Disable; + -- unspecified + Reserved_8_23 : HAL.UInt16 := 16#0#; + -- Enable/disable write access watch in PREGION[0] + PRGN0WA : REGIONEN_PRGN0WA_Field := NRF_SVD.MWU.Disable; + -- Enable/disable read access watch in PREGION[0] + PRGN0RA : REGIONEN_PRGN0RA_Field := NRF_SVD.MWU.Disable; + -- Enable/disable write access watch in PREGION[1] + PRGN1WA : REGIONEN_PRGN1WA_Field := NRF_SVD.MWU.Disable; + -- Enable/disable read access watch in PREGION[1] + PRGN1RA : REGIONEN_PRGN1RA_Field := NRF_SVD.MWU.Disable; + -- unspecified + Reserved_28_31 : HAL.UInt4 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for REGIONEN_Register use record + RGN0WA at 0 range 0 .. 0; + RGN0RA at 0 range 1 .. 1; + RGN1WA at 0 range 2 .. 2; + RGN1RA at 0 range 3 .. 3; + RGN2WA at 0 range 4 .. 4; + RGN2RA at 0 range 5 .. 5; + RGN3WA at 0 range 6 .. 6; + RGN3RA at 0 range 7 .. 7; + Reserved_8_23 at 0 range 8 .. 23; + PRGN0WA at 0 range 24 .. 24; + PRGN0RA at 0 range 25 .. 25; + PRGN1WA at 0 range 26 .. 26; + PRGN1RA at 0 range 27 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + -- Enable write access watch in region[0] + type REGIONENSET_RGN0WA_Field is + (-- Write access watch in this region is disabled + Disabled, + -- Write access watch in this region is enabled + Enabled) + with Size => 1; + for REGIONENSET_RGN0WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable write access watch in region[0] + type REGIONENSET_RGN0WA_Field_1 is + (-- Reset value for the field + Regionenset_Rgn0Wa_Field_Reset, + -- Enable write access watch in this region + Set) + with Size => 1; + for REGIONENSET_RGN0WA_Field_1 use + (Regionenset_Rgn0Wa_Field_Reset => 0, + Set => 1); + + -- Enable read access watch in region[0] + type REGIONENSET_RGN0RA_Field is + (-- Read access watch in this region is disabled + Disabled, + -- Read access watch in this region is enabled + Enabled) + with Size => 1; + for REGIONENSET_RGN0RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable read access watch in region[0] + type REGIONENSET_RGN0RA_Field_1 is + (-- Reset value for the field + Regionenset_Rgn0Ra_Field_Reset, + -- Enable read access watch in this region + Set) + with Size => 1; + for REGIONENSET_RGN0RA_Field_1 use + (Regionenset_Rgn0Ra_Field_Reset => 0, + Set => 1); + + -- Enable write access watch in region[1] + type REGIONENSET_RGN1WA_Field is + (-- Write access watch in this region is disabled + Disabled, + -- Write access watch in this region is enabled + Enabled) + with Size => 1; + for REGIONENSET_RGN1WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable write access watch in region[1] + type REGIONENSET_RGN1WA_Field_1 is + (-- Reset value for the field + Regionenset_Rgn1Wa_Field_Reset, + -- Enable write access watch in this region + Set) + with Size => 1; + for REGIONENSET_RGN1WA_Field_1 use + (Regionenset_Rgn1Wa_Field_Reset => 0, + Set => 1); + + -- Enable read access watch in region[1] + type REGIONENSET_RGN1RA_Field is + (-- Read access watch in this region is disabled + Disabled, + -- Read access watch in this region is enabled + Enabled) + with Size => 1; + for REGIONENSET_RGN1RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable read access watch in region[1] + type REGIONENSET_RGN1RA_Field_1 is + (-- Reset value for the field + Regionenset_Rgn1Ra_Field_Reset, + -- Enable read access watch in this region + Set) + with Size => 1; + for REGIONENSET_RGN1RA_Field_1 use + (Regionenset_Rgn1Ra_Field_Reset => 0, + Set => 1); + + -- Enable write access watch in region[2] + type REGIONENSET_RGN2WA_Field is + (-- Write access watch in this region is disabled + Disabled, + -- Write access watch in this region is enabled + Enabled) + with Size => 1; + for REGIONENSET_RGN2WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable write access watch in region[2] + type REGIONENSET_RGN2WA_Field_1 is + (-- Reset value for the field + Regionenset_Rgn2Wa_Field_Reset, + -- Enable write access watch in this region + Set) + with Size => 1; + for REGIONENSET_RGN2WA_Field_1 use + (Regionenset_Rgn2Wa_Field_Reset => 0, + Set => 1); + + -- Enable read access watch in region[2] + type REGIONENSET_RGN2RA_Field is + (-- Read access watch in this region is disabled + Disabled, + -- Read access watch in this region is enabled + Enabled) + with Size => 1; + for REGIONENSET_RGN2RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable read access watch in region[2] + type REGIONENSET_RGN2RA_Field_1 is + (-- Reset value for the field + Regionenset_Rgn2Ra_Field_Reset, + -- Enable read access watch in this region + Set) + with Size => 1; + for REGIONENSET_RGN2RA_Field_1 use + (Regionenset_Rgn2Ra_Field_Reset => 0, + Set => 1); + + -- Enable write access watch in region[3] + type REGIONENSET_RGN3WA_Field is + (-- Write access watch in this region is disabled + Disabled, + -- Write access watch in this region is enabled + Enabled) + with Size => 1; + for REGIONENSET_RGN3WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable write access watch in region[3] + type REGIONENSET_RGN3WA_Field_1 is + (-- Reset value for the field + Regionenset_Rgn3Wa_Field_Reset, + -- Enable write access watch in this region + Set) + with Size => 1; + for REGIONENSET_RGN3WA_Field_1 use + (Regionenset_Rgn3Wa_Field_Reset => 0, + Set => 1); + + -- Enable read access watch in region[3] + type REGIONENSET_RGN3RA_Field is + (-- Read access watch in this region is disabled + Disabled, + -- Read access watch in this region is enabled + Enabled) + with Size => 1; + for REGIONENSET_RGN3RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable read access watch in region[3] + type REGIONENSET_RGN3RA_Field_1 is + (-- Reset value for the field + Regionenset_Rgn3Ra_Field_Reset, + -- Enable read access watch in this region + Set) + with Size => 1; + for REGIONENSET_RGN3RA_Field_1 use + (Regionenset_Rgn3Ra_Field_Reset => 0, + Set => 1); + + -- Enable write access watch in PREGION[0] + type REGIONENSET_PRGN0WA_Field is + (-- Write access watch in this PREGION is disabled + Disabled, + -- Write access watch in this PREGION is enabled + Enabled) + with Size => 1; + for REGIONENSET_PRGN0WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable write access watch in PREGION[0] + type REGIONENSET_PRGN0WA_Field_1 is + (-- Reset value for the field + Regionenset_Prgn0Wa_Field_Reset, + -- Enable write access watch in this PREGION + Set) + with Size => 1; + for REGIONENSET_PRGN0WA_Field_1 use + (Regionenset_Prgn0Wa_Field_Reset => 0, + Set => 1); + + -- Enable read access watch in PREGION[0] + type REGIONENSET_PRGN0RA_Field is + (-- Read access watch in this PREGION is disabled + Disabled, + -- Read access watch in this PREGION is enabled + Enabled) + with Size => 1; + for REGIONENSET_PRGN0RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable read access watch in PREGION[0] + type REGIONENSET_PRGN0RA_Field_1 is + (-- Reset value for the field + Regionenset_Prgn0Ra_Field_Reset, + -- Enable read access watch in this PREGION + Set) + with Size => 1; + for REGIONENSET_PRGN0RA_Field_1 use + (Regionenset_Prgn0Ra_Field_Reset => 0, + Set => 1); + + -- Enable write access watch in PREGION[1] + type REGIONENSET_PRGN1WA_Field is + (-- Write access watch in this PREGION is disabled + Disabled, + -- Write access watch in this PREGION is enabled + Enabled) + with Size => 1; + for REGIONENSET_PRGN1WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable write access watch in PREGION[1] + type REGIONENSET_PRGN1WA_Field_1 is + (-- Reset value for the field + Regionenset_Prgn1Wa_Field_Reset, + -- Enable write access watch in this PREGION + Set) + with Size => 1; + for REGIONENSET_PRGN1WA_Field_1 use + (Regionenset_Prgn1Wa_Field_Reset => 0, + Set => 1); + + -- Enable read access watch in PREGION[1] + type REGIONENSET_PRGN1RA_Field is + (-- Read access watch in this PREGION is disabled + Disabled, + -- Read access watch in this PREGION is enabled + Enabled) + with Size => 1; + for REGIONENSET_PRGN1RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable read access watch in PREGION[1] + type REGIONENSET_PRGN1RA_Field_1 is + (-- Reset value for the field + Regionenset_Prgn1Ra_Field_Reset, + -- Enable read access watch in this PREGION + Set) + with Size => 1; + for REGIONENSET_PRGN1RA_Field_1 use + (Regionenset_Prgn1Ra_Field_Reset => 0, + Set => 1); + + -- Enable regions watch + type REGIONENSET_Register is record + -- Enable write access watch in region[0] + RGN0WA : REGIONENSET_RGN0WA_Field_1 := + Regionenset_Rgn0Wa_Field_Reset; + -- Enable read access watch in region[0] + RGN0RA : REGIONENSET_RGN0RA_Field_1 := + Regionenset_Rgn0Ra_Field_Reset; + -- Enable write access watch in region[1] + RGN1WA : REGIONENSET_RGN1WA_Field_1 := + Regionenset_Rgn1Wa_Field_Reset; + -- Enable read access watch in region[1] + RGN1RA : REGIONENSET_RGN1RA_Field_1 := + Regionenset_Rgn1Ra_Field_Reset; + -- Enable write access watch in region[2] + RGN2WA : REGIONENSET_RGN2WA_Field_1 := + Regionenset_Rgn2Wa_Field_Reset; + -- Enable read access watch in region[2] + RGN2RA : REGIONENSET_RGN2RA_Field_1 := + Regionenset_Rgn2Ra_Field_Reset; + -- Enable write access watch in region[3] + RGN3WA : REGIONENSET_RGN3WA_Field_1 := + Regionenset_Rgn3Wa_Field_Reset; + -- Enable read access watch in region[3] + RGN3RA : REGIONENSET_RGN3RA_Field_1 := + Regionenset_Rgn3Ra_Field_Reset; + -- unspecified + Reserved_8_23 : HAL.UInt16 := 16#0#; + -- Enable write access watch in PREGION[0] + PRGN0WA : REGIONENSET_PRGN0WA_Field_1 := + Regionenset_Prgn0Wa_Field_Reset; + -- Enable read access watch in PREGION[0] + PRGN0RA : REGIONENSET_PRGN0RA_Field_1 := + Regionenset_Prgn0Ra_Field_Reset; + -- Enable write access watch in PREGION[1] + PRGN1WA : REGIONENSET_PRGN1WA_Field_1 := + Regionenset_Prgn1Wa_Field_Reset; + -- Enable read access watch in PREGION[1] + PRGN1RA : REGIONENSET_PRGN1RA_Field_1 := + Regionenset_Prgn1Ra_Field_Reset; + -- unspecified + Reserved_28_31 : HAL.UInt4 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for REGIONENSET_Register use record + RGN0WA at 0 range 0 .. 0; + RGN0RA at 0 range 1 .. 1; + RGN1WA at 0 range 2 .. 2; + RGN1RA at 0 range 3 .. 3; + RGN2WA at 0 range 4 .. 4; + RGN2RA at 0 range 5 .. 5; + RGN3WA at 0 range 6 .. 6; + RGN3RA at 0 range 7 .. 7; + Reserved_8_23 at 0 range 8 .. 23; + PRGN0WA at 0 range 24 .. 24; + PRGN0RA at 0 range 25 .. 25; + PRGN1WA at 0 range 26 .. 26; + PRGN1RA at 0 range 27 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + -- Disable write access watch in region[0] + type REGIONENCLR_RGN0WA_Field is + (-- Write access watch in this region is disabled + Disabled, + -- Write access watch in this region is enabled + Enabled) + with Size => 1; + for REGIONENCLR_RGN0WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable write access watch in region[0] + type REGIONENCLR_RGN0WA_Field_1 is + (-- Reset value for the field + Regionenclr_Rgn0Wa_Field_Reset, + -- Disable write access watch in this region + Clear) + with Size => 1; + for REGIONENCLR_RGN0WA_Field_1 use + (Regionenclr_Rgn0Wa_Field_Reset => 0, + Clear => 1); + + -- Disable read access watch in region[0] + type REGIONENCLR_RGN0RA_Field is + (-- Read access watch in this region is disabled + Disabled, + -- Read access watch in this region is enabled + Enabled) + with Size => 1; + for REGIONENCLR_RGN0RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable read access watch in region[0] + type REGIONENCLR_RGN0RA_Field_1 is + (-- Reset value for the field + Regionenclr_Rgn0Ra_Field_Reset, + -- Disable read access watch in this region + Clear) + with Size => 1; + for REGIONENCLR_RGN0RA_Field_1 use + (Regionenclr_Rgn0Ra_Field_Reset => 0, + Clear => 1); + + -- Disable write access watch in region[1] + type REGIONENCLR_RGN1WA_Field is + (-- Write access watch in this region is disabled + Disabled, + -- Write access watch in this region is enabled + Enabled) + with Size => 1; + for REGIONENCLR_RGN1WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable write access watch in region[1] + type REGIONENCLR_RGN1WA_Field_1 is + (-- Reset value for the field + Regionenclr_Rgn1Wa_Field_Reset, + -- Disable write access watch in this region + Clear) + with Size => 1; + for REGIONENCLR_RGN1WA_Field_1 use + (Regionenclr_Rgn1Wa_Field_Reset => 0, + Clear => 1); + + -- Disable read access watch in region[1] + type REGIONENCLR_RGN1RA_Field is + (-- Read access watch in this region is disabled + Disabled, + -- Read access watch in this region is enabled + Enabled) + with Size => 1; + for REGIONENCLR_RGN1RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable read access watch in region[1] + type REGIONENCLR_RGN1RA_Field_1 is + (-- Reset value for the field + Regionenclr_Rgn1Ra_Field_Reset, + -- Disable read access watch in this region + Clear) + with Size => 1; + for REGIONENCLR_RGN1RA_Field_1 use + (Regionenclr_Rgn1Ra_Field_Reset => 0, + Clear => 1); + + -- Disable write access watch in region[2] + type REGIONENCLR_RGN2WA_Field is + (-- Write access watch in this region is disabled + Disabled, + -- Write access watch in this region is enabled + Enabled) + with Size => 1; + for REGIONENCLR_RGN2WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable write access watch in region[2] + type REGIONENCLR_RGN2WA_Field_1 is + (-- Reset value for the field + Regionenclr_Rgn2Wa_Field_Reset, + -- Disable write access watch in this region + Clear) + with Size => 1; + for REGIONENCLR_RGN2WA_Field_1 use + (Regionenclr_Rgn2Wa_Field_Reset => 0, + Clear => 1); + + -- Disable read access watch in region[2] + type REGIONENCLR_RGN2RA_Field is + (-- Read access watch in this region is disabled + Disabled, + -- Read access watch in this region is enabled + Enabled) + with Size => 1; + for REGIONENCLR_RGN2RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable read access watch in region[2] + type REGIONENCLR_RGN2RA_Field_1 is + (-- Reset value for the field + Regionenclr_Rgn2Ra_Field_Reset, + -- Disable read access watch in this region + Clear) + with Size => 1; + for REGIONENCLR_RGN2RA_Field_1 use + (Regionenclr_Rgn2Ra_Field_Reset => 0, + Clear => 1); + + -- Disable write access watch in region[3] + type REGIONENCLR_RGN3WA_Field is + (-- Write access watch in this region is disabled + Disabled, + -- Write access watch in this region is enabled + Enabled) + with Size => 1; + for REGIONENCLR_RGN3WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable write access watch in region[3] + type REGIONENCLR_RGN3WA_Field_1 is + (-- Reset value for the field + Regionenclr_Rgn3Wa_Field_Reset, + -- Disable write access watch in this region + Clear) + with Size => 1; + for REGIONENCLR_RGN3WA_Field_1 use + (Regionenclr_Rgn3Wa_Field_Reset => 0, + Clear => 1); + + -- Disable read access watch in region[3] + type REGIONENCLR_RGN3RA_Field is + (-- Read access watch in this region is disabled + Disabled, + -- Read access watch in this region is enabled + Enabled) + with Size => 1; + for REGIONENCLR_RGN3RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable read access watch in region[3] + type REGIONENCLR_RGN3RA_Field_1 is + (-- Reset value for the field + Regionenclr_Rgn3Ra_Field_Reset, + -- Disable read access watch in this region + Clear) + with Size => 1; + for REGIONENCLR_RGN3RA_Field_1 use + (Regionenclr_Rgn3Ra_Field_Reset => 0, + Clear => 1); + + -- Disable write access watch in PREGION[0] + type REGIONENCLR_PRGN0WA_Field is + (-- Write access watch in this PREGION is disabled + Disabled, + -- Write access watch in this PREGION is enabled + Enabled) + with Size => 1; + for REGIONENCLR_PRGN0WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable write access watch in PREGION[0] + type REGIONENCLR_PRGN0WA_Field_1 is + (-- Reset value for the field + Regionenclr_Prgn0Wa_Field_Reset, + -- Disable write access watch in this PREGION + Clear) + with Size => 1; + for REGIONENCLR_PRGN0WA_Field_1 use + (Regionenclr_Prgn0Wa_Field_Reset => 0, + Clear => 1); + + -- Disable read access watch in PREGION[0] + type REGIONENCLR_PRGN0RA_Field is + (-- Read access watch in this PREGION is disabled + Disabled, + -- Read access watch in this PREGION is enabled + Enabled) + with Size => 1; + for REGIONENCLR_PRGN0RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable read access watch in PREGION[0] + type REGIONENCLR_PRGN0RA_Field_1 is + (-- Reset value for the field + Regionenclr_Prgn0Ra_Field_Reset, + -- Disable read access watch in this PREGION + Clear) + with Size => 1; + for REGIONENCLR_PRGN0RA_Field_1 use + (Regionenclr_Prgn0Ra_Field_Reset => 0, + Clear => 1); + + -- Disable write access watch in PREGION[1] + type REGIONENCLR_PRGN1WA_Field is + (-- Write access watch in this PREGION is disabled + Disabled, + -- Write access watch in this PREGION is enabled + Enabled) + with Size => 1; + for REGIONENCLR_PRGN1WA_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable write access watch in PREGION[1] + type REGIONENCLR_PRGN1WA_Field_1 is + (-- Reset value for the field + Regionenclr_Prgn1Wa_Field_Reset, + -- Disable write access watch in this PREGION + Clear) + with Size => 1; + for REGIONENCLR_PRGN1WA_Field_1 use + (Regionenclr_Prgn1Wa_Field_Reset => 0, + Clear => 1); + + -- Disable read access watch in PREGION[1] + type REGIONENCLR_PRGN1RA_Field is + (-- Read access watch in this PREGION is disabled + Disabled, + -- Read access watch in this PREGION is enabled + Enabled) + with Size => 1; + for REGIONENCLR_PRGN1RA_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable read access watch in PREGION[1] + type REGIONENCLR_PRGN1RA_Field_1 is + (-- Reset value for the field + Regionenclr_Prgn1Ra_Field_Reset, + -- Disable read access watch in this PREGION + Clear) + with Size => 1; + for REGIONENCLR_PRGN1RA_Field_1 use + (Regionenclr_Prgn1Ra_Field_Reset => 0, + Clear => 1); + + -- Disable regions watch + type REGIONENCLR_Register is record + -- Disable write access watch in region[0] + RGN0WA : REGIONENCLR_RGN0WA_Field_1 := + Regionenclr_Rgn0Wa_Field_Reset; + -- Disable read access watch in region[0] + RGN0RA : REGIONENCLR_RGN0RA_Field_1 := + Regionenclr_Rgn0Ra_Field_Reset; + -- Disable write access watch in region[1] + RGN1WA : REGIONENCLR_RGN1WA_Field_1 := + Regionenclr_Rgn1Wa_Field_Reset; + -- Disable read access watch in region[1] + RGN1RA : REGIONENCLR_RGN1RA_Field_1 := + Regionenclr_Rgn1Ra_Field_Reset; + -- Disable write access watch in region[2] + RGN2WA : REGIONENCLR_RGN2WA_Field_1 := + Regionenclr_Rgn2Wa_Field_Reset; + -- Disable read access watch in region[2] + RGN2RA : REGIONENCLR_RGN2RA_Field_1 := + Regionenclr_Rgn2Ra_Field_Reset; + -- Disable write access watch in region[3] + RGN3WA : REGIONENCLR_RGN3WA_Field_1 := + Regionenclr_Rgn3Wa_Field_Reset; + -- Disable read access watch in region[3] + RGN3RA : REGIONENCLR_RGN3RA_Field_1 := + Regionenclr_Rgn3Ra_Field_Reset; + -- unspecified + Reserved_8_23 : HAL.UInt16 := 16#0#; + -- Disable write access watch in PREGION[0] + PRGN0WA : REGIONENCLR_PRGN0WA_Field_1 := + Regionenclr_Prgn0Wa_Field_Reset; + -- Disable read access watch in PREGION[0] + PRGN0RA : REGIONENCLR_PRGN0RA_Field_1 := + Regionenclr_Prgn0Ra_Field_Reset; + -- Disable write access watch in PREGION[1] + PRGN1WA : REGIONENCLR_PRGN1WA_Field_1 := + Regionenclr_Prgn1Wa_Field_Reset; + -- Disable read access watch in PREGION[1] + PRGN1RA : REGIONENCLR_PRGN1RA_Field_1 := + Regionenclr_Prgn1Ra_Field_Reset; + -- unspecified + Reserved_28_31 : HAL.UInt4 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for REGIONENCLR_Register use record + RGN0WA at 0 range 0 .. 0; + RGN0RA at 0 range 1 .. 1; + RGN1WA at 0 range 2 .. 2; + RGN1RA at 0 range 3 .. 3; + RGN2WA at 0 range 4 .. 4; + RGN2RA at 0 range 5 .. 5; + RGN3WA at 0 range 6 .. 6; + RGN3RA at 0 range 7 .. 7; + Reserved_8_23 at 0 range 8 .. 23; + PRGN0WA at 0 range 24 .. 24; + PRGN0RA at 0 range 25 .. 25; + PRGN1WA at 0 range 26 .. 26; + PRGN1RA at 0 range 27 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + -------------------------------- + -- REGION cluster's Registers -- + -------------------------------- + + -- Unspecified + type REGION_Cluster is record + -- Description cluster[0]: Start address for region 0 + START : aliased HAL.UInt32; + -- Description cluster[0]: End address of region 0 + END_k : aliased HAL.UInt32; + end record + with Size => 64; + + for REGION_Cluster use record + START at 16#0# range 0 .. 31; + END_k at 16#4# range 0 .. 31; + end record; + + -- Unspecified + type REGION_Clusters is array (0 .. 3) of REGION_Cluster; + + --------------------------------- + -- PREGION cluster's Registers -- + --------------------------------- + + -- Include or exclude subregion 0 in region + type SUBS_SR0_Field is + (-- Exclude + Exclude, + -- Include + Include) + with Size => 1; + for SUBS_SR0_Field use + (Exclude => 0, + Include => 1); + + -- SUBS_PREGION_SR array + type SUBS_PREGION_SR_Field_Array is array (0 .. 31) of SUBS_SR0_Field + with Component_Size => 1, Size => 32; + + -- Description cluster[0]: Subregions of region 0 + type SUBS_PREGION_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SR as a value + Val : HAL.UInt32; + when True => + -- SR as an array + Arr : SUBS_PREGION_SR_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SUBS_PREGION_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- Unspecified + type PREGION_Cluster is record + -- Description cluster[0]: Reserved for future use + START : aliased HAL.UInt32; + -- Description cluster[0]: Reserved for future use + END_k : aliased HAL.UInt32; + -- Description cluster[0]: Subregions of region 0 + SUBS : aliased SUBS_PREGION_Register; + end record + with Size => 96; + + for PREGION_Cluster use record + START at 16#0# range 0 .. 31; + END_k at 16#4# range 0 .. 31; + SUBS at 16#8# range 0 .. 31; + end record; + + -- Unspecified + type PREGION_Clusters is array (0 .. 1) of PREGION_Cluster; + + ----------------- + -- Peripherals -- + ----------------- + + -- Memory Watch Unit + type MWU_Peripheral is record + -- Unspecified + EVENTS_REGION : aliased EVENTS_REGION_Clusters; + -- Unspecified + EVENTS_PREGION : aliased EVENTS_PREGION_Clusters; + -- Enable or disable interrupt + INTEN : aliased INTEN_Register; + -- Enable interrupt + INTENSET : aliased INTENSET_Register; + -- Disable interrupt + INTENCLR : aliased INTENCLR_Register; + -- Enable or disable non-maskable interrupt + NMIEN : aliased NMIEN_Register; + -- Enable non-maskable interrupt + NMIENSET : aliased NMIENSET_Register; + -- Disable non-maskable interrupt + NMIENCLR : aliased NMIENCLR_Register; + -- Unspecified + PERREGION : aliased PERREGION_Clusters; + -- Enable/disable regions watch + REGIONEN : aliased REGIONEN_Register; + -- Enable regions watch + REGIONENSET : aliased REGIONENSET_Register; + -- Disable regions watch + REGIONENCLR : aliased REGIONENCLR_Register; + -- Unspecified + REGION : aliased REGION_Clusters; + -- Unspecified + PREGION : aliased PREGION_Clusters; + end record + with Volatile; + + for MWU_Peripheral use record + EVENTS_REGION at 16#100# range 0 .. 255; + EVENTS_PREGION at 16#160# range 0 .. 127; + INTEN at 16#300# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + NMIEN at 16#320# range 0 .. 31; + NMIENSET at 16#324# range 0 .. 31; + NMIENCLR at 16#328# range 0 .. 31; + PERREGION at 16#400# range 0 .. 127; + REGIONEN at 16#510# range 0 .. 31; + REGIONENSET at 16#514# range 0 .. 31; + REGIONENCLR at 16#518# range 0 .. 31; + REGION at 16#600# range 0 .. 255; + PREGION at 16#6C0# range 0 .. 191; + end record; + + -- Memory Watch Unit + MWU_Periph : aliased MWU_Peripheral + with Import, Address => MWU_Base; + +end NRF_SVD.MWU; diff --git a/arch/ARM/Nordic/svd/nrf52/nrf_svd-nfct.ads b/arch/ARM/Nordic/svd/nrf52/nrf_svd-nfct.ads new file mode 100644 index 000000000..d85e75da0 --- /dev/null +++ b/arch/ARM/Nordic/svd/nrf52/nrf_svd-nfct.ads @@ -0,0 +1,1924 @@ +-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- 2. Redistributions in binary form, except as embedded into a Nordic +-- Semiconductor ASA integrated circuit in a product or a software update for +-- such product, must reproduce the above copyright notice, this list of +-- conditions and the following disclaimer in the documentation and/or other +-- materials provided with the distribution. +-- +-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from this +-- software without specific prior written permission. +-- +-- 4. This software, with or without modification, must only be used with a +-- Nordic Semiconductor ASA integrated circuit. +-- +-- 5. Any software provided in binary form under this license must not be reverse +-- engineered, decompiled, modified and/or disassembled. +-- +-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +-- OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + +-- This spec has been automatically generated from nrf52.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package NRF_SVD.NFCT is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Shortcut between FIELDDETECTED event and ACTIVATE task + type SHORTS_FIELDDETECTED_ACTIVATE_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_FIELDDETECTED_ACTIVATE_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut between FIELDLOST event and SENSE task + type SHORTS_FIELDLOST_SENSE_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_FIELDLOST_SENSE_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut register + type SHORTS_Register is record + -- Shortcut between FIELDDETECTED event and ACTIVATE task + FIELDDETECTED_ACTIVATE : SHORTS_FIELDDETECTED_ACTIVATE_Field := + NRF_SVD.NFCT.Disabled; + -- Shortcut between FIELDLOST event and SENSE task + FIELDLOST_SENSE : SHORTS_FIELDLOST_SENSE_Field := + NRF_SVD.NFCT.Disabled; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SHORTS_Register use record + FIELDDETECTED_ACTIVATE at 0 range 0 .. 0; + FIELDLOST_SENSE at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + -- Enable or disable interrupt for READY event + type INTEN_READY_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_READY_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for FIELDDETECTED event + type INTEN_FIELDDETECTED_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_FIELDDETECTED_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for FIELDLOST event + type INTEN_FIELDLOST_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_FIELDLOST_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for TXFRAMESTART event + type INTEN_TXFRAMESTART_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_TXFRAMESTART_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for TXFRAMEEND event + type INTEN_TXFRAMEEND_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_TXFRAMEEND_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for RXFRAMESTART event + type INTEN_RXFRAMESTART_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_RXFRAMESTART_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for RXFRAMEEND event + type INTEN_RXFRAMEEND_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_RXFRAMEEND_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for ERROR event + type INTEN_ERROR_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_ERROR_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for RXERROR event + type INTEN_RXERROR_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_RXERROR_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for ENDRX event + type INTEN_ENDRX_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_ENDRX_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for ENDTX event + type INTEN_ENDTX_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_ENDTX_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for AUTOCOLRESSTARTED event + type INTEN_AUTOCOLRESSTARTED_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_AUTOCOLRESSTARTED_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for COLLISION event + type INTEN_COLLISION_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_COLLISION_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for SELECTED event + type INTEN_SELECTED_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_SELECTED_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for STARTED event + type INTEN_STARTED_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_STARTED_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt + type INTEN_Register is record + -- Enable or disable interrupt for READY event + READY : INTEN_READY_Field := NRF_SVD.NFCT.Disabled; + -- Enable or disable interrupt for FIELDDETECTED event + FIELDDETECTED : INTEN_FIELDDETECTED_Field := NRF_SVD.NFCT.Disabled; + -- Enable or disable interrupt for FIELDLOST event + FIELDLOST : INTEN_FIELDLOST_Field := NRF_SVD.NFCT.Disabled; + -- Enable or disable interrupt for TXFRAMESTART event + TXFRAMESTART : INTEN_TXFRAMESTART_Field := NRF_SVD.NFCT.Disabled; + -- Enable or disable interrupt for TXFRAMEEND event + TXFRAMEEND : INTEN_TXFRAMEEND_Field := NRF_SVD.NFCT.Disabled; + -- Enable or disable interrupt for RXFRAMESTART event + RXFRAMESTART : INTEN_RXFRAMESTART_Field := NRF_SVD.NFCT.Disabled; + -- Enable or disable interrupt for RXFRAMEEND event + RXFRAMEEND : INTEN_RXFRAMEEND_Field := NRF_SVD.NFCT.Disabled; + -- Enable or disable interrupt for ERROR event + ERROR : INTEN_ERROR_Field := NRF_SVD.NFCT.Disabled; + -- unspecified + Reserved_8_9 : HAL.UInt2 := 16#0#; + -- Enable or disable interrupt for RXERROR event + RXERROR : INTEN_RXERROR_Field := NRF_SVD.NFCT.Disabled; + -- Enable or disable interrupt for ENDRX event + ENDRX : INTEN_ENDRX_Field := NRF_SVD.NFCT.Disabled; + -- Enable or disable interrupt for ENDTX event + ENDTX : INTEN_ENDTX_Field := NRF_SVD.NFCT.Disabled; + -- unspecified + Reserved_13_13 : HAL.Bit := 16#0#; + -- Enable or disable interrupt for AUTOCOLRESSTARTED event + AUTOCOLRESSTARTED : INTEN_AUTOCOLRESSTARTED_Field := + NRF_SVD.NFCT.Disabled; + -- unspecified + Reserved_15_17 : HAL.UInt3 := 16#0#; + -- Enable or disable interrupt for COLLISION event + COLLISION : INTEN_COLLISION_Field := NRF_SVD.NFCT.Disabled; + -- Enable or disable interrupt for SELECTED event + SELECTED : INTEN_SELECTED_Field := NRF_SVD.NFCT.Disabled; + -- Enable or disable interrupt for STARTED event + STARTED : INTEN_STARTED_Field := NRF_SVD.NFCT.Disabled; + -- unspecified + Reserved_21_31 : HAL.UInt11 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTEN_Register use record + READY at 0 range 0 .. 0; + FIELDDETECTED at 0 range 1 .. 1; + FIELDLOST at 0 range 2 .. 2; + TXFRAMESTART at 0 range 3 .. 3; + TXFRAMEEND at 0 range 4 .. 4; + RXFRAMESTART at 0 range 5 .. 5; + RXFRAMEEND at 0 range 6 .. 6; + ERROR at 0 range 7 .. 7; + Reserved_8_9 at 0 range 8 .. 9; + RXERROR at 0 range 10 .. 10; + ENDRX at 0 range 11 .. 11; + ENDTX at 0 range 12 .. 12; + Reserved_13_13 at 0 range 13 .. 13; + AUTOCOLRESSTARTED at 0 range 14 .. 14; + Reserved_15_17 at 0 range 15 .. 17; + COLLISION at 0 range 18 .. 18; + SELECTED at 0 range 19 .. 19; + STARTED at 0 range 20 .. 20; + Reserved_21_31 at 0 range 21 .. 31; + end record; + + -- Write '1' to Enable interrupt for READY event + type INTENSET_READY_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_READY_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for READY event + type INTENSET_READY_Field_1 is + (-- Reset value for the field + Intenset_Ready_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_READY_Field_1 use + (Intenset_Ready_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for FIELDDETECTED event + type INTENSET_FIELDDETECTED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_FIELDDETECTED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for FIELDDETECTED event + type INTENSET_FIELDDETECTED_Field_1 is + (-- Reset value for the field + Intenset_Fielddetected_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_FIELDDETECTED_Field_1 use + (Intenset_Fielddetected_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for FIELDLOST event + type INTENSET_FIELDLOST_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_FIELDLOST_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for FIELDLOST event + type INTENSET_FIELDLOST_Field_1 is + (-- Reset value for the field + Intenset_Fieldlost_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_FIELDLOST_Field_1 use + (Intenset_Fieldlost_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for TXFRAMESTART event + type INTENSET_TXFRAMESTART_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_TXFRAMESTART_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for TXFRAMESTART event + type INTENSET_TXFRAMESTART_Field_1 is + (-- Reset value for the field + Intenset_Txframestart_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_TXFRAMESTART_Field_1 use + (Intenset_Txframestart_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for TXFRAMEEND event + type INTENSET_TXFRAMEEND_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_TXFRAMEEND_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for TXFRAMEEND event + type INTENSET_TXFRAMEEND_Field_1 is + (-- Reset value for the field + Intenset_Txframeend_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_TXFRAMEEND_Field_1 use + (Intenset_Txframeend_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for RXFRAMESTART event + type INTENSET_RXFRAMESTART_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_RXFRAMESTART_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for RXFRAMESTART event + type INTENSET_RXFRAMESTART_Field_1 is + (-- Reset value for the field + Intenset_Rxframestart_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_RXFRAMESTART_Field_1 use + (Intenset_Rxframestart_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for RXFRAMEEND event + type INTENSET_RXFRAMEEND_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_RXFRAMEEND_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for RXFRAMEEND event + type INTENSET_RXFRAMEEND_Field_1 is + (-- Reset value for the field + Intenset_Rxframeend_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_RXFRAMEEND_Field_1 use + (Intenset_Rxframeend_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for ERROR event + type INTENSET_ERROR_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_ERROR_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for ERROR event + type INTENSET_ERROR_Field_1 is + (-- Reset value for the field + Intenset_Error_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_ERROR_Field_1 use + (Intenset_Error_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for RXERROR event + type INTENSET_RXERROR_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_RXERROR_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for RXERROR event + type INTENSET_RXERROR_Field_1 is + (-- Reset value for the field + Intenset_Rxerror_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_RXERROR_Field_1 use + (Intenset_Rxerror_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for ENDRX event + type INTENSET_ENDRX_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_ENDRX_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for ENDRX event + type INTENSET_ENDRX_Field_1 is + (-- Reset value for the field + Intenset_Endrx_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_ENDRX_Field_1 use + (Intenset_Endrx_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for ENDTX event + type INTENSET_ENDTX_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_ENDTX_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for ENDTX event + type INTENSET_ENDTX_Field_1 is + (-- Reset value for the field + Intenset_Endtx_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_ENDTX_Field_1 use + (Intenset_Endtx_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for AUTOCOLRESSTARTED event + type INTENSET_AUTOCOLRESSTARTED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_AUTOCOLRESSTARTED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for AUTOCOLRESSTARTED event + type INTENSET_AUTOCOLRESSTARTED_Field_1 is + (-- Reset value for the field + Intenset_Autocolresstarted_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_AUTOCOLRESSTARTED_Field_1 use + (Intenset_Autocolresstarted_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for COLLISION event + type INTENSET_COLLISION_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_COLLISION_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for COLLISION event + type INTENSET_COLLISION_Field_1 is + (-- Reset value for the field + Intenset_Collision_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_COLLISION_Field_1 use + (Intenset_Collision_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for SELECTED event + type INTENSET_SELECTED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_SELECTED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for SELECTED event + type INTENSET_SELECTED_Field_1 is + (-- Reset value for the field + Intenset_Selected_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_SELECTED_Field_1 use + (Intenset_Selected_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for STARTED event + type INTENSET_STARTED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_STARTED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for STARTED event + type INTENSET_STARTED_Field_1 is + (-- Reset value for the field + Intenset_Started_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_STARTED_Field_1 use + (Intenset_Started_Field_Reset => 0, + Set => 1); + + -- Enable interrupt + type INTENSET_Register is record + -- Write '1' to Enable interrupt for READY event + READY : INTENSET_READY_Field_1 := + Intenset_Ready_Field_Reset; + -- Write '1' to Enable interrupt for FIELDDETECTED event + FIELDDETECTED : INTENSET_FIELDDETECTED_Field_1 := + Intenset_Fielddetected_Field_Reset; + -- Write '1' to Enable interrupt for FIELDLOST event + FIELDLOST : INTENSET_FIELDLOST_Field_1 := + Intenset_Fieldlost_Field_Reset; + -- Write '1' to Enable interrupt for TXFRAMESTART event + TXFRAMESTART : INTENSET_TXFRAMESTART_Field_1 := + Intenset_Txframestart_Field_Reset; + -- Write '1' to Enable interrupt for TXFRAMEEND event + TXFRAMEEND : INTENSET_TXFRAMEEND_Field_1 := + Intenset_Txframeend_Field_Reset; + -- Write '1' to Enable interrupt for RXFRAMESTART event + RXFRAMESTART : INTENSET_RXFRAMESTART_Field_1 := + Intenset_Rxframestart_Field_Reset; + -- Write '1' to Enable interrupt for RXFRAMEEND event + RXFRAMEEND : INTENSET_RXFRAMEEND_Field_1 := + Intenset_Rxframeend_Field_Reset; + -- Write '1' to Enable interrupt for ERROR event + ERROR : INTENSET_ERROR_Field_1 := + Intenset_Error_Field_Reset; + -- unspecified + Reserved_8_9 : HAL.UInt2 := 16#0#; + -- Write '1' to Enable interrupt for RXERROR event + RXERROR : INTENSET_RXERROR_Field_1 := + Intenset_Rxerror_Field_Reset; + -- Write '1' to Enable interrupt for ENDRX event + ENDRX : INTENSET_ENDRX_Field_1 := + Intenset_Endrx_Field_Reset; + -- Write '1' to Enable interrupt for ENDTX event + ENDTX : INTENSET_ENDTX_Field_1 := + Intenset_Endtx_Field_Reset; + -- unspecified + Reserved_13_13 : HAL.Bit := 16#0#; + -- Write '1' to Enable interrupt for AUTOCOLRESSTARTED event + AUTOCOLRESSTARTED : INTENSET_AUTOCOLRESSTARTED_Field_1 := + Intenset_Autocolresstarted_Field_Reset; + -- unspecified + Reserved_15_17 : HAL.UInt3 := 16#0#; + -- Write '1' to Enable interrupt for COLLISION event + COLLISION : INTENSET_COLLISION_Field_1 := + Intenset_Collision_Field_Reset; + -- Write '1' to Enable interrupt for SELECTED event + SELECTED : INTENSET_SELECTED_Field_1 := + Intenset_Selected_Field_Reset; + -- Write '1' to Enable interrupt for STARTED event + STARTED : INTENSET_STARTED_Field_1 := + Intenset_Started_Field_Reset; + -- unspecified + Reserved_21_31 : HAL.UInt11 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENSET_Register use record + READY at 0 range 0 .. 0; + FIELDDETECTED at 0 range 1 .. 1; + FIELDLOST at 0 range 2 .. 2; + TXFRAMESTART at 0 range 3 .. 3; + TXFRAMEEND at 0 range 4 .. 4; + RXFRAMESTART at 0 range 5 .. 5; + RXFRAMEEND at 0 range 6 .. 6; + ERROR at 0 range 7 .. 7; + Reserved_8_9 at 0 range 8 .. 9; + RXERROR at 0 range 10 .. 10; + ENDRX at 0 range 11 .. 11; + ENDTX at 0 range 12 .. 12; + Reserved_13_13 at 0 range 13 .. 13; + AUTOCOLRESSTARTED at 0 range 14 .. 14; + Reserved_15_17 at 0 range 15 .. 17; + COLLISION at 0 range 18 .. 18; + SELECTED at 0 range 19 .. 19; + STARTED at 0 range 20 .. 20; + Reserved_21_31 at 0 range 21 .. 31; + end record; + + -- Write '1' to Disable interrupt for READY event + type INTENCLR_READY_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_READY_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for READY event + type INTENCLR_READY_Field_1 is + (-- Reset value for the field + Intenclr_Ready_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_READY_Field_1 use + (Intenclr_Ready_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for FIELDDETECTED event + type INTENCLR_FIELDDETECTED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_FIELDDETECTED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for FIELDDETECTED event + type INTENCLR_FIELDDETECTED_Field_1 is + (-- Reset value for the field + Intenclr_Fielddetected_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_FIELDDETECTED_Field_1 use + (Intenclr_Fielddetected_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for FIELDLOST event + type INTENCLR_FIELDLOST_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_FIELDLOST_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for FIELDLOST event + type INTENCLR_FIELDLOST_Field_1 is + (-- Reset value for the field + Intenclr_Fieldlost_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_FIELDLOST_Field_1 use + (Intenclr_Fieldlost_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for TXFRAMESTART event + type INTENCLR_TXFRAMESTART_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_TXFRAMESTART_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for TXFRAMESTART event + type INTENCLR_TXFRAMESTART_Field_1 is + (-- Reset value for the field + Intenclr_Txframestart_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_TXFRAMESTART_Field_1 use + (Intenclr_Txframestart_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for TXFRAMEEND event + type INTENCLR_TXFRAMEEND_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_TXFRAMEEND_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for TXFRAMEEND event + type INTENCLR_TXFRAMEEND_Field_1 is + (-- Reset value for the field + Intenclr_Txframeend_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_TXFRAMEEND_Field_1 use + (Intenclr_Txframeend_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for RXFRAMESTART event + type INTENCLR_RXFRAMESTART_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_RXFRAMESTART_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for RXFRAMESTART event + type INTENCLR_RXFRAMESTART_Field_1 is + (-- Reset value for the field + Intenclr_Rxframestart_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_RXFRAMESTART_Field_1 use + (Intenclr_Rxframestart_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for RXFRAMEEND event + type INTENCLR_RXFRAMEEND_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_RXFRAMEEND_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for RXFRAMEEND event + type INTENCLR_RXFRAMEEND_Field_1 is + (-- Reset value for the field + Intenclr_Rxframeend_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_RXFRAMEEND_Field_1 use + (Intenclr_Rxframeend_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for ERROR event + type INTENCLR_ERROR_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_ERROR_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for ERROR event + type INTENCLR_ERROR_Field_1 is + (-- Reset value for the field + Intenclr_Error_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_ERROR_Field_1 use + (Intenclr_Error_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for RXERROR event + type INTENCLR_RXERROR_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_RXERROR_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for RXERROR event + type INTENCLR_RXERROR_Field_1 is + (-- Reset value for the field + Intenclr_Rxerror_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_RXERROR_Field_1 use + (Intenclr_Rxerror_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for ENDRX event + type INTENCLR_ENDRX_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_ENDRX_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for ENDRX event + type INTENCLR_ENDRX_Field_1 is + (-- Reset value for the field + Intenclr_Endrx_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_ENDRX_Field_1 use + (Intenclr_Endrx_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for ENDTX event + type INTENCLR_ENDTX_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_ENDTX_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for ENDTX event + type INTENCLR_ENDTX_Field_1 is + (-- Reset value for the field + Intenclr_Endtx_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_ENDTX_Field_1 use + (Intenclr_Endtx_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for AUTOCOLRESSTARTED event + type INTENCLR_AUTOCOLRESSTARTED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_AUTOCOLRESSTARTED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for AUTOCOLRESSTARTED event + type INTENCLR_AUTOCOLRESSTARTED_Field_1 is + (-- Reset value for the field + Intenclr_Autocolresstarted_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_AUTOCOLRESSTARTED_Field_1 use + (Intenclr_Autocolresstarted_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for COLLISION event + type INTENCLR_COLLISION_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_COLLISION_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for COLLISION event + type INTENCLR_COLLISION_Field_1 is + (-- Reset value for the field + Intenclr_Collision_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_COLLISION_Field_1 use + (Intenclr_Collision_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for SELECTED event + type INTENCLR_SELECTED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_SELECTED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for SELECTED event + type INTENCLR_SELECTED_Field_1 is + (-- Reset value for the field + Intenclr_Selected_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_SELECTED_Field_1 use + (Intenclr_Selected_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for STARTED event + type INTENCLR_STARTED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_STARTED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for STARTED event + type INTENCLR_STARTED_Field_1 is + (-- Reset value for the field + Intenclr_Started_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_STARTED_Field_1 use + (Intenclr_Started_Field_Reset => 0, + Clear => 1); + + -- Disable interrupt + type INTENCLR_Register is record + -- Write '1' to Disable interrupt for READY event + READY : INTENCLR_READY_Field_1 := + Intenclr_Ready_Field_Reset; + -- Write '1' to Disable interrupt for FIELDDETECTED event + FIELDDETECTED : INTENCLR_FIELDDETECTED_Field_1 := + Intenclr_Fielddetected_Field_Reset; + -- Write '1' to Disable interrupt for FIELDLOST event + FIELDLOST : INTENCLR_FIELDLOST_Field_1 := + Intenclr_Fieldlost_Field_Reset; + -- Write '1' to Disable interrupt for TXFRAMESTART event + TXFRAMESTART : INTENCLR_TXFRAMESTART_Field_1 := + Intenclr_Txframestart_Field_Reset; + -- Write '1' to Disable interrupt for TXFRAMEEND event + TXFRAMEEND : INTENCLR_TXFRAMEEND_Field_1 := + Intenclr_Txframeend_Field_Reset; + -- Write '1' to Disable interrupt for RXFRAMESTART event + RXFRAMESTART : INTENCLR_RXFRAMESTART_Field_1 := + Intenclr_Rxframestart_Field_Reset; + -- Write '1' to Disable interrupt for RXFRAMEEND event + RXFRAMEEND : INTENCLR_RXFRAMEEND_Field_1 := + Intenclr_Rxframeend_Field_Reset; + -- Write '1' to Disable interrupt for ERROR event + ERROR : INTENCLR_ERROR_Field_1 := + Intenclr_Error_Field_Reset; + -- unspecified + Reserved_8_9 : HAL.UInt2 := 16#0#; + -- Write '1' to Disable interrupt for RXERROR event + RXERROR : INTENCLR_RXERROR_Field_1 := + Intenclr_Rxerror_Field_Reset; + -- Write '1' to Disable interrupt for ENDRX event + ENDRX : INTENCLR_ENDRX_Field_1 := + Intenclr_Endrx_Field_Reset; + -- Write '1' to Disable interrupt for ENDTX event + ENDTX : INTENCLR_ENDTX_Field_1 := + Intenclr_Endtx_Field_Reset; + -- unspecified + Reserved_13_13 : HAL.Bit := 16#0#; + -- Write '1' to Disable interrupt for AUTOCOLRESSTARTED event + AUTOCOLRESSTARTED : INTENCLR_AUTOCOLRESSTARTED_Field_1 := + Intenclr_Autocolresstarted_Field_Reset; + -- unspecified + Reserved_15_17 : HAL.UInt3 := 16#0#; + -- Write '1' to Disable interrupt for COLLISION event + COLLISION : INTENCLR_COLLISION_Field_1 := + Intenclr_Collision_Field_Reset; + -- Write '1' to Disable interrupt for SELECTED event + SELECTED : INTENCLR_SELECTED_Field_1 := + Intenclr_Selected_Field_Reset; + -- Write '1' to Disable interrupt for STARTED event + STARTED : INTENCLR_STARTED_Field_1 := + Intenclr_Started_Field_Reset; + -- unspecified + Reserved_21_31 : HAL.UInt11 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENCLR_Register use record + READY at 0 range 0 .. 0; + FIELDDETECTED at 0 range 1 .. 1; + FIELDLOST at 0 range 2 .. 2; + TXFRAMESTART at 0 range 3 .. 3; + TXFRAMEEND at 0 range 4 .. 4; + RXFRAMESTART at 0 range 5 .. 5; + RXFRAMEEND at 0 range 6 .. 6; + ERROR at 0 range 7 .. 7; + Reserved_8_9 at 0 range 8 .. 9; + RXERROR at 0 range 10 .. 10; + ENDRX at 0 range 11 .. 11; + ENDTX at 0 range 12 .. 12; + Reserved_13_13 at 0 range 13 .. 13; + AUTOCOLRESSTARTED at 0 range 14 .. 14; + Reserved_15_17 at 0 range 15 .. 17; + COLLISION at 0 range 18 .. 18; + SELECTED at 0 range 19 .. 19; + STARTED at 0 range 20 .. 20; + Reserved_21_31 at 0 range 21 .. 31; + end record; + + -- NFC Error Status register + type ERRORSTATUS_Register is record + -- No STARTTX task triggered before expiration of the time set in + -- FRAMEDELAYMAX + FRAMEDELAYTIMEOUT : Boolean := False; + -- unspecified + Reserved_1_1 : HAL.Bit := 16#0#; + -- Field level is too high at max load resistance + NFCFIELDTOOSTRONG : Boolean := False; + -- Field level is too low at min load resistance + NFCFIELDTOOWEAK : Boolean := False; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ERRORSTATUS_Register use record + FRAMEDELAYTIMEOUT at 0 range 0 .. 0; + Reserved_1_1 at 0 range 1 .. 1; + NFCFIELDTOOSTRONG at 0 range 2 .. 2; + NFCFIELDTOOWEAK at 0 range 3 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + ------------------------------------- + -- FRAMESTATUS cluster's Registers -- + ------------------------------------- + + -- No valid End of Frame detected + type RX_CRCERROR_Field is + (-- Valid CRC detected + Crccorrect, + -- CRC received does not match local check + Crcerror) + with Size => 1; + for RX_CRCERROR_Field use + (Crccorrect => 0, + Crcerror => 1); + + -- Parity status of received frame + type RX_PARITYSTATUS_Field is + (-- Frame received with parity OK + Parityok, + -- Frame received with parity error + Parityerror) + with Size => 1; + for RX_PARITYSTATUS_Field use + (Parityok => 0, + Parityerror => 1); + + -- Overrun detected + type RX_OVERRUN_Field is + (-- No overrun detected + Nooverrun, + -- Overrun error + Overrun) + with Size => 1; + for RX_OVERRUN_Field use + (Nooverrun => 0, + Overrun => 1); + + -- Result of last incoming frames + type RX_FRAMESTATUS_Register is record + -- No valid End of Frame detected + CRCERROR : RX_CRCERROR_Field := NRF_SVD.NFCT.Crccorrect; + -- unspecified + Reserved_1_1 : HAL.Bit := 16#0#; + -- Parity status of received frame + PARITYSTATUS : RX_PARITYSTATUS_Field := NRF_SVD.NFCT.Parityok; + -- Overrun detected + OVERRUN : RX_OVERRUN_Field := NRF_SVD.NFCT.Nooverrun; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RX_FRAMESTATUS_Register use record + CRCERROR at 0 range 0 .. 0; + Reserved_1_1 at 0 range 1 .. 1; + PARITYSTATUS at 0 range 2 .. 2; + OVERRUN at 0 range 3 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- Unspecified + type FRAMESTATUS_Cluster is record + -- Result of last incoming frames + RX : aliased RX_FRAMESTATUS_Register; + end record + with Size => 32; + + for FRAMESTATUS_Cluster use record + RX at 0 range 0 .. 31; + end record; + + subtype CURRENTLOADCTRL_CURRENTLOADCTRL_Field is HAL.UInt6; + + -- Current value driven to the NFC Load Control + type CURRENTLOADCTRL_Register is record + -- Read-only. Current value driven to the NFC Load Control + CURRENTLOADCTRL : CURRENTLOADCTRL_CURRENTLOADCTRL_Field; + -- unspecified + Reserved_6_31 : HAL.UInt26; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CURRENTLOADCTRL_Register use record + CURRENTLOADCTRL at 0 range 0 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + -- Indicates the presence or not of a valid field. Available only in the + -- activated state. + type FIELDPRESENT_FIELDPRESENT_Field is + (-- No valid field detected + Nofield, + -- Valid field detected + Fieldpresent) + with Size => 1; + for FIELDPRESENT_FIELDPRESENT_Field use + (Nofield => 0, + Fieldpresent => 1); + + -- Indicates if the low level has locked to the field + type FIELDPRESENT_LOCKDETECT_Field is + (-- Not locked to field + Notlocked, + -- Locked to field + Locked) + with Size => 1; + for FIELDPRESENT_LOCKDETECT_Field use + (Notlocked => 0, + Locked => 1); + + -- Indicates the presence or not of a valid field + type FIELDPRESENT_Register is record + -- Read-only. Indicates the presence or not of a valid field. Available + -- only in the activated state. + FIELDPRESENT : FIELDPRESENT_FIELDPRESENT_Field; + -- Read-only. Indicates if the low level has locked to the field + LOCKDETECT : FIELDPRESENT_LOCKDETECT_Field; + -- unspecified + Reserved_2_31 : HAL.UInt30; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FIELDPRESENT_Register use record + FIELDPRESENT at 0 range 0 .. 0; + LOCKDETECT at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + subtype FRAMEDELAYMIN_FRAMEDELAYMIN_Field is HAL.UInt16; + + -- Minimum frame delay + type FRAMEDELAYMIN_Register is record + -- Minimum frame delay in number of 13.56 MHz clocks + FRAMEDELAYMIN : FRAMEDELAYMIN_FRAMEDELAYMIN_Field := 16#480#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FRAMEDELAYMIN_Register use record + FRAMEDELAYMIN at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype FRAMEDELAYMAX_FRAMEDELAYMAX_Field is HAL.UInt16; + + -- Maximum frame delay + type FRAMEDELAYMAX_Register is record + -- Maximum frame delay in number of 13.56 MHz clocks + FRAMEDELAYMAX : FRAMEDELAYMAX_FRAMEDELAYMAX_Field := 16#1000#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FRAMEDELAYMAX_Register use record + FRAMEDELAYMAX at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- Configuration register for the Frame Delay Timer + type FRAMEDELAYMODE_FRAMEDELAYMODE_Field is + (-- Transmission is independent of frame timer and will start when the STARTTX +-- task is triggered. No timeout. + Freerun, + -- Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX + Window, + -- Frame is transmitted exactly at FRAMEDELAYMAX + Exactval, + -- Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX + Windowgrid) + with Size => 2; + for FRAMEDELAYMODE_FRAMEDELAYMODE_Field use + (Freerun => 0, + Window => 1, + Exactval => 2, + Windowgrid => 3); + + -- Configuration register for the Frame Delay Timer + type FRAMEDELAYMODE_Register is record + -- Configuration register for the Frame Delay Timer + FRAMEDELAYMODE : FRAMEDELAYMODE_FRAMEDELAYMODE_Field := + NRF_SVD.NFCT.Window; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FRAMEDELAYMODE_Register use record + FRAMEDELAYMODE at 0 range 0 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + subtype MAXLEN_MAXLEN_Field is HAL.UInt9; + + -- Size of allocated for TXD and RXD data storage buffer in Data RAM + type MAXLEN_Register is record + -- Size of allocated for TXD and RXD data storage buffer in Data RAM + MAXLEN : MAXLEN_MAXLEN_Field := 16#0#; + -- unspecified + Reserved_9_31 : HAL.UInt23 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MAXLEN_Register use record + MAXLEN at 0 range 0 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + ----------------------------- + -- TXD cluster's Registers -- + ----------------------------- + + -- Adding parity or not in the frame + type FRAMECONFIG_PARITY_Field is + (-- Parity is not added in TX frames + Noparity, + -- Parity is added TX frames + Parity) + with Size => 1; + for FRAMECONFIG_PARITY_Field use + (Noparity => 0, + Parity => 1); + + -- Discarding unused bits in start or at end of a Frame + type FRAMECONFIG_DISCARDMODE_Field is + (-- Unused bits is discarded at end of frame + Discardend, + -- Unused bits is discarded at start of frame + Discardstart) + with Size => 1; + for FRAMECONFIG_DISCARDMODE_Field use + (Discardend => 0, + Discardstart => 1); + + -- Adding SoF or not in TX frames + type FRAMECONFIG_SOF_Field is + (-- Start of Frame symbol not added + Nosof, + -- Start of Frame symbol added + Sof) + with Size => 1; + for FRAMECONFIG_SOF_Field use + (Nosof => 0, + Sof => 1); + + -- CRC mode for outgoing frames + type FRAMECONFIG_CRCMODETX_Field is + (-- CRC is not added to the frame + Nocrctx, + -- 16 bit CRC added to the frame based on all the data read from RAM that is +-- used in the frame + Crc16Tx) + with Size => 1; + for FRAMECONFIG_CRCMODETX_Field use + (Nocrctx => 0, + Crc16Tx => 1); + + -- Configuration of outgoing frames + type FRAMECONFIG_TXD_Register is record + -- Adding parity or not in the frame + PARITY : FRAMECONFIG_PARITY_Field := NRF_SVD.NFCT.Parity; + -- Discarding unused bits in start or at end of a Frame + DISCARDMODE : FRAMECONFIG_DISCARDMODE_Field := + NRF_SVD.NFCT.Discardstart; + -- Adding SoF or not in TX frames + SOF : FRAMECONFIG_SOF_Field := NRF_SVD.NFCT.Sof; + -- unspecified + Reserved_3_3 : HAL.Bit := 16#0#; + -- CRC mode for outgoing frames + CRCMODETX : FRAMECONFIG_CRCMODETX_Field := NRF_SVD.NFCT.Crc16Tx; + -- unspecified + Reserved_5_31 : HAL.UInt27 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FRAMECONFIG_TXD_Register use record + PARITY at 0 range 0 .. 0; + DISCARDMODE at 0 range 1 .. 1; + SOF at 0 range 2 .. 2; + Reserved_3_3 at 0 range 3 .. 3; + CRCMODETX at 0 range 4 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + subtype AMOUNT_TXD_TXDATABITS_Field is HAL.UInt3; + subtype AMOUNT_TXD_TXDATABYTES_Field is HAL.UInt9; + + -- Size of outgoing frame + type AMOUNT_TXD_Register is record + -- Number of bits in the last or first byte read from RAM that shall be + -- included in the frame (excluding parity bit). + TXDATABITS : AMOUNT_TXD_TXDATABITS_Field := 16#0#; + -- Number of complete bytes that shall be included in the frame, + -- excluding CRC, parity and framing + TXDATABYTES : AMOUNT_TXD_TXDATABYTES_Field := 16#0#; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for AMOUNT_TXD_Register use record + TXDATABITS at 0 range 0 .. 2; + TXDATABYTES at 0 range 3 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + -- Unspecified + type TXD_Cluster is record + -- Configuration of outgoing frames + FRAMECONFIG : aliased FRAMECONFIG_TXD_Register; + -- Size of outgoing frame + AMOUNT : aliased AMOUNT_TXD_Register; + end record + with Size => 64; + + for TXD_Cluster use record + FRAMECONFIG at 16#0# range 0 .. 31; + AMOUNT at 16#4# range 0 .. 31; + end record; + + ----------------------------- + -- RXD cluster's Registers -- + ----------------------------- + + -- CRC mode for incoming frames + type FRAMECONFIG_CRCMODERX_Field is + (-- CRC is not expected in RX frames + Nocrcrx, + -- Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated + Crc16Rx) + with Size => 1; + for FRAMECONFIG_CRCMODERX_Field use + (Nocrcrx => 0, + Crc16Rx => 1); + + -- Configuration of incoming frames + type FRAMECONFIG_RXD_Register is record + -- Parity expected or not in RX frame + PARITY : FRAMECONFIG_PARITY_Field := NRF_SVD.NFCT.Parity; + -- unspecified + Reserved_1_1 : HAL.Bit := 16#0#; + -- SoF expected or not in RX frames + SOF : FRAMECONFIG_SOF_Field := NRF_SVD.NFCT.Sof; + -- unspecified + Reserved_3_3 : HAL.Bit := 16#0#; + -- CRC mode for incoming frames + CRCMODERX : FRAMECONFIG_CRCMODERX_Field := NRF_SVD.NFCT.Crc16Rx; + -- unspecified + Reserved_5_31 : HAL.UInt27 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FRAMECONFIG_RXD_Register use record + PARITY at 0 range 0 .. 0; + Reserved_1_1 at 0 range 1 .. 1; + SOF at 0 range 2 .. 2; + Reserved_3_3 at 0 range 3 .. 3; + CRCMODERX at 0 range 4 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + subtype AMOUNT_RXD_RXDATABITS_Field is HAL.UInt3; + subtype AMOUNT_RXD_RXDATABYTES_Field is HAL.UInt9; + + -- Size of last incoming frame + type AMOUNT_RXD_Register is record + -- Read-only. Number of bits in the last byte in the frame, if less than + -- 8 (including CRC, but excluding parity and SoF/EoF framing). + RXDATABITS : AMOUNT_RXD_RXDATABITS_Field; + -- Read-only. Number of complete bytes received in the frame (including + -- CRC, but excluding parity and SoF/EoF framing) + RXDATABYTES : AMOUNT_RXD_RXDATABYTES_Field; + -- unspecified + Reserved_12_31 : HAL.UInt20; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for AMOUNT_RXD_Register use record + RXDATABITS at 0 range 0 .. 2; + RXDATABYTES at 0 range 3 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + -- Unspecified + type RXD_Cluster is record + -- Configuration of incoming frames + FRAMECONFIG : aliased FRAMECONFIG_RXD_Register; + -- Size of last incoming frame + AMOUNT : aliased AMOUNT_RXD_Register; + end record + with Size => 64; + + for RXD_Cluster use record + FRAMECONFIG at 16#0# range 0 .. 31; + AMOUNT at 16#4# range 0 .. 31; + end record; + + subtype NFCID1_LAST_NFCID1_Z_Field is HAL.UInt8; + subtype NFCID1_LAST_NFCID1_Y_Field is HAL.UInt8; + subtype NFCID1_LAST_NFCID1_X_Field is HAL.UInt8; + subtype NFCID1_LAST_NFCID1_W_Field is HAL.UInt8; + + -- Last NFCID1 part (4, 7 or 10 bytes ID) + type NFCID1_LAST_Register is record + -- NFCID1 byte Z (very last byte sent) + NFCID1_Z : NFCID1_LAST_NFCID1_Z_Field := 16#63#; + -- NFCID1 byte Y + NFCID1_Y : NFCID1_LAST_NFCID1_Y_Field := 16#63#; + -- NFCID1 byte X + NFCID1_X : NFCID1_LAST_NFCID1_X_Field := 16#0#; + -- NFCID1 byte W + NFCID1_W : NFCID1_LAST_NFCID1_W_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for NFCID1_LAST_Register use record + NFCID1_Z at 0 range 0 .. 7; + NFCID1_Y at 0 range 8 .. 15; + NFCID1_X at 0 range 16 .. 23; + NFCID1_W at 0 range 24 .. 31; + end record; + + subtype NFCID1_2ND_LAST_NFCID1_V_Field is HAL.UInt8; + subtype NFCID1_2ND_LAST_NFCID1_U_Field is HAL.UInt8; + subtype NFCID1_2ND_LAST_NFCID1_T_Field is HAL.UInt8; + + -- Second last NFCID1 part (7 or 10 bytes ID) + type NFCID1_2ND_LAST_Register is record + -- NFCID1 byte V + NFCID1_V : NFCID1_2ND_LAST_NFCID1_V_Field := 16#0#; + -- NFCID1 byte U + NFCID1_U : NFCID1_2ND_LAST_NFCID1_U_Field := 16#0#; + -- NFCID1 byte T + NFCID1_T : NFCID1_2ND_LAST_NFCID1_T_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for NFCID1_2ND_LAST_Register use record + NFCID1_V at 0 range 0 .. 7; + NFCID1_U at 0 range 8 .. 15; + NFCID1_T at 0 range 16 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype NFCID1_3RD_LAST_NFCID1_S_Field is HAL.UInt8; + subtype NFCID1_3RD_LAST_NFCID1_R_Field is HAL.UInt8; + subtype NFCID1_3RD_LAST_NFCID1_Q_Field is HAL.UInt8; + + -- Third last NFCID1 part (10 bytes ID) + type NFCID1_3RD_LAST_Register is record + -- NFCID1 byte S + NFCID1_S : NFCID1_3RD_LAST_NFCID1_S_Field := 16#0#; + -- NFCID1 byte R + NFCID1_R : NFCID1_3RD_LAST_NFCID1_R_Field := 16#0#; + -- NFCID1 byte Q + NFCID1_Q : NFCID1_3RD_LAST_NFCID1_Q_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for NFCID1_3RD_LAST_Register use record + NFCID1_S at 0 range 0 .. 7; + NFCID1_R at 0 range 8 .. 15; + NFCID1_Q at 0 range 16 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in + -- the NFC Forum, NFC Digital Protocol Technical Specification + type SENSRES_BITFRAMESDD_Field is + (-- SDD pattern 00000 + Sdd00000, + -- SDD pattern 00001 + Sdd00001, + -- SDD pattern 00010 + Sdd00010, + -- SDD pattern 00100 + Sdd00100, + -- SDD pattern 01000 + Sdd01000, + -- SDD pattern 10000 + Sdd10000) + with Size => 5; + for SENSRES_BITFRAMESDD_Field use + (Sdd00000 => 0, + Sdd00001 => 1, + Sdd00010 => 2, + Sdd00100 => 4, + Sdd01000 => 8, + Sdd10000 => 16); + + -- NFCID1 size. This value is used by the Auto collision resolution engine. + type SENSRES_NFCIDSIZE_Field is + (-- NFCID1 size: single (4 bytes) + Nfcid1Single, + -- NFCID1 size: double (7 bytes) + Nfcid1Double, + -- NFCID1 size: triple (10 bytes) + Nfcid1Triple) + with Size => 2; + for SENSRES_NFCIDSIZE_Field use + (Nfcid1Single => 0, + Nfcid1Double => 1, + Nfcid1Triple => 2); + + subtype SENSRES_PLATFCONFIG_Field is HAL.UInt4; + subtype SENSRES_RFU74_Field is HAL.UInt4; + + -- NFC-A SENS_RES auto-response settings + type SENSRES_Register is record + -- Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response + -- in the NFC Forum, NFC Digital Protocol Technical Specification + BITFRAMESDD : SENSRES_BITFRAMESDD_Field := NRF_SVD.NFCT.Sdd00001; + -- Reserved for future use. Shall be 0. + RFU5 : Boolean := False; + -- NFCID1 size. This value is used by the Auto collision resolution + -- engine. + NFCIDSIZE : SENSRES_NFCIDSIZE_Field := NRF_SVD.NFCT.Nfcid1Single; + -- Tag platform configuration as defined by the b4:b1 of byte 2 in + -- SENS_RES response in the NFC Forum, NFC Digital Protocol Technical + -- Specification + PLATFCONFIG : SENSRES_PLATFCONFIG_Field := 16#0#; + -- Reserved for future use. Shall be 0. + RFU74 : SENSRES_RFU74_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SENSRES_Register use record + BITFRAMESDD at 0 range 0 .. 4; + RFU5 at 0 range 5 .. 5; + NFCIDSIZE at 0 range 6 .. 7; + PLATFCONFIG at 0 range 8 .. 11; + RFU74 at 0 range 12 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype SELRES_RFU10_Field is HAL.UInt2; + + -- Cascade bit (controlled by hardware, write has no effect) + type SELRES_CASCADE_Field is + (-- NFCID1 complete + Complete, + -- NFCID1 not complete + Notcomplete) + with Size => 1; + for SELRES_CASCADE_Field use + (Complete => 0, + Notcomplete => 1); + + subtype SELRES_RFU43_Field is HAL.UInt2; + subtype SELRES_PROTOCOL_Field is HAL.UInt2; + + -- NFC-A SEL_RES auto-response settings + type SELRES_Register is record + -- Reserved for future use. Shall be 0. + RFU10 : SELRES_RFU10_Field := 16#0#; + -- Cascade bit (controlled by hardware, write has no effect) + CASCADE : SELRES_CASCADE_Field := NRF_SVD.NFCT.Complete; + -- Reserved for future use. Shall be 0. + RFU43 : SELRES_RFU43_Field := 16#0#; + -- Protocol as defined by the b7:b6 of SEL_RES response in the NFC + -- Forum, NFC Digital Protocol Technical Specification + PROTOCOL : SELRES_PROTOCOL_Field := 16#0#; + -- Reserved for future use. Shall be 0. + RFU7 : Boolean := False; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SELRES_Register use record + RFU10 at 0 range 0 .. 1; + CASCADE at 0 range 2 .. 2; + RFU43 at 0 range 3 .. 4; + PROTOCOL at 0 range 5 .. 6; + RFU7 at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- NFC-A compatible radio + type NFCT_Peripheral is record + -- Activate NFC peripheral for incoming and outgoing frames, change + -- state to activated + TASKS_ACTIVATE : aliased HAL.UInt32; + -- Disable NFC peripheral + TASKS_DISABLE : aliased HAL.UInt32; + -- Enable NFC sense field mode, change state to sense mode + TASKS_SENSE : aliased HAL.UInt32; + -- Start transmission of a outgoing frame, change state to transmit + TASKS_STARTTX : aliased HAL.UInt32; + -- Initializes the EasyDMA for receive. + TASKS_ENABLERXDATA : aliased HAL.UInt32; + -- Force state machine to IDLE state + TASKS_GOIDLE : aliased HAL.UInt32; + -- Force state machine to SLEEP_A state + TASKS_GOSLEEP : aliased HAL.UInt32; + -- The NFC peripheral is ready to receive and send frames + EVENTS_READY : aliased HAL.UInt32; + -- Remote NFC field detected + EVENTS_FIELDDETECTED : aliased HAL.UInt32; + -- Remote NFC field lost + EVENTS_FIELDLOST : aliased HAL.UInt32; + -- Marks the start of the first symbol of a transmitted frame + EVENTS_TXFRAMESTART : aliased HAL.UInt32; + -- Marks the end of the last transmitted on-air symbol of a frame + EVENTS_TXFRAMEEND : aliased HAL.UInt32; + -- Marks the end of the first symbol of a received frame + EVENTS_RXFRAMESTART : aliased HAL.UInt32; + -- Received data have been checked (CRC, parity) and transferred to RAM, + -- and EasyDMA has ended accessing the RX buffer + EVENTS_RXFRAMEEND : aliased HAL.UInt32; + -- NFC error reported. The ERRORSTATUS register contains details on the + -- source of the error. + EVENTS_ERROR : aliased HAL.UInt32; + -- NFC RX frame error reported. The FRAMESTATUS.RX register contains + -- details on the source of the error. + EVENTS_RXERROR : aliased HAL.UInt32; + -- RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. + EVENTS_ENDRX : aliased HAL.UInt32; + -- Transmission of data in RAM has ended, and EasyDMA has ended + -- accessing the TX buffer + EVENTS_ENDTX : aliased HAL.UInt32; + -- Auto collision resolution process has started + EVENTS_AUTOCOLRESSTARTED : aliased HAL.UInt32; + -- NFC Auto collision resolution error reported. + EVENTS_COLLISION : aliased HAL.UInt32; + -- NFC Auto collision resolution successfully completed + EVENTS_SELECTED : aliased HAL.UInt32; + -- EasyDMA is ready to receive or send frames. + EVENTS_STARTED : aliased HAL.UInt32; + -- Shortcut register + SHORTS : aliased SHORTS_Register; + -- Enable or disable interrupt + INTEN : aliased INTEN_Register; + -- Enable interrupt + INTENSET : aliased INTENSET_Register; + -- Disable interrupt + INTENCLR : aliased INTENCLR_Register; + -- NFC Error Status register + ERRORSTATUS : aliased ERRORSTATUS_Register; + -- Unspecified + FRAMESTATUS : aliased FRAMESTATUS_Cluster; + -- Current value driven to the NFC Load Control + CURRENTLOADCTRL : aliased CURRENTLOADCTRL_Register; + -- Indicates the presence or not of a valid field + FIELDPRESENT : aliased FIELDPRESENT_Register; + -- Minimum frame delay + FRAMEDELAYMIN : aliased FRAMEDELAYMIN_Register; + -- Maximum frame delay + FRAMEDELAYMAX : aliased FRAMEDELAYMAX_Register; + -- Configuration register for the Frame Delay Timer + FRAMEDELAYMODE : aliased FRAMEDELAYMODE_Register; + -- Packet pointer for TXD and RXD data storage in Data RAM + PACKETPTR : aliased HAL.UInt32; + -- Size of allocated for TXD and RXD data storage buffer in Data RAM + MAXLEN : aliased MAXLEN_Register; + -- Unspecified + TXD : aliased TXD_Cluster; + -- Unspecified + RXD : aliased RXD_Cluster; + -- Last NFCID1 part (4, 7 or 10 bytes ID) + NFCID1_LAST : aliased NFCID1_LAST_Register; + -- Second last NFCID1 part (7 or 10 bytes ID) + NFCID1_2ND_LAST : aliased NFCID1_2ND_LAST_Register; + -- Third last NFCID1 part (10 bytes ID) + NFCID1_3RD_LAST : aliased NFCID1_3RD_LAST_Register; + -- NFC-A SENS_RES auto-response settings + SENSRES : aliased SENSRES_Register; + -- NFC-A SEL_RES auto-response settings + SELRES : aliased SELRES_Register; + end record + with Volatile; + + for NFCT_Peripheral use record + TASKS_ACTIVATE at 16#0# range 0 .. 31; + TASKS_DISABLE at 16#4# range 0 .. 31; + TASKS_SENSE at 16#8# range 0 .. 31; + TASKS_STARTTX at 16#C# range 0 .. 31; + TASKS_ENABLERXDATA at 16#1C# range 0 .. 31; + TASKS_GOIDLE at 16#24# range 0 .. 31; + TASKS_GOSLEEP at 16#28# range 0 .. 31; + EVENTS_READY at 16#100# range 0 .. 31; + EVENTS_FIELDDETECTED at 16#104# range 0 .. 31; + EVENTS_FIELDLOST at 16#108# range 0 .. 31; + EVENTS_TXFRAMESTART at 16#10C# range 0 .. 31; + EVENTS_TXFRAMEEND at 16#110# range 0 .. 31; + EVENTS_RXFRAMESTART at 16#114# range 0 .. 31; + EVENTS_RXFRAMEEND at 16#118# range 0 .. 31; + EVENTS_ERROR at 16#11C# range 0 .. 31; + EVENTS_RXERROR at 16#128# range 0 .. 31; + EVENTS_ENDRX at 16#12C# range 0 .. 31; + EVENTS_ENDTX at 16#130# range 0 .. 31; + EVENTS_AUTOCOLRESSTARTED at 16#138# range 0 .. 31; + EVENTS_COLLISION at 16#148# range 0 .. 31; + EVENTS_SELECTED at 16#14C# range 0 .. 31; + EVENTS_STARTED at 16#150# range 0 .. 31; + SHORTS at 16#200# range 0 .. 31; + INTEN at 16#300# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + ERRORSTATUS at 16#404# range 0 .. 31; + FRAMESTATUS at 16#40C# range 0 .. 31; + CURRENTLOADCTRL at 16#430# range 0 .. 31; + FIELDPRESENT at 16#43C# range 0 .. 31; + FRAMEDELAYMIN at 16#504# range 0 .. 31; + FRAMEDELAYMAX at 16#508# range 0 .. 31; + FRAMEDELAYMODE at 16#50C# range 0 .. 31; + PACKETPTR at 16#510# range 0 .. 31; + MAXLEN at 16#514# range 0 .. 31; + TXD at 16#518# range 0 .. 63; + RXD at 16#520# range 0 .. 63; + NFCID1_LAST at 16#590# range 0 .. 31; + NFCID1_2ND_LAST at 16#594# range 0 .. 31; + NFCID1_3RD_LAST at 16#598# range 0 .. 31; + SENSRES at 16#5A0# range 0 .. 31; + SELRES at 16#5A4# range 0 .. 31; + end record; + + -- NFC-A compatible radio + NFCT_Periph : aliased NFCT_Peripheral + with Import, Address => NFCT_Base; + +end NRF_SVD.NFCT; diff --git a/arch/ARM/Nordic/svd/nrf52/nrf_svd-nvmc.ads b/arch/ARM/Nordic/svd/nrf52/nrf_svd-nvmc.ads new file mode 100644 index 000000000..4e23a05d1 --- /dev/null +++ b/arch/ARM/Nordic/svd/nrf52/nrf_svd-nvmc.ads @@ -0,0 +1,274 @@ +-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- 2. Redistributions in binary form, except as embedded into a Nordic +-- Semiconductor ASA integrated circuit in a product or a software update for +-- such product, must reproduce the above copyright notice, this list of +-- conditions and the following disclaimer in the documentation and/or other +-- materials provided with the distribution. +-- +-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from this +-- software without specific prior written permission. +-- +-- 4. This software, with or without modification, must only be used with a +-- Nordic Semiconductor ASA integrated circuit. +-- +-- 5. Any software provided in binary form under this license must not be reverse +-- engineered, decompiled, modified and/or disassembled. +-- +-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +-- OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + +-- This spec has been automatically generated from nrf52.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package NRF_SVD.NVMC is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- NVMC is ready or busy + type READY_READY_Field is + (-- NVMC is busy (on-going write or erase operation) + Busy, + -- NVMC is ready + Ready) + with Size => 1; + for READY_READY_Field use + (Busy => 0, + Ready => 1); + + -- Ready flag + type READY_Register is record + -- Read-only. NVMC is ready or busy + READY : READY_READY_Field; + -- unspecified + Reserved_1_31 : HAL.UInt31; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for READY_Register use record + READY at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Program memory access mode. It is strongly recommended to only activate + -- erase and write modes when they are actively used. Enabling write or + -- erase will invalidate the cache and keep it invalidated. + type CONFIG_WEN_Field is + (-- Read only access + Ren, + -- Write Enabled + Wen, + -- Erase enabled + Een) + with Size => 2; + for CONFIG_WEN_Field use + (Ren => 0, + Wen => 1, + Een => 2); + + -- Configuration register + type CONFIG_Register is record + -- Program memory access mode. It is strongly recommended to only + -- activate erase and write modes when they are actively used. Enabling + -- write or erase will invalidate the cache and keep it invalidated. + WEN : CONFIG_WEN_Field := NRF_SVD.NVMC.Ren; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CONFIG_Register use record + WEN at 0 range 0 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + -- Erase all non-volatile memory including UICR registers. Note that code + -- erase has to be enabled by CONFIG.EEN before the UICR can be erased. + type ERASEALL_ERASEALL_Field is + (-- No operation + Nooperation, + -- Start chip erase + Erase) + with Size => 1; + for ERASEALL_ERASEALL_Field use + (Nooperation => 0, + Erase => 1); + + -- Register for erasing all non-volatile user memory + type ERASEALL_Register is record + -- Erase all non-volatile memory including UICR registers. Note that + -- code erase has to be enabled by CONFIG.EEN before the UICR can be + -- erased. + ERASEALL : ERASEALL_ERASEALL_Field := NRF_SVD.NVMC.Nooperation; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ERASEALL_Register use record + ERASEALL at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Register starting erase of all User Information Configuration Registers. + -- Note that code erase has to be enabled by CONFIG.EEN before the UICR can + -- be erased. + type ERASEUICR_ERASEUICR_Field is + (-- No operation + Nooperation, + -- Start erase of UICR + Erase) + with Size => 1; + for ERASEUICR_ERASEUICR_Field use + (Nooperation => 0, + Erase => 1); + + -- Register for erasing User Information Configuration Registers + type ERASEUICR_Register is record + -- Register starting erase of all User Information Configuration + -- Registers. Note that code erase has to be enabled by CONFIG.EEN + -- before the UICR can be erased. + ERASEUICR : ERASEUICR_ERASEUICR_Field := NRF_SVD.NVMC.Nooperation; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ERASEUICR_Register use record + ERASEUICR at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Cache enable + type ICACHECNF_CACHEEN_Field is + (-- Disable cache. Invalidates all cache entries. + Disabled, + -- Enable cache + Enabled) + with Size => 1; + for ICACHECNF_CACHEEN_Field use + (Disabled => 0, + Enabled => 1); + + -- Cache profiling enable + type ICACHECNF_CACHEPROFEN_Field is + (-- Disable cache profiling + Disabled, + -- Enable cache profiling + Enabled) + with Size => 1; + for ICACHECNF_CACHEPROFEN_Field use + (Disabled => 0, + Enabled => 1); + + -- I-Code cache configuration register. + type ICACHECNF_Register is record + -- Cache enable + CACHEEN : ICACHECNF_CACHEEN_Field := NRF_SVD.NVMC.Disabled; + -- unspecified + Reserved_1_7 : HAL.UInt7 := 16#0#; + -- Cache profiling enable + CACHEPROFEN : ICACHECNF_CACHEPROFEN_Field := NRF_SVD.NVMC.Disabled; + -- unspecified + Reserved_9_31 : HAL.UInt23 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ICACHECNF_Register use record + CACHEEN at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + CACHEPROFEN at 0 range 8 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + type NVMC_Disc is + (Age, + Cr1); + + -- Non Volatile Memory Controller + type NVMC_Peripheral + (Discriminent : NVMC_Disc := Age) + is record + -- Ready flag + READY : aliased READY_Register; + -- Configuration register + CONFIG : aliased CONFIG_Register; + -- Register for erasing all non-volatile user memory + ERASEALL : aliased ERASEALL_Register; + -- Deprecated register - Register for erasing a page in Code area. + -- Equivalent to ERASEPAGE. + ERASEPCR0 : aliased HAL.UInt32; + -- Register for erasing User Information Configuration Registers + ERASEUICR : aliased ERASEUICR_Register; + -- I-Code cache configuration register. + ICACHECNF : aliased ICACHECNF_Register; + -- I-Code cache hit counter. + IHIT : aliased HAL.UInt32; + -- I-Code cache miss counter. + IMISS : aliased HAL.UInt32; + case Discriminent is + when Age => + -- Register for erasing a page in Code area + ERASEPAGE : aliased HAL.UInt32; + when Cr1 => + -- Deprecated register - Register for erasing a page in Code area. + -- Equivalent to ERASEPAGE. + ERASEPCR1 : aliased HAL.UInt32; + end case; + end record + with Unchecked_Union, Volatile; + + for NVMC_Peripheral use record + READY at 16#400# range 0 .. 31; + CONFIG at 16#504# range 0 .. 31; + ERASEALL at 16#50C# range 0 .. 31; + ERASEPCR0 at 16#510# range 0 .. 31; + ERASEUICR at 16#514# range 0 .. 31; + ICACHECNF at 16#540# range 0 .. 31; + IHIT at 16#548# range 0 .. 31; + IMISS at 16#54C# range 0 .. 31; + ERASEPAGE at 16#508# range 0 .. 31; + ERASEPCR1 at 16#508# range 0 .. 31; + end record; + + -- Non Volatile Memory Controller + NVMC_Periph : aliased NVMC_Peripheral + with Import, Address => NVMC_Base; + +end NRF_SVD.NVMC; diff --git a/arch/ARM/Nordic/svd/nrf52/nrf_svd-pdm.ads b/arch/ARM/Nordic/svd/nrf52/nrf_svd-pdm.ads new file mode 100644 index 000000000..57883fba0 --- /dev/null +++ b/arch/ARM/Nordic/svd/nrf52/nrf_svd-pdm.ads @@ -0,0 +1,600 @@ +-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- 2. Redistributions in binary form, except as embedded into a Nordic +-- Semiconductor ASA integrated circuit in a product or a software update for +-- such product, must reproduce the above copyright notice, this list of +-- conditions and the following disclaimer in the documentation and/or other +-- materials provided with the distribution. +-- +-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from this +-- software without specific prior written permission. +-- +-- 4. This software, with or without modification, must only be used with a +-- Nordic Semiconductor ASA integrated circuit. +-- +-- 5. Any software provided in binary form under this license must not be reverse +-- engineered, decompiled, modified and/or disassembled. +-- +-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +-- OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + +-- This spec has been automatically generated from nrf52.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package NRF_SVD.PDM is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Enable or disable interrupt for STARTED event + type INTEN_STARTED_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_STARTED_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for STOPPED event + type INTEN_STOPPED_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_STOPPED_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for END event + type INTEN_END_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_END_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt + type INTEN_Register is record + -- Enable or disable interrupt for STARTED event + STARTED : INTEN_STARTED_Field := NRF_SVD.PDM.Disabled; + -- Enable or disable interrupt for STOPPED event + STOPPED : INTEN_STOPPED_Field := NRF_SVD.PDM.Disabled; + -- Enable or disable interrupt for END event + END_k : INTEN_END_Field := NRF_SVD.PDM.Disabled; + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTEN_Register use record + STARTED at 0 range 0 .. 0; + STOPPED at 0 range 1 .. 1; + END_k at 0 range 2 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + -- Write '1' to Enable interrupt for STARTED event + type INTENSET_STARTED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_STARTED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for STARTED event + type INTENSET_STARTED_Field_1 is + (-- Reset value for the field + Intenset_Started_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_STARTED_Field_1 use + (Intenset_Started_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for STOPPED event + type INTENSET_STOPPED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_STOPPED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for STOPPED event + type INTENSET_STOPPED_Field_1 is + (-- Reset value for the field + Intenset_Stopped_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_STOPPED_Field_1 use + (Intenset_Stopped_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for END event + type INTENSET_END_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_END_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for END event + type INTENSET_END_Field_1 is + (-- Reset value for the field + Intenset_End_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_END_Field_1 use + (Intenset_End_Field_Reset => 0, + Set => 1); + + -- Enable interrupt + type INTENSET_Register is record + -- Write '1' to Enable interrupt for STARTED event + STARTED : INTENSET_STARTED_Field_1 := + Intenset_Started_Field_Reset; + -- Write '1' to Enable interrupt for STOPPED event + STOPPED : INTENSET_STOPPED_Field_1 := + Intenset_Stopped_Field_Reset; + -- Write '1' to Enable interrupt for END event + END_k : INTENSET_END_Field_1 := Intenset_End_Field_Reset; + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENSET_Register use record + STARTED at 0 range 0 .. 0; + STOPPED at 0 range 1 .. 1; + END_k at 0 range 2 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + -- Write '1' to Disable interrupt for STARTED event + type INTENCLR_STARTED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_STARTED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for STARTED event + type INTENCLR_STARTED_Field_1 is + (-- Reset value for the field + Intenclr_Started_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_STARTED_Field_1 use + (Intenclr_Started_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for STOPPED event + type INTENCLR_STOPPED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_STOPPED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for STOPPED event + type INTENCLR_STOPPED_Field_1 is + (-- Reset value for the field + Intenclr_Stopped_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_STOPPED_Field_1 use + (Intenclr_Stopped_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for END event + type INTENCLR_END_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_END_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for END event + type INTENCLR_END_Field_1 is + (-- Reset value for the field + Intenclr_End_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_END_Field_1 use + (Intenclr_End_Field_Reset => 0, + Clear => 1); + + -- Disable interrupt + type INTENCLR_Register is record + -- Write '1' to Disable interrupt for STARTED event + STARTED : INTENCLR_STARTED_Field_1 := + Intenclr_Started_Field_Reset; + -- Write '1' to Disable interrupt for STOPPED event + STOPPED : INTENCLR_STOPPED_Field_1 := + Intenclr_Stopped_Field_Reset; + -- Write '1' to Disable interrupt for END event + END_k : INTENCLR_END_Field_1 := Intenclr_End_Field_Reset; + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENCLR_Register use record + STARTED at 0 range 0 .. 0; + STOPPED at 0 range 1 .. 1; + END_k at 0 range 2 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + -- Enable or disable PDM module + type ENABLE_ENABLE_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for ENABLE_ENABLE_Field use + (Disabled => 0, + Enabled => 1); + + -- PDM module enable register + type ENABLE_Register is record + -- Enable or disable PDM module + ENABLE : ENABLE_ENABLE_Field := NRF_SVD.PDM.Disabled; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ENABLE_Register use record + ENABLE at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Mono or stereo operation + type MODE_OPERATION_Field is + (-- Sample and store one pair (Left + Right) of 16bit samples per RAM word +-- R=[31:16]; L=[15:0] + Stereo, + -- Sample and store two successive Left samples (16 bit each) per RAM word +-- L1=[31:16]; L0=[15:0] + Mono) + with Size => 1; + for MODE_OPERATION_Field use + (Stereo => 0, + Mono => 1); + + -- Defines on which PDM_CLK edge Left (or mono) is sampled + type MODE_EDGE_Field is + (-- Left (or mono) is sampled on falling edge of PDM_CLK + Leftfalling, + -- Left (or mono) is sampled on rising edge of PDM_CLK + Leftrising) + with Size => 1; + for MODE_EDGE_Field use + (Leftfalling => 0, + Leftrising => 1); + + -- Defines the routing of the connected PDM microphones' signals + type MODE_Register is record + -- Mono or stereo operation + OPERATION : MODE_OPERATION_Field := NRF_SVD.PDM.Stereo; + -- Defines on which PDM_CLK edge Left (or mono) is sampled + EDGE : MODE_EDGE_Field := NRF_SVD.PDM.Leftfalling; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MODE_Register use record + OPERATION at 0 range 0 .. 0; + EDGE at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + -- Left output gain adjustment, in 0.5 dB steps, around the default module + -- gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB + -- gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 + -- +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain + -- adjust + type GAINL_GAINL_Field is + (-- -20dB gain adjustment (minimum) + Mingain, + -- 0dB gain adjustment ('2500 RMS' requirement) + Defaultgain, + -- +20dB gain adjustment (maximum) + Maxgain) + with Size => 7; + for GAINL_GAINL_Field use + (Mingain => 0, + Defaultgain => 40, + Maxgain => 80); + + -- Left output gain adjustment + type GAINL_Register is record + -- Left output gain adjustment, in 0.5 dB steps, around the default + -- module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 + -- -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain + -- adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 + -- +20 dB gain adjust + GAINL : GAINL_GAINL_Field := NRF_SVD.PDM.Defaultgain; + -- unspecified + Reserved_7_31 : HAL.UInt25 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GAINL_Register use record + GAINL at 0 range 0 .. 6; + Reserved_7_31 at 0 range 7 .. 31; + end record; + + -- Right output gain adjustment, in 0.5 dB steps, around the default module + -- gain (see electrical parameters) + type GAINR_GAINR_Field is + (-- -20dB gain adjustment (minimum) + Mingain, + -- 0dB gain adjustment ('2500 RMS' requirement) + Defaultgain, + -- +20dB gain adjustment (maximum) + Maxgain) + with Size => 8; + for GAINR_GAINR_Field use + (Mingain => 0, + Defaultgain => 40, + Maxgain => 80); + + -- Right output gain adjustment + type GAINR_Register is record + -- Right output gain adjustment, in 0.5 dB steps, around the default + -- module gain (see electrical parameters) + GAINR : GAINR_GAINR_Field := NRF_SVD.PDM.Defaultgain; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GAINR_Register use record + GAINR at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + ------------------------------ + -- PSEL cluster's Registers -- + ------------------------------ + + subtype CLK_PSEL_PIN_Field is HAL.UInt5; + + -- Connection + type CLK_CONNECT_Field is + (-- Connect + Connected, + -- Disconnect + Disconnected) + with Size => 1; + for CLK_CONNECT_Field use + (Connected => 0, + Disconnected => 1); + + -- Pin number configuration for PDM CLK signal + type CLK_PSEL_Register is record + -- Pin number + PIN : CLK_PSEL_PIN_Field := 16#1F#; + -- unspecified + Reserved_5_30 : HAL.UInt26 := 16#3FFFFFF#; + -- Connection + CONNECT : CLK_CONNECT_Field := NRF_SVD.PDM.Disconnected; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CLK_PSEL_Register use record + PIN at 0 range 0 .. 4; + Reserved_5_30 at 0 range 5 .. 30; + CONNECT at 0 range 31 .. 31; + end record; + + subtype DIN_PSEL_PIN_Field is HAL.UInt5; + + -- Connection + type DIN_CONNECT_Field is + (-- Connect + Connected, + -- Disconnect + Disconnected) + with Size => 1; + for DIN_CONNECT_Field use + (Connected => 0, + Disconnected => 1); + + -- Pin number configuration for PDM DIN signal + type DIN_PSEL_Register is record + -- Pin number + PIN : DIN_PSEL_PIN_Field := 16#1F#; + -- unspecified + Reserved_5_30 : HAL.UInt26 := 16#3FFFFFF#; + -- Connection + CONNECT : DIN_CONNECT_Field := NRF_SVD.PDM.Disconnected; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DIN_PSEL_Register use record + PIN at 0 range 0 .. 4; + Reserved_5_30 at 0 range 5 .. 30; + CONNECT at 0 range 31 .. 31; + end record; + + -- Unspecified + type PSEL_Cluster is record + -- Pin number configuration for PDM CLK signal + CLK : aliased CLK_PSEL_Register; + -- Pin number configuration for PDM DIN signal + DIN : aliased DIN_PSEL_Register; + end record + with Size => 64; + + for PSEL_Cluster use record + CLK at 16#0# range 0 .. 31; + DIN at 16#4# range 0 .. 31; + end record; + + -------------------------------- + -- SAMPLE cluster's Registers -- + -------------------------------- + + subtype MAXCNT_SAMPLE_BUFFSIZE_Field is HAL.UInt15; + + -- Number of samples to allocate memory for in EasyDMA mode + type MAXCNT_SAMPLE_Register is record + -- Length of DMA RAM allocation in number of samples + BUFFSIZE : MAXCNT_SAMPLE_BUFFSIZE_Field := 16#0#; + -- unspecified + Reserved_15_31 : HAL.UInt17 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MAXCNT_SAMPLE_Register use record + BUFFSIZE at 0 range 0 .. 14; + Reserved_15_31 at 0 range 15 .. 31; + end record; + + -- Unspecified + type SAMPLE_Cluster is record + -- RAM address pointer to write samples to with EasyDMA + PTR : aliased HAL.UInt32; + -- Number of samples to allocate memory for in EasyDMA mode + MAXCNT : aliased MAXCNT_SAMPLE_Register; + end record + with Size => 64; + + for SAMPLE_Cluster use record + PTR at 16#0# range 0 .. 31; + MAXCNT at 16#4# range 0 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Pulse Density Modulation (Digital Microphone) Interface + type PDM_Peripheral is record + -- Starts continuous PDM transfer + TASKS_START : aliased HAL.UInt32; + -- Stops PDM transfer + TASKS_STOP : aliased HAL.UInt32; + -- PDM transfer has started + EVENTS_STARTED : aliased HAL.UInt32; + -- PDM transfer has finished + EVENTS_STOPPED : aliased HAL.UInt32; + -- The PDM has written the last sample specified by SAMPLE.MAXCNT (or + -- the last sample after a STOP task has been received) to Data RAM + EVENTS_END : aliased HAL.UInt32; + -- Enable or disable interrupt + INTEN : aliased INTEN_Register; + -- Enable interrupt + INTENSET : aliased INTENSET_Register; + -- Disable interrupt + INTENCLR : aliased INTENCLR_Register; + -- PDM module enable register + ENABLE : aliased ENABLE_Register; + -- PDM clock generator control + PDMCLKCTRL : aliased HAL.UInt32; + -- Defines the routing of the connected PDM microphones' signals + MODE : aliased MODE_Register; + -- Left output gain adjustment + GAINL : aliased GAINL_Register; + -- Right output gain adjustment + GAINR : aliased GAINR_Register; + -- Unspecified + PSEL : aliased PSEL_Cluster; + -- Unspecified + SAMPLE : aliased SAMPLE_Cluster; + end record + with Volatile; + + for PDM_Peripheral use record + TASKS_START at 16#0# range 0 .. 31; + TASKS_STOP at 16#4# range 0 .. 31; + EVENTS_STARTED at 16#100# range 0 .. 31; + EVENTS_STOPPED at 16#104# range 0 .. 31; + EVENTS_END at 16#108# range 0 .. 31; + INTEN at 16#300# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + ENABLE at 16#500# range 0 .. 31; + PDMCLKCTRL at 16#504# range 0 .. 31; + MODE at 16#508# range 0 .. 31; + GAINL at 16#518# range 0 .. 31; + GAINR at 16#51C# range 0 .. 31; + PSEL at 16#540# range 0 .. 63; + SAMPLE at 16#560# range 0 .. 63; + end record; + + -- Pulse Density Modulation (Digital Microphone) Interface + PDM_Periph : aliased PDM_Peripheral + with Import, Address => PDM_Base; + +end NRF_SVD.PDM; diff --git a/arch/ARM/Nordic/svd/nrf52/nrf_svd-power.ads b/arch/ARM/Nordic/svd/nrf52/nrf_svd-power.ads new file mode 100644 index 000000000..5be1e8878 --- /dev/null +++ b/arch/ARM/Nordic/svd/nrf52/nrf_svd-power.ads @@ -0,0 +1,1016 @@ +-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- 2. Redistributions in binary form, except as embedded into a Nordic +-- Semiconductor ASA integrated circuit in a product or a software update for +-- such product, must reproduce the above copyright notice, this list of +-- conditions and the following disclaimer in the documentation and/or other +-- materials provided with the distribution. +-- +-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from this +-- software without specific prior written permission. +-- +-- 4. This software, with or without modification, must only be used with a +-- Nordic Semiconductor ASA integrated circuit. +-- +-- 5. Any software provided in binary form under this license must not be reverse +-- engineered, decompiled, modified and/or disassembled. +-- +-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +-- OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + +-- This spec has been automatically generated from nrf52.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package NRF_SVD.POWER is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Write '1' to Enable interrupt for POFWARN event + type INTENSET_POFWARN_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_POFWARN_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for POFWARN event + type INTENSET_POFWARN_Field_1 is + (-- Reset value for the field + Intenset_Pofwarn_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_POFWARN_Field_1 use + (Intenset_Pofwarn_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for SLEEPENTER event + type INTENSET_SLEEPENTER_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_SLEEPENTER_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for SLEEPENTER event + type INTENSET_SLEEPENTER_Field_1 is + (-- Reset value for the field + Intenset_Sleepenter_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_SLEEPENTER_Field_1 use + (Intenset_Sleepenter_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for SLEEPEXIT event + type INTENSET_SLEEPEXIT_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_SLEEPEXIT_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for SLEEPEXIT event + type INTENSET_SLEEPEXIT_Field_1 is + (-- Reset value for the field + Intenset_Sleepexit_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_SLEEPEXIT_Field_1 use + (Intenset_Sleepexit_Field_Reset => 0, + Set => 1); + + -- Enable interrupt + type INTENSET_Register is record + -- unspecified + Reserved_0_1 : HAL.UInt2 := 16#0#; + -- Write '1' to Enable interrupt for POFWARN event + POFWARN : INTENSET_POFWARN_Field_1 := + Intenset_Pofwarn_Field_Reset; + -- unspecified + Reserved_3_4 : HAL.UInt2 := 16#0#; + -- Write '1' to Enable interrupt for SLEEPENTER event + SLEEPENTER : INTENSET_SLEEPENTER_Field_1 := + Intenset_Sleepenter_Field_Reset; + -- Write '1' to Enable interrupt for SLEEPEXIT event + SLEEPEXIT : INTENSET_SLEEPEXIT_Field_1 := + Intenset_Sleepexit_Field_Reset; + -- unspecified + Reserved_7_31 : HAL.UInt25 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENSET_Register use record + Reserved_0_1 at 0 range 0 .. 1; + POFWARN at 0 range 2 .. 2; + Reserved_3_4 at 0 range 3 .. 4; + SLEEPENTER at 0 range 5 .. 5; + SLEEPEXIT at 0 range 6 .. 6; + Reserved_7_31 at 0 range 7 .. 31; + end record; + + -- Write '1' to Disable interrupt for POFWARN event + type INTENCLR_POFWARN_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_POFWARN_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for POFWARN event + type INTENCLR_POFWARN_Field_1 is + (-- Reset value for the field + Intenclr_Pofwarn_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_POFWARN_Field_1 use + (Intenclr_Pofwarn_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for SLEEPENTER event + type INTENCLR_SLEEPENTER_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_SLEEPENTER_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for SLEEPENTER event + type INTENCLR_SLEEPENTER_Field_1 is + (-- Reset value for the field + Intenclr_Sleepenter_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_SLEEPENTER_Field_1 use + (Intenclr_Sleepenter_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for SLEEPEXIT event + type INTENCLR_SLEEPEXIT_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_SLEEPEXIT_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for SLEEPEXIT event + type INTENCLR_SLEEPEXIT_Field_1 is + (-- Reset value for the field + Intenclr_Sleepexit_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_SLEEPEXIT_Field_1 use + (Intenclr_Sleepexit_Field_Reset => 0, + Clear => 1); + + -- Disable interrupt + type INTENCLR_Register is record + -- unspecified + Reserved_0_1 : HAL.UInt2 := 16#0#; + -- Write '1' to Disable interrupt for POFWARN event + POFWARN : INTENCLR_POFWARN_Field_1 := + Intenclr_Pofwarn_Field_Reset; + -- unspecified + Reserved_3_4 : HAL.UInt2 := 16#0#; + -- Write '1' to Disable interrupt for SLEEPENTER event + SLEEPENTER : INTENCLR_SLEEPENTER_Field_1 := + Intenclr_Sleepenter_Field_Reset; + -- Write '1' to Disable interrupt for SLEEPEXIT event + SLEEPEXIT : INTENCLR_SLEEPEXIT_Field_1 := + Intenclr_Sleepexit_Field_Reset; + -- unspecified + Reserved_7_31 : HAL.UInt25 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENCLR_Register use record + Reserved_0_1 at 0 range 0 .. 1; + POFWARN at 0 range 2 .. 2; + Reserved_3_4 at 0 range 3 .. 4; + SLEEPENTER at 0 range 5 .. 5; + SLEEPEXIT at 0 range 6 .. 6; + Reserved_7_31 at 0 range 7 .. 31; + end record; + + -- Reset from pin-reset detected + type RESETREAS_RESETPIN_Field is + (-- Not detected + Notdetected, + -- Detected + Detected) + with Size => 1; + for RESETREAS_RESETPIN_Field use + (Notdetected => 0, + Detected => 1); + + -- Reset from watchdog detected + type RESETREAS_DOG_Field is + (-- Not detected + Notdetected, + -- Detected + Detected) + with Size => 1; + for RESETREAS_DOG_Field use + (Notdetected => 0, + Detected => 1); + + -- Reset from soft reset detected + type RESETREAS_SREQ_Field is + (-- Not detected + Notdetected, + -- Detected + Detected) + with Size => 1; + for RESETREAS_SREQ_Field use + (Notdetected => 0, + Detected => 1); + + -- Reset from CPU lock-up detected + type RESETREAS_LOCKUP_Field is + (-- Not detected + Notdetected, + -- Detected + Detected) + with Size => 1; + for RESETREAS_LOCKUP_Field use + (Notdetected => 0, + Detected => 1); + + -- Reset due to wake up from System OFF mode when wakeup is triggered from + -- DETECT signal from GPIO + type RESETREAS_OFF_Field is + (-- Not detected + Notdetected, + -- Detected + Detected) + with Size => 1; + for RESETREAS_OFF_Field use + (Notdetected => 0, + Detected => 1); + + -- Reset due to wake up from System OFF mode when wakeup is triggered from + -- ANADETECT signal from LPCOMP + type RESETREAS_LPCOMP_Field is + (-- Not detected + Notdetected, + -- Detected + Detected) + with Size => 1; + for RESETREAS_LPCOMP_Field use + (Notdetected => 0, + Detected => 1); + + -- Reset due to wake up from System OFF mode when wakeup is triggered from + -- entering into debug interface mode + type RESETREAS_DIF_Field is + (-- Not detected + Notdetected, + -- Detected + Detected) + with Size => 1; + for RESETREAS_DIF_Field use + (Notdetected => 0, + Detected => 1); + + -- Reset due to wake up from System OFF mode by NFC field detect + type RESETREAS_NFC_Field is + (-- Not detected + Notdetected, + -- Detected + Detected) + with Size => 1; + for RESETREAS_NFC_Field use + (Notdetected => 0, + Detected => 1); + + -- Reset reason + type RESETREAS_Register is record + -- Reset from pin-reset detected + RESETPIN : RESETREAS_RESETPIN_Field := NRF_SVD.POWER.Notdetected; + -- Reset from watchdog detected + DOG : RESETREAS_DOG_Field := NRF_SVD.POWER.Notdetected; + -- Reset from soft reset detected + SREQ : RESETREAS_SREQ_Field := NRF_SVD.POWER.Notdetected; + -- Reset from CPU lock-up detected + LOCKUP : RESETREAS_LOCKUP_Field := NRF_SVD.POWER.Notdetected; + -- unspecified + Reserved_4_15 : HAL.UInt12 := 16#0#; + -- Reset due to wake up from System OFF mode when wakeup is triggered + -- from DETECT signal from GPIO + OFF : RESETREAS_OFF_Field := NRF_SVD.POWER.Notdetected; + -- Reset due to wake up from System OFF mode when wakeup is triggered + -- from ANADETECT signal from LPCOMP + LPCOMP : RESETREAS_LPCOMP_Field := NRF_SVD.POWER.Notdetected; + -- Reset due to wake up from System OFF mode when wakeup is triggered + -- from entering into debug interface mode + DIF : RESETREAS_DIF_Field := NRF_SVD.POWER.Notdetected; + -- Reset due to wake up from System OFF mode by NFC field detect + NFC : RESETREAS_NFC_Field := NRF_SVD.POWER.Notdetected; + -- unspecified + Reserved_20_31 : HAL.UInt12 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RESETREAS_Register use record + RESETPIN at 0 range 0 .. 0; + DOG at 0 range 1 .. 1; + SREQ at 0 range 2 .. 2; + LOCKUP at 0 range 3 .. 3; + Reserved_4_15 at 0 range 4 .. 15; + OFF at 0 range 16 .. 16; + LPCOMP at 0 range 17 .. 17; + DIF at 0 range 18 .. 18; + NFC at 0 range 19 .. 19; + Reserved_20_31 at 0 range 20 .. 31; + end record; + + -- RAM block 0 is on or off/powering up + type RAMSTATUS_RAMBLOCK0_Field is + (-- Off + Off, + -- On + On) + with Size => 1; + for RAMSTATUS_RAMBLOCK0_Field use + (Off => 0, + On => 1); + + -- RAMSTATUS_RAMBLOCK array + type RAMSTATUS_RAMBLOCK_Field_Array is array (0 .. 3) + of RAMSTATUS_RAMBLOCK0_Field + with Component_Size => 1, Size => 4; + + -- Type definition for RAMSTATUS_RAMBLOCK + type RAMSTATUS_RAMBLOCK_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- RAMBLOCK as a value + Val : HAL.UInt4; + when True => + -- RAMBLOCK as an array + Arr : RAMSTATUS_RAMBLOCK_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for RAMSTATUS_RAMBLOCK_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- Deprecated register - RAM status register + type RAMSTATUS_Register is record + -- Read-only. RAM block 0 is on or off/powering up + RAMBLOCK : RAMSTATUS_RAMBLOCK_Field; + -- unspecified + Reserved_4_31 : HAL.UInt28; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RAMSTATUS_Register use record + RAMBLOCK at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- Enable System OFF mode + type SYSTEMOFF_SYSTEMOFF_Field is + (-- Reset value for the field + Systemoff_Systemoff_Field_Reset, + -- Enable System OFF mode + Enter) + with Size => 1; + for SYSTEMOFF_SYSTEMOFF_Field use + (Systemoff_Systemoff_Field_Reset => 0, + Enter => 1); + + -- System OFF register + type SYSTEMOFF_Register is record + -- Write-only. Enable System OFF mode + SYSTEMOFF : SYSTEMOFF_SYSTEMOFF_Field := + Systemoff_Systemoff_Field_Reset; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SYSTEMOFF_Register use record + SYSTEMOFF at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Enable or disable power failure comparator + type POFCON_POF_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for POFCON_POF_Field use + (Disabled => 0, + Enabled => 1); + + -- Power failure comparator threshold setting + type POFCON_THRESHOLD_Field is + (-- Reset value for the field + Pofcon_Threshold_Field_Reset, + -- Set threshold to 1.7 V + V17, + -- Set threshold to 1.8 V + V18, + -- Set threshold to 1.9 V + V19, + -- Set threshold to 2.0 V + V20, + -- Set threshold to 2.1 V + V21, + -- Set threshold to 2.2 V + V22, + -- Set threshold to 2.3 V + V23, + -- Set threshold to 2.4 V + V24, + -- Set threshold to 2.5 V + V25, + -- Set threshold to 2.6 V + V26, + -- Set threshold to 2.7 V + V27, + -- Set threshold to 2.8 V + V28) + with Size => 4; + for POFCON_THRESHOLD_Field use + (Pofcon_Threshold_Field_Reset => 0, + V17 => 4, + V18 => 5, + V19 => 6, + V20 => 7, + V21 => 8, + V22 => 9, + V23 => 10, + V24 => 11, + V25 => 12, + V26 => 13, + V27 => 14, + V28 => 15); + + -- Power failure comparator configuration + type POFCON_Register is record + -- Enable or disable power failure comparator + POF : POFCON_POF_Field := NRF_SVD.POWER.Disabled; + -- Power failure comparator threshold setting + THRESHOLD : POFCON_THRESHOLD_Field := Pofcon_Threshold_Field_Reset; + -- unspecified + Reserved_5_31 : HAL.UInt27 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for POFCON_Register use record + POF at 0 range 0 .. 0; + THRESHOLD at 0 range 1 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + subtype GPREGRET_GPREGRET_Field is HAL.UInt8; + + -- General purpose retention register + type GPREGRET_Register is record + -- General purpose retention register + GPREGRET : GPREGRET_GPREGRET_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPREGRET_Register use record + GPREGRET at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- Keep RAM block 0 on or off in system ON Mode + type RAMON_ONRAM0_Field is + (-- Off + Ram0Off, + -- On + Ram0On) + with Size => 1; + for RAMON_ONRAM0_Field use + (Ram0Off => 0, + Ram0On => 1); + + -- Keep RAM block 1 on or off in system ON Mode + type RAMON_ONRAM1_Field is + (-- Off + Ram1Off, + -- On + Ram1On) + with Size => 1; + for RAMON_ONRAM1_Field use + (Ram1Off => 0, + Ram1On => 1); + + -- Keep retention on RAM block 0 when RAM block is switched off + type RAMON_OFFRAM0_Field is + (-- Off + Ram0Off, + -- On + Ram0On) + with Size => 1; + for RAMON_OFFRAM0_Field use + (Ram0Off => 0, + Ram0On => 1); + + -- Keep retention on RAM block 1 when RAM block is switched off + type RAMON_OFFRAM1_Field is + (-- Off + Ram1Off, + -- On + Ram1On) + with Size => 1; + for RAMON_OFFRAM1_Field use + (Ram1Off => 0, + Ram1On => 1); + + -- Deprecated register - RAM on/off register (this register is retained) + type RAMON_Register is record + -- Keep RAM block 0 on or off in system ON Mode + ONRAM0 : RAMON_ONRAM0_Field := NRF_SVD.POWER.Ram0On; + -- Keep RAM block 1 on or off in system ON Mode + ONRAM1 : RAMON_ONRAM1_Field := NRF_SVD.POWER.Ram1On; + -- unspecified + Reserved_2_15 : HAL.UInt14 := 16#0#; + -- Keep retention on RAM block 0 when RAM block is switched off + OFFRAM0 : RAMON_OFFRAM0_Field := NRF_SVD.POWER.Ram0Off; + -- Keep retention on RAM block 1 when RAM block is switched off + OFFRAM1 : RAMON_OFFRAM1_Field := NRF_SVD.POWER.Ram1Off; + -- unspecified + Reserved_18_31 : HAL.UInt14 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RAMON_Register use record + ONRAM0 at 0 range 0 .. 0; + ONRAM1 at 0 range 1 .. 1; + Reserved_2_15 at 0 range 2 .. 15; + OFFRAM0 at 0 range 16 .. 16; + OFFRAM1 at 0 range 17 .. 17; + Reserved_18_31 at 0 range 18 .. 31; + end record; + + -- Keep RAM block 2 on or off in system ON Mode + type RAMONB_ONRAM2_Field is + (-- Off + Ram2Off, + -- On + Ram2On) + with Size => 1; + for RAMONB_ONRAM2_Field use + (Ram2Off => 0, + Ram2On => 1); + + -- Keep RAM block 3 on or off in system ON Mode + type RAMONB_ONRAM3_Field is + (-- Off + Ram3Off, + -- On + Ram3On) + with Size => 1; + for RAMONB_ONRAM3_Field use + (Ram3Off => 0, + Ram3On => 1); + + -- Keep retention on RAM block 2 when RAM block is switched off + type RAMONB_OFFRAM2_Field is + (-- Off + Ram2Off, + -- On + Ram2On) + with Size => 1; + for RAMONB_OFFRAM2_Field use + (Ram2Off => 0, + Ram2On => 1); + + -- Keep retention on RAM block 3 when RAM block is switched off + type RAMONB_OFFRAM3_Field is + (-- Off + Ram3Off, + -- On + Ram3On) + with Size => 1; + for RAMONB_OFFRAM3_Field use + (Ram3Off => 0, + Ram3On => 1); + + -- Deprecated register - RAM on/off register (this register is retained) + type RAMONB_Register is record + -- Keep RAM block 2 on or off in system ON Mode + ONRAM2 : RAMONB_ONRAM2_Field := NRF_SVD.POWER.Ram2On; + -- Keep RAM block 3 on or off in system ON Mode + ONRAM3 : RAMONB_ONRAM3_Field := NRF_SVD.POWER.Ram3On; + -- unspecified + Reserved_2_15 : HAL.UInt14 := 16#0#; + -- Keep retention on RAM block 2 when RAM block is switched off + OFFRAM2 : RAMONB_OFFRAM2_Field := NRF_SVD.POWER.Ram2Off; + -- Keep retention on RAM block 3 when RAM block is switched off + OFFRAM3 : RAMONB_OFFRAM3_Field := NRF_SVD.POWER.Ram3Off; + -- unspecified + Reserved_18_31 : HAL.UInt14 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RAMONB_Register use record + ONRAM2 at 0 range 0 .. 0; + ONRAM3 at 0 range 1 .. 1; + Reserved_2_15 at 0 range 2 .. 15; + OFFRAM2 at 0 range 16 .. 16; + OFFRAM3 at 0 range 17 .. 17; + Reserved_18_31 at 0 range 18 .. 31; + end record; + + -- Enable or disable DC/DC converter + type DCDCEN_DCDCEN_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for DCDCEN_DCDCEN_Field use + (Disabled => 0, + Enabled => 1); + + -- DC/DC enable register + type DCDCEN_Register is record + -- Enable or disable DC/DC converter + DCDCEN : DCDCEN_DCDCEN_Field := NRF_SVD.POWER.Disabled; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DCDCEN_Register use record + DCDCEN at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + ----------------------------- + -- RAM cluster's Registers -- + ----------------------------- + + -- Keep RAM section S0 ON or OFF in System ON mode. + type POWER_S0POWER_Field is + (-- Off + Off, + -- On + On) + with Size => 1; + for POWER_S0POWER_Field use + (Off => 0, + On => 1); + + -- Keep RAM section S1 ON or OFF in System ON mode. + type POWER_S1POWER_Field is + (-- Off + Off, + -- On + On) + with Size => 1; + for POWER_S1POWER_Field use + (Off => 0, + On => 1); + + -- Keep retention on RAM section S0 when RAM section is in OFF + type POWER_S0RETENTION_Field is + (-- Off + Off, + -- On + On) + with Size => 1; + for POWER_S0RETENTION_Field use + (Off => 0, + On => 1); + + -- Keep retention on RAM section S1 when RAM section is in OFF + type POWER_S1RETENTION_Field is + (-- Off + Off, + -- On + On) + with Size => 1; + for POWER_S1RETENTION_Field use + (Off => 0, + On => 1); + + -- Description cluster[0]: RAM0 power control register + type POWER_RAM_Register is record + -- Keep RAM section S0 ON or OFF in System ON mode. + S0POWER : POWER_S0POWER_Field := NRF_SVD.POWER.On; + -- Keep RAM section S1 ON or OFF in System ON mode. + S1POWER : POWER_S1POWER_Field := NRF_SVD.POWER.On; + -- unspecified + Reserved_2_15 : HAL.UInt14 := 16#3FFF#; + -- Keep retention on RAM section S0 when RAM section is in OFF + S0RETENTION : POWER_S0RETENTION_Field := NRF_SVD.POWER.Off; + -- Keep retention on RAM section S1 when RAM section is in OFF + S1RETENTION : POWER_S1RETENTION_Field := NRF_SVD.POWER.Off; + -- unspecified + Reserved_18_31 : HAL.UInt14 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for POWER_RAM_Register use record + S0POWER at 0 range 0 .. 0; + S1POWER at 0 range 1 .. 1; + Reserved_2_15 at 0 range 2 .. 15; + S0RETENTION at 0 range 16 .. 16; + S1RETENTION at 0 range 17 .. 17; + Reserved_18_31 at 0 range 18 .. 31; + end record; + + -- Keep RAM section S0 of RAM0 on or off in System ON mode + type POWERSET_S0POWER_Field is + (-- On + On) + with Size => 1; + for POWERSET_S0POWER_Field use + (On => 1); + + -- Keep RAM section S1 of RAM0 on or off in System ON mode + type POWERSET_S1POWER_Field is + (-- On + On) + with Size => 1; + for POWERSET_S1POWER_Field use + (On => 1); + + -- Keep retention on RAM section S0 when RAM section is switched off + type POWERSET_S0RETENTION_Field is + (-- Reset value for the field + Powerset_S0Retention_Field_Reset, + -- On + On) + with Size => 1; + for POWERSET_S0RETENTION_Field use + (Powerset_S0Retention_Field_Reset => 0, + On => 1); + + -- Keep retention on RAM section S1 when RAM section is switched off + type POWERSET_S1RETENTION_Field is + (-- Reset value for the field + Powerset_S1Retention_Field_Reset, + -- On + On) + with Size => 1; + for POWERSET_S1RETENTION_Field use + (Powerset_S1Retention_Field_Reset => 0, + On => 1); + + -- Description cluster[0]: RAM0 power control set register + type POWERSET_RAM_Register is record + -- Write-only. Keep RAM section S0 of RAM0 on or off in System ON mode + S0POWER : POWERSET_S0POWER_Field := NRF_SVD.POWER.On; + -- Write-only. Keep RAM section S1 of RAM0 on or off in System ON mode + S1POWER : POWERSET_S1POWER_Field := NRF_SVD.POWER.On; + -- unspecified + Reserved_2_15 : HAL.UInt14 := 16#3FFF#; + -- Write-only. Keep retention on RAM section S0 when RAM section is + -- switched off + S0RETENTION : POWERSET_S0RETENTION_Field := + Powerset_S0Retention_Field_Reset; + -- Write-only. Keep retention on RAM section S1 when RAM section is + -- switched off + S1RETENTION : POWERSET_S1RETENTION_Field := + Powerset_S1Retention_Field_Reset; + -- unspecified + Reserved_18_31 : HAL.UInt14 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for POWERSET_RAM_Register use record + S0POWER at 0 range 0 .. 0; + S1POWER at 0 range 1 .. 1; + Reserved_2_15 at 0 range 2 .. 15; + S0RETENTION at 0 range 16 .. 16; + S1RETENTION at 0 range 17 .. 17; + Reserved_18_31 at 0 range 18 .. 31; + end record; + + -- Keep RAM section S0 of RAM0 on or off in System ON mode + type POWERCLR_S0POWER_Field is + (-- Off + Off) + with Size => 1; + for POWERCLR_S0POWER_Field use + (Off => 1); + + -- Keep RAM section S1 of RAM0 on or off in System ON mode + type POWERCLR_S1POWER_Field is + (-- Off + Off) + with Size => 1; + for POWERCLR_S1POWER_Field use + (Off => 1); + + -- Keep retention on RAM section S0 when RAM section is switched off + type POWERCLR_S0RETENTION_Field is + (-- Reset value for the field + Powerclr_S0Retention_Field_Reset, + -- Off + Off) + with Size => 1; + for POWERCLR_S0RETENTION_Field use + (Powerclr_S0Retention_Field_Reset => 0, + Off => 1); + + -- Keep retention on RAM section S1 when RAM section is switched off + type POWERCLR_S1RETENTION_Field is + (-- Reset value for the field + Powerclr_S1Retention_Field_Reset, + -- Off + Off) + with Size => 1; + for POWERCLR_S1RETENTION_Field use + (Powerclr_S1Retention_Field_Reset => 0, + Off => 1); + + -- Description cluster[0]: RAM0 power control clear register + type POWERCLR_RAM_Register is record + -- Write-only. Keep RAM section S0 of RAM0 on or off in System ON mode + S0POWER : POWERCLR_S0POWER_Field := NRF_SVD.POWER.Off; + -- Write-only. Keep RAM section S1 of RAM0 on or off in System ON mode + S1POWER : POWERCLR_S1POWER_Field := NRF_SVD.POWER.Off; + -- unspecified + Reserved_2_15 : HAL.UInt14 := 16#3FFF#; + -- Write-only. Keep retention on RAM section S0 when RAM section is + -- switched off + S0RETENTION : POWERCLR_S0RETENTION_Field := + Powerclr_S0Retention_Field_Reset; + -- Write-only. Keep retention on RAM section S1 when RAM section is + -- switched off + S1RETENTION : POWERCLR_S1RETENTION_Field := + Powerclr_S1Retention_Field_Reset; + -- unspecified + Reserved_18_31 : HAL.UInt14 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for POWERCLR_RAM_Register use record + S0POWER at 0 range 0 .. 0; + S1POWER at 0 range 1 .. 1; + Reserved_2_15 at 0 range 2 .. 15; + S0RETENTION at 0 range 16 .. 16; + S1RETENTION at 0 range 17 .. 17; + Reserved_18_31 at 0 range 18 .. 31; + end record; + + -- Unspecified + type RAM_Cluster is record + -- Description cluster[0]: RAM0 power control register + POWER : aliased POWER_RAM_Register; + -- Description cluster[0]: RAM0 power control set register + POWERSET : aliased POWERSET_RAM_Register; + -- Description cluster[0]: RAM0 power control clear register + POWERCLR : aliased POWERCLR_RAM_Register; + end record + with Size => 96; + + for RAM_Cluster use record + POWER at 16#0# range 0 .. 31; + POWERSET at 16#4# range 0 .. 31; + POWERCLR at 16#8# range 0 .. 31; + end record; + + -- Unspecified + type RAM_Clusters is array (0 .. 7) of RAM_Cluster; + + ----------------- + -- Peripherals -- + ----------------- + + -- Power control + type POWER_Peripheral is record + -- Enable constant latency mode + TASKS_CONSTLAT : aliased HAL.UInt32; + -- Enable low power mode (variable latency) + TASKS_LOWPWR : aliased HAL.UInt32; + -- Power failure warning + EVENTS_POFWARN : aliased HAL.UInt32; + -- CPU entered WFI/WFE sleep + EVENTS_SLEEPENTER : aliased HAL.UInt32; + -- CPU exited WFI/WFE sleep + EVENTS_SLEEPEXIT : aliased HAL.UInt32; + -- Enable interrupt + INTENSET : aliased INTENSET_Register; + -- Disable interrupt + INTENCLR : aliased INTENCLR_Register; + -- Reset reason + RESETREAS : aliased RESETREAS_Register; + -- Deprecated register - RAM status register + RAMSTATUS : aliased RAMSTATUS_Register; + -- System OFF register + SYSTEMOFF : aliased SYSTEMOFF_Register; + -- Power failure comparator configuration + POFCON : aliased POFCON_Register; + -- General purpose retention register + GPREGRET : aliased GPREGRET_Register; + -- General purpose retention register + GPREGRET2 : aliased GPREGRET_Register; + -- Deprecated register - RAM on/off register (this register is retained) + RAMON : aliased RAMON_Register; + -- Deprecated register - RAM on/off register (this register is retained) + RAMONB : aliased RAMONB_Register; + -- DC/DC enable register + DCDCEN : aliased DCDCEN_Register; + -- Unspecified + RAM : aliased RAM_Clusters; + end record + with Volatile; + + for POWER_Peripheral use record + TASKS_CONSTLAT at 16#78# range 0 .. 31; + TASKS_LOWPWR at 16#7C# range 0 .. 31; + EVENTS_POFWARN at 16#108# range 0 .. 31; + EVENTS_SLEEPENTER at 16#114# range 0 .. 31; + EVENTS_SLEEPEXIT at 16#118# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + RESETREAS at 16#400# range 0 .. 31; + RAMSTATUS at 16#428# range 0 .. 31; + SYSTEMOFF at 16#500# range 0 .. 31; + POFCON at 16#510# range 0 .. 31; + GPREGRET at 16#51C# range 0 .. 31; + GPREGRET2 at 16#520# range 0 .. 31; + RAMON at 16#524# range 0 .. 31; + RAMONB at 16#554# range 0 .. 31; + DCDCEN at 16#578# range 0 .. 31; + RAM at 16#900# range 0 .. 767; + end record; + + -- Power control + POWER_Periph : aliased POWER_Peripheral + with Import, Address => POWER_Base; + +end NRF_SVD.POWER; diff --git a/arch/ARM/Nordic/svd/nrf52/nrf_svd-ppi.ads b/arch/ARM/Nordic/svd/nrf52/nrf_svd-ppi.ads new file mode 100644 index 000000000..cce98cfbd --- /dev/null +++ b/arch/ARM/Nordic/svd/nrf52/nrf_svd-ppi.ads @@ -0,0 +1,321 @@ +-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- 2. Redistributions in binary form, except as embedded into a Nordic +-- Semiconductor ASA integrated circuit in a product or a software update for +-- such product, must reproduce the above copyright notice, this list of +-- conditions and the following disclaimer in the documentation and/or other +-- materials provided with the distribution. +-- +-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from this +-- software without specific prior written permission. +-- +-- 4. This software, with or without modification, must only be used with a +-- Nordic Semiconductor ASA integrated circuit. +-- +-- 5. Any software provided in binary form under this license must not be reverse +-- engineered, decompiled, modified and/or disassembled. +-- +-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +-- OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + +-- This spec has been automatically generated from nrf52.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package NRF_SVD.PPI is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + ----------------------------------- + -- TASKS_CHG cluster's Registers -- + ----------------------------------- + + -- Channel group tasks + type TASKS_CHG_Cluster is record + -- Description cluster[0]: Enable channel group 0 + EN : aliased HAL.UInt32; + -- Description cluster[0]: Disable channel group 0 + DIS : aliased HAL.UInt32; + end record + with Size => 64; + + for TASKS_CHG_Cluster use record + EN at 16#0# range 0 .. 31; + DIS at 16#4# range 0 .. 31; + end record; + + -- Channel group tasks + type TASKS_CHG_Clusters is array (0 .. 5) of TASKS_CHG_Cluster; + + -- Enable or disable channel 0 + type CHEN_CH0_Field is + (-- Disable channel + Disabled, + -- Enable channel + Enabled) + with Size => 1; + for CHEN_CH0_Field use + (Disabled => 0, + Enabled => 1); + + -- CHEN_CH array + type CHEN_CH_Field_Array is array (0 .. 31) of CHEN_CH0_Field + with Component_Size => 1, Size => 32; + + -- Channel enable register + type CHEN_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CH as a value + Val : HAL.UInt32; + when True => + -- CH as an array + Arr : CHEN_CH_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CHEN_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- Channel 0 enable set register. Writing '0' has no effect + type CHENSET_CH0_Field is + (-- Read: channel disabled + Disabled, + -- Read: channel enabled + Enabled) + with Size => 1; + for CHENSET_CH0_Field use + (Disabled => 0, + Enabled => 1); + + -- Channel 0 enable set register. Writing '0' has no effect + type CHENSET_CH0_Field_1 is + (-- Reset value for the field + Chenset_Ch0_Field_Reset, + -- Write: Enable channel + Set) + with Size => 1; + for CHENSET_CH0_Field_1 use + (Chenset_Ch0_Field_Reset => 0, + Set => 1); + + -- CHENSET_CH array + type CHENSET_CH_Field_Array is array (0 .. 31) of CHENSET_CH0_Field_1 + with Component_Size => 1, Size => 32; + + -- Channel enable set register + type CHENSET_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CH as a value + Val : HAL.UInt32; + when True => + -- CH as an array + Arr : CHENSET_CH_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CHENSET_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- Channel 0 enable clear register. Writing '0' has no effect + type CHENCLR_CH0_Field is + (-- Read: channel disabled + Disabled, + -- Read: channel enabled + Enabled) + with Size => 1; + for CHENCLR_CH0_Field use + (Disabled => 0, + Enabled => 1); + + -- Channel 0 enable clear register. Writing '0' has no effect + type CHENCLR_CH0_Field_1 is + (-- Reset value for the field + Chenclr_Ch0_Field_Reset, + -- Write: disable channel + Clear) + with Size => 1; + for CHENCLR_CH0_Field_1 use + (Chenclr_Ch0_Field_Reset => 0, + Clear => 1); + + -- CHENCLR_CH array + type CHENCLR_CH_Field_Array is array (0 .. 31) of CHENCLR_CH0_Field_1 + with Component_Size => 1, Size => 32; + + -- Channel enable clear register + type CHENCLR_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CH as a value + Val : HAL.UInt32; + when True => + -- CH as an array + Arr : CHENCLR_CH_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CHENCLR_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + ---------------------------- + -- CH cluster's Registers -- + ---------------------------- + + -- PPI Channel + type CH_Cluster is record + -- Description cluster[0]: Channel 0 event end-point + EEP : aliased HAL.UInt32; + -- Description cluster[0]: Channel 0 task end-point + TEP : aliased HAL.UInt32; + end record + with Size => 64; + + for CH_Cluster use record + EEP at 16#0# range 0 .. 31; + TEP at 16#4# range 0 .. 31; + end record; + + -- PPI Channel + type CH_Clusters is array (0 .. 19) of CH_Cluster; + + -- Include or exclude channel 0 + type CHG_CH0_Field is + (-- Exclude + Excluded, + -- Include + Included) + with Size => 1; + for CHG_CH0_Field use + (Excluded => 0, + Included => 1); + + -- CHG_CH array + type CHG_CH_Field_Array is array (0 .. 31) of CHG_CH0_Field + with Component_Size => 1, Size => 32; + + -- Description collection[0]: Channel group 0 + type CHG_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CH as a value + Val : HAL.UInt32; + when True => + -- CH as an array + Arr : CHG_CH_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CHG_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- Description collection[0]: Channel group 0 + type CHG_Registers is array (0 .. 5) of CHG_Register; + + ------------------------------ + -- FORK cluster's Registers -- + ------------------------------ + + -- Fork + type FORK_Cluster is record + -- Description cluster[0]: Channel 0 task end-point + TEP : aliased HAL.UInt32; + end record + with Size => 32; + + for FORK_Cluster use record + TEP at 0 range 0 .. 31; + end record; + + -- Fork + type FORK_Clusters is array (0 .. 31) of FORK_Cluster; + + ----------------- + -- Peripherals -- + ----------------- + + -- Programmable Peripheral Interconnect + type PPI_Peripheral is record + -- Channel group tasks + TASKS_CHG : aliased TASKS_CHG_Clusters; + -- Channel enable register + CHEN : aliased CHEN_Register; + -- Channel enable set register + CHENSET : aliased CHENSET_Register; + -- Channel enable clear register + CHENCLR : aliased CHENCLR_Register; + -- PPI Channel + CH : aliased CH_Clusters; + -- Description collection[0]: Channel group 0 + CHG : aliased CHG_Registers; + -- Fork + FORK : aliased FORK_Clusters; + end record + with Volatile; + + for PPI_Peripheral use record + TASKS_CHG at 16#0# range 0 .. 383; + CHEN at 16#500# range 0 .. 31; + CHENSET at 16#504# range 0 .. 31; + CHENCLR at 16#508# range 0 .. 31; + CH at 16#510# range 0 .. 1279; + CHG at 16#800# range 0 .. 191; + FORK at 16#910# range 0 .. 1023; + end record; + + -- Programmable Peripheral Interconnect + PPI_Periph : aliased PPI_Peripheral + with Import, Address => PPI_Base; + +end NRF_SVD.PPI; diff --git a/arch/ARM/Nordic/svd/nrf52/nrf_svd-pwm.ads b/arch/ARM/Nordic/svd/nrf52/nrf_svd-pwm.ads new file mode 100644 index 000000000..3e09dc81f --- /dev/null +++ b/arch/ARM/Nordic/svd/nrf52/nrf_svd-pwm.ads @@ -0,0 +1,1138 @@ +-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- 2. Redistributions in binary form, except as embedded into a Nordic +-- Semiconductor ASA integrated circuit in a product or a software update for +-- such product, must reproduce the above copyright notice, this list of +-- conditions and the following disclaimer in the documentation and/or other +-- materials provided with the distribution. +-- +-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from this +-- software without specific prior written permission. +-- +-- 4. This software, with or without modification, must only be used with a +-- Nordic Semiconductor ASA integrated circuit. +-- +-- 5. Any software provided in binary form under this license must not be reverse +-- engineered, decompiled, modified and/or disassembled. +-- +-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +-- OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + +-- This spec has been automatically generated from nrf52.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package NRF_SVD.PWM is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Description collection[0]: Loads the first PWM value on all enabled channels from sequence 0, and starts playing that sequence at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not running. + + -- Description collection[0]: Loads the first PWM value on all enabled + -- channels from sequence 0, and starts playing that sequence at the rate + -- defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to + -- start it was not running. + type TASKS_SEQSTART_Registers is array (0 .. 1) of HAL.UInt32; + + -- Description collection[0]: First PWM period started on sequence 0 + + -- Description collection[0]: First PWM period started on sequence 0 + type EVENTS_SEQSTARTED_Registers is array (0 .. 1) of HAL.UInt32; + + -- Description collection[0]: Emitted at end of every sequence 0, when last value from RAM has been applied to wave counter + + -- Description collection[0]: Emitted at end of every sequence 0, when last + -- value from RAM has been applied to wave counter + type EVENTS_SEQEND_Registers is array (0 .. 1) of HAL.UInt32; + + -- Shortcut between SEQEND[0] event and STOP task + type SHORTS_SEQEND0_STOP_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_SEQEND0_STOP_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut between SEQEND[1] event and STOP task + type SHORTS_SEQEND1_STOP_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_SEQEND1_STOP_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut between LOOPSDONE event and SEQSTART[0] task + type SHORTS_LOOPSDONE_SEQSTART0_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_LOOPSDONE_SEQSTART0_Field use + (Disabled => 0, + Enabled => 1); + + -- SHORTS_LOOPSDONE_SEQSTART array + type SHORTS_LOOPSDONE_SEQSTART_Field_Array is array (0 .. 1) + of SHORTS_LOOPSDONE_SEQSTART0_Field + with Component_Size => 1, Size => 2; + + -- Type definition for SHORTS_LOOPSDONE_SEQSTART + type SHORTS_LOOPSDONE_SEQSTART_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- LOOPSDONE_SEQSTART as a value + Val : HAL.UInt2; + when True => + -- LOOPSDONE_SEQSTART as an array + Arr : SHORTS_LOOPSDONE_SEQSTART_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for SHORTS_LOOPSDONE_SEQSTART_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Shortcut between LOOPSDONE event and STOP task + type SHORTS_LOOPSDONE_STOP_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_LOOPSDONE_STOP_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut register + type SHORTS_Register is record + -- Shortcut between SEQEND[0] event and STOP task + SEQEND0_STOP : SHORTS_SEQEND0_STOP_Field := NRF_SVD.PWM.Disabled; + -- Shortcut between SEQEND[1] event and STOP task + SEQEND1_STOP : SHORTS_SEQEND1_STOP_Field := NRF_SVD.PWM.Disabled; + -- Shortcut between LOOPSDONE event and SEQSTART[0] task + LOOPSDONE_SEQSTART : SHORTS_LOOPSDONE_SEQSTART_Field := + (As_Array => False, Val => 16#0#); + -- Shortcut between LOOPSDONE event and STOP task + LOOPSDONE_STOP : SHORTS_LOOPSDONE_STOP_Field := + NRF_SVD.PWM.Disabled; + -- unspecified + Reserved_5_31 : HAL.UInt27 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SHORTS_Register use record + SEQEND0_STOP at 0 range 0 .. 0; + SEQEND1_STOP at 0 range 1 .. 1; + LOOPSDONE_SEQSTART at 0 range 2 .. 3; + LOOPSDONE_STOP at 0 range 4 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + -- Enable or disable interrupt for STOPPED event + type INTEN_STOPPED_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_STOPPED_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for SEQSTARTED[0] event + type INTEN_SEQSTARTED0_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_SEQSTARTED0_Field use + (Disabled => 0, + Enabled => 1); + + -- INTEN_SEQSTARTED array + type INTEN_SEQSTARTED_Field_Array is array (0 .. 1) + of INTEN_SEQSTARTED0_Field + with Component_Size => 1, Size => 2; + + -- Type definition for INTEN_SEQSTARTED + type INTEN_SEQSTARTED_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SEQSTARTED as a value + Val : HAL.UInt2; + when True => + -- SEQSTARTED as an array + Arr : INTEN_SEQSTARTED_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for INTEN_SEQSTARTED_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Enable or disable interrupt for SEQEND[0] event + type INTEN_SEQEND0_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_SEQEND0_Field use + (Disabled => 0, + Enabled => 1); + + -- INTEN_SEQEND array + type INTEN_SEQEND_Field_Array is array (0 .. 1) of INTEN_SEQEND0_Field + with Component_Size => 1, Size => 2; + + -- Type definition for INTEN_SEQEND + type INTEN_SEQEND_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SEQEND as a value + Val : HAL.UInt2; + when True => + -- SEQEND as an array + Arr : INTEN_SEQEND_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for INTEN_SEQEND_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Enable or disable interrupt for PWMPERIODEND event + type INTEN_PWMPERIODEND_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_PWMPERIODEND_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for LOOPSDONE event + type INTEN_LOOPSDONE_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_LOOPSDONE_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt + type INTEN_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#0#; + -- Enable or disable interrupt for STOPPED event + STOPPED : INTEN_STOPPED_Field := NRF_SVD.PWM.Disabled; + -- Enable or disable interrupt for SEQSTARTED[0] event + SEQSTARTED : INTEN_SEQSTARTED_Field := + (As_Array => False, Val => 16#0#); + -- Enable or disable interrupt for SEQEND[0] event + SEQEND : INTEN_SEQEND_Field := (As_Array => False, Val => 16#0#); + -- Enable or disable interrupt for PWMPERIODEND event + PWMPERIODEND : INTEN_PWMPERIODEND_Field := NRF_SVD.PWM.Disabled; + -- Enable or disable interrupt for LOOPSDONE event + LOOPSDONE : INTEN_LOOPSDONE_Field := NRF_SVD.PWM.Disabled; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTEN_Register use record + Reserved_0_0 at 0 range 0 .. 0; + STOPPED at 0 range 1 .. 1; + SEQSTARTED at 0 range 2 .. 3; + SEQEND at 0 range 4 .. 5; + PWMPERIODEND at 0 range 6 .. 6; + LOOPSDONE at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- Write '1' to Enable interrupt for STOPPED event + type INTENSET_STOPPED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_STOPPED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for STOPPED event + type INTENSET_STOPPED_Field_1 is + (-- Reset value for the field + Intenset_Stopped_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_STOPPED_Field_1 use + (Intenset_Stopped_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for SEQSTARTED[0] event + type INTENSET_SEQSTARTED0_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_SEQSTARTED0_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for SEQSTARTED[0] event + type INTENSET_SEQSTARTED0_Field_1 is + (-- Reset value for the field + Intenset_Seqstarted0_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_SEQSTARTED0_Field_1 use + (Intenset_Seqstarted0_Field_Reset => 0, + Set => 1); + + -- INTENSET_SEQSTARTED array + type INTENSET_SEQSTARTED_Field_Array is array (0 .. 1) + of INTENSET_SEQSTARTED0_Field_1 + with Component_Size => 1, Size => 2; + + -- Type definition for INTENSET_SEQSTARTED + type INTENSET_SEQSTARTED_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SEQSTARTED as a value + Val : HAL.UInt2; + when True => + -- SEQSTARTED as an array + Arr : INTENSET_SEQSTARTED_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for INTENSET_SEQSTARTED_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Write '1' to Enable interrupt for SEQEND[0] event + type INTENSET_SEQEND0_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_SEQEND0_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for SEQEND[0] event + type INTENSET_SEQEND0_Field_1 is + (-- Reset value for the field + Intenset_Seqend0_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_SEQEND0_Field_1 use + (Intenset_Seqend0_Field_Reset => 0, + Set => 1); + + -- INTENSET_SEQEND array + type INTENSET_SEQEND_Field_Array is array (0 .. 1) + of INTENSET_SEQEND0_Field_1 + with Component_Size => 1, Size => 2; + + -- Type definition for INTENSET_SEQEND + type INTENSET_SEQEND_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SEQEND as a value + Val : HAL.UInt2; + when True => + -- SEQEND as an array + Arr : INTENSET_SEQEND_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for INTENSET_SEQEND_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Write '1' to Enable interrupt for PWMPERIODEND event + type INTENSET_PWMPERIODEND_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_PWMPERIODEND_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for PWMPERIODEND event + type INTENSET_PWMPERIODEND_Field_1 is + (-- Reset value for the field + Intenset_Pwmperiodend_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_PWMPERIODEND_Field_1 use + (Intenset_Pwmperiodend_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for LOOPSDONE event + type INTENSET_LOOPSDONE_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_LOOPSDONE_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for LOOPSDONE event + type INTENSET_LOOPSDONE_Field_1 is + (-- Reset value for the field + Intenset_Loopsdone_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_LOOPSDONE_Field_1 use + (Intenset_Loopsdone_Field_Reset => 0, + Set => 1); + + -- Enable interrupt + type INTENSET_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#0#; + -- Write '1' to Enable interrupt for STOPPED event + STOPPED : INTENSET_STOPPED_Field_1 := + Intenset_Stopped_Field_Reset; + -- Write '1' to Enable interrupt for SEQSTARTED[0] event + SEQSTARTED : INTENSET_SEQSTARTED_Field := + (As_Array => False, Val => 16#0#); + -- Write '1' to Enable interrupt for SEQEND[0] event + SEQEND : INTENSET_SEQEND_Field := + (As_Array => False, Val => 16#0#); + -- Write '1' to Enable interrupt for PWMPERIODEND event + PWMPERIODEND : INTENSET_PWMPERIODEND_Field_1 := + Intenset_Pwmperiodend_Field_Reset; + -- Write '1' to Enable interrupt for LOOPSDONE event + LOOPSDONE : INTENSET_LOOPSDONE_Field_1 := + Intenset_Loopsdone_Field_Reset; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENSET_Register use record + Reserved_0_0 at 0 range 0 .. 0; + STOPPED at 0 range 1 .. 1; + SEQSTARTED at 0 range 2 .. 3; + SEQEND at 0 range 4 .. 5; + PWMPERIODEND at 0 range 6 .. 6; + LOOPSDONE at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- Write '1' to Disable interrupt for STOPPED event + type INTENCLR_STOPPED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_STOPPED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for STOPPED event + type INTENCLR_STOPPED_Field_1 is + (-- Reset value for the field + Intenclr_Stopped_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_STOPPED_Field_1 use + (Intenclr_Stopped_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for SEQSTARTED[0] event + type INTENCLR_SEQSTARTED0_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_SEQSTARTED0_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for SEQSTARTED[0] event + type INTENCLR_SEQSTARTED0_Field_1 is + (-- Reset value for the field + Intenclr_Seqstarted0_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_SEQSTARTED0_Field_1 use + (Intenclr_Seqstarted0_Field_Reset => 0, + Clear => 1); + + -- INTENCLR_SEQSTARTED array + type INTENCLR_SEQSTARTED_Field_Array is array (0 .. 1) + of INTENCLR_SEQSTARTED0_Field_1 + with Component_Size => 1, Size => 2; + + -- Type definition for INTENCLR_SEQSTARTED + type INTENCLR_SEQSTARTED_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SEQSTARTED as a value + Val : HAL.UInt2; + when True => + -- SEQSTARTED as an array + Arr : INTENCLR_SEQSTARTED_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for INTENCLR_SEQSTARTED_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Write '1' to Disable interrupt for SEQEND[0] event + type INTENCLR_SEQEND0_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_SEQEND0_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for SEQEND[0] event + type INTENCLR_SEQEND0_Field_1 is + (-- Reset value for the field + Intenclr_Seqend0_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_SEQEND0_Field_1 use + (Intenclr_Seqend0_Field_Reset => 0, + Clear => 1); + + -- INTENCLR_SEQEND array + type INTENCLR_SEQEND_Field_Array is array (0 .. 1) + of INTENCLR_SEQEND0_Field_1 + with Component_Size => 1, Size => 2; + + -- Type definition for INTENCLR_SEQEND + type INTENCLR_SEQEND_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SEQEND as a value + Val : HAL.UInt2; + when True => + -- SEQEND as an array + Arr : INTENCLR_SEQEND_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for INTENCLR_SEQEND_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Write '1' to Disable interrupt for PWMPERIODEND event + type INTENCLR_PWMPERIODEND_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_PWMPERIODEND_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for PWMPERIODEND event + type INTENCLR_PWMPERIODEND_Field_1 is + (-- Reset value for the field + Intenclr_Pwmperiodend_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_PWMPERIODEND_Field_1 use + (Intenclr_Pwmperiodend_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for LOOPSDONE event + type INTENCLR_LOOPSDONE_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_LOOPSDONE_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for LOOPSDONE event + type INTENCLR_LOOPSDONE_Field_1 is + (-- Reset value for the field + Intenclr_Loopsdone_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_LOOPSDONE_Field_1 use + (Intenclr_Loopsdone_Field_Reset => 0, + Clear => 1); + + -- Disable interrupt + type INTENCLR_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#0#; + -- Write '1' to Disable interrupt for STOPPED event + STOPPED : INTENCLR_STOPPED_Field_1 := + Intenclr_Stopped_Field_Reset; + -- Write '1' to Disable interrupt for SEQSTARTED[0] event + SEQSTARTED : INTENCLR_SEQSTARTED_Field := + (As_Array => False, Val => 16#0#); + -- Write '1' to Disable interrupt for SEQEND[0] event + SEQEND : INTENCLR_SEQEND_Field := + (As_Array => False, Val => 16#0#); + -- Write '1' to Disable interrupt for PWMPERIODEND event + PWMPERIODEND : INTENCLR_PWMPERIODEND_Field_1 := + Intenclr_Pwmperiodend_Field_Reset; + -- Write '1' to Disable interrupt for LOOPSDONE event + LOOPSDONE : INTENCLR_LOOPSDONE_Field_1 := + Intenclr_Loopsdone_Field_Reset; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENCLR_Register use record + Reserved_0_0 at 0 range 0 .. 0; + STOPPED at 0 range 1 .. 1; + SEQSTARTED at 0 range 2 .. 3; + SEQEND at 0 range 4 .. 5; + PWMPERIODEND at 0 range 6 .. 6; + LOOPSDONE at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- Enable or disable PWM module + type ENABLE_ENABLE_Field is + (-- Disabled + Disabled, + -- Enable + Enabled) + with Size => 1; + for ENABLE_ENABLE_Field use + (Disabled => 0, + Enabled => 1); + + -- PWM module enable register + type ENABLE_Register is record + -- Enable or disable PWM module + ENABLE : ENABLE_ENABLE_Field := NRF_SVD.PWM.Disabled; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ENABLE_Register use record + ENABLE at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Selects up or up and down as wave counter mode + type MODE_UPDOWN_Field is + (-- Up counter - edge aligned PWM duty-cycle + Up, + -- Up and down counter - center aligned PWM duty cycle + Upanddown) + with Size => 1; + for MODE_UPDOWN_Field use + (Up => 0, + Upanddown => 1); + + -- Selects operating mode of the wave counter + type MODE_Register is record + -- Selects up or up and down as wave counter mode + UPDOWN : MODE_UPDOWN_Field := NRF_SVD.PWM.Up; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MODE_Register use record + UPDOWN at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + subtype COUNTERTOP_COUNTERTOP_Field is HAL.UInt15; + + -- Value up to which the pulse generator counter counts + type COUNTERTOP_Register is record + -- Value up to which the pulse generator counter counts. This register + -- is ignored when DECODER.MODE=WaveForm and only values from RAM will + -- be used. + COUNTERTOP : COUNTERTOP_COUNTERTOP_Field := 16#3FF#; + -- unspecified + Reserved_15_31 : HAL.UInt17 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for COUNTERTOP_Register use record + COUNTERTOP at 0 range 0 .. 14; + Reserved_15_31 at 0 range 15 .. 31; + end record; + + -- Pre-scaler of PWM_CLK + type PRESCALER_PRESCALER_Field is + (-- Divide by 1 (16MHz) + Div_1, + -- Divide by 2 ( 8MHz) + Div_2, + -- Divide by 4 ( 4MHz) + Div_4, + -- Divide by 8 ( 2MHz) + Div_8, + -- Divide by 16 ( 1MHz) + Div_16, + -- Divide by 32 ( 500kHz) + Div_32, + -- Divide by 64 ( 250kHz) + Div_64, + -- Divide by 128 ( 125kHz) + Div_128) + with Size => 3; + for PRESCALER_PRESCALER_Field use + (Div_1 => 0, + Div_2 => 1, + Div_4 => 2, + Div_8 => 3, + Div_16 => 4, + Div_32 => 5, + Div_64 => 6, + Div_128 => 7); + + -- Configuration for PWM_CLK + type PRESCALER_Register is record + -- Pre-scaler of PWM_CLK + PRESCALER : PRESCALER_PRESCALER_Field := NRF_SVD.PWM.Div_1; + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PRESCALER_Register use record + PRESCALER at 0 range 0 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + -- How a sequence is read from RAM and spread to the compare register + type DECODER_LOAD_Field is + (-- 1st half word (16-bit) used in all PWM channels 0..3 + Common, + -- 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 + Grouped, + -- 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 + Individual, + -- 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP + Waveform) + with Size => 2; + for DECODER_LOAD_Field use + (Common => 0, + Grouped => 1, + Individual => 2, + Waveform => 3); + + -- Selects source for advancing the active sequence + type DECODER_MODE_Field is + (-- SEQ[n].REFRESH is used to determine loading internal compare registers + Refreshcount, + -- NEXTSTEP task causes a new value to be loaded to internal compare registers + Nextstep) + with Size => 1; + for DECODER_MODE_Field use + (Refreshcount => 0, + Nextstep => 1); + + -- Configuration of the decoder + type DECODER_Register is record + -- How a sequence is read from RAM and spread to the compare register + LOAD : DECODER_LOAD_Field := NRF_SVD.PWM.Common; + -- unspecified + Reserved_2_7 : HAL.UInt6 := 16#0#; + -- Selects source for advancing the active sequence + MODE : DECODER_MODE_Field := NRF_SVD.PWM.Refreshcount; + -- unspecified + Reserved_9_31 : HAL.UInt23 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DECODER_Register use record + LOAD at 0 range 0 .. 1; + Reserved_2_7 at 0 range 2 .. 7; + MODE at 0 range 8 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + -- Amount of playback of pattern cycles + type LOOP_CNT_Field is + (-- Looping disabled (stop at the end of the sequence) + Disabled) + with Size => 16; + for LOOP_CNT_Field use + (Disabled => 0); + + -- Amount of playback of a loop + type LOOP_Register is record + -- Amount of playback of pattern cycles + CNT : LOOP_CNT_Field := NRF_SVD.PWM.Disabled; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for LOOP_Register use record + CNT at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + --------------------------------- + -- PWM_SEQ cluster's Registers -- + --------------------------------- + + -- Amount of values (duty cycles) in this sequence + type CNT_CNT_Field is + (-- Sequence is disabled, and shall not be started as it is empty + Disabled) + with Size => 15; + for CNT_CNT_Field use + (Disabled => 0); + + -- Description cluster[0]: Amount of values (duty cycles) in this sequence + type CNT_SEQ_Register is record + -- Amount of values (duty cycles) in this sequence + CNT : CNT_CNT_Field := NRF_SVD.PWM.Disabled; + -- unspecified + Reserved_15_31 : HAL.UInt17 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CNT_SEQ_Register use record + CNT at 0 range 0 .. 14; + Reserved_15_31 at 0 range 15 .. 31; + end record; + + -- Amount of additional PWM periods between samples loaded into compare + -- register (load every REFRESH.CNT+1 PWM periods) + type REFRESH_CNT_Field is + (-- Update every PWM period + Continuous, + -- Reset value for the field + Refresh_Cnt_Field_Reset) + with Size => 24; + for REFRESH_CNT_Field use + (Continuous => 0, + Refresh_Cnt_Field_Reset => 1); + + -- Description cluster[0]: Amount of additional PWM periods between samples + -- loaded into compare register + type REFRESH_SEQ_Register is record + -- Amount of additional PWM periods between samples loaded into compare + -- register (load every REFRESH.CNT+1 PWM periods) + CNT : REFRESH_CNT_Field := Refresh_Cnt_Field_Reset; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for REFRESH_SEQ_Register use record + CNT at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype ENDDELAY_SEQ_CNT_Field is HAL.UInt24; + + -- Description cluster[0]: Time added after the sequence + type ENDDELAY_SEQ_Register is record + -- Time added after the sequence in PWM periods + CNT : ENDDELAY_SEQ_CNT_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ENDDELAY_SEQ_Register use record + CNT at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Unspecified + type PWM_SEQ_Cluster is record + -- Description cluster[0]: Beginning address in Data RAM of this + -- sequence + PTR : aliased HAL.UInt32; + -- Description cluster[0]: Amount of values (duty cycles) in this + -- sequence + CNT : aliased CNT_SEQ_Register; + -- Description cluster[0]: Amount of additional PWM periods between + -- samples loaded into compare register + REFRESH : aliased REFRESH_SEQ_Register; + -- Description cluster[0]: Time added after the sequence + ENDDELAY : aliased ENDDELAY_SEQ_Register; + end record + with Size => 128; + + for PWM_SEQ_Cluster use record + PTR at 16#0# range 0 .. 31; + CNT at 16#4# range 0 .. 31; + REFRESH at 16#8# range 0 .. 31; + ENDDELAY at 16#C# range 0 .. 31; + end record; + + -- Unspecified + type PWM_SEQ_Clusters is array (0 .. 1) of PWM_SEQ_Cluster; + + ---------------------------------- + -- PWM_PSEL cluster's Registers -- + ---------------------------------- + + subtype OUT_PSEL_PIN_Field is HAL.UInt5; + + -- Connection + type OUT_CONNECT_Field is + (-- Connect + Connected, + -- Disconnect + Disconnected) + with Size => 1; + for OUT_CONNECT_Field use + (Connected => 0, + Disconnected => 1); + + -- Description collection[0]: Output pin select for PWM channel 0 + type OUT_PSEL_Register is record + -- Pin number + PIN : OUT_PSEL_PIN_Field := 16#1F#; + -- unspecified + Reserved_5_30 : HAL.UInt26 := 16#3FFFFFF#; + -- Connection + CONNECT : OUT_CONNECT_Field := NRF_SVD.PWM.Disconnected; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for OUT_PSEL_Register use record + PIN at 0 range 0 .. 4; + Reserved_5_30 at 0 range 5 .. 30; + CONNECT at 0 range 31 .. 31; + end record; + + -- Description collection[0]: Output pin select for PWM channel 0 + type OUT_PSEL_Registers is array (0 .. 3) of OUT_PSEL_Register; + + -- Unspecified + type PWM_PSEL_Cluster is record + -- Description collection[0]: Output pin select for PWM channel 0 + OUT_k : aliased OUT_PSEL_Registers; + end record + with Size => 128; + + for PWM_PSEL_Cluster use record + OUT_k at 0 range 0 .. 127; + end record; + + --------------------------------- + -- PWM_SEQ cluster's Registers -- + --------------------------------- + + ---------------------------------- + -- PWM_PSEL cluster's Registers -- + ---------------------------------- + + --------------------------------- + -- PWM_SEQ cluster's Registers -- + --------------------------------- + + ---------------------------------- + -- PWM_PSEL cluster's Registers -- + ---------------------------------- + + ----------------- + -- Peripherals -- + ----------------- + + -- Pulse Width Modulation Unit 0 + type PWM_Peripheral is record + -- Stops PWM pulse generation on all channels at the end of current PWM + -- period, and stops sequence playback + TASKS_STOP : aliased HAL.UInt32; + -- Description collection[0]: Loads the first PWM value on all enabled + -- channels from sequence 0, and starts playing that sequence at the + -- rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM + -- generation to start it was not running. + TASKS_SEQSTART : aliased TASKS_SEQSTART_Registers; + -- Steps by one value in the current sequence on all enabled channels if + -- DECODER.MODE=NextStep. Does not cause PWM generation to start it was + -- not running. + TASKS_NEXTSTEP : aliased HAL.UInt32; + -- Response to STOP task, emitted when PWM pulses are no longer + -- generated + EVENTS_STOPPED : aliased HAL.UInt32; + -- Description collection[0]: First PWM period started on sequence 0 + EVENTS_SEQSTARTED : aliased EVENTS_SEQSTARTED_Registers; + -- Description collection[0]: Emitted at end of every sequence 0, when + -- last value from RAM has been applied to wave counter + EVENTS_SEQEND : aliased EVENTS_SEQEND_Registers; + -- Emitted at the end of each PWM period + EVENTS_PWMPERIODEND : aliased HAL.UInt32; + -- Concatenated sequences have been played the amount of times defined + -- in LOOP.CNT + EVENTS_LOOPSDONE : aliased HAL.UInt32; + -- Shortcut register + SHORTS : aliased SHORTS_Register; + -- Enable or disable interrupt + INTEN : aliased INTEN_Register; + -- Enable interrupt + INTENSET : aliased INTENSET_Register; + -- Disable interrupt + INTENCLR : aliased INTENCLR_Register; + -- PWM module enable register + ENABLE : aliased ENABLE_Register; + -- Selects operating mode of the wave counter + MODE : aliased MODE_Register; + -- Value up to which the pulse generator counter counts + COUNTERTOP : aliased COUNTERTOP_Register; + -- Configuration for PWM_CLK + PRESCALER : aliased PRESCALER_Register; + -- Configuration of the decoder + DECODER : aliased DECODER_Register; + -- Amount of playback of a loop + LOOP_k : aliased LOOP_Register; + -- Unspecified + SEQ : aliased PWM_SEQ_Clusters; + -- Unspecified + PSEL : aliased PWM_PSEL_Cluster; + end record + with Volatile; + + for PWM_Peripheral use record + TASKS_STOP at 16#4# range 0 .. 31; + TASKS_SEQSTART at 16#8# range 0 .. 63; + TASKS_NEXTSTEP at 16#10# range 0 .. 31; + EVENTS_STOPPED at 16#104# range 0 .. 31; + EVENTS_SEQSTARTED at 16#108# range 0 .. 63; + EVENTS_SEQEND at 16#110# range 0 .. 63; + EVENTS_PWMPERIODEND at 16#118# range 0 .. 31; + EVENTS_LOOPSDONE at 16#11C# range 0 .. 31; + SHORTS at 16#200# range 0 .. 31; + INTEN at 16#300# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + ENABLE at 16#500# range 0 .. 31; + MODE at 16#504# range 0 .. 31; + COUNTERTOP at 16#508# range 0 .. 31; + PRESCALER at 16#50C# range 0 .. 31; + DECODER at 16#510# range 0 .. 31; + LOOP_k at 16#514# range 0 .. 31; + SEQ at 16#520# range 0 .. 255; + PSEL at 16#560# range 0 .. 127; + end record; + + -- Pulse Width Modulation Unit 0 + PWM0_Periph : aliased PWM_Peripheral + with Import, Address => PWM0_Base; + + -- Pulse Width Modulation Unit 1 + PWM1_Periph : aliased PWM_Peripheral + with Import, Address => PWM1_Base; + + -- Pulse Width Modulation Unit 2 + PWM2_Periph : aliased PWM_Peripheral + with Import, Address => PWM2_Base; + +end NRF_SVD.PWM; diff --git a/arch/ARM/Nordic/svd/nrf52/nrf_svd-qdec.ads b/arch/ARM/Nordic/svd/nrf52/nrf_svd-qdec.ads new file mode 100644 index 000000000..30b071e5f --- /dev/null +++ b/arch/ARM/Nordic/svd/nrf52/nrf_svd-qdec.ads @@ -0,0 +1,895 @@ +-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- 2. Redistributions in binary form, except as embedded into a Nordic +-- Semiconductor ASA integrated circuit in a product or a software update for +-- such product, must reproduce the above copyright notice, this list of +-- conditions and the following disclaimer in the documentation and/or other +-- materials provided with the distribution. +-- +-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from this +-- software without specific prior written permission. +-- +-- 4. This software, with or without modification, must only be used with a +-- Nordic Semiconductor ASA integrated circuit. +-- +-- 5. Any software provided in binary form under this license must not be reverse +-- engineered, decompiled, modified and/or disassembled. +-- +-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +-- OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + +-- This spec has been automatically generated from nrf52.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package NRF_SVD.QDEC is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Shortcut between REPORTRDY event and READCLRACC task + type SHORTS_REPORTRDY_READCLRACC_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_REPORTRDY_READCLRACC_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut between SAMPLERDY event and STOP task + type SHORTS_SAMPLERDY_STOP_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_SAMPLERDY_STOP_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut between REPORTRDY event and RDCLRACC task + type SHORTS_REPORTRDY_RDCLRACC_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_REPORTRDY_RDCLRACC_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut between REPORTRDY event and STOP task + type SHORTS_REPORTRDY_STOP_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_REPORTRDY_STOP_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut between DBLRDY event and RDCLRDBL task + type SHORTS_DBLRDY_RDCLRDBL_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_DBLRDY_RDCLRDBL_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut between DBLRDY event and STOP task + type SHORTS_DBLRDY_STOP_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_DBLRDY_STOP_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut between SAMPLERDY event and READCLRACC task + type SHORTS_SAMPLERDY_READCLRACC_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_SAMPLERDY_READCLRACC_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut register + type SHORTS_Register is record + -- Shortcut between REPORTRDY event and READCLRACC task + REPORTRDY_READCLRACC : SHORTS_REPORTRDY_READCLRACC_Field := + NRF_SVD.QDEC.Disabled; + -- Shortcut between SAMPLERDY event and STOP task + SAMPLERDY_STOP : SHORTS_SAMPLERDY_STOP_Field := + NRF_SVD.QDEC.Disabled; + -- Shortcut between REPORTRDY event and RDCLRACC task + REPORTRDY_RDCLRACC : SHORTS_REPORTRDY_RDCLRACC_Field := + NRF_SVD.QDEC.Disabled; + -- Shortcut between REPORTRDY event and STOP task + REPORTRDY_STOP : SHORTS_REPORTRDY_STOP_Field := + NRF_SVD.QDEC.Disabled; + -- Shortcut between DBLRDY event and RDCLRDBL task + DBLRDY_RDCLRDBL : SHORTS_DBLRDY_RDCLRDBL_Field := + NRF_SVD.QDEC.Disabled; + -- Shortcut between DBLRDY event and STOP task + DBLRDY_STOP : SHORTS_DBLRDY_STOP_Field := + NRF_SVD.QDEC.Disabled; + -- Shortcut between SAMPLERDY event and READCLRACC task + SAMPLERDY_READCLRACC : SHORTS_SAMPLERDY_READCLRACC_Field := + NRF_SVD.QDEC.Disabled; + -- unspecified + Reserved_7_31 : HAL.UInt25 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SHORTS_Register use record + REPORTRDY_READCLRACC at 0 range 0 .. 0; + SAMPLERDY_STOP at 0 range 1 .. 1; + REPORTRDY_RDCLRACC at 0 range 2 .. 2; + REPORTRDY_STOP at 0 range 3 .. 3; + DBLRDY_RDCLRDBL at 0 range 4 .. 4; + DBLRDY_STOP at 0 range 5 .. 5; + SAMPLERDY_READCLRACC at 0 range 6 .. 6; + Reserved_7_31 at 0 range 7 .. 31; + end record; + + -- Write '1' to Enable interrupt for SAMPLERDY event + type INTENSET_SAMPLERDY_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_SAMPLERDY_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for SAMPLERDY event + type INTENSET_SAMPLERDY_Field_1 is + (-- Reset value for the field + Intenset_Samplerdy_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_SAMPLERDY_Field_1 use + (Intenset_Samplerdy_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for REPORTRDY event + type INTENSET_REPORTRDY_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_REPORTRDY_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for REPORTRDY event + type INTENSET_REPORTRDY_Field_1 is + (-- Reset value for the field + Intenset_Reportrdy_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_REPORTRDY_Field_1 use + (Intenset_Reportrdy_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for ACCOF event + type INTENSET_ACCOF_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_ACCOF_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for ACCOF event + type INTENSET_ACCOF_Field_1 is + (-- Reset value for the field + Intenset_Accof_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_ACCOF_Field_1 use + (Intenset_Accof_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for DBLRDY event + type INTENSET_DBLRDY_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_DBLRDY_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for DBLRDY event + type INTENSET_DBLRDY_Field_1 is + (-- Reset value for the field + Intenset_Dblrdy_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_DBLRDY_Field_1 use + (Intenset_Dblrdy_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for STOPPED event + type INTENSET_STOPPED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_STOPPED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for STOPPED event + type INTENSET_STOPPED_Field_1 is + (-- Reset value for the field + Intenset_Stopped_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_STOPPED_Field_1 use + (Intenset_Stopped_Field_Reset => 0, + Set => 1); + + -- Enable interrupt + type INTENSET_Register is record + -- Write '1' to Enable interrupt for SAMPLERDY event + SAMPLERDY : INTENSET_SAMPLERDY_Field_1 := + Intenset_Samplerdy_Field_Reset; + -- Write '1' to Enable interrupt for REPORTRDY event + REPORTRDY : INTENSET_REPORTRDY_Field_1 := + Intenset_Reportrdy_Field_Reset; + -- Write '1' to Enable interrupt for ACCOF event + ACCOF : INTENSET_ACCOF_Field_1 := Intenset_Accof_Field_Reset; + -- Write '1' to Enable interrupt for DBLRDY event + DBLRDY : INTENSET_DBLRDY_Field_1 := Intenset_Dblrdy_Field_Reset; + -- Write '1' to Enable interrupt for STOPPED event + STOPPED : INTENSET_STOPPED_Field_1 := + Intenset_Stopped_Field_Reset; + -- unspecified + Reserved_5_31 : HAL.UInt27 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENSET_Register use record + SAMPLERDY at 0 range 0 .. 0; + REPORTRDY at 0 range 1 .. 1; + ACCOF at 0 range 2 .. 2; + DBLRDY at 0 range 3 .. 3; + STOPPED at 0 range 4 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + -- Write '1' to Disable interrupt for SAMPLERDY event + type INTENCLR_SAMPLERDY_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_SAMPLERDY_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for SAMPLERDY event + type INTENCLR_SAMPLERDY_Field_1 is + (-- Reset value for the field + Intenclr_Samplerdy_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_SAMPLERDY_Field_1 use + (Intenclr_Samplerdy_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for REPORTRDY event + type INTENCLR_REPORTRDY_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_REPORTRDY_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for REPORTRDY event + type INTENCLR_REPORTRDY_Field_1 is + (-- Reset value for the field + Intenclr_Reportrdy_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_REPORTRDY_Field_1 use + (Intenclr_Reportrdy_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for ACCOF event + type INTENCLR_ACCOF_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_ACCOF_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for ACCOF event + type INTENCLR_ACCOF_Field_1 is + (-- Reset value for the field + Intenclr_Accof_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_ACCOF_Field_1 use + (Intenclr_Accof_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for DBLRDY event + type INTENCLR_DBLRDY_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_DBLRDY_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for DBLRDY event + type INTENCLR_DBLRDY_Field_1 is + (-- Reset value for the field + Intenclr_Dblrdy_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_DBLRDY_Field_1 use + (Intenclr_Dblrdy_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for STOPPED event + type INTENCLR_STOPPED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_STOPPED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for STOPPED event + type INTENCLR_STOPPED_Field_1 is + (-- Reset value for the field + Intenclr_Stopped_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_STOPPED_Field_1 use + (Intenclr_Stopped_Field_Reset => 0, + Clear => 1); + + -- Disable interrupt + type INTENCLR_Register is record + -- Write '1' to Disable interrupt for SAMPLERDY event + SAMPLERDY : INTENCLR_SAMPLERDY_Field_1 := + Intenclr_Samplerdy_Field_Reset; + -- Write '1' to Disable interrupt for REPORTRDY event + REPORTRDY : INTENCLR_REPORTRDY_Field_1 := + Intenclr_Reportrdy_Field_Reset; + -- Write '1' to Disable interrupt for ACCOF event + ACCOF : INTENCLR_ACCOF_Field_1 := Intenclr_Accof_Field_Reset; + -- Write '1' to Disable interrupt for DBLRDY event + DBLRDY : INTENCLR_DBLRDY_Field_1 := Intenclr_Dblrdy_Field_Reset; + -- Write '1' to Disable interrupt for STOPPED event + STOPPED : INTENCLR_STOPPED_Field_1 := + Intenclr_Stopped_Field_Reset; + -- unspecified + Reserved_5_31 : HAL.UInt27 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENCLR_Register use record + SAMPLERDY at 0 range 0 .. 0; + REPORTRDY at 0 range 1 .. 1; + ACCOF at 0 range 2 .. 2; + DBLRDY at 0 range 3 .. 3; + STOPPED at 0 range 4 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + -- Enable or disable the quadrature decoder + type ENABLE_ENABLE_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for ENABLE_ENABLE_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable the quadrature decoder + type ENABLE_Register is record + -- Enable or disable the quadrature decoder + ENABLE : ENABLE_ENABLE_Field := NRF_SVD.QDEC.Disabled; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ENABLE_Register use record + ENABLE at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- LED output pin polarity + type LEDPOL_LEDPOL_Field is + (-- Led active on output pin low + Activelow, + -- Led active on output pin high + Activehigh) + with Size => 1; + for LEDPOL_LEDPOL_Field use + (Activelow => 0, + Activehigh => 1); + + -- LED output pin polarity + type LEDPOL_Register is record + -- LED output pin polarity + LEDPOL : LEDPOL_LEDPOL_Field := NRF_SVD.QDEC.Activelow; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for LEDPOL_Register use record + LEDPOL at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Sample period. The SAMPLE register will be updated for every new sample + type SAMPLEPER_SAMPLEPER_Field is + (-- 128 us + Val_128US, + -- 256 us + Val_256US, + -- 512 us + Val_512US, + -- 1024 us + Val_1024US, + -- 2048 us + Val_2048US, + -- 4096 us + Val_4096US, + -- 8192 us + Val_8192US, + -- 16384 us + Val_16384US, + -- 32768 us + Val_32MS, + -- 65536 us + Val_65MS, + -- 131072 us + Val_131MS) + with Size => 4; + for SAMPLEPER_SAMPLEPER_Field use + (Val_128US => 0, + Val_256US => 1, + Val_512US => 2, + Val_1024US => 3, + Val_2048US => 4, + Val_4096US => 5, + Val_8192US => 6, + Val_16384US => 7, + Val_32MS => 8, + Val_65MS => 9, + Val_131MS => 10); + + -- Sample period + type SAMPLEPER_Register is record + -- Sample period. The SAMPLE register will be updated for every new + -- sample + SAMPLEPER : SAMPLEPER_SAMPLEPER_Field := NRF_SVD.QDEC.Val_128US; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SAMPLEPER_Register use record + SAMPLEPER at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- Specifies the number of samples to be accumulated in the ACC register + -- before the REPORTRDY and DBLRDY events can be generated + type REPORTPER_REPORTPER_Field is + (-- 10 samples / report + Val_10Smpl, + -- 40 samples / report + Val_40Smpl, + -- 80 samples / report + Val_80Smpl, + -- 120 samples / report + Val_120Smpl, + -- 160 samples / report + Val_160Smpl, + -- 200 samples / report + Val_200Smpl, + -- 240 samples / report + Val_240Smpl, + -- 280 samples / report + Val_280Smpl, + -- 1 sample / report + Val_1Smpl) + with Size => 4; + for REPORTPER_REPORTPER_Field use + (Val_10Smpl => 0, + Val_40Smpl => 1, + Val_80Smpl => 2, + Val_120Smpl => 3, + Val_160Smpl => 4, + Val_200Smpl => 5, + Val_240Smpl => 6, + Val_280Smpl => 7, + Val_1Smpl => 8); + + -- Number of samples to be taken before REPORTRDY and DBLRDY events can be + -- generated + type REPORTPER_Register is record + -- Specifies the number of samples to be accumulated in the ACC register + -- before the REPORTRDY and DBLRDY events can be generated + REPORTPER : REPORTPER_REPORTPER_Field := NRF_SVD.QDEC.Val_10Smpl; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for REPORTPER_Register use record + REPORTPER at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + ------------------------------ + -- PSEL cluster's Registers -- + ------------------------------ + + subtype LED_PSEL_PIN_Field is HAL.UInt5; + + -- Connection + type LED_CONNECT_Field is + (-- Connect + Connected, + -- Disconnect + Disconnected) + with Size => 1; + for LED_CONNECT_Field use + (Connected => 0, + Disconnected => 1); + + -- Pin select for LED signal + type LED_PSEL_Register is record + -- Pin number + PIN : LED_PSEL_PIN_Field := 16#1F#; + -- unspecified + Reserved_5_30 : HAL.UInt26 := 16#3FFFFFF#; + -- Connection + CONNECT : LED_CONNECT_Field := NRF_SVD.QDEC.Disconnected; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for LED_PSEL_Register use record + PIN at 0 range 0 .. 4; + Reserved_5_30 at 0 range 5 .. 30; + CONNECT at 0 range 31 .. 31; + end record; + + subtype A_PSEL_PIN_Field is HAL.UInt5; + + -- Connection + type A_CONNECT_Field is + (-- Connect + Connected, + -- Disconnect + Disconnected) + with Size => 1; + for A_CONNECT_Field use + (Connected => 0, + Disconnected => 1); + + -- Pin select for A signal + type A_PSEL_Register is record + -- Pin number + PIN : A_PSEL_PIN_Field := 16#1F#; + -- unspecified + Reserved_5_30 : HAL.UInt26 := 16#3FFFFFF#; + -- Connection + CONNECT : A_CONNECT_Field := NRF_SVD.QDEC.Disconnected; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for A_PSEL_Register use record + PIN at 0 range 0 .. 4; + Reserved_5_30 at 0 range 5 .. 30; + CONNECT at 0 range 31 .. 31; + end record; + + subtype B_PSEL_PIN_Field is HAL.UInt5; + + -- Connection + type B_CONNECT_Field is + (-- Connect + Connected, + -- Disconnect + Disconnected) + with Size => 1; + for B_CONNECT_Field use + (Connected => 0, + Disconnected => 1); + + -- Pin select for B signal + type B_PSEL_Register is record + -- Pin number + PIN : B_PSEL_PIN_Field := 16#1F#; + -- unspecified + Reserved_5_30 : HAL.UInt26 := 16#3FFFFFF#; + -- Connection + CONNECT : B_CONNECT_Field := NRF_SVD.QDEC.Disconnected; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for B_PSEL_Register use record + PIN at 0 range 0 .. 4; + Reserved_5_30 at 0 range 5 .. 30; + CONNECT at 0 range 31 .. 31; + end record; + + -- Unspecified + type PSEL_Cluster is record + -- Pin select for LED signal + LED : aliased LED_PSEL_Register; + -- Pin select for A signal + A : aliased A_PSEL_Register; + -- Pin select for B signal + B : aliased B_PSEL_Register; + end record + with Size => 96; + + for PSEL_Cluster use record + LED at 16#0# range 0 .. 31; + A at 16#4# range 0 .. 31; + B at 16#8# range 0 .. 31; + end record; + + -- Enable input debounce filters + type DBFEN_DBFEN_Field is + (-- Debounce input filters disabled + Disabled, + -- Debounce input filters enabled + Enabled) + with Size => 1; + for DBFEN_DBFEN_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable input debounce filters + type DBFEN_Register is record + -- Enable input debounce filters + DBFEN : DBFEN_DBFEN_Field := NRF_SVD.QDEC.Disabled; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DBFEN_Register use record + DBFEN at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + subtype LEDPRE_LEDPRE_Field is HAL.UInt9; + + -- Time period the LED is switched ON prior to sampling + type LEDPRE_Register is record + -- Period in us the LED is switched on prior to sampling + LEDPRE : LEDPRE_LEDPRE_Field := 16#10#; + -- unspecified + Reserved_9_31 : HAL.UInt23 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for LEDPRE_Register use record + LEDPRE at 0 range 0 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + subtype ACCDBL_ACCDBL_Field is HAL.UInt4; + + -- Register accumulating the number of detected double transitions + type ACCDBL_Register is record + -- Read-only. Register accumulating the number of detected double or + -- illegal transitions. ( SAMPLE = 2 ). + ACCDBL : ACCDBL_ACCDBL_Field; + -- unspecified + Reserved_4_31 : HAL.UInt28; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ACCDBL_Register use record + ACCDBL at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + subtype ACCDBLREAD_ACCDBLREAD_Field is HAL.UInt4; + + -- Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task + type ACCDBLREAD_Register is record + -- Read-only. Snapshot of the ACCDBL register. This field is updated + -- when the READCLRACC or RDCLRDBL task is triggered. + ACCDBLREAD : ACCDBLREAD_ACCDBLREAD_Field; + -- unspecified + Reserved_4_31 : HAL.UInt28; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ACCDBLREAD_Register use record + ACCDBLREAD at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Quadrature Decoder + type QDEC_Peripheral is record + -- Task starting the quadrature decoder + TASKS_START : aliased HAL.UInt32; + -- Task stopping the quadrature decoder + TASKS_STOP : aliased HAL.UInt32; + -- Read and clear ACC and ACCDBL + TASKS_READCLRACC : aliased HAL.UInt32; + -- Read and clear ACC + TASKS_RDCLRACC : aliased HAL.UInt32; + -- Read and clear ACCDBL + TASKS_RDCLRDBL : aliased HAL.UInt32; + -- Event being generated for every new sample value written to the + -- SAMPLE register + EVENTS_SAMPLERDY : aliased HAL.UInt32; + -- Non-null report ready + EVENTS_REPORTRDY : aliased HAL.UInt32; + -- ACC or ACCDBL register overflow + EVENTS_ACCOF : aliased HAL.UInt32; + -- Double displacement(s) detected + EVENTS_DBLRDY : aliased HAL.UInt32; + -- QDEC has been stopped + EVENTS_STOPPED : aliased HAL.UInt32; + -- Shortcut register + SHORTS : aliased SHORTS_Register; + -- Enable interrupt + INTENSET : aliased INTENSET_Register; + -- Disable interrupt + INTENCLR : aliased INTENCLR_Register; + -- Enable the quadrature decoder + ENABLE : aliased ENABLE_Register; + -- LED output pin polarity + LEDPOL : aliased LEDPOL_Register; + -- Sample period + SAMPLEPER : aliased SAMPLEPER_Register; + -- Motion sample value + SAMPLE : aliased HAL.UInt32; + -- Number of samples to be taken before REPORTRDY and DBLRDY events can + -- be generated + REPORTPER : aliased REPORTPER_Register; + -- Register accumulating the valid transitions + ACC : aliased HAL.UInt32; + -- Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC + -- task + ACCREAD : aliased HAL.UInt32; + -- Unspecified + PSEL : aliased PSEL_Cluster; + -- Enable input debounce filters + DBFEN : aliased DBFEN_Register; + -- Time period the LED is switched ON prior to sampling + LEDPRE : aliased LEDPRE_Register; + -- Register accumulating the number of detected double transitions + ACCDBL : aliased ACCDBL_Register; + -- Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task + ACCDBLREAD : aliased ACCDBLREAD_Register; + end record + with Volatile; + + for QDEC_Peripheral use record + TASKS_START at 16#0# range 0 .. 31; + TASKS_STOP at 16#4# range 0 .. 31; + TASKS_READCLRACC at 16#8# range 0 .. 31; + TASKS_RDCLRACC at 16#C# range 0 .. 31; + TASKS_RDCLRDBL at 16#10# range 0 .. 31; + EVENTS_SAMPLERDY at 16#100# range 0 .. 31; + EVENTS_REPORTRDY at 16#104# range 0 .. 31; + EVENTS_ACCOF at 16#108# range 0 .. 31; + EVENTS_DBLRDY at 16#10C# range 0 .. 31; + EVENTS_STOPPED at 16#110# range 0 .. 31; + SHORTS at 16#200# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + ENABLE at 16#500# range 0 .. 31; + LEDPOL at 16#504# range 0 .. 31; + SAMPLEPER at 16#508# range 0 .. 31; + SAMPLE at 16#50C# range 0 .. 31; + REPORTPER at 16#510# range 0 .. 31; + ACC at 16#514# range 0 .. 31; + ACCREAD at 16#518# range 0 .. 31; + PSEL at 16#51C# range 0 .. 95; + DBFEN at 16#528# range 0 .. 31; + LEDPRE at 16#540# range 0 .. 31; + ACCDBL at 16#544# range 0 .. 31; + ACCDBLREAD at 16#548# range 0 .. 31; + end record; + + -- Quadrature Decoder + QDEC_Periph : aliased QDEC_Peripheral + with Import, Address => QDEC_Base; + +end NRF_SVD.QDEC; diff --git a/arch/ARM/Nordic/svd/nrf52/nrf_svd-radio.ads b/arch/ARM/Nordic/svd/nrf52/nrf_svd-radio.ads new file mode 100644 index 000000000..bf99ba720 --- /dev/null +++ b/arch/ARM/Nordic/svd/nrf52/nrf_svd-radio.ads @@ -0,0 +1,1771 @@ +-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- 2. Redistributions in binary form, except as embedded into a Nordic +-- Semiconductor ASA integrated circuit in a product or a software update for +-- such product, must reproduce the above copyright notice, this list of +-- conditions and the following disclaimer in the documentation and/or other +-- materials provided with the distribution. +-- +-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from this +-- software without specific prior written permission. +-- +-- 4. This software, with or without modification, must only be used with a +-- Nordic Semiconductor ASA integrated circuit. +-- +-- 5. Any software provided in binary form under this license must not be reverse +-- engineered, decompiled, modified and/or disassembled. +-- +-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +-- OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + +-- This spec has been automatically generated from nrf52.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package NRF_SVD.RADIO is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Shortcut between READY event and START task + type SHORTS_READY_START_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_READY_START_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut between END event and DISABLE task + type SHORTS_END_DISABLE_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_END_DISABLE_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut between DISABLED event and TXEN task + type SHORTS_DISABLED_TXEN_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_DISABLED_TXEN_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut between DISABLED event and RXEN task + type SHORTS_DISABLED_RXEN_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_DISABLED_RXEN_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut between ADDRESS event and RSSISTART task + type SHORTS_ADDRESS_RSSISTART_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_ADDRESS_RSSISTART_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut between END event and START task + type SHORTS_END_START_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_END_START_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut between ADDRESS event and BCSTART task + type SHORTS_ADDRESS_BCSTART_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_ADDRESS_BCSTART_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut between DISABLED event and RSSISTOP task + type SHORTS_DISABLED_RSSISTOP_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_DISABLED_RSSISTOP_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut register + type SHORTS_Register is record + -- Shortcut between READY event and START task + READY_START : SHORTS_READY_START_Field := NRF_SVD.RADIO.Disabled; + -- Shortcut between END event and DISABLE task + END_DISABLE : SHORTS_END_DISABLE_Field := NRF_SVD.RADIO.Disabled; + -- Shortcut between DISABLED event and TXEN task + DISABLED_TXEN : SHORTS_DISABLED_TXEN_Field := + NRF_SVD.RADIO.Disabled; + -- Shortcut between DISABLED event and RXEN task + DISABLED_RXEN : SHORTS_DISABLED_RXEN_Field := + NRF_SVD.RADIO.Disabled; + -- Shortcut between ADDRESS event and RSSISTART task + ADDRESS_RSSISTART : SHORTS_ADDRESS_RSSISTART_Field := + NRF_SVD.RADIO.Disabled; + -- Shortcut between END event and START task + END_START : SHORTS_END_START_Field := NRF_SVD.RADIO.Disabled; + -- Shortcut between ADDRESS event and BCSTART task + ADDRESS_BCSTART : SHORTS_ADDRESS_BCSTART_Field := + NRF_SVD.RADIO.Disabled; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- Shortcut between DISABLED event and RSSISTOP task + DISABLED_RSSISTOP : SHORTS_DISABLED_RSSISTOP_Field := + NRF_SVD.RADIO.Disabled; + -- unspecified + Reserved_9_31 : HAL.UInt23 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SHORTS_Register use record + READY_START at 0 range 0 .. 0; + END_DISABLE at 0 range 1 .. 1; + DISABLED_TXEN at 0 range 2 .. 2; + DISABLED_RXEN at 0 range 3 .. 3; + ADDRESS_RSSISTART at 0 range 4 .. 4; + END_START at 0 range 5 .. 5; + ADDRESS_BCSTART at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + DISABLED_RSSISTOP at 0 range 8 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + -- Write '1' to Enable interrupt for READY event + type INTENSET_READY_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_READY_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for READY event + type INTENSET_READY_Field_1 is + (-- Reset value for the field + Intenset_Ready_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_READY_Field_1 use + (Intenset_Ready_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for ADDRESS event + type INTENSET_ADDRESS_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_ADDRESS_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for ADDRESS event + type INTENSET_ADDRESS_Field_1 is + (-- Reset value for the field + Intenset_Address_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_ADDRESS_Field_1 use + (Intenset_Address_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for PAYLOAD event + type INTENSET_PAYLOAD_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_PAYLOAD_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for PAYLOAD event + type INTENSET_PAYLOAD_Field_1 is + (-- Reset value for the field + Intenset_Payload_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_PAYLOAD_Field_1 use + (Intenset_Payload_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for END event + type INTENSET_END_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_END_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for END event + type INTENSET_END_Field_1 is + (-- Reset value for the field + Intenset_End_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_END_Field_1 use + (Intenset_End_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for DISABLED event + type INTENSET_DISABLED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_DISABLED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for DISABLED event + type INTENSET_DISABLED_Field_1 is + (-- Reset value for the field + Intenset_Disabled_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_DISABLED_Field_1 use + (Intenset_Disabled_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for DEVMATCH event + type INTENSET_DEVMATCH_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_DEVMATCH_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for DEVMATCH event + type INTENSET_DEVMATCH_Field_1 is + (-- Reset value for the field + Intenset_Devmatch_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_DEVMATCH_Field_1 use + (Intenset_Devmatch_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for DEVMISS event + type INTENSET_DEVMISS_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_DEVMISS_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for DEVMISS event + type INTENSET_DEVMISS_Field_1 is + (-- Reset value for the field + Intenset_Devmiss_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_DEVMISS_Field_1 use + (Intenset_Devmiss_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for RSSIEND event + type INTENSET_RSSIEND_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_RSSIEND_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for RSSIEND event + type INTENSET_RSSIEND_Field_1 is + (-- Reset value for the field + Intenset_Rssiend_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_RSSIEND_Field_1 use + (Intenset_Rssiend_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for BCMATCH event + type INTENSET_BCMATCH_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_BCMATCH_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for BCMATCH event + type INTENSET_BCMATCH_Field_1 is + (-- Reset value for the field + Intenset_Bcmatch_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_BCMATCH_Field_1 use + (Intenset_Bcmatch_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for CRCOK event + type INTENSET_CRCOK_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_CRCOK_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for CRCOK event + type INTENSET_CRCOK_Field_1 is + (-- Reset value for the field + Intenset_Crcok_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_CRCOK_Field_1 use + (Intenset_Crcok_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for CRCERROR event + type INTENSET_CRCERROR_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_CRCERROR_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for CRCERROR event + type INTENSET_CRCERROR_Field_1 is + (-- Reset value for the field + Intenset_Crcerror_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_CRCERROR_Field_1 use + (Intenset_Crcerror_Field_Reset => 0, + Set => 1); + + -- Enable interrupt + type INTENSET_Register is record + -- Write '1' to Enable interrupt for READY event + READY : INTENSET_READY_Field_1 := Intenset_Ready_Field_Reset; + -- Write '1' to Enable interrupt for ADDRESS event + ADDRESS : INTENSET_ADDRESS_Field_1 := + Intenset_Address_Field_Reset; + -- Write '1' to Enable interrupt for PAYLOAD event + PAYLOAD : INTENSET_PAYLOAD_Field_1 := + Intenset_Payload_Field_Reset; + -- Write '1' to Enable interrupt for END event + END_k : INTENSET_END_Field_1 := Intenset_End_Field_Reset; + -- Write '1' to Enable interrupt for DISABLED event + DISABLED : INTENSET_DISABLED_Field_1 := + Intenset_Disabled_Field_Reset; + -- Write '1' to Enable interrupt for DEVMATCH event + DEVMATCH : INTENSET_DEVMATCH_Field_1 := + Intenset_Devmatch_Field_Reset; + -- Write '1' to Enable interrupt for DEVMISS event + DEVMISS : INTENSET_DEVMISS_Field_1 := + Intenset_Devmiss_Field_Reset; + -- Write '1' to Enable interrupt for RSSIEND event + RSSIEND : INTENSET_RSSIEND_Field_1 := + Intenset_Rssiend_Field_Reset; + -- unspecified + Reserved_8_9 : HAL.UInt2 := 16#0#; + -- Write '1' to Enable interrupt for BCMATCH event + BCMATCH : INTENSET_BCMATCH_Field_1 := + Intenset_Bcmatch_Field_Reset; + -- unspecified + Reserved_11_11 : HAL.Bit := 16#0#; + -- Write '1' to Enable interrupt for CRCOK event + CRCOK : INTENSET_CRCOK_Field_1 := Intenset_Crcok_Field_Reset; + -- Write '1' to Enable interrupt for CRCERROR event + CRCERROR : INTENSET_CRCERROR_Field_1 := + Intenset_Crcerror_Field_Reset; + -- unspecified + Reserved_14_31 : HAL.UInt18 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENSET_Register use record + READY at 0 range 0 .. 0; + ADDRESS at 0 range 1 .. 1; + PAYLOAD at 0 range 2 .. 2; + END_k at 0 range 3 .. 3; + DISABLED at 0 range 4 .. 4; + DEVMATCH at 0 range 5 .. 5; + DEVMISS at 0 range 6 .. 6; + RSSIEND at 0 range 7 .. 7; + Reserved_8_9 at 0 range 8 .. 9; + BCMATCH at 0 range 10 .. 10; + Reserved_11_11 at 0 range 11 .. 11; + CRCOK at 0 range 12 .. 12; + CRCERROR at 0 range 13 .. 13; + Reserved_14_31 at 0 range 14 .. 31; + end record; + + -- Write '1' to Disable interrupt for READY event + type INTENCLR_READY_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_READY_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for READY event + type INTENCLR_READY_Field_1 is + (-- Reset value for the field + Intenclr_Ready_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_READY_Field_1 use + (Intenclr_Ready_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for ADDRESS event + type INTENCLR_ADDRESS_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_ADDRESS_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for ADDRESS event + type INTENCLR_ADDRESS_Field_1 is + (-- Reset value for the field + Intenclr_Address_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_ADDRESS_Field_1 use + (Intenclr_Address_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for PAYLOAD event + type INTENCLR_PAYLOAD_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_PAYLOAD_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for PAYLOAD event + type INTENCLR_PAYLOAD_Field_1 is + (-- Reset value for the field + Intenclr_Payload_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_PAYLOAD_Field_1 use + (Intenclr_Payload_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for END event + type INTENCLR_END_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_END_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for END event + type INTENCLR_END_Field_1 is + (-- Reset value for the field + Intenclr_End_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_END_Field_1 use + (Intenclr_End_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for DISABLED event + type INTENCLR_DISABLED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_DISABLED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for DISABLED event + type INTENCLR_DISABLED_Field_1 is + (-- Reset value for the field + Intenclr_Disabled_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_DISABLED_Field_1 use + (Intenclr_Disabled_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for DEVMATCH event + type INTENCLR_DEVMATCH_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_DEVMATCH_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for DEVMATCH event + type INTENCLR_DEVMATCH_Field_1 is + (-- Reset value for the field + Intenclr_Devmatch_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_DEVMATCH_Field_1 use + (Intenclr_Devmatch_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for DEVMISS event + type INTENCLR_DEVMISS_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_DEVMISS_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for DEVMISS event + type INTENCLR_DEVMISS_Field_1 is + (-- Reset value for the field + Intenclr_Devmiss_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_DEVMISS_Field_1 use + (Intenclr_Devmiss_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for RSSIEND event + type INTENCLR_RSSIEND_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_RSSIEND_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for RSSIEND event + type INTENCLR_RSSIEND_Field_1 is + (-- Reset value for the field + Intenclr_Rssiend_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_RSSIEND_Field_1 use + (Intenclr_Rssiend_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for BCMATCH event + type INTENCLR_BCMATCH_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_BCMATCH_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for BCMATCH event + type INTENCLR_BCMATCH_Field_1 is + (-- Reset value for the field + Intenclr_Bcmatch_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_BCMATCH_Field_1 use + (Intenclr_Bcmatch_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for CRCOK event + type INTENCLR_CRCOK_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_CRCOK_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for CRCOK event + type INTENCLR_CRCOK_Field_1 is + (-- Reset value for the field + Intenclr_Crcok_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_CRCOK_Field_1 use + (Intenclr_Crcok_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for CRCERROR event + type INTENCLR_CRCERROR_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_CRCERROR_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for CRCERROR event + type INTENCLR_CRCERROR_Field_1 is + (-- Reset value for the field + Intenclr_Crcerror_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_CRCERROR_Field_1 use + (Intenclr_Crcerror_Field_Reset => 0, + Clear => 1); + + -- Disable interrupt + type INTENCLR_Register is record + -- Write '1' to Disable interrupt for READY event + READY : INTENCLR_READY_Field_1 := Intenclr_Ready_Field_Reset; + -- Write '1' to Disable interrupt for ADDRESS event + ADDRESS : INTENCLR_ADDRESS_Field_1 := + Intenclr_Address_Field_Reset; + -- Write '1' to Disable interrupt for PAYLOAD event + PAYLOAD : INTENCLR_PAYLOAD_Field_1 := + Intenclr_Payload_Field_Reset; + -- Write '1' to Disable interrupt for END event + END_k : INTENCLR_END_Field_1 := Intenclr_End_Field_Reset; + -- Write '1' to Disable interrupt for DISABLED event + DISABLED : INTENCLR_DISABLED_Field_1 := + Intenclr_Disabled_Field_Reset; + -- Write '1' to Disable interrupt for DEVMATCH event + DEVMATCH : INTENCLR_DEVMATCH_Field_1 := + Intenclr_Devmatch_Field_Reset; + -- Write '1' to Disable interrupt for DEVMISS event + DEVMISS : INTENCLR_DEVMISS_Field_1 := + Intenclr_Devmiss_Field_Reset; + -- Write '1' to Disable interrupt for RSSIEND event + RSSIEND : INTENCLR_RSSIEND_Field_1 := + Intenclr_Rssiend_Field_Reset; + -- unspecified + Reserved_8_9 : HAL.UInt2 := 16#0#; + -- Write '1' to Disable interrupt for BCMATCH event + BCMATCH : INTENCLR_BCMATCH_Field_1 := + Intenclr_Bcmatch_Field_Reset; + -- unspecified + Reserved_11_11 : HAL.Bit := 16#0#; + -- Write '1' to Disable interrupt for CRCOK event + CRCOK : INTENCLR_CRCOK_Field_1 := Intenclr_Crcok_Field_Reset; + -- Write '1' to Disable interrupt for CRCERROR event + CRCERROR : INTENCLR_CRCERROR_Field_1 := + Intenclr_Crcerror_Field_Reset; + -- unspecified + Reserved_14_31 : HAL.UInt18 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENCLR_Register use record + READY at 0 range 0 .. 0; + ADDRESS at 0 range 1 .. 1; + PAYLOAD at 0 range 2 .. 2; + END_k at 0 range 3 .. 3; + DISABLED at 0 range 4 .. 4; + DEVMATCH at 0 range 5 .. 5; + DEVMISS at 0 range 6 .. 6; + RSSIEND at 0 range 7 .. 7; + Reserved_8_9 at 0 range 8 .. 9; + BCMATCH at 0 range 10 .. 10; + Reserved_11_11 at 0 range 11 .. 11; + CRCOK at 0 range 12 .. 12; + CRCERROR at 0 range 13 .. 13; + Reserved_14_31 at 0 range 14 .. 31; + end record; + + -- CRC status of packet received + type CRCSTATUS_CRCSTATUS_Field is + (-- Packet received with CRC error + Crcerror, + -- Packet received with CRC ok + Crcok) + with Size => 1; + for CRCSTATUS_CRCSTATUS_Field use + (Crcerror => 0, + Crcok => 1); + + -- CRC status + type CRCSTATUS_Register is record + -- Read-only. CRC status of packet received + CRCSTATUS : CRCSTATUS_CRCSTATUS_Field; + -- unspecified + Reserved_1_31 : HAL.UInt31; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CRCSTATUS_Register use record + CRCSTATUS at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + subtype RXMATCH_RXMATCH_Field is HAL.UInt3; + + -- Received address + type RXMATCH_Register is record + -- Read-only. Received address + RXMATCH : RXMATCH_RXMATCH_Field; + -- unspecified + Reserved_3_31 : HAL.UInt29; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RXMATCH_Register use record + RXMATCH at 0 range 0 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + subtype RXCRC_RXCRC_Field is HAL.UInt24; + + -- CRC field of previously received packet + type RXCRC_Register is record + -- Read-only. CRC field of previously received packet + RXCRC : RXCRC_RXCRC_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RXCRC_Register use record + RXCRC at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype DAI_DAI_Field is HAL.UInt3; + + -- Device address match index + type DAI_Register is record + -- Read-only. Device address match index + DAI : DAI_DAI_Field; + -- unspecified + Reserved_3_31 : HAL.UInt29; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DAI_Register use record + DAI at 0 range 0 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + subtype FREQUENCY_FREQUENCY_Field is HAL.UInt7; + + -- Channel map selection. + type FREQUENCY_MAP_Field is + (-- Channel map between 2400 MHZ .. 2500 MHz + Default, + -- Channel map between 2360 MHZ .. 2460 MHz + Low) + with Size => 1; + for FREQUENCY_MAP_Field use + (Default => 0, + Low => 1); + + -- Frequency + type FREQUENCY_Register is record + -- Radio channel frequency + FREQUENCY : FREQUENCY_FREQUENCY_Field := 16#2#; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- Channel map selection. + MAP : FREQUENCY_MAP_Field := NRF_SVD.RADIO.Default; + -- unspecified + Reserved_9_31 : HAL.UInt23 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FREQUENCY_Register use record + FREQUENCY at 0 range 0 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + MAP at 0 range 8 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + -- RADIO output power. + type TXPOWER_TXPOWER_Field is + (-- 0 dBm + Val_0DBm, + -- +3 dBm + Pos3DBm, + -- +4 dBm + Pos4DBm, + -- -40 dBm + Neg40DBm, + -- -20 dBm + Neg20DBm, + -- -16 dBm + Neg16DBm, + -- -12 dBm + Neg12DBm, + -- -8 dBm + Neg8DBm, + -- -4 dBm + Neg4DBm, + -- Deprecated enumerator - -40 dBm + Neg30DBm) + with Size => 8; + for TXPOWER_TXPOWER_Field use + (Val_0DBm => 0, + Pos3DBm => 3, + Pos4DBm => 4, + Neg40DBm => 216, + Neg20DBm => 236, + Neg16DBm => 240, + Neg12DBm => 244, + Neg8DBm => 248, + Neg4DBm => 252, + Neg30DBm => 255); + + -- Output power + type TXPOWER_Register is record + -- RADIO output power. + TXPOWER : TXPOWER_TXPOWER_Field := NRF_SVD.RADIO.Val_0DBm; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TXPOWER_Register use record + TXPOWER at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- Radio data rate and modulation setting. The radio supports + -- Frequency-shift Keying (FSK) modulation. + type MODE_MODE_Field is + (-- 1 Mbit/s Nordic proprietary radio mode + Nrf_1Mbit, + -- 2 Mbit/s Nordic proprietary radio mode + Nrf_2Mbit, + -- Deprecated enumerator - 250 kbit/s Nordic proprietary radio mode + Nrf_250Kbit, + -- 1 Mbit/s Bluetooth Low Energy + Ble_1Mbit, + -- 2 Mbit/s Bluetooth Low Energy + Ble_2Mbit) + with Size => 4; + for MODE_MODE_Field use + (Nrf_1Mbit => 0, + Nrf_2Mbit => 1, + Nrf_250Kbit => 2, + Ble_1Mbit => 3, + Ble_2Mbit => 4); + + -- Data rate and modulation + type MODE_Register is record + -- Radio data rate and modulation setting. The radio supports + -- Frequency-shift Keying (FSK) modulation. + MODE : MODE_MODE_Field := NRF_SVD.RADIO.Nrf_1Mbit; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MODE_Register use record + MODE at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + subtype PCNF0_LFLEN_Field is HAL.UInt4; + subtype PCNF0_S1LEN_Field is HAL.UInt4; + + -- Include or exclude S1 field in RAM + type PCNF0_S1INCL_Field is + (-- Include S1 field in RAM only if S1LEN > 0 + Automatic, + -- Always include S1 field in RAM independent of S1LEN + Include) + with Size => 1; + for PCNF0_S1INCL_Field use + (Automatic => 0, + Include => 1); + + -- Length of preamble on air. Decision point: TASKS_START task + type PCNF0_PLEN_Field is + (-- 8-bit preamble + Val_8BIT, + -- 16-bit preamble + Val_16BIT) + with Size => 1; + for PCNF0_PLEN_Field use + (Val_8BIT => 0, + Val_16BIT => 1); + + -- Packet configuration register 0 + type PCNF0_Register is record + -- Length on air of LENGTH field in number of bits. + LFLEN : PCNF0_LFLEN_Field := 16#0#; + -- unspecified + Reserved_4_7 : HAL.UInt4 := 16#0#; + -- Length on air of S0 field in number of bytes. + S0LEN : Boolean := False; + -- unspecified + Reserved_9_15 : HAL.UInt7 := 16#0#; + -- Length on air of S1 field in number of bits. + S1LEN : PCNF0_S1LEN_Field := 16#0#; + -- Include or exclude S1 field in RAM + S1INCL : PCNF0_S1INCL_Field := NRF_SVD.RADIO.Automatic; + -- unspecified + Reserved_21_23 : HAL.UInt3 := 16#0#; + -- Length of preamble on air. Decision point: TASKS_START task + PLEN : PCNF0_PLEN_Field := NRF_SVD.RADIO.Val_8BIT; + -- unspecified + Reserved_25_31 : HAL.UInt7 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PCNF0_Register use record + LFLEN at 0 range 0 .. 3; + Reserved_4_7 at 0 range 4 .. 7; + S0LEN at 0 range 8 .. 8; + Reserved_9_15 at 0 range 9 .. 15; + S1LEN at 0 range 16 .. 19; + S1INCL at 0 range 20 .. 20; + Reserved_21_23 at 0 range 21 .. 23; + PLEN at 0 range 24 .. 24; + Reserved_25_31 at 0 range 25 .. 31; + end record; + + subtype PCNF1_MAXLEN_Field is HAL.UInt8; + subtype PCNF1_STATLEN_Field is HAL.UInt8; + subtype PCNF1_BALEN_Field is HAL.UInt3; + + -- On air endianness of packet, this applies to the S0, LENGTH, S1 and the + -- PAYLOAD fields. + type PCNF1_ENDIAN_Field is + (-- Least Significant bit on air first + Little, + -- Most significant bit on air first + Big) + with Size => 1; + for PCNF1_ENDIAN_Field use + (Little => 0, + Big => 1); + + -- Enable or disable packet whitening + type PCNF1_WHITEEN_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for PCNF1_WHITEEN_Field use + (Disabled => 0, + Enabled => 1); + + -- Packet configuration register 1 + type PCNF1_Register is record + -- Maximum length of packet payload. If the packet payload is larger + -- than MAXLEN, the radio will truncate the payload to MAXLEN. + MAXLEN : PCNF1_MAXLEN_Field := 16#0#; + -- Static length in number of bytes + STATLEN : PCNF1_STATLEN_Field := 16#0#; + -- Base address length in number of bytes + BALEN : PCNF1_BALEN_Field := 16#0#; + -- unspecified + Reserved_19_23 : HAL.UInt5 := 16#0#; + -- On air endianness of packet, this applies to the S0, LENGTH, S1 and + -- the PAYLOAD fields. + ENDIAN : PCNF1_ENDIAN_Field := NRF_SVD.RADIO.Little; + -- Enable or disable packet whitening + WHITEEN : PCNF1_WHITEEN_Field := NRF_SVD.RADIO.Disabled; + -- unspecified + Reserved_26_31 : HAL.UInt6 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PCNF1_Register use record + MAXLEN at 0 range 0 .. 7; + STATLEN at 0 range 8 .. 15; + BALEN at 0 range 16 .. 18; + Reserved_19_23 at 0 range 19 .. 23; + ENDIAN at 0 range 24 .. 24; + WHITEEN at 0 range 25 .. 25; + Reserved_26_31 at 0 range 26 .. 31; + end record; + + -- PREFIX0_AP array element + subtype PREFIX0_AP_Element is HAL.UInt8; + + -- PREFIX0_AP array + type PREFIX0_AP_Field_Array is array (0 .. 3) of PREFIX0_AP_Element + with Component_Size => 8, Size => 32; + + -- Prefixes bytes for logical addresses 0-3 + type PREFIX0_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- AP as a value + Val : HAL.UInt32; + when True => + -- AP as an array + Arr : PREFIX0_AP_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PREFIX0_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- PREFIX1_AP array element + subtype PREFIX1_AP_Element is HAL.UInt8; + + -- PREFIX1_AP array + type PREFIX1_AP_Field_Array is array (4 .. 7) of PREFIX1_AP_Element + with Component_Size => 8, Size => 32; + + -- Prefixes bytes for logical addresses 4-7 + type PREFIX1_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- AP as a value + Val : HAL.UInt32; + when True => + -- AP as an array + Arr : PREFIX1_AP_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PREFIX1_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + subtype TXADDRESS_TXADDRESS_Field is HAL.UInt3; + + -- Transmit address select + type TXADDRESS_Register is record + -- Transmit address select + TXADDRESS : TXADDRESS_TXADDRESS_Field := 16#0#; + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TXADDRESS_Register use record + TXADDRESS at 0 range 0 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + -- Enable or disable reception on logical address 0. + type RXADDRESSES_ADDR0_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for RXADDRESSES_ADDR0_Field use + (Disabled => 0, + Enabled => 1); + + -- RXADDRESSES_ADDR array + type RXADDRESSES_ADDR_Field_Array is array (0 .. 7) + of RXADDRESSES_ADDR0_Field + with Component_Size => 1, Size => 8; + + -- Type definition for RXADDRESSES_ADDR + type RXADDRESSES_ADDR_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- ADDR as a value + Val : HAL.UInt8; + when True => + -- ADDR as an array + Arr : RXADDRESSES_ADDR_Field_Array; + end case; + end record + with Unchecked_Union, Size => 8; + + for RXADDRESSES_ADDR_Field use record + Val at 0 range 0 .. 7; + Arr at 0 range 0 .. 7; + end record; + + -- Receive address select + type RXADDRESSES_Register is record + -- Enable or disable reception on logical address 0. + ADDR : RXADDRESSES_ADDR_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RXADDRESSES_Register use record + ADDR at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- CRC length in number of bytes. + type CRCCNF_LEN_Field is + (-- CRC length is zero and CRC calculation is disabled + Disabled, + -- CRC length is one byte and CRC calculation is enabled + One, + -- CRC length is two bytes and CRC calculation is enabled + Two, + -- CRC length is three bytes and CRC calculation is enabled + Three) + with Size => 2; + for CRCCNF_LEN_Field use + (Disabled => 0, + One => 1, + Two => 2, + Three => 3); + + -- Include or exclude packet address field out of CRC calculation. + type CRCCNF_SKIPADDR_Field is + (-- CRC calculation includes address field + Include, + -- CRC calculation does not include address field. The CRC calculation will +-- start at the first byte after the address. + Skip) + with Size => 1; + for CRCCNF_SKIPADDR_Field use + (Include => 0, + Skip => 1); + + -- CRC configuration + type CRCCNF_Register is record + -- CRC length in number of bytes. + LEN : CRCCNF_LEN_Field := NRF_SVD.RADIO.Disabled; + -- unspecified + Reserved_2_7 : HAL.UInt6 := 16#0#; + -- Include or exclude packet address field out of CRC calculation. + SKIPADDR : CRCCNF_SKIPADDR_Field := NRF_SVD.RADIO.Include; + -- unspecified + Reserved_9_31 : HAL.UInt23 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CRCCNF_Register use record + LEN at 0 range 0 .. 1; + Reserved_2_7 at 0 range 2 .. 7; + SKIPADDR at 0 range 8 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + subtype CRCPOLY_CRCPOLY_Field is HAL.UInt24; + + -- CRC polynomial + type CRCPOLY_Register is record + -- CRC polynomial + CRCPOLY : CRCPOLY_CRCPOLY_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CRCPOLY_Register use record + CRCPOLY at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype CRCINIT_CRCINIT_Field is HAL.UInt24; + + -- CRC initial value + type CRCINIT_Register is record + -- CRC initial value + CRCINIT : CRCINIT_CRCINIT_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CRCINIT_Register use record + CRCINIT at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype TIFS_TIFS_Field is HAL.UInt8; + + -- Inter Frame Spacing in us + type TIFS_Register is record + -- Inter Frame Spacing in us + TIFS : TIFS_TIFS_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TIFS_Register use record + TIFS at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype RSSISAMPLE_RSSISAMPLE_Field is HAL.UInt7; + + -- RSSI sample + type RSSISAMPLE_Register is record + -- Read-only. RSSI sample + RSSISAMPLE : RSSISAMPLE_RSSISAMPLE_Field; + -- unspecified + Reserved_7_31 : HAL.UInt25; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RSSISAMPLE_Register use record + RSSISAMPLE at 0 range 0 .. 6; + Reserved_7_31 at 0 range 7 .. 31; + end record; + + -- Current radio state + type STATE_STATE_Field is + (-- RADIO is in the Disabled state + Disabled, + -- RADIO is in the RXRU state + Rxru, + -- RADIO is in the RXIDLE state + Rxidle, + -- RADIO is in the RX state + Rx, + -- RADIO is in the RXDISABLED state + Rxdisable, + -- RADIO is in the TXRU state + Txru, + -- RADIO is in the TXIDLE state + Txidle, + -- RADIO is in the TX state + Tx, + -- RADIO is in the TXDISABLED state + Txdisable) + with Size => 4; + for STATE_STATE_Field use + (Disabled => 0, + Rxru => 1, + Rxidle => 2, + Rx => 3, + Rxdisable => 4, + Txru => 9, + Txidle => 10, + Tx => 11, + Txdisable => 12); + + -- Current radio state + type STATE_Register is record + -- Read-only. Current radio state + STATE : STATE_STATE_Field; + -- unspecified + Reserved_4_31 : HAL.UInt28; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for STATE_Register use record + STATE at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + subtype DATAWHITEIV_DATAWHITEIV_Field is HAL.UInt7; + + -- Data whitening initial value + type DATAWHITEIV_Register is record + -- Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' + -- to it has no effect, and it will always be read back and used by the + -- device as '1'. + DATAWHITEIV : DATAWHITEIV_DATAWHITEIV_Field := 16#40#; + -- unspecified + Reserved_7_31 : HAL.UInt25 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DATAWHITEIV_Register use record + DATAWHITEIV at 0 range 0 .. 6; + Reserved_7_31 at 0 range 7 .. 31; + end record; + + -- Description collection[0]: Device address base segment 0 + + -- Description collection[0]: Device address base segment 0 + type DAB_Registers is array (0 .. 7) of HAL.UInt32; + + subtype DAP_DAP_Field is HAL.UInt16; + + -- Description collection[0]: Device address prefix 0 + type DAP_Register is record + -- Device address prefix 0 + DAP : DAP_DAP_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DAP_Register use record + DAP at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- Description collection[0]: Device address prefix 0 + type DAP_Registers is array (0 .. 7) of DAP_Register; + + -- Enable or disable device address matching using device address 0 + type DACNF_ENA0_Field is + (-- Disabled + Disabled, + -- Enabled + Enabled) + with Size => 1; + for DACNF_ENA0_Field use + (Disabled => 0, + Enabled => 1); + + -- DACNF_ENA array + type DACNF_ENA_Field_Array is array (0 .. 7) of DACNF_ENA0_Field + with Component_Size => 1, Size => 8; + + -- Type definition for DACNF_ENA + type DACNF_ENA_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- ENA as a value + Val : HAL.UInt8; + when True => + -- ENA as an array + Arr : DACNF_ENA_Field_Array; + end case; + end record + with Unchecked_Union, Size => 8; + + for DACNF_ENA_Field use record + Val at 0 range 0 .. 7; + Arr at 0 range 0 .. 7; + end record; + + -- DACNF_TXADD array + type DACNF_TXADD_Field_Array is array (0 .. 7) of Boolean + with Component_Size => 1, Size => 8; + + -- Type definition for DACNF_TXADD + type DACNF_TXADD_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- TXADD as a value + Val : HAL.UInt8; + when True => + -- TXADD as an array + Arr : DACNF_TXADD_Field_Array; + end case; + end record + with Unchecked_Union, Size => 8; + + for DACNF_TXADD_Field use record + Val at 0 range 0 .. 7; + Arr at 0 range 0 .. 7; + end record; + + -- Device address match configuration + type DACNF_Register is record + -- Enable or disable device address matching using device address 0 + ENA : DACNF_ENA_Field := (As_Array => False, Val => 16#0#); + -- TxAdd for device address 0 + TXADD : DACNF_TXADD_Field := (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DACNF_Register use record + ENA at 0 range 0 .. 7; + TXADD at 0 range 8 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- Radio ramp-up time + type MODECNF0_RU_Field is + (-- Default ramp-up time (tRXEN), compatible with firmware written for nRF51 + Default, + -- Fast ramp-up (tRXEN,FAST), see electrical specification for more +-- information + Fast) + with Size => 1; + for MODECNF0_RU_Field use + (Default => 0, + Fast => 1); + + -- Default TX value + type MODECNF0_DTX_Field is + (-- Transmit '1' + B1, + -- Transmit '0' + B0, + -- Transmit center frequency + Center) + with Size => 2; + for MODECNF0_DTX_Field use + (B1 => 0, + B0 => 1, + Center => 2); + + -- Radio mode configuration register 0 + type MODECNF0_Register is record + -- Radio ramp-up time + RU : MODECNF0_RU_Field := NRF_SVD.RADIO.Default; + -- unspecified + Reserved_1_7 : HAL.UInt7 := 16#0#; + -- Default TX value + DTX : MODECNF0_DTX_Field := NRF_SVD.RADIO.Center; + -- unspecified + Reserved_10_31 : HAL.UInt22 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MODECNF0_Register use record + RU at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + DTX at 0 range 8 .. 9; + Reserved_10_31 at 0 range 10 .. 31; + end record; + + -- Peripheral power control. The peripheral and its registers will be reset + -- to its initial state by switching the peripheral off and then back on + -- again. + type POWER_POWER_Field is + (-- Peripheral is powered off + Disabled, + -- Peripheral is powered on + Enabled) + with Size => 1; + for POWER_POWER_Field use + (Disabled => 0, + Enabled => 1); + + -- Peripheral power control + type POWER_Register is record + -- Peripheral power control. The peripheral and its registers will be + -- reset to its initial state by switching the peripheral off and then + -- back on again. + POWER : POWER_POWER_Field := NRF_SVD.RADIO.Enabled; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for POWER_Register use record + POWER at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- 2.4 GHz Radio + type RADIO_Peripheral is record + -- Enable RADIO in TX mode + TASKS_TXEN : aliased HAL.UInt32; + -- Enable RADIO in RX mode + TASKS_RXEN : aliased HAL.UInt32; + -- Start RADIO + TASKS_START : aliased HAL.UInt32; + -- Stop RADIO + TASKS_STOP : aliased HAL.UInt32; + -- Disable RADIO + TASKS_DISABLE : aliased HAL.UInt32; + -- Start the RSSI and take one single sample of the receive signal + -- strength. + TASKS_RSSISTART : aliased HAL.UInt32; + -- Stop the RSSI measurement + TASKS_RSSISTOP : aliased HAL.UInt32; + -- Start the bit counter + TASKS_BCSTART : aliased HAL.UInt32; + -- Stop the bit counter + TASKS_BCSTOP : aliased HAL.UInt32; + -- RADIO has ramped up and is ready to be started + EVENTS_READY : aliased HAL.UInt32; + -- Address sent or received + EVENTS_ADDRESS : aliased HAL.UInt32; + -- Packet payload sent or received + EVENTS_PAYLOAD : aliased HAL.UInt32; + -- Packet sent or received + EVENTS_END : aliased HAL.UInt32; + -- RADIO has been disabled + EVENTS_DISABLED : aliased HAL.UInt32; + -- A device address match occurred on the last received packet + EVENTS_DEVMATCH : aliased HAL.UInt32; + -- No device address match occurred on the last received packet + EVENTS_DEVMISS : aliased HAL.UInt32; + -- Sampling of receive signal strength complete. + EVENTS_RSSIEND : aliased HAL.UInt32; + -- Bit counter reached bit count value. + EVENTS_BCMATCH : aliased HAL.UInt32; + -- Packet received with CRC ok + EVENTS_CRCOK : aliased HAL.UInt32; + -- Packet received with CRC error + EVENTS_CRCERROR : aliased HAL.UInt32; + -- Shortcut register + SHORTS : aliased SHORTS_Register; + -- Enable interrupt + INTENSET : aliased INTENSET_Register; + -- Disable interrupt + INTENCLR : aliased INTENCLR_Register; + -- CRC status + CRCSTATUS : aliased CRCSTATUS_Register; + -- Received address + RXMATCH : aliased RXMATCH_Register; + -- CRC field of previously received packet + RXCRC : aliased RXCRC_Register; + -- Device address match index + DAI : aliased DAI_Register; + -- Packet pointer + PACKETPTR : aliased HAL.UInt32; + -- Frequency + FREQUENCY : aliased FREQUENCY_Register; + -- Output power + TXPOWER : aliased TXPOWER_Register; + -- Data rate and modulation + MODE : aliased MODE_Register; + -- Packet configuration register 0 + PCNF0 : aliased PCNF0_Register; + -- Packet configuration register 1 + PCNF1 : aliased PCNF1_Register; + -- Base address 0 + BASE0 : aliased HAL.UInt32; + -- Base address 1 + BASE1 : aliased HAL.UInt32; + -- Prefixes bytes for logical addresses 0-3 + PREFIX0 : aliased PREFIX0_Register; + -- Prefixes bytes for logical addresses 4-7 + PREFIX1 : aliased PREFIX1_Register; + -- Transmit address select + TXADDRESS : aliased TXADDRESS_Register; + -- Receive address select + RXADDRESSES : aliased RXADDRESSES_Register; + -- CRC configuration + CRCCNF : aliased CRCCNF_Register; + -- CRC polynomial + CRCPOLY : aliased CRCPOLY_Register; + -- CRC initial value + CRCINIT : aliased CRCINIT_Register; + -- Unspecified + UNUSED0 : aliased HAL.UInt32; + -- Inter Frame Spacing in us + TIFS : aliased TIFS_Register; + -- RSSI sample + RSSISAMPLE : aliased RSSISAMPLE_Register; + -- Current radio state + STATE : aliased STATE_Register; + -- Data whitening initial value + DATAWHITEIV : aliased DATAWHITEIV_Register; + -- Bit counter compare + BCC : aliased HAL.UInt32; + -- Description collection[0]: Device address base segment 0 + DAB : aliased DAB_Registers; + -- Description collection[0]: Device address prefix 0 + DAP : aliased DAP_Registers; + -- Device address match configuration + DACNF : aliased DACNF_Register; + -- Radio mode configuration register 0 + MODECNF0 : aliased MODECNF0_Register; + -- Peripheral power control + POWER : aliased POWER_Register; + end record + with Volatile; + + for RADIO_Peripheral use record + TASKS_TXEN at 16#0# range 0 .. 31; + TASKS_RXEN at 16#4# range 0 .. 31; + TASKS_START at 16#8# range 0 .. 31; + TASKS_STOP at 16#C# range 0 .. 31; + TASKS_DISABLE at 16#10# range 0 .. 31; + TASKS_RSSISTART at 16#14# range 0 .. 31; + TASKS_RSSISTOP at 16#18# range 0 .. 31; + TASKS_BCSTART at 16#1C# range 0 .. 31; + TASKS_BCSTOP at 16#20# range 0 .. 31; + EVENTS_READY at 16#100# range 0 .. 31; + EVENTS_ADDRESS at 16#104# range 0 .. 31; + EVENTS_PAYLOAD at 16#108# range 0 .. 31; + EVENTS_END at 16#10C# range 0 .. 31; + EVENTS_DISABLED at 16#110# range 0 .. 31; + EVENTS_DEVMATCH at 16#114# range 0 .. 31; + EVENTS_DEVMISS at 16#118# range 0 .. 31; + EVENTS_RSSIEND at 16#11C# range 0 .. 31; + EVENTS_BCMATCH at 16#128# range 0 .. 31; + EVENTS_CRCOK at 16#130# range 0 .. 31; + EVENTS_CRCERROR at 16#134# range 0 .. 31; + SHORTS at 16#200# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + CRCSTATUS at 16#400# range 0 .. 31; + RXMATCH at 16#408# range 0 .. 31; + RXCRC at 16#40C# range 0 .. 31; + DAI at 16#410# range 0 .. 31; + PACKETPTR at 16#504# range 0 .. 31; + FREQUENCY at 16#508# range 0 .. 31; + TXPOWER at 16#50C# range 0 .. 31; + MODE at 16#510# range 0 .. 31; + PCNF0 at 16#514# range 0 .. 31; + PCNF1 at 16#518# range 0 .. 31; + BASE0 at 16#51C# range 0 .. 31; + BASE1 at 16#520# range 0 .. 31; + PREFIX0 at 16#524# range 0 .. 31; + PREFIX1 at 16#528# range 0 .. 31; + TXADDRESS at 16#52C# range 0 .. 31; + RXADDRESSES at 16#530# range 0 .. 31; + CRCCNF at 16#534# range 0 .. 31; + CRCPOLY at 16#538# range 0 .. 31; + CRCINIT at 16#53C# range 0 .. 31; + UNUSED0 at 16#540# range 0 .. 31; + TIFS at 16#544# range 0 .. 31; + RSSISAMPLE at 16#548# range 0 .. 31; + STATE at 16#550# range 0 .. 31; + DATAWHITEIV at 16#554# range 0 .. 31; + BCC at 16#560# range 0 .. 31; + DAB at 16#600# range 0 .. 255; + DAP at 16#620# range 0 .. 255; + DACNF at 16#640# range 0 .. 31; + MODECNF0 at 16#650# range 0 .. 31; + POWER at 16#FFC# range 0 .. 31; + end record; + + -- 2.4 GHz Radio + RADIO_Periph : aliased RADIO_Peripheral + with Import, Address => RADIO_Base; + +end NRF_SVD.RADIO; diff --git a/arch/ARM/Nordic/svd/nrf52/nrf_svd-rng.ads b/arch/ARM/Nordic/svd/nrf52/nrf_svd-rng.ads new file mode 100644 index 000000000..4edf75937 --- /dev/null +++ b/arch/ARM/Nordic/svd/nrf52/nrf_svd-rng.ads @@ -0,0 +1,239 @@ +-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- 2. Redistributions in binary form, except as embedded into a Nordic +-- Semiconductor ASA integrated circuit in a product or a software update for +-- such product, must reproduce the above copyright notice, this list of +-- conditions and the following disclaimer in the documentation and/or other +-- materials provided with the distribution. +-- +-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from this +-- software without specific prior written permission. +-- +-- 4. This software, with or without modification, must only be used with a +-- Nordic Semiconductor ASA integrated circuit. +-- +-- 5. Any software provided in binary form under this license must not be reverse +-- engineered, decompiled, modified and/or disassembled. +-- +-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +-- OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + +-- This spec has been automatically generated from nrf52.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package NRF_SVD.RNG is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Shortcut between VALRDY event and STOP task + type SHORTS_VALRDY_STOP_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_VALRDY_STOP_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut register + type SHORTS_Register is record + -- Shortcut between VALRDY event and STOP task + VALRDY_STOP : SHORTS_VALRDY_STOP_Field := NRF_SVD.RNG.Disabled; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SHORTS_Register use record + VALRDY_STOP at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Write '1' to Enable interrupt for VALRDY event + type INTENSET_VALRDY_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_VALRDY_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for VALRDY event + type INTENSET_VALRDY_Field_1 is + (-- Reset value for the field + Intenset_Valrdy_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_VALRDY_Field_1 use + (Intenset_Valrdy_Field_Reset => 0, + Set => 1); + + -- Enable interrupt + type INTENSET_Register is record + -- Write '1' to Enable interrupt for VALRDY event + VALRDY : INTENSET_VALRDY_Field_1 := Intenset_Valrdy_Field_Reset; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENSET_Register use record + VALRDY at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Write '1' to Disable interrupt for VALRDY event + type INTENCLR_VALRDY_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_VALRDY_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for VALRDY event + type INTENCLR_VALRDY_Field_1 is + (-- Reset value for the field + Intenclr_Valrdy_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_VALRDY_Field_1 use + (Intenclr_Valrdy_Field_Reset => 0, + Clear => 1); + + -- Disable interrupt + type INTENCLR_Register is record + -- Write '1' to Disable interrupt for VALRDY event + VALRDY : INTENCLR_VALRDY_Field_1 := Intenclr_Valrdy_Field_Reset; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENCLR_Register use record + VALRDY at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Bias correction + type CONFIG_DERCEN_Field is + (-- Disabled + Disabled, + -- Enabled + Enabled) + with Size => 1; + for CONFIG_DERCEN_Field use + (Disabled => 0, + Enabled => 1); + + -- Configuration register + type CONFIG_Register is record + -- Bias correction + DERCEN : CONFIG_DERCEN_Field := NRF_SVD.RNG.Disabled; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CONFIG_Register use record + DERCEN at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + subtype VALUE_VALUE_Field is HAL.UInt8; + + -- Output random number + type VALUE_Register is record + -- Read-only. Generated random number + VALUE : VALUE_VALUE_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for VALUE_Register use record + VALUE at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Random Number Generator + type RNG_Peripheral is record + -- Task starting the random number generator + TASKS_START : aliased HAL.UInt32; + -- Task stopping the random number generator + TASKS_STOP : aliased HAL.UInt32; + -- Event being generated for every new random number written to the + -- VALUE register + EVENTS_VALRDY : aliased HAL.UInt32; + -- Shortcut register + SHORTS : aliased SHORTS_Register; + -- Enable interrupt + INTENSET : aliased INTENSET_Register; + -- Disable interrupt + INTENCLR : aliased INTENCLR_Register; + -- Configuration register + CONFIG : aliased CONFIG_Register; + -- Output random number + VALUE : aliased VALUE_Register; + end record + with Volatile; + + for RNG_Peripheral use record + TASKS_START at 16#0# range 0 .. 31; + TASKS_STOP at 16#4# range 0 .. 31; + EVENTS_VALRDY at 16#100# range 0 .. 31; + SHORTS at 16#200# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + CONFIG at 16#504# range 0 .. 31; + VALUE at 16#508# range 0 .. 31; + end record; + + -- Random Number Generator + RNG_Periph : aliased RNG_Peripheral + with Import, Address => RNG_Base; + +end NRF_SVD.RNG; diff --git a/arch/ARM/Nordic/svd/nrf52/nrf_svd-rtc.ads b/arch/ARM/Nordic/svd/nrf52/nrf_svd-rtc.ads new file mode 100644 index 000000000..530631e39 --- /dev/null +++ b/arch/ARM/Nordic/svd/nrf52/nrf_svd-rtc.ads @@ -0,0 +1,731 @@ +-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- 2. Redistributions in binary form, except as embedded into a Nordic +-- Semiconductor ASA integrated circuit in a product or a software update for +-- such product, must reproduce the above copyright notice, this list of +-- conditions and the following disclaimer in the documentation and/or other +-- materials provided with the distribution. +-- +-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from this +-- software without specific prior written permission. +-- +-- 4. This software, with or without modification, must only be used with a +-- Nordic Semiconductor ASA integrated circuit. +-- +-- 5. Any software provided in binary form under this license must not be reverse +-- engineered, decompiled, modified and/or disassembled. +-- +-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +-- OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + +-- This spec has been automatically generated from nrf52.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package NRF_SVD.RTC is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Description collection[0]: Compare event on CC[0] match + + -- Description collection[0]: Compare event on CC[0] match + type EVENTS_COMPARE_Registers is array (0 .. 3) of HAL.UInt32; + + -- Write '1' to Enable interrupt for TICK event + type INTENSET_TICK_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_TICK_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for TICK event + type INTENSET_TICK_Field_1 is + (-- Reset value for the field + Intenset_Tick_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_TICK_Field_1 use + (Intenset_Tick_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for OVRFLW event + type INTENSET_OVRFLW_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_OVRFLW_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for OVRFLW event + type INTENSET_OVRFLW_Field_1 is + (-- Reset value for the field + Intenset_Ovrflw_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_OVRFLW_Field_1 use + (Intenset_Ovrflw_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for COMPARE[0] event + type INTENSET_COMPARE0_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_COMPARE0_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for COMPARE[0] event + type INTENSET_COMPARE0_Field_1 is + (-- Reset value for the field + Intenset_Compare0_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_COMPARE0_Field_1 use + (Intenset_Compare0_Field_Reset => 0, + Set => 1); + + -- INTENSET_COMPARE array + type INTENSET_COMPARE_Field_Array is array (0 .. 3) + of INTENSET_COMPARE0_Field_1 + with Component_Size => 1, Size => 4; + + -- Type definition for INTENSET_COMPARE + type INTENSET_COMPARE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- COMPARE as a value + Val : HAL.UInt4; + when True => + -- COMPARE as an array + Arr : INTENSET_COMPARE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for INTENSET_COMPARE_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- Enable interrupt + type INTENSET_Register is record + -- Write '1' to Enable interrupt for TICK event + TICK : INTENSET_TICK_Field_1 := Intenset_Tick_Field_Reset; + -- Write '1' to Enable interrupt for OVRFLW event + OVRFLW : INTENSET_OVRFLW_Field_1 := Intenset_Ovrflw_Field_Reset; + -- unspecified + Reserved_2_15 : HAL.UInt14 := 16#0#; + -- Write '1' to Enable interrupt for COMPARE[0] event + COMPARE : INTENSET_COMPARE_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_20_31 : HAL.UInt12 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENSET_Register use record + TICK at 0 range 0 .. 0; + OVRFLW at 0 range 1 .. 1; + Reserved_2_15 at 0 range 2 .. 15; + COMPARE at 0 range 16 .. 19; + Reserved_20_31 at 0 range 20 .. 31; + end record; + + -- Write '1' to Disable interrupt for TICK event + type INTENCLR_TICK_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_TICK_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for TICK event + type INTENCLR_TICK_Field_1 is + (-- Reset value for the field + Intenclr_Tick_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_TICK_Field_1 use + (Intenclr_Tick_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for OVRFLW event + type INTENCLR_OVRFLW_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_OVRFLW_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for OVRFLW event + type INTENCLR_OVRFLW_Field_1 is + (-- Reset value for the field + Intenclr_Ovrflw_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_OVRFLW_Field_1 use + (Intenclr_Ovrflw_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for COMPARE[0] event + type INTENCLR_COMPARE0_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_COMPARE0_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for COMPARE[0] event + type INTENCLR_COMPARE0_Field_1 is + (-- Reset value for the field + Intenclr_Compare0_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_COMPARE0_Field_1 use + (Intenclr_Compare0_Field_Reset => 0, + Clear => 1); + + -- INTENCLR_COMPARE array + type INTENCLR_COMPARE_Field_Array is array (0 .. 3) + of INTENCLR_COMPARE0_Field_1 + with Component_Size => 1, Size => 4; + + -- Type definition for INTENCLR_COMPARE + type INTENCLR_COMPARE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- COMPARE as a value + Val : HAL.UInt4; + when True => + -- COMPARE as an array + Arr : INTENCLR_COMPARE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for INTENCLR_COMPARE_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- Disable interrupt + type INTENCLR_Register is record + -- Write '1' to Disable interrupt for TICK event + TICK : INTENCLR_TICK_Field_1 := Intenclr_Tick_Field_Reset; + -- Write '1' to Disable interrupt for OVRFLW event + OVRFLW : INTENCLR_OVRFLW_Field_1 := Intenclr_Ovrflw_Field_Reset; + -- unspecified + Reserved_2_15 : HAL.UInt14 := 16#0#; + -- Write '1' to Disable interrupt for COMPARE[0] event + COMPARE : INTENCLR_COMPARE_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_20_31 : HAL.UInt12 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENCLR_Register use record + TICK at 0 range 0 .. 0; + OVRFLW at 0 range 1 .. 1; + Reserved_2_15 at 0 range 2 .. 15; + COMPARE at 0 range 16 .. 19; + Reserved_20_31 at 0 range 20 .. 31; + end record; + + -- Enable or disable event routing for TICK event + type EVTEN_TICK_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for EVTEN_TICK_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable event routing for OVRFLW event + type EVTEN_OVRFLW_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for EVTEN_OVRFLW_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable event routing for COMPARE[0] event + type EVTEN_COMPARE0_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for EVTEN_COMPARE0_Field use + (Disabled => 0, + Enabled => 1); + + -- EVTEN_COMPARE array + type EVTEN_COMPARE_Field_Array is array (0 .. 3) of EVTEN_COMPARE0_Field + with Component_Size => 1, Size => 4; + + -- Type definition for EVTEN_COMPARE + type EVTEN_COMPARE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- COMPARE as a value + Val : HAL.UInt4; + when True => + -- COMPARE as an array + Arr : EVTEN_COMPARE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for EVTEN_COMPARE_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- Enable or disable event routing + type EVTEN_Register is record + -- Enable or disable event routing for TICK event + TICK : EVTEN_TICK_Field := NRF_SVD.RTC.Disabled; + -- Enable or disable event routing for OVRFLW event + OVRFLW : EVTEN_OVRFLW_Field := NRF_SVD.RTC.Disabled; + -- unspecified + Reserved_2_15 : HAL.UInt14 := 16#0#; + -- Enable or disable event routing for COMPARE[0] event + COMPARE : EVTEN_COMPARE_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_20_31 : HAL.UInt12 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EVTEN_Register use record + TICK at 0 range 0 .. 0; + OVRFLW at 0 range 1 .. 1; + Reserved_2_15 at 0 range 2 .. 15; + COMPARE at 0 range 16 .. 19; + Reserved_20_31 at 0 range 20 .. 31; + end record; + + -- Write '1' to Enable event routing for TICK event + type EVTENSET_TICK_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for EVTENSET_TICK_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable event routing for TICK event + type EVTENSET_TICK_Field_1 is + (-- Reset value for the field + Evtenset_Tick_Field_Reset, + -- Enable + Set) + with Size => 1; + for EVTENSET_TICK_Field_1 use + (Evtenset_Tick_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable event routing for OVRFLW event + type EVTENSET_OVRFLW_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for EVTENSET_OVRFLW_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable event routing for OVRFLW event + type EVTENSET_OVRFLW_Field_1 is + (-- Reset value for the field + Evtenset_Ovrflw_Field_Reset, + -- Enable + Set) + with Size => 1; + for EVTENSET_OVRFLW_Field_1 use + (Evtenset_Ovrflw_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable event routing for COMPARE[0] event + type EVTENSET_COMPARE0_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for EVTENSET_COMPARE0_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable event routing for COMPARE[0] event + type EVTENSET_COMPARE0_Field_1 is + (-- Reset value for the field + Evtenset_Compare0_Field_Reset, + -- Enable + Set) + with Size => 1; + for EVTENSET_COMPARE0_Field_1 use + (Evtenset_Compare0_Field_Reset => 0, + Set => 1); + + -- EVTENSET_COMPARE array + type EVTENSET_COMPARE_Field_Array is array (0 .. 3) + of EVTENSET_COMPARE0_Field_1 + with Component_Size => 1, Size => 4; + + -- Type definition for EVTENSET_COMPARE + type EVTENSET_COMPARE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- COMPARE as a value + Val : HAL.UInt4; + when True => + -- COMPARE as an array + Arr : EVTENSET_COMPARE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for EVTENSET_COMPARE_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- Enable event routing + type EVTENSET_Register is record + -- Write '1' to Enable event routing for TICK event + TICK : EVTENSET_TICK_Field_1 := Evtenset_Tick_Field_Reset; + -- Write '1' to Enable event routing for OVRFLW event + OVRFLW : EVTENSET_OVRFLW_Field_1 := Evtenset_Ovrflw_Field_Reset; + -- unspecified + Reserved_2_15 : HAL.UInt14 := 16#0#; + -- Write '1' to Enable event routing for COMPARE[0] event + COMPARE : EVTENSET_COMPARE_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_20_31 : HAL.UInt12 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EVTENSET_Register use record + TICK at 0 range 0 .. 0; + OVRFLW at 0 range 1 .. 1; + Reserved_2_15 at 0 range 2 .. 15; + COMPARE at 0 range 16 .. 19; + Reserved_20_31 at 0 range 20 .. 31; + end record; + + -- Write '1' to Disable event routing for TICK event + type EVTENCLR_TICK_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for EVTENCLR_TICK_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable event routing for TICK event + type EVTENCLR_TICK_Field_1 is + (-- Reset value for the field + Evtenclr_Tick_Field_Reset, + -- Disable + Clear) + with Size => 1; + for EVTENCLR_TICK_Field_1 use + (Evtenclr_Tick_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable event routing for OVRFLW event + type EVTENCLR_OVRFLW_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for EVTENCLR_OVRFLW_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable event routing for OVRFLW event + type EVTENCLR_OVRFLW_Field_1 is + (-- Reset value for the field + Evtenclr_Ovrflw_Field_Reset, + -- Disable + Clear) + with Size => 1; + for EVTENCLR_OVRFLW_Field_1 use + (Evtenclr_Ovrflw_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable event routing for COMPARE[0] event + type EVTENCLR_COMPARE0_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for EVTENCLR_COMPARE0_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable event routing for COMPARE[0] event + type EVTENCLR_COMPARE0_Field_1 is + (-- Reset value for the field + Evtenclr_Compare0_Field_Reset, + -- Disable + Clear) + with Size => 1; + for EVTENCLR_COMPARE0_Field_1 use + (Evtenclr_Compare0_Field_Reset => 0, + Clear => 1); + + -- EVTENCLR_COMPARE array + type EVTENCLR_COMPARE_Field_Array is array (0 .. 3) + of EVTENCLR_COMPARE0_Field_1 + with Component_Size => 1, Size => 4; + + -- Type definition for EVTENCLR_COMPARE + type EVTENCLR_COMPARE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- COMPARE as a value + Val : HAL.UInt4; + when True => + -- COMPARE as an array + Arr : EVTENCLR_COMPARE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for EVTENCLR_COMPARE_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- Disable event routing + type EVTENCLR_Register is record + -- Write '1' to Disable event routing for TICK event + TICK : EVTENCLR_TICK_Field_1 := Evtenclr_Tick_Field_Reset; + -- Write '1' to Disable event routing for OVRFLW event + OVRFLW : EVTENCLR_OVRFLW_Field_1 := Evtenclr_Ovrflw_Field_Reset; + -- unspecified + Reserved_2_15 : HAL.UInt14 := 16#0#; + -- Write '1' to Disable event routing for COMPARE[0] event + COMPARE : EVTENCLR_COMPARE_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_20_31 : HAL.UInt12 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EVTENCLR_Register use record + TICK at 0 range 0 .. 0; + OVRFLW at 0 range 1 .. 1; + Reserved_2_15 at 0 range 2 .. 15; + COMPARE at 0 range 16 .. 19; + Reserved_20_31 at 0 range 20 .. 31; + end record; + + subtype COUNTER_COUNTER_Field is HAL.UInt24; + + -- Current COUNTER value + type COUNTER_Register is record + -- Read-only. Counter value + COUNTER : COUNTER_COUNTER_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for COUNTER_Register use record + COUNTER at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PRESCALER_PRESCALER_Field is HAL.UInt12; + + -- 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be + -- written when RTC is stopped + type PRESCALER_Register is record + -- Prescaler value + PRESCALER : PRESCALER_PRESCALER_Field := 16#0#; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PRESCALER_Register use record + PRESCALER at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype CC_COMPARE_Field is HAL.UInt24; + + -- Description collection[0]: Compare register 0 + type CC_Register is record + -- Compare value + COMPARE : CC_COMPARE_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CC_Register use record + COMPARE at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Description collection[0]: Compare register 0 + type CC_Registers is array (0 .. 3) of CC_Register; + + ----------------- + -- Peripherals -- + ----------------- + + -- Real time counter 0 + type RTC_Peripheral is record + -- Start RTC COUNTER + TASKS_START : aliased HAL.UInt32; + -- Stop RTC COUNTER + TASKS_STOP : aliased HAL.UInt32; + -- Clear RTC COUNTER + TASKS_CLEAR : aliased HAL.UInt32; + -- Set COUNTER to 0xFFFFF0 + TASKS_TRIGOVRFLW : aliased HAL.UInt32; + -- Event on COUNTER increment + EVENTS_TICK : aliased HAL.UInt32; + -- Event on COUNTER overflow + EVENTS_OVRFLW : aliased HAL.UInt32; + -- Description collection[0]: Compare event on CC[0] match + EVENTS_COMPARE : aliased EVENTS_COMPARE_Registers; + -- Enable interrupt + INTENSET : aliased INTENSET_Register; + -- Disable interrupt + INTENCLR : aliased INTENCLR_Register; + -- Enable or disable event routing + EVTEN : aliased EVTEN_Register; + -- Enable event routing + EVTENSET : aliased EVTENSET_Register; + -- Disable event routing + EVTENCLR : aliased EVTENCLR_Register; + -- Current COUNTER value + COUNTER : aliased COUNTER_Register; + -- 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be + -- written when RTC is stopped + PRESCALER : aliased PRESCALER_Register; + -- Description collection[0]: Compare register 0 + CC : aliased CC_Registers; + end record + with Volatile; + + for RTC_Peripheral use record + TASKS_START at 16#0# range 0 .. 31; + TASKS_STOP at 16#4# range 0 .. 31; + TASKS_CLEAR at 16#8# range 0 .. 31; + TASKS_TRIGOVRFLW at 16#C# range 0 .. 31; + EVENTS_TICK at 16#100# range 0 .. 31; + EVENTS_OVRFLW at 16#104# range 0 .. 31; + EVENTS_COMPARE at 16#140# range 0 .. 127; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + EVTEN at 16#340# range 0 .. 31; + EVTENSET at 16#344# range 0 .. 31; + EVTENCLR at 16#348# range 0 .. 31; + COUNTER at 16#504# range 0 .. 31; + PRESCALER at 16#508# range 0 .. 31; + CC at 16#540# range 0 .. 127; + end record; + + -- Real time counter 0 + RTC0_Periph : aliased RTC_Peripheral + with Import, Address => RTC0_Base; + + -- Real time counter 1 + RTC1_Periph : aliased RTC_Peripheral + with Import, Address => RTC1_Base; + + -- Real time counter 2 + RTC2_Periph : aliased RTC_Peripheral + with Import, Address => RTC2_Base; + +end NRF_SVD.RTC; diff --git a/arch/ARM/Nordic/svd/nrf52/nrf_svd-saadc.ads b/arch/ARM/Nordic/svd/nrf52/nrf_svd-saadc.ads new file mode 100644 index 000000000..9f7a3ba5b --- /dev/null +++ b/arch/ARM/Nordic/svd/nrf52/nrf_svd-saadc.ads @@ -0,0 +1,2184 @@ +-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- 2. Redistributions in binary form, except as embedded into a Nordic +-- Semiconductor ASA integrated circuit in a product or a software update for +-- such product, must reproduce the above copyright notice, this list of +-- conditions and the following disclaimer in the documentation and/or other +-- materials provided with the distribution. +-- +-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from this +-- software without specific prior written permission. +-- +-- 4. This software, with or without modification, must only be used with a +-- Nordic Semiconductor ASA integrated circuit. +-- +-- 5. Any software provided in binary form under this license must not be reverse +-- engineered, decompiled, modified and/or disassembled. +-- +-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +-- OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + +-- This spec has been automatically generated from nrf52.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package NRF_SVD.SAADC is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + ----------------------------------- + -- EVENTS_CH cluster's Registers -- + ----------------------------------- + + -- Unspecified + type EVENTS_CH_Cluster is record + -- Description cluster[0]: Last results is equal or above + -- CH[0].LIMIT.HIGH + LIMITH : aliased HAL.UInt32; + -- Description cluster[0]: Last results is equal or below + -- CH[0].LIMIT.LOW + LIMITL : aliased HAL.UInt32; + end record + with Size => 64; + + for EVENTS_CH_Cluster use record + LIMITH at 16#0# range 0 .. 31; + LIMITL at 16#4# range 0 .. 31; + end record; + + -- Unspecified + type EVENTS_CH_Clusters is array (0 .. 7) of EVENTS_CH_Cluster; + + -- Enable or disable interrupt for STARTED event + type INTEN_STARTED_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_STARTED_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for END event + type INTEN_END_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_END_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for DONE event + type INTEN_DONE_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_DONE_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for RESULTDONE event + type INTEN_RESULTDONE_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_RESULTDONE_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for CALIBRATEDONE event + type INTEN_CALIBRATEDONE_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_CALIBRATEDONE_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for STOPPED event + type INTEN_STOPPED_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_STOPPED_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for CH[0].LIMITH event + type INTEN_CH0LIMITH_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_CH0LIMITH_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for CH[0].LIMITL event + type INTEN_CH0LIMITL_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_CH0LIMITL_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for CH[1].LIMITH event + type INTEN_CH1LIMITH_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_CH1LIMITH_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for CH[1].LIMITL event + type INTEN_CH1LIMITL_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_CH1LIMITL_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for CH[2].LIMITH event + type INTEN_CH2LIMITH_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_CH2LIMITH_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for CH[2].LIMITL event + type INTEN_CH2LIMITL_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_CH2LIMITL_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for CH[3].LIMITH event + type INTEN_CH3LIMITH_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_CH3LIMITH_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for CH[3].LIMITL event + type INTEN_CH3LIMITL_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_CH3LIMITL_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for CH[4].LIMITH event + type INTEN_CH4LIMITH_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_CH4LIMITH_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for CH[4].LIMITL event + type INTEN_CH4LIMITL_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_CH4LIMITL_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for CH[5].LIMITH event + type INTEN_CH5LIMITH_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_CH5LIMITH_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for CH[5].LIMITL event + type INTEN_CH5LIMITL_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_CH5LIMITL_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for CH[6].LIMITH event + type INTEN_CH6LIMITH_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_CH6LIMITH_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for CH[6].LIMITL event + type INTEN_CH6LIMITL_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_CH6LIMITL_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for CH[7].LIMITH event + type INTEN_CH7LIMITH_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_CH7LIMITH_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for CH[7].LIMITL event + type INTEN_CH7LIMITL_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_CH7LIMITL_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt + type INTEN_Register is record + -- Enable or disable interrupt for STARTED event + STARTED : INTEN_STARTED_Field := NRF_SVD.SAADC.Disabled; + -- Enable or disable interrupt for END event + END_k : INTEN_END_Field := NRF_SVD.SAADC.Disabled; + -- Enable or disable interrupt for DONE event + DONE : INTEN_DONE_Field := NRF_SVD.SAADC.Disabled; + -- Enable or disable interrupt for RESULTDONE event + RESULTDONE : INTEN_RESULTDONE_Field := NRF_SVD.SAADC.Disabled; + -- Enable or disable interrupt for CALIBRATEDONE event + CALIBRATEDONE : INTEN_CALIBRATEDONE_Field := NRF_SVD.SAADC.Disabled; + -- Enable or disable interrupt for STOPPED event + STOPPED : INTEN_STOPPED_Field := NRF_SVD.SAADC.Disabled; + -- Enable or disable interrupt for CH[0].LIMITH event + CH0LIMITH : INTEN_CH0LIMITH_Field := NRF_SVD.SAADC.Disabled; + -- Enable or disable interrupt for CH[0].LIMITL event + CH0LIMITL : INTEN_CH0LIMITL_Field := NRF_SVD.SAADC.Disabled; + -- Enable or disable interrupt for CH[1].LIMITH event + CH1LIMITH : INTEN_CH1LIMITH_Field := NRF_SVD.SAADC.Disabled; + -- Enable or disable interrupt for CH[1].LIMITL event + CH1LIMITL : INTEN_CH1LIMITL_Field := NRF_SVD.SAADC.Disabled; + -- Enable or disable interrupt for CH[2].LIMITH event + CH2LIMITH : INTEN_CH2LIMITH_Field := NRF_SVD.SAADC.Disabled; + -- Enable or disable interrupt for CH[2].LIMITL event + CH2LIMITL : INTEN_CH2LIMITL_Field := NRF_SVD.SAADC.Disabled; + -- Enable or disable interrupt for CH[3].LIMITH event + CH3LIMITH : INTEN_CH3LIMITH_Field := NRF_SVD.SAADC.Disabled; + -- Enable or disable interrupt for CH[3].LIMITL event + CH3LIMITL : INTEN_CH3LIMITL_Field := NRF_SVD.SAADC.Disabled; + -- Enable or disable interrupt for CH[4].LIMITH event + CH4LIMITH : INTEN_CH4LIMITH_Field := NRF_SVD.SAADC.Disabled; + -- Enable or disable interrupt for CH[4].LIMITL event + CH4LIMITL : INTEN_CH4LIMITL_Field := NRF_SVD.SAADC.Disabled; + -- Enable or disable interrupt for CH[5].LIMITH event + CH5LIMITH : INTEN_CH5LIMITH_Field := NRF_SVD.SAADC.Disabled; + -- Enable or disable interrupt for CH[5].LIMITL event + CH5LIMITL : INTEN_CH5LIMITL_Field := NRF_SVD.SAADC.Disabled; + -- Enable or disable interrupt for CH[6].LIMITH event + CH6LIMITH : INTEN_CH6LIMITH_Field := NRF_SVD.SAADC.Disabled; + -- Enable or disable interrupt for CH[6].LIMITL event + CH6LIMITL : INTEN_CH6LIMITL_Field := NRF_SVD.SAADC.Disabled; + -- Enable or disable interrupt for CH[7].LIMITH event + CH7LIMITH : INTEN_CH7LIMITH_Field := NRF_SVD.SAADC.Disabled; + -- Enable or disable interrupt for CH[7].LIMITL event + CH7LIMITL : INTEN_CH7LIMITL_Field := NRF_SVD.SAADC.Disabled; + -- unspecified + Reserved_22_31 : HAL.UInt10 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTEN_Register use record + STARTED at 0 range 0 .. 0; + END_k at 0 range 1 .. 1; + DONE at 0 range 2 .. 2; + RESULTDONE at 0 range 3 .. 3; + CALIBRATEDONE at 0 range 4 .. 4; + STOPPED at 0 range 5 .. 5; + CH0LIMITH at 0 range 6 .. 6; + CH0LIMITL at 0 range 7 .. 7; + CH1LIMITH at 0 range 8 .. 8; + CH1LIMITL at 0 range 9 .. 9; + CH2LIMITH at 0 range 10 .. 10; + CH2LIMITL at 0 range 11 .. 11; + CH3LIMITH at 0 range 12 .. 12; + CH3LIMITL at 0 range 13 .. 13; + CH4LIMITH at 0 range 14 .. 14; + CH4LIMITL at 0 range 15 .. 15; + CH5LIMITH at 0 range 16 .. 16; + CH5LIMITL at 0 range 17 .. 17; + CH6LIMITH at 0 range 18 .. 18; + CH6LIMITL at 0 range 19 .. 19; + CH7LIMITH at 0 range 20 .. 20; + CH7LIMITL at 0 range 21 .. 21; + Reserved_22_31 at 0 range 22 .. 31; + end record; + + -- Write '1' to Enable interrupt for STARTED event + type INTENSET_STARTED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_STARTED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for STARTED event + type INTENSET_STARTED_Field_1 is + (-- Reset value for the field + Intenset_Started_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_STARTED_Field_1 use + (Intenset_Started_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for END event + type INTENSET_END_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_END_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for END event + type INTENSET_END_Field_1 is + (-- Reset value for the field + Intenset_End_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_END_Field_1 use + (Intenset_End_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for DONE event + type INTENSET_DONE_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_DONE_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for DONE event + type INTENSET_DONE_Field_1 is + (-- Reset value for the field + Intenset_Done_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_DONE_Field_1 use + (Intenset_Done_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for RESULTDONE event + type INTENSET_RESULTDONE_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_RESULTDONE_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for RESULTDONE event + type INTENSET_RESULTDONE_Field_1 is + (-- Reset value for the field + Intenset_Resultdone_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_RESULTDONE_Field_1 use + (Intenset_Resultdone_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for CALIBRATEDONE event + type INTENSET_CALIBRATEDONE_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_CALIBRATEDONE_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for CALIBRATEDONE event + type INTENSET_CALIBRATEDONE_Field_1 is + (-- Reset value for the field + Intenset_Calibratedone_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_CALIBRATEDONE_Field_1 use + (Intenset_Calibratedone_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for STOPPED event + type INTENSET_STOPPED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_STOPPED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for STOPPED event + type INTENSET_STOPPED_Field_1 is + (-- Reset value for the field + Intenset_Stopped_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_STOPPED_Field_1 use + (Intenset_Stopped_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for CH[0].LIMITH event + type INTENSET_CH0LIMITH_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_CH0LIMITH_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for CH[0].LIMITH event + type INTENSET_CH0LIMITH_Field_1 is + (-- Reset value for the field + Intenset_Ch0Limith_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_CH0LIMITH_Field_1 use + (Intenset_Ch0Limith_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for CH[0].LIMITL event + type INTENSET_CH0LIMITL_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_CH0LIMITL_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for CH[0].LIMITL event + type INTENSET_CH0LIMITL_Field_1 is + (-- Reset value for the field + Intenset_Ch0Limitl_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_CH0LIMITL_Field_1 use + (Intenset_Ch0Limitl_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for CH[1].LIMITH event + type INTENSET_CH1LIMITH_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_CH1LIMITH_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for CH[1].LIMITH event + type INTENSET_CH1LIMITH_Field_1 is + (-- Reset value for the field + Intenset_Ch1Limith_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_CH1LIMITH_Field_1 use + (Intenset_Ch1Limith_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for CH[1].LIMITL event + type INTENSET_CH1LIMITL_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_CH1LIMITL_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for CH[1].LIMITL event + type INTENSET_CH1LIMITL_Field_1 is + (-- Reset value for the field + Intenset_Ch1Limitl_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_CH1LIMITL_Field_1 use + (Intenset_Ch1Limitl_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for CH[2].LIMITH event + type INTENSET_CH2LIMITH_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_CH2LIMITH_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for CH[2].LIMITH event + type INTENSET_CH2LIMITH_Field_1 is + (-- Reset value for the field + Intenset_Ch2Limith_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_CH2LIMITH_Field_1 use + (Intenset_Ch2Limith_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for CH[2].LIMITL event + type INTENSET_CH2LIMITL_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_CH2LIMITL_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for CH[2].LIMITL event + type INTENSET_CH2LIMITL_Field_1 is + (-- Reset value for the field + Intenset_Ch2Limitl_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_CH2LIMITL_Field_1 use + (Intenset_Ch2Limitl_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for CH[3].LIMITH event + type INTENSET_CH3LIMITH_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_CH3LIMITH_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for CH[3].LIMITH event + type INTENSET_CH3LIMITH_Field_1 is + (-- Reset value for the field + Intenset_Ch3Limith_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_CH3LIMITH_Field_1 use + (Intenset_Ch3Limith_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for CH[3].LIMITL event + type INTENSET_CH3LIMITL_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_CH3LIMITL_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for CH[3].LIMITL event + type INTENSET_CH3LIMITL_Field_1 is + (-- Reset value for the field + Intenset_Ch3Limitl_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_CH3LIMITL_Field_1 use + (Intenset_Ch3Limitl_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for CH[4].LIMITH event + type INTENSET_CH4LIMITH_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_CH4LIMITH_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for CH[4].LIMITH event + type INTENSET_CH4LIMITH_Field_1 is + (-- Reset value for the field + Intenset_Ch4Limith_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_CH4LIMITH_Field_1 use + (Intenset_Ch4Limith_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for CH[4].LIMITL event + type INTENSET_CH4LIMITL_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_CH4LIMITL_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for CH[4].LIMITL event + type INTENSET_CH4LIMITL_Field_1 is + (-- Reset value for the field + Intenset_Ch4Limitl_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_CH4LIMITL_Field_1 use + (Intenset_Ch4Limitl_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for CH[5].LIMITH event + type INTENSET_CH5LIMITH_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_CH5LIMITH_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for CH[5].LIMITH event + type INTENSET_CH5LIMITH_Field_1 is + (-- Reset value for the field + Intenset_Ch5Limith_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_CH5LIMITH_Field_1 use + (Intenset_Ch5Limith_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for CH[5].LIMITL event + type INTENSET_CH5LIMITL_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_CH5LIMITL_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for CH[5].LIMITL event + type INTENSET_CH5LIMITL_Field_1 is + (-- Reset value for the field + Intenset_Ch5Limitl_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_CH5LIMITL_Field_1 use + (Intenset_Ch5Limitl_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for CH[6].LIMITH event + type INTENSET_CH6LIMITH_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_CH6LIMITH_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for CH[6].LIMITH event + type INTENSET_CH6LIMITH_Field_1 is + (-- Reset value for the field + Intenset_Ch6Limith_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_CH6LIMITH_Field_1 use + (Intenset_Ch6Limith_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for CH[6].LIMITL event + type INTENSET_CH6LIMITL_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_CH6LIMITL_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for CH[6].LIMITL event + type INTENSET_CH6LIMITL_Field_1 is + (-- Reset value for the field + Intenset_Ch6Limitl_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_CH6LIMITL_Field_1 use + (Intenset_Ch6Limitl_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for CH[7].LIMITH event + type INTENSET_CH7LIMITH_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_CH7LIMITH_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for CH[7].LIMITH event + type INTENSET_CH7LIMITH_Field_1 is + (-- Reset value for the field + Intenset_Ch7Limith_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_CH7LIMITH_Field_1 use + (Intenset_Ch7Limith_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for CH[7].LIMITL event + type INTENSET_CH7LIMITL_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_CH7LIMITL_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for CH[7].LIMITL event + type INTENSET_CH7LIMITL_Field_1 is + (-- Reset value for the field + Intenset_Ch7Limitl_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_CH7LIMITL_Field_1 use + (Intenset_Ch7Limitl_Field_Reset => 0, + Set => 1); + + -- Enable interrupt + type INTENSET_Register is record + -- Write '1' to Enable interrupt for STARTED event + STARTED : INTENSET_STARTED_Field_1 := + Intenset_Started_Field_Reset; + -- Write '1' to Enable interrupt for END event + END_k : INTENSET_END_Field_1 := Intenset_End_Field_Reset; + -- Write '1' to Enable interrupt for DONE event + DONE : INTENSET_DONE_Field_1 := Intenset_Done_Field_Reset; + -- Write '1' to Enable interrupt for RESULTDONE event + RESULTDONE : INTENSET_RESULTDONE_Field_1 := + Intenset_Resultdone_Field_Reset; + -- Write '1' to Enable interrupt for CALIBRATEDONE event + CALIBRATEDONE : INTENSET_CALIBRATEDONE_Field_1 := + Intenset_Calibratedone_Field_Reset; + -- Write '1' to Enable interrupt for STOPPED event + STOPPED : INTENSET_STOPPED_Field_1 := + Intenset_Stopped_Field_Reset; + -- Write '1' to Enable interrupt for CH[0].LIMITH event + CH0LIMITH : INTENSET_CH0LIMITH_Field_1 := + Intenset_Ch0Limith_Field_Reset; + -- Write '1' to Enable interrupt for CH[0].LIMITL event + CH0LIMITL : INTENSET_CH0LIMITL_Field_1 := + Intenset_Ch0Limitl_Field_Reset; + -- Write '1' to Enable interrupt for CH[1].LIMITH event + CH1LIMITH : INTENSET_CH1LIMITH_Field_1 := + Intenset_Ch1Limith_Field_Reset; + -- Write '1' to Enable interrupt for CH[1].LIMITL event + CH1LIMITL : INTENSET_CH1LIMITL_Field_1 := + Intenset_Ch1Limitl_Field_Reset; + -- Write '1' to Enable interrupt for CH[2].LIMITH event + CH2LIMITH : INTENSET_CH2LIMITH_Field_1 := + Intenset_Ch2Limith_Field_Reset; + -- Write '1' to Enable interrupt for CH[2].LIMITL event + CH2LIMITL : INTENSET_CH2LIMITL_Field_1 := + Intenset_Ch2Limitl_Field_Reset; + -- Write '1' to Enable interrupt for CH[3].LIMITH event + CH3LIMITH : INTENSET_CH3LIMITH_Field_1 := + Intenset_Ch3Limith_Field_Reset; + -- Write '1' to Enable interrupt for CH[3].LIMITL event + CH3LIMITL : INTENSET_CH3LIMITL_Field_1 := + Intenset_Ch3Limitl_Field_Reset; + -- Write '1' to Enable interrupt for CH[4].LIMITH event + CH4LIMITH : INTENSET_CH4LIMITH_Field_1 := + Intenset_Ch4Limith_Field_Reset; + -- Write '1' to Enable interrupt for CH[4].LIMITL event + CH4LIMITL : INTENSET_CH4LIMITL_Field_1 := + Intenset_Ch4Limitl_Field_Reset; + -- Write '1' to Enable interrupt for CH[5].LIMITH event + CH5LIMITH : INTENSET_CH5LIMITH_Field_1 := + Intenset_Ch5Limith_Field_Reset; + -- Write '1' to Enable interrupt for CH[5].LIMITL event + CH5LIMITL : INTENSET_CH5LIMITL_Field_1 := + Intenset_Ch5Limitl_Field_Reset; + -- Write '1' to Enable interrupt for CH[6].LIMITH event + CH6LIMITH : INTENSET_CH6LIMITH_Field_1 := + Intenset_Ch6Limith_Field_Reset; + -- Write '1' to Enable interrupt for CH[6].LIMITL event + CH6LIMITL : INTENSET_CH6LIMITL_Field_1 := + Intenset_Ch6Limitl_Field_Reset; + -- Write '1' to Enable interrupt for CH[7].LIMITH event + CH7LIMITH : INTENSET_CH7LIMITH_Field_1 := + Intenset_Ch7Limith_Field_Reset; + -- Write '1' to Enable interrupt for CH[7].LIMITL event + CH7LIMITL : INTENSET_CH7LIMITL_Field_1 := + Intenset_Ch7Limitl_Field_Reset; + -- unspecified + Reserved_22_31 : HAL.UInt10 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENSET_Register use record + STARTED at 0 range 0 .. 0; + END_k at 0 range 1 .. 1; + DONE at 0 range 2 .. 2; + RESULTDONE at 0 range 3 .. 3; + CALIBRATEDONE at 0 range 4 .. 4; + STOPPED at 0 range 5 .. 5; + CH0LIMITH at 0 range 6 .. 6; + CH0LIMITL at 0 range 7 .. 7; + CH1LIMITH at 0 range 8 .. 8; + CH1LIMITL at 0 range 9 .. 9; + CH2LIMITH at 0 range 10 .. 10; + CH2LIMITL at 0 range 11 .. 11; + CH3LIMITH at 0 range 12 .. 12; + CH3LIMITL at 0 range 13 .. 13; + CH4LIMITH at 0 range 14 .. 14; + CH4LIMITL at 0 range 15 .. 15; + CH5LIMITH at 0 range 16 .. 16; + CH5LIMITL at 0 range 17 .. 17; + CH6LIMITH at 0 range 18 .. 18; + CH6LIMITL at 0 range 19 .. 19; + CH7LIMITH at 0 range 20 .. 20; + CH7LIMITL at 0 range 21 .. 21; + Reserved_22_31 at 0 range 22 .. 31; + end record; + + -- Write '1' to Disable interrupt for STARTED event + type INTENCLR_STARTED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_STARTED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for STARTED event + type INTENCLR_STARTED_Field_1 is + (-- Reset value for the field + Intenclr_Started_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_STARTED_Field_1 use + (Intenclr_Started_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for END event + type INTENCLR_END_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_END_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for END event + type INTENCLR_END_Field_1 is + (-- Reset value for the field + Intenclr_End_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_END_Field_1 use + (Intenclr_End_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for DONE event + type INTENCLR_DONE_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_DONE_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for DONE event + type INTENCLR_DONE_Field_1 is + (-- Reset value for the field + Intenclr_Done_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_DONE_Field_1 use + (Intenclr_Done_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for RESULTDONE event + type INTENCLR_RESULTDONE_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_RESULTDONE_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for RESULTDONE event + type INTENCLR_RESULTDONE_Field_1 is + (-- Reset value for the field + Intenclr_Resultdone_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_RESULTDONE_Field_1 use + (Intenclr_Resultdone_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for CALIBRATEDONE event + type INTENCLR_CALIBRATEDONE_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_CALIBRATEDONE_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for CALIBRATEDONE event + type INTENCLR_CALIBRATEDONE_Field_1 is + (-- Reset value for the field + Intenclr_Calibratedone_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_CALIBRATEDONE_Field_1 use + (Intenclr_Calibratedone_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for STOPPED event + type INTENCLR_STOPPED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_STOPPED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for STOPPED event + type INTENCLR_STOPPED_Field_1 is + (-- Reset value for the field + Intenclr_Stopped_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_STOPPED_Field_1 use + (Intenclr_Stopped_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for CH[0].LIMITH event + type INTENCLR_CH0LIMITH_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_CH0LIMITH_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for CH[0].LIMITH event + type INTENCLR_CH0LIMITH_Field_1 is + (-- Reset value for the field + Intenclr_Ch0Limith_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_CH0LIMITH_Field_1 use + (Intenclr_Ch0Limith_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for CH[0].LIMITL event + type INTENCLR_CH0LIMITL_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_CH0LIMITL_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for CH[0].LIMITL event + type INTENCLR_CH0LIMITL_Field_1 is + (-- Reset value for the field + Intenclr_Ch0Limitl_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_CH0LIMITL_Field_1 use + (Intenclr_Ch0Limitl_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for CH[1].LIMITH event + type INTENCLR_CH1LIMITH_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_CH1LIMITH_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for CH[1].LIMITH event + type INTENCLR_CH1LIMITH_Field_1 is + (-- Reset value for the field + Intenclr_Ch1Limith_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_CH1LIMITH_Field_1 use + (Intenclr_Ch1Limith_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for CH[1].LIMITL event + type INTENCLR_CH1LIMITL_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_CH1LIMITL_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for CH[1].LIMITL event + type INTENCLR_CH1LIMITL_Field_1 is + (-- Reset value for the field + Intenclr_Ch1Limitl_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_CH1LIMITL_Field_1 use + (Intenclr_Ch1Limitl_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for CH[2].LIMITH event + type INTENCLR_CH2LIMITH_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_CH2LIMITH_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for CH[2].LIMITH event + type INTENCLR_CH2LIMITH_Field_1 is + (-- Reset value for the field + Intenclr_Ch2Limith_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_CH2LIMITH_Field_1 use + (Intenclr_Ch2Limith_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for CH[2].LIMITL event + type INTENCLR_CH2LIMITL_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_CH2LIMITL_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for CH[2].LIMITL event + type INTENCLR_CH2LIMITL_Field_1 is + (-- Reset value for the field + Intenclr_Ch2Limitl_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_CH2LIMITL_Field_1 use + (Intenclr_Ch2Limitl_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for CH[3].LIMITH event + type INTENCLR_CH3LIMITH_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_CH3LIMITH_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for CH[3].LIMITH event + type INTENCLR_CH3LIMITH_Field_1 is + (-- Reset value for the field + Intenclr_Ch3Limith_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_CH3LIMITH_Field_1 use + (Intenclr_Ch3Limith_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for CH[3].LIMITL event + type INTENCLR_CH3LIMITL_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_CH3LIMITL_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for CH[3].LIMITL event + type INTENCLR_CH3LIMITL_Field_1 is + (-- Reset value for the field + Intenclr_Ch3Limitl_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_CH3LIMITL_Field_1 use + (Intenclr_Ch3Limitl_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for CH[4].LIMITH event + type INTENCLR_CH4LIMITH_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_CH4LIMITH_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for CH[4].LIMITH event + type INTENCLR_CH4LIMITH_Field_1 is + (-- Reset value for the field + Intenclr_Ch4Limith_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_CH4LIMITH_Field_1 use + (Intenclr_Ch4Limith_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for CH[4].LIMITL event + type INTENCLR_CH4LIMITL_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_CH4LIMITL_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for CH[4].LIMITL event + type INTENCLR_CH4LIMITL_Field_1 is + (-- Reset value for the field + Intenclr_Ch4Limitl_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_CH4LIMITL_Field_1 use + (Intenclr_Ch4Limitl_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for CH[5].LIMITH event + type INTENCLR_CH5LIMITH_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_CH5LIMITH_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for CH[5].LIMITH event + type INTENCLR_CH5LIMITH_Field_1 is + (-- Reset value for the field + Intenclr_Ch5Limith_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_CH5LIMITH_Field_1 use + (Intenclr_Ch5Limith_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for CH[5].LIMITL event + type INTENCLR_CH5LIMITL_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_CH5LIMITL_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for CH[5].LIMITL event + type INTENCLR_CH5LIMITL_Field_1 is + (-- Reset value for the field + Intenclr_Ch5Limitl_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_CH5LIMITL_Field_1 use + (Intenclr_Ch5Limitl_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for CH[6].LIMITH event + type INTENCLR_CH6LIMITH_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_CH6LIMITH_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for CH[6].LIMITH event + type INTENCLR_CH6LIMITH_Field_1 is + (-- Reset value for the field + Intenclr_Ch6Limith_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_CH6LIMITH_Field_1 use + (Intenclr_Ch6Limith_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for CH[6].LIMITL event + type INTENCLR_CH6LIMITL_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_CH6LIMITL_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for CH[6].LIMITL event + type INTENCLR_CH6LIMITL_Field_1 is + (-- Reset value for the field + Intenclr_Ch6Limitl_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_CH6LIMITL_Field_1 use + (Intenclr_Ch6Limitl_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for CH[7].LIMITH event + type INTENCLR_CH7LIMITH_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_CH7LIMITH_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for CH[7].LIMITH event + type INTENCLR_CH7LIMITH_Field_1 is + (-- Reset value for the field + Intenclr_Ch7Limith_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_CH7LIMITH_Field_1 use + (Intenclr_Ch7Limith_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for CH[7].LIMITL event + type INTENCLR_CH7LIMITL_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_CH7LIMITL_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for CH[7].LIMITL event + type INTENCLR_CH7LIMITL_Field_1 is + (-- Reset value for the field + Intenclr_Ch7Limitl_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_CH7LIMITL_Field_1 use + (Intenclr_Ch7Limitl_Field_Reset => 0, + Clear => 1); + + -- Disable interrupt + type INTENCLR_Register is record + -- Write '1' to Disable interrupt for STARTED event + STARTED : INTENCLR_STARTED_Field_1 := + Intenclr_Started_Field_Reset; + -- Write '1' to Disable interrupt for END event + END_k : INTENCLR_END_Field_1 := Intenclr_End_Field_Reset; + -- Write '1' to Disable interrupt for DONE event + DONE : INTENCLR_DONE_Field_1 := Intenclr_Done_Field_Reset; + -- Write '1' to Disable interrupt for RESULTDONE event + RESULTDONE : INTENCLR_RESULTDONE_Field_1 := + Intenclr_Resultdone_Field_Reset; + -- Write '1' to Disable interrupt for CALIBRATEDONE event + CALIBRATEDONE : INTENCLR_CALIBRATEDONE_Field_1 := + Intenclr_Calibratedone_Field_Reset; + -- Write '1' to Disable interrupt for STOPPED event + STOPPED : INTENCLR_STOPPED_Field_1 := + Intenclr_Stopped_Field_Reset; + -- Write '1' to Disable interrupt for CH[0].LIMITH event + CH0LIMITH : INTENCLR_CH0LIMITH_Field_1 := + Intenclr_Ch0Limith_Field_Reset; + -- Write '1' to Disable interrupt for CH[0].LIMITL event + CH0LIMITL : INTENCLR_CH0LIMITL_Field_1 := + Intenclr_Ch0Limitl_Field_Reset; + -- Write '1' to Disable interrupt for CH[1].LIMITH event + CH1LIMITH : INTENCLR_CH1LIMITH_Field_1 := + Intenclr_Ch1Limith_Field_Reset; + -- Write '1' to Disable interrupt for CH[1].LIMITL event + CH1LIMITL : INTENCLR_CH1LIMITL_Field_1 := + Intenclr_Ch1Limitl_Field_Reset; + -- Write '1' to Disable interrupt for CH[2].LIMITH event + CH2LIMITH : INTENCLR_CH2LIMITH_Field_1 := + Intenclr_Ch2Limith_Field_Reset; + -- Write '1' to Disable interrupt for CH[2].LIMITL event + CH2LIMITL : INTENCLR_CH2LIMITL_Field_1 := + Intenclr_Ch2Limitl_Field_Reset; + -- Write '1' to Disable interrupt for CH[3].LIMITH event + CH3LIMITH : INTENCLR_CH3LIMITH_Field_1 := + Intenclr_Ch3Limith_Field_Reset; + -- Write '1' to Disable interrupt for CH[3].LIMITL event + CH3LIMITL : INTENCLR_CH3LIMITL_Field_1 := + Intenclr_Ch3Limitl_Field_Reset; + -- Write '1' to Disable interrupt for CH[4].LIMITH event + CH4LIMITH : INTENCLR_CH4LIMITH_Field_1 := + Intenclr_Ch4Limith_Field_Reset; + -- Write '1' to Disable interrupt for CH[4].LIMITL event + CH4LIMITL : INTENCLR_CH4LIMITL_Field_1 := + Intenclr_Ch4Limitl_Field_Reset; + -- Write '1' to Disable interrupt for CH[5].LIMITH event + CH5LIMITH : INTENCLR_CH5LIMITH_Field_1 := + Intenclr_Ch5Limith_Field_Reset; + -- Write '1' to Disable interrupt for CH[5].LIMITL event + CH5LIMITL : INTENCLR_CH5LIMITL_Field_1 := + Intenclr_Ch5Limitl_Field_Reset; + -- Write '1' to Disable interrupt for CH[6].LIMITH event + CH6LIMITH : INTENCLR_CH6LIMITH_Field_1 := + Intenclr_Ch6Limith_Field_Reset; + -- Write '1' to Disable interrupt for CH[6].LIMITL event + CH6LIMITL : INTENCLR_CH6LIMITL_Field_1 := + Intenclr_Ch6Limitl_Field_Reset; + -- Write '1' to Disable interrupt for CH[7].LIMITH event + CH7LIMITH : INTENCLR_CH7LIMITH_Field_1 := + Intenclr_Ch7Limith_Field_Reset; + -- Write '1' to Disable interrupt for CH[7].LIMITL event + CH7LIMITL : INTENCLR_CH7LIMITL_Field_1 := + Intenclr_Ch7Limitl_Field_Reset; + -- unspecified + Reserved_22_31 : HAL.UInt10 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENCLR_Register use record + STARTED at 0 range 0 .. 0; + END_k at 0 range 1 .. 1; + DONE at 0 range 2 .. 2; + RESULTDONE at 0 range 3 .. 3; + CALIBRATEDONE at 0 range 4 .. 4; + STOPPED at 0 range 5 .. 5; + CH0LIMITH at 0 range 6 .. 6; + CH0LIMITL at 0 range 7 .. 7; + CH1LIMITH at 0 range 8 .. 8; + CH1LIMITL at 0 range 9 .. 9; + CH2LIMITH at 0 range 10 .. 10; + CH2LIMITL at 0 range 11 .. 11; + CH3LIMITH at 0 range 12 .. 12; + CH3LIMITL at 0 range 13 .. 13; + CH4LIMITH at 0 range 14 .. 14; + CH4LIMITL at 0 range 15 .. 15; + CH5LIMITH at 0 range 16 .. 16; + CH5LIMITL at 0 range 17 .. 17; + CH6LIMITH at 0 range 18 .. 18; + CH6LIMITL at 0 range 19 .. 19; + CH7LIMITH at 0 range 20 .. 20; + CH7LIMITL at 0 range 21 .. 21; + Reserved_22_31 at 0 range 22 .. 31; + end record; + + -- Status + type STATUS_STATUS_Field is + (-- ADC is ready. No on-going conversion. + Ready, + -- ADC is busy. Conversion in progress. + Busy) + with Size => 1; + for STATUS_STATUS_Field use + (Ready => 0, + Busy => 1); + + -- Status + type STATUS_Register is record + -- Read-only. Status + STATUS : STATUS_STATUS_Field; + -- unspecified + Reserved_1_31 : HAL.UInt31; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for STATUS_Register use record + STATUS at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Enable or disable ADC + type ENABLE_ENABLE_Field is + (-- Disable ADC + Disabled, + -- Enable ADC + Enabled) + with Size => 1; + for ENABLE_ENABLE_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable ADC + type ENABLE_Register is record + -- Enable or disable ADC + ENABLE : ENABLE_ENABLE_Field := NRF_SVD.SAADC.Disabled; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ENABLE_Register use record + ENABLE at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + ---------------------------- + -- CH cluster's Registers -- + ---------------------------- + + -- Analog positive input channel + type PSELP_PSELP_Field is + (-- Not connected + Nc, + -- AIN0 + Analoginput0, + -- AIN1 + Analoginput1, + -- AIN2 + Analoginput2, + -- AIN3 + Analoginput3, + -- AIN4 + Analoginput4, + -- AIN5 + Analoginput5, + -- AIN6 + Analoginput6, + -- AIN7 + Analoginput7, + -- VDD + Vdd) + with Size => 5; + for PSELP_PSELP_Field use + (Nc => 0, + Analoginput0 => 1, + Analoginput1 => 2, + Analoginput2 => 3, + Analoginput3 => 4, + Analoginput4 => 5, + Analoginput5 => 6, + Analoginput6 => 7, + Analoginput7 => 8, + Vdd => 9); + + -- Description cluster[0]: Input positive pin selection for CH[0] + type PSELP_CH_Register is record + -- Analog positive input channel + PSELP : PSELP_PSELP_Field := NRF_SVD.SAADC.Nc; + -- unspecified + Reserved_5_31 : HAL.UInt27 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PSELP_CH_Register use record + PSELP at 0 range 0 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + -- Analog negative input, enables differential channel + type PSELN_PSELN_Field is + (-- Not connected + Nc, + -- AIN0 + Analoginput0, + -- AIN1 + Analoginput1, + -- AIN2 + Analoginput2, + -- AIN3 + Analoginput3, + -- AIN4 + Analoginput4, + -- AIN5 + Analoginput5, + -- AIN6 + Analoginput6, + -- AIN7 + Analoginput7, + -- VDD + Vdd) + with Size => 5; + for PSELN_PSELN_Field use + (Nc => 0, + Analoginput0 => 1, + Analoginput1 => 2, + Analoginput2 => 3, + Analoginput3 => 4, + Analoginput4 => 5, + Analoginput5 => 6, + Analoginput6 => 7, + Analoginput7 => 8, + Vdd => 9); + + -- Description cluster[0]: Input negative pin selection for CH[0] + type PSELN_CH_Register is record + -- Analog negative input, enables differential channel + PSELN : PSELN_PSELN_Field := NRF_SVD.SAADC.Nc; + -- unspecified + Reserved_5_31 : HAL.UInt27 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PSELN_CH_Register use record + PSELN at 0 range 0 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + -- Positive channel resistor control + type CONFIG_RESP_Field is + (-- Bypass resistor ladder + Bypass, + -- Pull-down to GND + Pulldown, + -- Pull-up to VDD + Pullup, + -- Set input at VDD/2 + Vdd1_2) + with Size => 2; + for CONFIG_RESP_Field use + (Bypass => 0, + Pulldown => 1, + Pullup => 2, + Vdd1_2 => 3); + + -- Negative channel resistor control + type CONFIG_RESN_Field is + (-- Bypass resistor ladder + Bypass, + -- Pull-down to GND + Pulldown, + -- Pull-up to VDD + Pullup, + -- Set input at VDD/2 + Vdd1_2) + with Size => 2; + for CONFIG_RESN_Field use + (Bypass => 0, + Pulldown => 1, + Pullup => 2, + Vdd1_2 => 3); + + -- Gain control + type CONFIG_GAIN_Field is + (-- 1/6 + Gain1_6, + -- 1/5 + Gain1_5, + -- 1/4 + Gain1_4, + -- 1/3 + Gain1_3, + -- 1/2 + Gain1_2, + -- 1 + Gain1, + -- 2 + Gain2, + -- 4 + Gain4) + with Size => 3; + for CONFIG_GAIN_Field use + (Gain1_6 => 0, + Gain1_5 => 1, + Gain1_4 => 2, + Gain1_3 => 3, + Gain1_2 => 4, + Gain1 => 5, + Gain2 => 6, + Gain4 => 7); + + -- Reference control + type CONFIG_REFSEL_Field is + (-- Internal reference (0.6 V) + Internal, + -- VDD/4 as reference + Vdd1_4) + with Size => 1; + for CONFIG_REFSEL_Field use + (Internal => 0, + Vdd1_4 => 1); + + -- Acquisition time, the time the ADC uses to sample the input voltage + type CONFIG_TACQ_Field is + (-- 3 us + Val_3US, + -- 5 us + Val_5US, + -- 10 us + Val_10US, + -- 15 us + Val_15US, + -- 20 us + Val_20US, + -- 40 us + Val_40US) + with Size => 3; + for CONFIG_TACQ_Field use + (Val_3US => 0, + Val_5US => 1, + Val_10US => 2, + Val_15US => 3, + Val_20US => 4, + Val_40US => 5); + + -- Enable differential mode + type CONFIG_MODE_Field is + (-- Single ended, PSELN will be ignored, negative input to ADC shorted to GND + Se, + -- Differential + Diff) + with Size => 1; + for CONFIG_MODE_Field use + (Se => 0, + Diff => 1); + + -- Enable burst mode + type CONFIG_BURST_Field is + (-- Burst mode is disabled (normal operation) + Disabled, + -- Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast +-- as it can, and sends the average to Data RAM. + Enabled) + with Size => 1; + for CONFIG_BURST_Field use + (Disabled => 0, + Enabled => 1); + + -- Description cluster[0]: Input configuration for CH[0] + type CONFIG_CH_Register is record + -- Positive channel resistor control + RESP : CONFIG_RESP_Field := NRF_SVD.SAADC.Bypass; + -- unspecified + Reserved_2_3 : HAL.UInt2 := 16#0#; + -- Negative channel resistor control + RESN : CONFIG_RESN_Field := NRF_SVD.SAADC.Bypass; + -- unspecified + Reserved_6_7 : HAL.UInt2 := 16#0#; + -- Gain control + GAIN : CONFIG_GAIN_Field := NRF_SVD.SAADC.Gain1_6; + -- unspecified + Reserved_11_11 : HAL.Bit := 16#0#; + -- Reference control + REFSEL : CONFIG_REFSEL_Field := NRF_SVD.SAADC.Internal; + -- unspecified + Reserved_13_15 : HAL.UInt3 := 16#0#; + -- Acquisition time, the time the ADC uses to sample the input voltage + TACQ : CONFIG_TACQ_Field := NRF_SVD.SAADC.Val_10US; + -- unspecified + Reserved_19_19 : HAL.Bit := 16#0#; + -- Enable differential mode + MODE : CONFIG_MODE_Field := NRF_SVD.SAADC.Se; + -- unspecified + Reserved_21_23 : HAL.UInt3 := 16#0#; + -- Enable burst mode + BURST : CONFIG_BURST_Field := NRF_SVD.SAADC.Disabled; + -- unspecified + Reserved_25_31 : HAL.UInt7 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CONFIG_CH_Register use record + RESP at 0 range 0 .. 1; + Reserved_2_3 at 0 range 2 .. 3; + RESN at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + GAIN at 0 range 8 .. 10; + Reserved_11_11 at 0 range 11 .. 11; + REFSEL at 0 range 12 .. 12; + Reserved_13_15 at 0 range 13 .. 15; + TACQ at 0 range 16 .. 18; + Reserved_19_19 at 0 range 19 .. 19; + MODE at 0 range 20 .. 20; + Reserved_21_23 at 0 range 21 .. 23; + BURST at 0 range 24 .. 24; + Reserved_25_31 at 0 range 25 .. 31; + end record; + + subtype LIMIT_CH_LOW_Field is HAL.UInt16; + subtype LIMIT_CH_HIGH_Field is HAL.UInt16; + + -- Description cluster[0]: High/low limits for event monitoring a channel + type LIMIT_CH_Register is record + -- Low level limit + LOW : LIMIT_CH_LOW_Field := 16#8000#; + -- High level limit + HIGH : LIMIT_CH_HIGH_Field := 16#7FFF#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for LIMIT_CH_Register use record + LOW at 0 range 0 .. 15; + HIGH at 0 range 16 .. 31; + end record; + + -- Unspecified + type CH_Cluster is record + -- Description cluster[0]: Input positive pin selection for CH[0] + PSELP : aliased PSELP_CH_Register; + -- Description cluster[0]: Input negative pin selection for CH[0] + PSELN : aliased PSELN_CH_Register; + -- Description cluster[0]: Input configuration for CH[0] + CONFIG : aliased CONFIG_CH_Register; + -- Description cluster[0]: High/low limits for event monitoring a + -- channel + LIMIT : aliased LIMIT_CH_Register; + end record + with Size => 128; + + for CH_Cluster use record + PSELP at 16#0# range 0 .. 31; + PSELN at 16#4# range 0 .. 31; + CONFIG at 16#8# range 0 .. 31; + LIMIT at 16#C# range 0 .. 31; + end record; + + -- Unspecified + type CH_Clusters is array (0 .. 7) of CH_Cluster; + + -- Set the resolution + type RESOLUTION_VAL_Field is + (-- 8 bit + Val_8BIT, + -- 10 bit + Val_10BIT, + -- 12 bit + Val_12BIT, + -- 14 bit + Val_14BIT) + with Size => 3; + for RESOLUTION_VAL_Field use + (Val_8BIT => 0, + Val_10BIT => 1, + Val_12BIT => 2, + Val_14BIT => 3); + + -- Resolution configuration + type RESOLUTION_Register is record + -- Set the resolution + VAL : RESOLUTION_VAL_Field := NRF_SVD.SAADC.Val_10BIT; + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RESOLUTION_Register use record + VAL at 0 range 0 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + -- Oversample control + type OVERSAMPLE_OVERSAMPLE_Field is + (-- Bypass oversampling + Bypass, + -- Oversample 2x + Over2X, + -- Oversample 4x + Over4X, + -- Oversample 8x + Over8X, + -- Oversample 16x + Over16X, + -- Oversample 32x + Over32X, + -- Oversample 64x + Over64X, + -- Oversample 128x + Over128X, + -- Oversample 256x + Over256X) + with Size => 4; + for OVERSAMPLE_OVERSAMPLE_Field use + (Bypass => 0, + Over2X => 1, + Over4X => 2, + Over8X => 3, + Over16X => 4, + Over32X => 5, + Over64X => 6, + Over128X => 7, + Over256X => 8); + + -- Oversampling configuration. OVERSAMPLE should not be combined with SCAN. + -- The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a + -- higher RESOLUTION should be used. + type OVERSAMPLE_Register is record + -- Oversample control + OVERSAMPLE : OVERSAMPLE_OVERSAMPLE_Field := NRF_SVD.SAADC.Bypass; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for OVERSAMPLE_Register use record + OVERSAMPLE at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + subtype SAMPLERATE_CC_Field is HAL.UInt11; + + -- Select mode for sample rate control + type SAMPLERATE_MODE_Field is + (-- Rate is controlled from SAMPLE task + Task_k, + -- Rate is controlled from local timer (use CC to control the rate) + Timers) + with Size => 1; + for SAMPLERATE_MODE_Field use + (Task_k => 0, + Timers => 1); + + -- Controls normal or continuous sample rate + type SAMPLERATE_Register is record + -- Capture and compare value. Sample rate is 16 MHz/CC + CC : SAMPLERATE_CC_Field := 16#0#; + -- unspecified + Reserved_11_11 : HAL.Bit := 16#0#; + -- Select mode for sample rate control + MODE : SAMPLERATE_MODE_Field := NRF_SVD.SAADC.Task_k; + -- unspecified + Reserved_13_31 : HAL.UInt19 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SAMPLERATE_Register use record + CC at 0 range 0 .. 10; + Reserved_11_11 at 0 range 11 .. 11; + MODE at 0 range 12 .. 12; + Reserved_13_31 at 0 range 13 .. 31; + end record; + + -------------------------------- + -- RESULT cluster's Registers -- + -------------------------------- + + subtype MAXCNT_RESULT_MAXCNT_Field is HAL.UInt15; + + -- Maximum number of buffer words to transfer + type MAXCNT_RESULT_Register is record + -- Maximum number of buffer words to transfer + MAXCNT : MAXCNT_RESULT_MAXCNT_Field := 16#0#; + -- unspecified + Reserved_15_31 : HAL.UInt17 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MAXCNT_RESULT_Register use record + MAXCNT at 0 range 0 .. 14; + Reserved_15_31 at 0 range 15 .. 31; + end record; + + subtype AMOUNT_RESULT_AMOUNT_Field is HAL.UInt15; + + -- Number of buffer words transferred since last START + type AMOUNT_RESULT_Register is record + -- Read-only. Number of buffer words transferred since last START. This + -- register can be read after an END or STOPPED event. + AMOUNT : AMOUNT_RESULT_AMOUNT_Field; + -- unspecified + Reserved_15_31 : HAL.UInt17; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for AMOUNT_RESULT_Register use record + AMOUNT at 0 range 0 .. 14; + Reserved_15_31 at 0 range 15 .. 31; + end record; + + -- RESULT EasyDMA channel + type RESULT_Cluster is record + -- Data pointer + PTR : aliased HAL.UInt32; + -- Maximum number of buffer words to transfer + MAXCNT : aliased MAXCNT_RESULT_Register; + -- Number of buffer words transferred since last START + AMOUNT : aliased AMOUNT_RESULT_Register; + end record + with Size => 96; + + for RESULT_Cluster use record + PTR at 16#0# range 0 .. 31; + MAXCNT at 16#4# range 0 .. 31; + AMOUNT at 16#8# range 0 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Analog to Digital Converter + type SAADC_Peripheral is record + -- Start the ADC and prepare the result buffer in RAM + TASKS_START : aliased HAL.UInt32; + -- Take one ADC sample, if scan is enabled all channels are sampled + TASKS_SAMPLE : aliased HAL.UInt32; + -- Stop the ADC and terminate any on-going conversion + TASKS_STOP : aliased HAL.UInt32; + -- Starts offset auto-calibration + TASKS_CALIBRATEOFFSET : aliased HAL.UInt32; + -- The ADC has started + EVENTS_STARTED : aliased HAL.UInt32; + -- The ADC has filled up the Result buffer + EVENTS_END : aliased HAL.UInt32; + -- A conversion task has been completed. Depending on the mode, multiple + -- conversions might be needed for a result to be transferred to RAM. + EVENTS_DONE : aliased HAL.UInt32; + -- A result is ready to get transferred to RAM. + EVENTS_RESULTDONE : aliased HAL.UInt32; + -- Calibration is complete + EVENTS_CALIBRATEDONE : aliased HAL.UInt32; + -- The ADC has stopped + EVENTS_STOPPED : aliased HAL.UInt32; + -- Unspecified + EVENTS_CH : aliased EVENTS_CH_Clusters; + -- Enable or disable interrupt + INTEN : aliased INTEN_Register; + -- Enable interrupt + INTENSET : aliased INTENSET_Register; + -- Disable interrupt + INTENCLR : aliased INTENCLR_Register; + -- Status + STATUS : aliased STATUS_Register; + -- Enable or disable ADC + ENABLE : aliased ENABLE_Register; + -- Unspecified + CH : aliased CH_Clusters; + -- Resolution configuration + RESOLUTION : aliased RESOLUTION_Register; + -- Oversampling configuration. OVERSAMPLE should not be combined with + -- SCAN. The RESOLUTION is applied before averaging, thus for high + -- OVERSAMPLE a higher RESOLUTION should be used. + OVERSAMPLE : aliased OVERSAMPLE_Register; + -- Controls normal or continuous sample rate + SAMPLERATE : aliased SAMPLERATE_Register; + -- RESULT EasyDMA channel + RESULT : aliased RESULT_Cluster; + end record + with Volatile; + + for SAADC_Peripheral use record + TASKS_START at 16#0# range 0 .. 31; + TASKS_SAMPLE at 16#4# range 0 .. 31; + TASKS_STOP at 16#8# range 0 .. 31; + TASKS_CALIBRATEOFFSET at 16#C# range 0 .. 31; + EVENTS_STARTED at 16#100# range 0 .. 31; + EVENTS_END at 16#104# range 0 .. 31; + EVENTS_DONE at 16#108# range 0 .. 31; + EVENTS_RESULTDONE at 16#10C# range 0 .. 31; + EVENTS_CALIBRATEDONE at 16#110# range 0 .. 31; + EVENTS_STOPPED at 16#114# range 0 .. 31; + EVENTS_CH at 16#118# range 0 .. 511; + INTEN at 16#300# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + STATUS at 16#400# range 0 .. 31; + ENABLE at 16#500# range 0 .. 31; + CH at 16#510# range 0 .. 1023; + RESOLUTION at 16#5F0# range 0 .. 31; + OVERSAMPLE at 16#5F4# range 0 .. 31; + SAMPLERATE at 16#5F8# range 0 .. 31; + RESULT at 16#62C# range 0 .. 95; + end record; + + -- Analog to Digital Converter + SAADC_Periph : aliased SAADC_Peripheral + with Import, Address => SAADC_Base; + +end NRF_SVD.SAADC; diff --git a/arch/ARM/Nordic/svd/nrf52/nrf_svd-spi.ads b/arch/ARM/Nordic/svd/nrf52/nrf_svd-spi.ads new file mode 100644 index 000000000..edb1c575c --- /dev/null +++ b/arch/ARM/Nordic/svd/nrf52/nrf_svd-spi.ads @@ -0,0 +1,307 @@ +-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- 2. Redistributions in binary form, except as embedded into a Nordic +-- Semiconductor ASA integrated circuit in a product or a software update for +-- such product, must reproduce the above copyright notice, this list of +-- conditions and the following disclaimer in the documentation and/or other +-- materials provided with the distribution. +-- +-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from this +-- software without specific prior written permission. +-- +-- 4. This software, with or without modification, must only be used with a +-- Nordic Semiconductor ASA integrated circuit. +-- +-- 5. Any software provided in binary form under this license must not be reverse +-- engineered, decompiled, modified and/or disassembled. +-- +-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +-- OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + +-- This spec has been automatically generated from nrf52.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package NRF_SVD.SPI is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Write '1' to Enable interrupt for READY event + type INTENSET_READY_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_READY_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for READY event + type INTENSET_READY_Field_1 is + (-- Reset value for the field + Intenset_Ready_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_READY_Field_1 use + (Intenset_Ready_Field_Reset => 0, + Set => 1); + + -- Enable interrupt + type INTENSET_Register is record + -- unspecified + Reserved_0_1 : HAL.UInt2 := 16#0#; + -- Write '1' to Enable interrupt for READY event + READY : INTENSET_READY_Field_1 := Intenset_Ready_Field_Reset; + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENSET_Register use record + Reserved_0_1 at 0 range 0 .. 1; + READY at 0 range 2 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + -- Write '1' to Disable interrupt for READY event + type INTENCLR_READY_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_READY_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for READY event + type INTENCLR_READY_Field_1 is + (-- Reset value for the field + Intenclr_Ready_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_READY_Field_1 use + (Intenclr_Ready_Field_Reset => 0, + Clear => 1); + + -- Disable interrupt + type INTENCLR_Register is record + -- unspecified + Reserved_0_1 : HAL.UInt2 := 16#0#; + -- Write '1' to Disable interrupt for READY event + READY : INTENCLR_READY_Field_1 := Intenclr_Ready_Field_Reset; + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENCLR_Register use record + Reserved_0_1 at 0 range 0 .. 1; + READY at 0 range 2 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + -- Enable or disable SPI + type ENABLE_ENABLE_Field is + (-- Disable SPI + Disabled, + -- Enable SPI + Enabled) + with Size => 4; + for ENABLE_ENABLE_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable SPI + type ENABLE_Register is record + -- Enable or disable SPI + ENABLE : ENABLE_ENABLE_Field := NRF_SVD.SPI.Disabled; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ENABLE_Register use record + ENABLE at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + subtype RXD_RXD_Field is HAL.UInt8; + + -- RXD register + type RXD_Register is record + -- Read-only. *** Reading this field has side effects on other resources + -- ***. RX data received. Double buffered + RXD : RXD_RXD_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RXD_Register use record + RXD at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype TXD_TXD_Field is HAL.UInt8; + + -- TXD register + type TXD_Register is record + -- TX data to send. Double buffered + TXD : TXD_TXD_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TXD_Register use record + TXD at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- Bit order + type CONFIG_ORDER_Field is + (-- Most significant bit shifted out first + Msbfirst, + -- Least significant bit shifted out first + Lsbfirst) + with Size => 1; + for CONFIG_ORDER_Field use + (Msbfirst => 0, + Lsbfirst => 1); + + -- Serial clock (SCK) phase + type CONFIG_CPHA_Field is + (-- Sample on leading edge of clock, shift serial data on trailing edge + Leading, + -- Sample on trailing edge of clock, shift serial data on leading edge + Trailing) + with Size => 1; + for CONFIG_CPHA_Field use + (Leading => 0, + Trailing => 1); + + -- Serial clock (SCK) polarity + type CONFIG_CPOL_Field is + (-- Active high + Activehigh, + -- Active low + Activelow) + with Size => 1; + for CONFIG_CPOL_Field use + (Activehigh => 0, + Activelow => 1); + + -- Configuration register + type CONFIG_Register is record + -- Bit order + ORDER : CONFIG_ORDER_Field := NRF_SVD.SPI.Msbfirst; + -- Serial clock (SCK) phase + CPHA : CONFIG_CPHA_Field := NRF_SVD.SPI.Leading; + -- Serial clock (SCK) polarity + CPOL : CONFIG_CPOL_Field := NRF_SVD.SPI.Activehigh; + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CONFIG_Register use record + ORDER at 0 range 0 .. 0; + CPHA at 0 range 1 .. 1; + CPOL at 0 range 2 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Serial Peripheral Interface 0 + type SPI_Peripheral is record + -- TXD byte sent and RXD byte received + EVENTS_READY : aliased HAL.UInt32; + -- Enable interrupt + INTENSET : aliased INTENSET_Register; + -- Disable interrupt + INTENCLR : aliased INTENCLR_Register; + -- Enable SPI + ENABLE : aliased ENABLE_Register; + -- Pin select for SCK. + PSELSCK : aliased HAL.UInt32; + -- Pin select for MISO. + PSELMISO : aliased HAL.UInt32; + -- Pin select for MOSI. + PSELMOSI : aliased HAL.UInt32; + -- RXD register + RXD : aliased RXD_Register; + -- TXD register + TXD : aliased TXD_Register; + -- SPI frequency + FREQUENCY : aliased HAL.UInt32; + -- Configuration register + CONFIG : aliased CONFIG_Register; + end record + with Volatile; + + for SPI_Peripheral use record + EVENTS_READY at 16#108# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + ENABLE at 16#500# range 0 .. 31; + PSELSCK at 16#508# range 0 .. 31; + PSELMISO at 16#50C# range 0 .. 31; + PSELMOSI at 16#510# range 0 .. 31; + RXD at 16#518# range 0 .. 31; + TXD at 16#51C# range 0 .. 31; + FREQUENCY at 16#524# range 0 .. 31; + CONFIG at 16#554# range 0 .. 31; + end record; + + -- Serial Peripheral Interface 0 + SPI0_Periph : aliased SPI_Peripheral + with Import, Address => SPI0_Base; + + -- Serial Peripheral Interface 1 + SPI1_Periph : aliased SPI_Peripheral + with Import, Address => SPI1_Base; + + -- Serial Peripheral Interface 2 + SPI2_Periph : aliased SPI_Peripheral + with Import, Address => SPI2_Base; + +end NRF_SVD.SPI; diff --git a/arch/ARM/Nordic/svd/nrf52/nrf_svd-spim.ads b/arch/ARM/Nordic/svd/nrf52/nrf_svd-spim.ads new file mode 100644 index 000000000..85f29c307 --- /dev/null +++ b/arch/ARM/Nordic/svd/nrf52/nrf_svd-spim.ads @@ -0,0 +1,868 @@ +-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- 2. Redistributions in binary form, except as embedded into a Nordic +-- Semiconductor ASA integrated circuit in a product or a software update for +-- such product, must reproduce the above copyright notice, this list of +-- conditions and the following disclaimer in the documentation and/or other +-- materials provided with the distribution. +-- +-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from this +-- software without specific prior written permission. +-- +-- 4. This software, with or without modification, must only be used with a +-- Nordic Semiconductor ASA integrated circuit. +-- +-- 5. Any software provided in binary form under this license must not be reverse +-- engineered, decompiled, modified and/or disassembled. +-- +-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +-- OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + +-- This spec has been automatically generated from nrf52.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package NRF_SVD.SPIM is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Shortcut between END event and START task + type SHORTS_END_START_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_END_START_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut register + type SHORTS_Register is record + -- unspecified + Reserved_0_16 : HAL.UInt17 := 16#0#; + -- Shortcut between END event and START task + END_START : SHORTS_END_START_Field := NRF_SVD.SPIM.Disabled; + -- unspecified + Reserved_18_31 : HAL.UInt14 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SHORTS_Register use record + Reserved_0_16 at 0 range 0 .. 16; + END_START at 0 range 17 .. 17; + Reserved_18_31 at 0 range 18 .. 31; + end record; + + -- Write '1' to Enable interrupt for STOPPED event + type INTENSET_STOPPED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_STOPPED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for STOPPED event + type INTENSET_STOPPED_Field_1 is + (-- Reset value for the field + Intenset_Stopped_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_STOPPED_Field_1 use + (Intenset_Stopped_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for ENDRX event + type INTENSET_ENDRX_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_ENDRX_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for ENDRX event + type INTENSET_ENDRX_Field_1 is + (-- Reset value for the field + Intenset_Endrx_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_ENDRX_Field_1 use + (Intenset_Endrx_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for END event + type INTENSET_END_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_END_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for END event + type INTENSET_END_Field_1 is + (-- Reset value for the field + Intenset_End_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_END_Field_1 use + (Intenset_End_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for ENDTX event + type INTENSET_ENDTX_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_ENDTX_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for ENDTX event + type INTENSET_ENDTX_Field_1 is + (-- Reset value for the field + Intenset_Endtx_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_ENDTX_Field_1 use + (Intenset_Endtx_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for STARTED event + type INTENSET_STARTED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_STARTED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for STARTED event + type INTENSET_STARTED_Field_1 is + (-- Reset value for the field + Intenset_Started_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_STARTED_Field_1 use + (Intenset_Started_Field_Reset => 0, + Set => 1); + + -- Enable interrupt + type INTENSET_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#0#; + -- Write '1' to Enable interrupt for STOPPED event + STOPPED : INTENSET_STOPPED_Field_1 := + Intenset_Stopped_Field_Reset; + -- unspecified + Reserved_2_3 : HAL.UInt2 := 16#0#; + -- Write '1' to Enable interrupt for ENDRX event + ENDRX : INTENSET_ENDRX_Field_1 := Intenset_Endrx_Field_Reset; + -- unspecified + Reserved_5_5 : HAL.Bit := 16#0#; + -- Write '1' to Enable interrupt for END event + END_k : INTENSET_END_Field_1 := Intenset_End_Field_Reset; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- Write '1' to Enable interrupt for ENDTX event + ENDTX : INTENSET_ENDTX_Field_1 := Intenset_Endtx_Field_Reset; + -- unspecified + Reserved_9_18 : HAL.UInt10 := 16#0#; + -- Write '1' to Enable interrupt for STARTED event + STARTED : INTENSET_STARTED_Field_1 := + Intenset_Started_Field_Reset; + -- unspecified + Reserved_20_31 : HAL.UInt12 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENSET_Register use record + Reserved_0_0 at 0 range 0 .. 0; + STOPPED at 0 range 1 .. 1; + Reserved_2_3 at 0 range 2 .. 3; + ENDRX at 0 range 4 .. 4; + Reserved_5_5 at 0 range 5 .. 5; + END_k at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + ENDTX at 0 range 8 .. 8; + Reserved_9_18 at 0 range 9 .. 18; + STARTED at 0 range 19 .. 19; + Reserved_20_31 at 0 range 20 .. 31; + end record; + + -- Write '1' to Disable interrupt for STOPPED event + type INTENCLR_STOPPED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_STOPPED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for STOPPED event + type INTENCLR_STOPPED_Field_1 is + (-- Reset value for the field + Intenclr_Stopped_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_STOPPED_Field_1 use + (Intenclr_Stopped_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for ENDRX event + type INTENCLR_ENDRX_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_ENDRX_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for ENDRX event + type INTENCLR_ENDRX_Field_1 is + (-- Reset value for the field + Intenclr_Endrx_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_ENDRX_Field_1 use + (Intenclr_Endrx_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for END event + type INTENCLR_END_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_END_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for END event + type INTENCLR_END_Field_1 is + (-- Reset value for the field + Intenclr_End_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_END_Field_1 use + (Intenclr_End_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for ENDTX event + type INTENCLR_ENDTX_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_ENDTX_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for ENDTX event + type INTENCLR_ENDTX_Field_1 is + (-- Reset value for the field + Intenclr_Endtx_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_ENDTX_Field_1 use + (Intenclr_Endtx_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for STARTED event + type INTENCLR_STARTED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_STARTED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for STARTED event + type INTENCLR_STARTED_Field_1 is + (-- Reset value for the field + Intenclr_Started_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_STARTED_Field_1 use + (Intenclr_Started_Field_Reset => 0, + Clear => 1); + + -- Disable interrupt + type INTENCLR_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#0#; + -- Write '1' to Disable interrupt for STOPPED event + STOPPED : INTENCLR_STOPPED_Field_1 := + Intenclr_Stopped_Field_Reset; + -- unspecified + Reserved_2_3 : HAL.UInt2 := 16#0#; + -- Write '1' to Disable interrupt for ENDRX event + ENDRX : INTENCLR_ENDRX_Field_1 := Intenclr_Endrx_Field_Reset; + -- unspecified + Reserved_5_5 : HAL.Bit := 16#0#; + -- Write '1' to Disable interrupt for END event + END_k : INTENCLR_END_Field_1 := Intenclr_End_Field_Reset; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- Write '1' to Disable interrupt for ENDTX event + ENDTX : INTENCLR_ENDTX_Field_1 := Intenclr_Endtx_Field_Reset; + -- unspecified + Reserved_9_18 : HAL.UInt10 := 16#0#; + -- Write '1' to Disable interrupt for STARTED event + STARTED : INTENCLR_STARTED_Field_1 := + Intenclr_Started_Field_Reset; + -- unspecified + Reserved_20_31 : HAL.UInt12 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENCLR_Register use record + Reserved_0_0 at 0 range 0 .. 0; + STOPPED at 0 range 1 .. 1; + Reserved_2_3 at 0 range 2 .. 3; + ENDRX at 0 range 4 .. 4; + Reserved_5_5 at 0 range 5 .. 5; + END_k at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + ENDTX at 0 range 8 .. 8; + Reserved_9_18 at 0 range 9 .. 18; + STARTED at 0 range 19 .. 19; + Reserved_20_31 at 0 range 20 .. 31; + end record; + + -- Enable or disable SPIM + type ENABLE_ENABLE_Field is + (-- Disable SPIM + Disabled, + -- Enable SPIM + Enabled) + with Size => 4; + for ENABLE_ENABLE_Field use + (Disabled => 0, + Enabled => 7); + + -- Enable SPIM + type ENABLE_Register is record + -- Enable or disable SPIM + ENABLE : ENABLE_ENABLE_Field := NRF_SVD.SPIM.Disabled; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ENABLE_Register use record + ENABLE at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + ----------------------------------- + -- SPIM_PSEL cluster's Registers -- + ----------------------------------- + + subtype SCK_PSEL_PIN_Field is HAL.UInt5; + + -- Connection + type SCK_CONNECT_Field is + (-- Connect + Connected, + -- Disconnect + Disconnected) + with Size => 1; + for SCK_CONNECT_Field use + (Connected => 0, + Disconnected => 1); + + -- Pin select for SCK + type SCK_PSEL_Register is record + -- Pin number + PIN : SCK_PSEL_PIN_Field := 16#1F#; + -- unspecified + Reserved_5_30 : HAL.UInt26 := 16#3FFFFFF#; + -- Connection + CONNECT : SCK_CONNECT_Field := NRF_SVD.SPIM.Disconnected; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SCK_PSEL_Register use record + PIN at 0 range 0 .. 4; + Reserved_5_30 at 0 range 5 .. 30; + CONNECT at 0 range 31 .. 31; + end record; + + subtype MOSI_PSEL_PIN_Field is HAL.UInt5; + + -- Connection + type MOSI_CONNECT_Field is + (-- Connect + Connected, + -- Disconnect + Disconnected) + with Size => 1; + for MOSI_CONNECT_Field use + (Connected => 0, + Disconnected => 1); + + -- Pin select for MOSI signal + type MOSI_PSEL_Register is record + -- Pin number + PIN : MOSI_PSEL_PIN_Field := 16#1F#; + -- unspecified + Reserved_5_30 : HAL.UInt26 := 16#3FFFFFF#; + -- Connection + CONNECT : MOSI_CONNECT_Field := NRF_SVD.SPIM.Disconnected; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MOSI_PSEL_Register use record + PIN at 0 range 0 .. 4; + Reserved_5_30 at 0 range 5 .. 30; + CONNECT at 0 range 31 .. 31; + end record; + + subtype MISO_PSEL_PIN_Field is HAL.UInt5; + + -- Connection + type MISO_CONNECT_Field is + (-- Connect + Connected, + -- Disconnect + Disconnected) + with Size => 1; + for MISO_CONNECT_Field use + (Connected => 0, + Disconnected => 1); + + -- Pin select for MISO signal + type MISO_PSEL_Register is record + -- Pin number + PIN : MISO_PSEL_PIN_Field := 16#1F#; + -- unspecified + Reserved_5_30 : HAL.UInt26 := 16#3FFFFFF#; + -- Connection + CONNECT : MISO_CONNECT_Field := NRF_SVD.SPIM.Disconnected; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MISO_PSEL_Register use record + PIN at 0 range 0 .. 4; + Reserved_5_30 at 0 range 5 .. 30; + CONNECT at 0 range 31 .. 31; + end record; + + -- Unspecified + type SPIM_PSEL_Cluster is record + -- Pin select for SCK + SCK : aliased SCK_PSEL_Register; + -- Pin select for MOSI signal + MOSI : aliased MOSI_PSEL_Register; + -- Pin select for MISO signal + MISO : aliased MISO_PSEL_Register; + end record + with Size => 96; + + for SPIM_PSEL_Cluster use record + SCK at 16#0# range 0 .. 31; + MOSI at 16#4# range 0 .. 31; + MISO at 16#8# range 0 .. 31; + end record; + + ---------------------------------- + -- SPIM_RXD cluster's Registers -- + ---------------------------------- + + subtype MAXCNT_RXD_MAXCNT_Field is HAL.UInt8; + + -- Maximum number of bytes in receive buffer + type MAXCNT_RXD_Register is record + -- Maximum number of bytes in receive buffer + MAXCNT : MAXCNT_RXD_MAXCNT_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MAXCNT_RXD_Register use record + MAXCNT at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype AMOUNT_RXD_AMOUNT_Field is HAL.UInt8; + + -- Number of bytes transferred in the last transaction + type AMOUNT_RXD_Register is record + -- Read-only. Number of bytes transferred in the last transaction + AMOUNT : AMOUNT_RXD_AMOUNT_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for AMOUNT_RXD_Register use record + AMOUNT at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- List type + type LIST_LIST_Field is + (-- Disable EasyDMA list + Disabled, + -- Use array list + Arraylist) + with Size => 3; + for LIST_LIST_Field use + (Disabled => 0, + Arraylist => 1); + + -- EasyDMA list type + type LIST_RXD_Register is record + -- List type + LIST : LIST_LIST_Field := NRF_SVD.SPIM.Disabled; + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for LIST_RXD_Register use record + LIST at 0 range 0 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + -- RXD EasyDMA channel + type SPIM_RXD_Cluster is record + -- Data pointer + PTR : aliased HAL.UInt32; + -- Maximum number of bytes in receive buffer + MAXCNT : aliased MAXCNT_RXD_Register; + -- Number of bytes transferred in the last transaction + AMOUNT : aliased AMOUNT_RXD_Register; + -- EasyDMA list type + LIST : aliased LIST_RXD_Register; + end record + with Size => 128; + + for SPIM_RXD_Cluster use record + PTR at 16#0# range 0 .. 31; + MAXCNT at 16#4# range 0 .. 31; + AMOUNT at 16#8# range 0 .. 31; + LIST at 16#C# range 0 .. 31; + end record; + + ---------------------------------- + -- SPIM_TXD cluster's Registers -- + ---------------------------------- + + subtype MAXCNT_TXD_MAXCNT_Field is HAL.UInt8; + + -- Maximum number of bytes in transmit buffer + type MAXCNT_TXD_Register is record + -- Maximum number of bytes in transmit buffer + MAXCNT : MAXCNT_TXD_MAXCNT_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MAXCNT_TXD_Register use record + MAXCNT at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype AMOUNT_TXD_AMOUNT_Field is HAL.UInt8; + + -- Number of bytes transferred in the last transaction + type AMOUNT_TXD_Register is record + -- Read-only. Number of bytes transferred in the last transaction + AMOUNT : AMOUNT_TXD_AMOUNT_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for AMOUNT_TXD_Register use record + AMOUNT at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- EasyDMA list type + type LIST_TXD_Register is record + -- List type + LIST : LIST_LIST_Field := NRF_SVD.SPIM.Disabled; + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for LIST_TXD_Register use record + LIST at 0 range 0 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + -- TXD EasyDMA channel + type SPIM_TXD_Cluster is record + -- Data pointer + PTR : aliased HAL.UInt32; + -- Maximum number of bytes in transmit buffer + MAXCNT : aliased MAXCNT_TXD_Register; + -- Number of bytes transferred in the last transaction + AMOUNT : aliased AMOUNT_TXD_Register; + -- EasyDMA list type + LIST : aliased LIST_TXD_Register; + end record + with Size => 128; + + for SPIM_TXD_Cluster use record + PTR at 16#0# range 0 .. 31; + MAXCNT at 16#4# range 0 .. 31; + AMOUNT at 16#8# range 0 .. 31; + LIST at 16#C# range 0 .. 31; + end record; + + -- Bit order + type CONFIG_ORDER_Field is + (-- Most significant bit shifted out first + Msbfirst, + -- Least significant bit shifted out first + Lsbfirst) + with Size => 1; + for CONFIG_ORDER_Field use + (Msbfirst => 0, + Lsbfirst => 1); + + -- Serial clock (SCK) phase + type CONFIG_CPHA_Field is + (-- Sample on leading edge of clock, shift serial data on trailing edge + Leading, + -- Sample on trailing edge of clock, shift serial data on leading edge + Trailing) + with Size => 1; + for CONFIG_CPHA_Field use + (Leading => 0, + Trailing => 1); + + -- Serial clock (SCK) polarity + type CONFIG_CPOL_Field is + (-- Active high + Activehigh, + -- Active low + Activelow) + with Size => 1; + for CONFIG_CPOL_Field use + (Activehigh => 0, + Activelow => 1); + + -- Configuration register + type CONFIG_Register is record + -- Bit order + ORDER : CONFIG_ORDER_Field := NRF_SVD.SPIM.Msbfirst; + -- Serial clock (SCK) phase + CPHA : CONFIG_CPHA_Field := NRF_SVD.SPIM.Leading; + -- Serial clock (SCK) polarity + CPOL : CONFIG_CPOL_Field := NRF_SVD.SPIM.Activehigh; + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CONFIG_Register use record + ORDER at 0 range 0 .. 0; + CPHA at 0 range 1 .. 1; + CPOL at 0 range 2 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + subtype ORC_ORC_Field is HAL.UInt8; + + -- Over-read character. Character clocked out in case and over-read of the + -- TXD buffer. + type ORC_Register is record + -- Over-read character. Character clocked out in case and over-read of + -- the TXD buffer. + ORC : ORC_ORC_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ORC_Register use record + ORC at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + ----------------------------------- + -- SPIM_PSEL cluster's Registers -- + ----------------------------------- + + ---------------------------------- + -- SPIM_RXD cluster's Registers -- + ---------------------------------- + + ---------------------------------- + -- SPIM_TXD cluster's Registers -- + ---------------------------------- + + ----------------------------------- + -- SPIM_PSEL cluster's Registers -- + ----------------------------------- + + ---------------------------------- + -- SPIM_RXD cluster's Registers -- + ---------------------------------- + + ---------------------------------- + -- SPIM_TXD cluster's Registers -- + ---------------------------------- + + ----------------- + -- Peripherals -- + ----------------- + + -- Serial Peripheral Interface Master with EasyDMA 0 + type SPIM_Peripheral is record + -- Start SPI transaction + TASKS_START : aliased HAL.UInt32; + -- Stop SPI transaction + TASKS_STOP : aliased HAL.UInt32; + -- Suspend SPI transaction + TASKS_SUSPEND : aliased HAL.UInt32; + -- Resume SPI transaction + TASKS_RESUME : aliased HAL.UInt32; + -- SPI transaction has stopped + EVENTS_STOPPED : aliased HAL.UInt32; + -- End of RXD buffer reached + EVENTS_ENDRX : aliased HAL.UInt32; + -- End of RXD buffer and TXD buffer reached + EVENTS_END : aliased HAL.UInt32; + -- End of TXD buffer reached + EVENTS_ENDTX : aliased HAL.UInt32; + -- Transaction started + EVENTS_STARTED : aliased HAL.UInt32; + -- Shortcut register + SHORTS : aliased SHORTS_Register; + -- Enable interrupt + INTENSET : aliased INTENSET_Register; + -- Disable interrupt + INTENCLR : aliased INTENCLR_Register; + -- Enable SPIM + ENABLE : aliased ENABLE_Register; + -- Unspecified + PSEL : aliased SPIM_PSEL_Cluster; + -- SPI frequency. Accuracy depends on the HFCLK source selected. + FREQUENCY : aliased HAL.UInt32; + -- RXD EasyDMA channel + RXD : aliased SPIM_RXD_Cluster; + -- TXD EasyDMA channel + TXD : aliased SPIM_TXD_Cluster; + -- Configuration register + CONFIG : aliased CONFIG_Register; + -- Over-read character. Character clocked out in case and over-read of + -- the TXD buffer. + ORC : aliased ORC_Register; + end record + with Volatile; + + for SPIM_Peripheral use record + TASKS_START at 16#10# range 0 .. 31; + TASKS_STOP at 16#14# range 0 .. 31; + TASKS_SUSPEND at 16#1C# range 0 .. 31; + TASKS_RESUME at 16#20# range 0 .. 31; + EVENTS_STOPPED at 16#104# range 0 .. 31; + EVENTS_ENDRX at 16#110# range 0 .. 31; + EVENTS_END at 16#118# range 0 .. 31; + EVENTS_ENDTX at 16#120# range 0 .. 31; + EVENTS_STARTED at 16#14C# range 0 .. 31; + SHORTS at 16#200# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + ENABLE at 16#500# range 0 .. 31; + PSEL at 16#508# range 0 .. 95; + FREQUENCY at 16#524# range 0 .. 31; + RXD at 16#534# range 0 .. 127; + TXD at 16#544# range 0 .. 127; + CONFIG at 16#554# range 0 .. 31; + ORC at 16#5C0# range 0 .. 31; + end record; + + -- Serial Peripheral Interface Master with EasyDMA 0 + SPIM0_Periph : aliased SPIM_Peripheral + with Import, Address => SPIM0_Base; + + -- Serial Peripheral Interface Master with EasyDMA 1 + SPIM1_Periph : aliased SPIM_Peripheral + with Import, Address => SPIM1_Base; + + -- Serial Peripheral Interface Master with EasyDMA 2 + SPIM2_Periph : aliased SPIM_Peripheral + with Import, Address => SPIM2_Base; + +end NRF_SVD.SPIM; diff --git a/arch/ARM/Nordic/svd/nrf52/nrf_svd-spis.ads b/arch/ARM/Nordic/svd/nrf52/nrf_svd-spis.ads new file mode 100644 index 000000000..260818fac --- /dev/null +++ b/arch/ARM/Nordic/svd/nrf52/nrf_svd-spis.ads @@ -0,0 +1,847 @@ +-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- 2. Redistributions in binary form, except as embedded into a Nordic +-- Semiconductor ASA integrated circuit in a product or a software update for +-- such product, must reproduce the above copyright notice, this list of +-- conditions and the following disclaimer in the documentation and/or other +-- materials provided with the distribution. +-- +-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from this +-- software without specific prior written permission. +-- +-- 4. This software, with or without modification, must only be used with a +-- Nordic Semiconductor ASA integrated circuit. +-- +-- 5. Any software provided in binary form under this license must not be reverse +-- engineered, decompiled, modified and/or disassembled. +-- +-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +-- OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + +-- This spec has been automatically generated from nrf52.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package NRF_SVD.SPIS is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Shortcut between END event and ACQUIRE task + type SHORTS_END_ACQUIRE_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_END_ACQUIRE_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut register + type SHORTS_Register is record + -- unspecified + Reserved_0_1 : HAL.UInt2 := 16#0#; + -- Shortcut between END event and ACQUIRE task + END_ACQUIRE : SHORTS_END_ACQUIRE_Field := NRF_SVD.SPIS.Disabled; + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SHORTS_Register use record + Reserved_0_1 at 0 range 0 .. 1; + END_ACQUIRE at 0 range 2 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + -- Write '1' to Enable interrupt for END event + type INTENSET_END_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_END_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for END event + type INTENSET_END_Field_1 is + (-- Reset value for the field + Intenset_End_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_END_Field_1 use + (Intenset_End_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for ENDRX event + type INTENSET_ENDRX_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_ENDRX_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for ENDRX event + type INTENSET_ENDRX_Field_1 is + (-- Reset value for the field + Intenset_Endrx_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_ENDRX_Field_1 use + (Intenset_Endrx_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for ACQUIRED event + type INTENSET_ACQUIRED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_ACQUIRED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for ACQUIRED event + type INTENSET_ACQUIRED_Field_1 is + (-- Reset value for the field + Intenset_Acquired_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_ACQUIRED_Field_1 use + (Intenset_Acquired_Field_Reset => 0, + Set => 1); + + -- Enable interrupt + type INTENSET_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#0#; + -- Write '1' to Enable interrupt for END event + END_k : INTENSET_END_Field_1 := Intenset_End_Field_Reset; + -- unspecified + Reserved_2_3 : HAL.UInt2 := 16#0#; + -- Write '1' to Enable interrupt for ENDRX event + ENDRX : INTENSET_ENDRX_Field_1 := Intenset_Endrx_Field_Reset; + -- unspecified + Reserved_5_9 : HAL.UInt5 := 16#0#; + -- Write '1' to Enable interrupt for ACQUIRED event + ACQUIRED : INTENSET_ACQUIRED_Field_1 := + Intenset_Acquired_Field_Reset; + -- unspecified + Reserved_11_31 : HAL.UInt21 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENSET_Register use record + Reserved_0_0 at 0 range 0 .. 0; + END_k at 0 range 1 .. 1; + Reserved_2_3 at 0 range 2 .. 3; + ENDRX at 0 range 4 .. 4; + Reserved_5_9 at 0 range 5 .. 9; + ACQUIRED at 0 range 10 .. 10; + Reserved_11_31 at 0 range 11 .. 31; + end record; + + -- Write '1' to Disable interrupt for END event + type INTENCLR_END_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_END_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for END event + type INTENCLR_END_Field_1 is + (-- Reset value for the field + Intenclr_End_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_END_Field_1 use + (Intenclr_End_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for ENDRX event + type INTENCLR_ENDRX_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_ENDRX_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for ENDRX event + type INTENCLR_ENDRX_Field_1 is + (-- Reset value for the field + Intenclr_Endrx_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_ENDRX_Field_1 use + (Intenclr_Endrx_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for ACQUIRED event + type INTENCLR_ACQUIRED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_ACQUIRED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for ACQUIRED event + type INTENCLR_ACQUIRED_Field_1 is + (-- Reset value for the field + Intenclr_Acquired_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_ACQUIRED_Field_1 use + (Intenclr_Acquired_Field_Reset => 0, + Clear => 1); + + -- Disable interrupt + type INTENCLR_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#0#; + -- Write '1' to Disable interrupt for END event + END_k : INTENCLR_END_Field_1 := Intenclr_End_Field_Reset; + -- unspecified + Reserved_2_3 : HAL.UInt2 := 16#0#; + -- Write '1' to Disable interrupt for ENDRX event + ENDRX : INTENCLR_ENDRX_Field_1 := Intenclr_Endrx_Field_Reset; + -- unspecified + Reserved_5_9 : HAL.UInt5 := 16#0#; + -- Write '1' to Disable interrupt for ACQUIRED event + ACQUIRED : INTENCLR_ACQUIRED_Field_1 := + Intenclr_Acquired_Field_Reset; + -- unspecified + Reserved_11_31 : HAL.UInt21 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENCLR_Register use record + Reserved_0_0 at 0 range 0 .. 0; + END_k at 0 range 1 .. 1; + Reserved_2_3 at 0 range 2 .. 3; + ENDRX at 0 range 4 .. 4; + Reserved_5_9 at 0 range 5 .. 9; + ACQUIRED at 0 range 10 .. 10; + Reserved_11_31 at 0 range 11 .. 31; + end record; + + -- Semaphore status + type SEMSTAT_SEMSTAT_Field is + (-- Semaphore is free + Free, + -- Semaphore is assigned to CPU + Cpu, + -- Semaphore is assigned to SPI slave + Spis, + -- Semaphore is assigned to SPI but a handover to the CPU is pending + Cpupending) + with Size => 2; + for SEMSTAT_SEMSTAT_Field use + (Free => 0, + Cpu => 1, + Spis => 2, + Cpupending => 3); + + -- Semaphore status register + type SEMSTAT_Register is record + -- Read-only. Semaphore status + SEMSTAT : SEMSTAT_SEMSTAT_Field; + -- unspecified + Reserved_2_31 : HAL.UInt30; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SEMSTAT_Register use record + SEMSTAT at 0 range 0 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + -- TX buffer over-read detected, and prevented + type STATUS_OVERREAD_Field is + (-- Read: error not present + Notpresent, + -- Read: error present + Present) + with Size => 1; + for STATUS_OVERREAD_Field use + (Notpresent => 0, + Present => 1); + + -- TX buffer over-read detected, and prevented + type STATUS_OVERREAD_Field_1 is + (-- Reset value for the field + Status_Overread_Field_Reset, + -- Write: clear error on writing '1' + Clear) + with Size => 1; + for STATUS_OVERREAD_Field_1 use + (Status_Overread_Field_Reset => 0, + Clear => 1); + + -- RX buffer overflow detected, and prevented + type STATUS_OVERFLOW_Field is + (-- Read: error not present + Notpresent, + -- Read: error present + Present) + with Size => 1; + for STATUS_OVERFLOW_Field use + (Notpresent => 0, + Present => 1); + + -- RX buffer overflow detected, and prevented + type STATUS_OVERFLOW_Field_1 is + (-- Reset value for the field + Status_Overflow_Field_Reset, + -- Write: clear error on writing '1' + Clear) + with Size => 1; + for STATUS_OVERFLOW_Field_1 use + (Status_Overflow_Field_Reset => 0, + Clear => 1); + + -- Status from last transaction + type STATUS_Register is record + -- TX buffer over-read detected, and prevented + OVERREAD : STATUS_OVERREAD_Field_1 := Status_Overread_Field_Reset; + -- RX buffer overflow detected, and prevented + OVERFLOW : STATUS_OVERFLOW_Field_1 := Status_Overflow_Field_Reset; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for STATUS_Register use record + OVERREAD at 0 range 0 .. 0; + OVERFLOW at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + -- Enable or disable SPI slave + type ENABLE_ENABLE_Field is + (-- Disable SPI slave + Disabled, + -- Enable SPI slave + Enabled) + with Size => 4; + for ENABLE_ENABLE_Field use + (Disabled => 0, + Enabled => 2); + + -- Enable SPI slave + type ENABLE_Register is record + -- Enable or disable SPI slave + ENABLE : ENABLE_ENABLE_Field := NRF_SVD.SPIS.Disabled; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ENABLE_Register use record + ENABLE at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + ----------------------------------- + -- SPIS_PSEL cluster's Registers -- + ----------------------------------- + + subtype SCK_PSEL_PIN_Field is HAL.UInt5; + + -- Connection + type SCK_CONNECT_Field is + (-- Connect + Connected, + -- Disconnect + Disconnected) + with Size => 1; + for SCK_CONNECT_Field use + (Connected => 0, + Disconnected => 1); + + -- Pin select for SCK + type SCK_PSEL_Register is record + -- Pin number + PIN : SCK_PSEL_PIN_Field := 16#1F#; + -- unspecified + Reserved_5_30 : HAL.UInt26 := 16#3FFFFFF#; + -- Connection + CONNECT : SCK_CONNECT_Field := NRF_SVD.SPIS.Disconnected; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SCK_PSEL_Register use record + PIN at 0 range 0 .. 4; + Reserved_5_30 at 0 range 5 .. 30; + CONNECT at 0 range 31 .. 31; + end record; + + subtype MISO_PSEL_PIN_Field is HAL.UInt5; + + -- Connection + type MISO_CONNECT_Field is + (-- Connect + Connected, + -- Disconnect + Disconnected) + with Size => 1; + for MISO_CONNECT_Field use + (Connected => 0, + Disconnected => 1); + + -- Pin select for MISO signal + type MISO_PSEL_Register is record + -- Pin number + PIN : MISO_PSEL_PIN_Field := 16#1F#; + -- unspecified + Reserved_5_30 : HAL.UInt26 := 16#3FFFFFF#; + -- Connection + CONNECT : MISO_CONNECT_Field := NRF_SVD.SPIS.Disconnected; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MISO_PSEL_Register use record + PIN at 0 range 0 .. 4; + Reserved_5_30 at 0 range 5 .. 30; + CONNECT at 0 range 31 .. 31; + end record; + + subtype MOSI_PSEL_PIN_Field is HAL.UInt5; + + -- Connection + type MOSI_CONNECT_Field is + (-- Connect + Connected, + -- Disconnect + Disconnected) + with Size => 1; + for MOSI_CONNECT_Field use + (Connected => 0, + Disconnected => 1); + + -- Pin select for MOSI signal + type MOSI_PSEL_Register is record + -- Pin number + PIN : MOSI_PSEL_PIN_Field := 16#1F#; + -- unspecified + Reserved_5_30 : HAL.UInt26 := 16#3FFFFFF#; + -- Connection + CONNECT : MOSI_CONNECT_Field := NRF_SVD.SPIS.Disconnected; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MOSI_PSEL_Register use record + PIN at 0 range 0 .. 4; + Reserved_5_30 at 0 range 5 .. 30; + CONNECT at 0 range 31 .. 31; + end record; + + subtype CSN_PSEL_PIN_Field is HAL.UInt5; + + -- Connection + type CSN_CONNECT_Field is + (-- Connect + Connected, + -- Disconnect + Disconnected) + with Size => 1; + for CSN_CONNECT_Field use + (Connected => 0, + Disconnected => 1); + + -- Pin select for CSN signal + type CSN_PSEL_Register is record + -- Pin number + PIN : CSN_PSEL_PIN_Field := 16#1F#; + -- unspecified + Reserved_5_30 : HAL.UInt26 := 16#3FFFFFF#; + -- Connection + CONNECT : CSN_CONNECT_Field := NRF_SVD.SPIS.Disconnected; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CSN_PSEL_Register use record + PIN at 0 range 0 .. 4; + Reserved_5_30 at 0 range 5 .. 30; + CONNECT at 0 range 31 .. 31; + end record; + + -- Unspecified + type SPIS_PSEL_Cluster is record + -- Pin select for SCK + SCK : aliased SCK_PSEL_Register; + -- Pin select for MISO signal + MISO : aliased MISO_PSEL_Register; + -- Pin select for MOSI signal + MOSI : aliased MOSI_PSEL_Register; + -- Pin select for CSN signal + CSN : aliased CSN_PSEL_Register; + end record + with Size => 128; + + for SPIS_PSEL_Cluster use record + SCK at 16#0# range 0 .. 31; + MISO at 16#4# range 0 .. 31; + MOSI at 16#8# range 0 .. 31; + CSN at 16#C# range 0 .. 31; + end record; + + ---------------------------------- + -- SPIS_RXD cluster's Registers -- + ---------------------------------- + + subtype MAXCNT_RXD_MAXCNT_Field is HAL.UInt8; + + -- Maximum number of bytes in receive buffer + type MAXCNT_RXD_Register is record + -- Maximum number of bytes in receive buffer + MAXCNT : MAXCNT_RXD_MAXCNT_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MAXCNT_RXD_Register use record + MAXCNT at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype AMOUNT_RXD_AMOUNT_Field is HAL.UInt8; + + -- Number of bytes received in last granted transaction + type AMOUNT_RXD_Register is record + -- Read-only. Number of bytes received in the last granted transaction + AMOUNT : AMOUNT_RXD_AMOUNT_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for AMOUNT_RXD_Register use record + AMOUNT at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- Unspecified + type SPIS_RXD_Cluster is record + -- RXD data pointer + PTR : aliased HAL.UInt32; + -- Maximum number of bytes in receive buffer + MAXCNT : aliased MAXCNT_RXD_Register; + -- Number of bytes received in last granted transaction + AMOUNT : aliased AMOUNT_RXD_Register; + end record + with Size => 96; + + for SPIS_RXD_Cluster use record + PTR at 16#0# range 0 .. 31; + MAXCNT at 16#4# range 0 .. 31; + AMOUNT at 16#8# range 0 .. 31; + end record; + + ---------------------------------- + -- SPIS_TXD cluster's Registers -- + ---------------------------------- + + subtype MAXCNT_TXD_MAXCNT_Field is HAL.UInt8; + + -- Maximum number of bytes in transmit buffer + type MAXCNT_TXD_Register is record + -- Maximum number of bytes in transmit buffer + MAXCNT : MAXCNT_TXD_MAXCNT_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MAXCNT_TXD_Register use record + MAXCNT at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype AMOUNT_TXD_AMOUNT_Field is HAL.UInt8; + + -- Number of bytes transmitted in last granted transaction + type AMOUNT_TXD_Register is record + -- Read-only. Number of bytes transmitted in last granted transaction + AMOUNT : AMOUNT_TXD_AMOUNT_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for AMOUNT_TXD_Register use record + AMOUNT at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- Unspecified + type SPIS_TXD_Cluster is record + -- TXD data pointer + PTR : aliased HAL.UInt32; + -- Maximum number of bytes in transmit buffer + MAXCNT : aliased MAXCNT_TXD_Register; + -- Number of bytes transmitted in last granted transaction + AMOUNT : aliased AMOUNT_TXD_Register; + end record + with Size => 96; + + for SPIS_TXD_Cluster use record + PTR at 16#0# range 0 .. 31; + MAXCNT at 16#4# range 0 .. 31; + AMOUNT at 16#8# range 0 .. 31; + end record; + + -- Bit order + type CONFIG_ORDER_Field is + (-- Most significant bit shifted out first + Msbfirst, + -- Least significant bit shifted out first + Lsbfirst) + with Size => 1; + for CONFIG_ORDER_Field use + (Msbfirst => 0, + Lsbfirst => 1); + + -- Serial clock (SCK) phase + type CONFIG_CPHA_Field is + (-- Sample on leading edge of clock, shift serial data on trailing edge + Leading, + -- Sample on trailing edge of clock, shift serial data on leading edge + Trailing) + with Size => 1; + for CONFIG_CPHA_Field use + (Leading => 0, + Trailing => 1); + + -- Serial clock (SCK) polarity + type CONFIG_CPOL_Field is + (-- Active high + Activehigh, + -- Active low + Activelow) + with Size => 1; + for CONFIG_CPOL_Field use + (Activehigh => 0, + Activelow => 1); + + -- Configuration register + type CONFIG_Register is record + -- Bit order + ORDER : CONFIG_ORDER_Field := NRF_SVD.SPIS.Msbfirst; + -- Serial clock (SCK) phase + CPHA : CONFIG_CPHA_Field := NRF_SVD.SPIS.Leading; + -- Serial clock (SCK) polarity + CPOL : CONFIG_CPOL_Field := NRF_SVD.SPIS.Activehigh; + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CONFIG_Register use record + ORDER at 0 range 0 .. 0; + CPHA at 0 range 1 .. 1; + CPOL at 0 range 2 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + subtype DEF_DEF_Field is HAL.UInt8; + + -- Default character. Character clocked out in case of an ignored + -- transaction. + type DEF_Register is record + -- Default character. Character clocked out in case of an ignored + -- transaction. + DEF : DEF_DEF_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DEF_Register use record + DEF at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype ORC_ORC_Field is HAL.UInt8; + + -- Over-read character + type ORC_Register is record + -- Over-read character. Character clocked out after an over-read of the + -- transmit buffer. + ORC : ORC_ORC_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ORC_Register use record + ORC at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + ----------------------------------- + -- SPIS_PSEL cluster's Registers -- + ----------------------------------- + + ---------------------------------- + -- SPIS_RXD cluster's Registers -- + ---------------------------------- + + ---------------------------------- + -- SPIS_TXD cluster's Registers -- + ---------------------------------- + + ----------------------------------- + -- SPIS_PSEL cluster's Registers -- + ----------------------------------- + + ---------------------------------- + -- SPIS_RXD cluster's Registers -- + ---------------------------------- + + ---------------------------------- + -- SPIS_TXD cluster's Registers -- + ---------------------------------- + + ----------------- + -- Peripherals -- + ----------------- + + -- SPI Slave 0 + type SPIS_Peripheral is record + -- Acquire SPI semaphore + TASKS_ACQUIRE : aliased HAL.UInt32; + -- Release SPI semaphore, enabling the SPI slave to acquire it + TASKS_RELEASE : aliased HAL.UInt32; + -- Granted transaction completed + EVENTS_END : aliased HAL.UInt32; + -- End of RXD buffer reached + EVENTS_ENDRX : aliased HAL.UInt32; + -- Semaphore acquired + EVENTS_ACQUIRED : aliased HAL.UInt32; + -- Shortcut register + SHORTS : aliased SHORTS_Register; + -- Enable interrupt + INTENSET : aliased INTENSET_Register; + -- Disable interrupt + INTENCLR : aliased INTENCLR_Register; + -- Semaphore status register + SEMSTAT : aliased SEMSTAT_Register; + -- Status from last transaction + STATUS : aliased STATUS_Register; + -- Enable SPI slave + ENABLE : aliased ENABLE_Register; + -- Unspecified + PSEL : aliased SPIS_PSEL_Cluster; + -- Unspecified + RXD : aliased SPIS_RXD_Cluster; + -- Unspecified + TXD : aliased SPIS_TXD_Cluster; + -- Configuration register + CONFIG : aliased CONFIG_Register; + -- Default character. Character clocked out in case of an ignored + -- transaction. + DEF : aliased DEF_Register; + -- Over-read character + ORC : aliased ORC_Register; + end record + with Volatile; + + for SPIS_Peripheral use record + TASKS_ACQUIRE at 16#24# range 0 .. 31; + TASKS_RELEASE at 16#28# range 0 .. 31; + EVENTS_END at 16#104# range 0 .. 31; + EVENTS_ENDRX at 16#110# range 0 .. 31; + EVENTS_ACQUIRED at 16#128# range 0 .. 31; + SHORTS at 16#200# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + SEMSTAT at 16#400# range 0 .. 31; + STATUS at 16#440# range 0 .. 31; + ENABLE at 16#500# range 0 .. 31; + PSEL at 16#508# range 0 .. 127; + RXD at 16#534# range 0 .. 95; + TXD at 16#544# range 0 .. 95; + CONFIG at 16#554# range 0 .. 31; + DEF at 16#55C# range 0 .. 31; + ORC at 16#5C0# range 0 .. 31; + end record; + + -- SPI Slave 0 + SPIS0_Periph : aliased SPIS_Peripheral + with Import, Address => SPIS0_Base; + + -- SPI Slave 1 + SPIS1_Periph : aliased SPIS_Peripheral + with Import, Address => SPIS1_Base; + + -- SPI Slave 2 + SPIS2_Periph : aliased SPIS_Peripheral + with Import, Address => SPIS2_Base; + +end NRF_SVD.SPIS; diff --git a/arch/ARM/Nordic/svd/nrf52/nrf_svd-temp.ads b/arch/ARM/Nordic/svd/nrf52/nrf_svd-temp.ads new file mode 100644 index 000000000..fddb5387f --- /dev/null +++ b/arch/ARM/Nordic/svd/nrf52/nrf_svd-temp.ads @@ -0,0 +1,505 @@ +-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- 2. Redistributions in binary form, except as embedded into a Nordic +-- Semiconductor ASA integrated circuit in a product or a software update for +-- such product, must reproduce the above copyright notice, this list of +-- conditions and the following disclaimer in the documentation and/or other +-- materials provided with the distribution. +-- +-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from this +-- software without specific prior written permission. +-- +-- 4. This software, with or without modification, must only be used with a +-- Nordic Semiconductor ASA integrated circuit. +-- +-- 5. Any software provided in binary form under this license must not be reverse +-- engineered, decompiled, modified and/or disassembled. +-- +-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +-- OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + +-- This spec has been automatically generated from nrf52.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package NRF_SVD.TEMP is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Write '1' to Enable interrupt for DATARDY event + type INTENSET_DATARDY_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_DATARDY_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for DATARDY event + type INTENSET_DATARDY_Field_1 is + (-- Reset value for the field + Intenset_Datardy_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_DATARDY_Field_1 use + (Intenset_Datardy_Field_Reset => 0, + Set => 1); + + -- Enable interrupt + type INTENSET_Register is record + -- Write '1' to Enable interrupt for DATARDY event + DATARDY : INTENSET_DATARDY_Field_1 := + Intenset_Datardy_Field_Reset; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENSET_Register use record + DATARDY at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Write '1' to Disable interrupt for DATARDY event + type INTENCLR_DATARDY_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_DATARDY_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for DATARDY event + type INTENCLR_DATARDY_Field_1 is + (-- Reset value for the field + Intenclr_Datardy_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_DATARDY_Field_1 use + (Intenclr_Datardy_Field_Reset => 0, + Clear => 1); + + -- Disable interrupt + type INTENCLR_Register is record + -- Write '1' to Disable interrupt for DATARDY event + DATARDY : INTENCLR_DATARDY_Field_1 := + Intenclr_Datardy_Field_Reset; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENCLR_Register use record + DATARDY at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + subtype A0_A0_Field is HAL.UInt12; + + -- Slope of 1st piece wise linear function + type A0_Register is record + -- Slope of 1st piece wise linear function + A0 : A0_A0_Field := 16#320#; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for A0_Register use record + A0 at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype A1_A1_Field is HAL.UInt12; + + -- Slope of 2nd piece wise linear function + type A1_Register is record + -- Slope of 2nd piece wise linear function + A1 : A1_A1_Field := 16#343#; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for A1_Register use record + A1 at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype A2_A2_Field is HAL.UInt12; + + -- Slope of 3rd piece wise linear function + type A2_Register is record + -- Slope of 3rd piece wise linear function + A2 : A2_A2_Field := 16#35D#; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for A2_Register use record + A2 at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype A3_A3_Field is HAL.UInt12; + + -- Slope of 4th piece wise linear function + type A3_Register is record + -- Slope of 4th piece wise linear function + A3 : A3_A3_Field := 16#400#; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for A3_Register use record + A3 at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype A4_A4_Field is HAL.UInt12; + + -- Slope of 5th piece wise linear function + type A4_Register is record + -- Slope of 5th piece wise linear function + A4 : A4_A4_Field := 16#47F#; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for A4_Register use record + A4 at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype A5_A5_Field is HAL.UInt12; + + -- Slope of 6th piece wise linear function + type A5_Register is record + -- Slope of 6th piece wise linear function + A5 : A5_A5_Field := 16#37B#; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for A5_Register use record + A5 at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype B0_B0_Field is HAL.UInt14; + + -- y-intercept of 1st piece wise linear function + type B0_Register is record + -- y-intercept of 1st piece wise linear function + B0 : B0_B0_Field := 16#3FCC#; + -- unspecified + Reserved_14_31 : HAL.UInt18 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for B0_Register use record + B0 at 0 range 0 .. 13; + Reserved_14_31 at 0 range 14 .. 31; + end record; + + subtype B1_B1_Field is HAL.UInt14; + + -- y-intercept of 2nd piece wise linear function + type B1_Register is record + -- y-intercept of 2nd piece wise linear function + B1 : B1_B1_Field := 16#3F98#; + -- unspecified + Reserved_14_31 : HAL.UInt18 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for B1_Register use record + B1 at 0 range 0 .. 13; + Reserved_14_31 at 0 range 14 .. 31; + end record; + + subtype B2_B2_Field is HAL.UInt14; + + -- y-intercept of 3rd piece wise linear function + type B2_Register is record + -- y-intercept of 3rd piece wise linear function + B2 : B2_B2_Field := 16#3F98#; + -- unspecified + Reserved_14_31 : HAL.UInt18 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for B2_Register use record + B2 at 0 range 0 .. 13; + Reserved_14_31 at 0 range 14 .. 31; + end record; + + subtype B3_B3_Field is HAL.UInt14; + + -- y-intercept of 4th piece wise linear function + type B3_Register is record + -- y-intercept of 4th piece wise linear function + B3 : B3_B3_Field := 16#12#; + -- unspecified + Reserved_14_31 : HAL.UInt18 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for B3_Register use record + B3 at 0 range 0 .. 13; + Reserved_14_31 at 0 range 14 .. 31; + end record; + + subtype B4_B4_Field is HAL.UInt14; + + -- y-intercept of 5th piece wise linear function + type B4_Register is record + -- y-intercept of 5th piece wise linear function + B4 : B4_B4_Field := 16#6A#; + -- unspecified + Reserved_14_31 : HAL.UInt18 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for B4_Register use record + B4 at 0 range 0 .. 13; + Reserved_14_31 at 0 range 14 .. 31; + end record; + + subtype B5_B5_Field is HAL.UInt14; + + -- y-intercept of 6th piece wise linear function + type B5_Register is record + -- y-intercept of 6th piece wise linear function + B5 : B5_B5_Field := 16#3DD0#; + -- unspecified + Reserved_14_31 : HAL.UInt18 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for B5_Register use record + B5 at 0 range 0 .. 13; + Reserved_14_31 at 0 range 14 .. 31; + end record; + + subtype T0_T0_Field is HAL.UInt8; + + -- End point of 1st piece wise linear function + type T0_Register is record + -- End point of 1st piece wise linear function + T0 : T0_T0_Field := 16#E2#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for T0_Register use record + T0 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype T1_T1_Field is HAL.UInt8; + + -- End point of 2nd piece wise linear function + type T1_Register is record + -- End point of 2nd piece wise linear function + T1 : T1_T1_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for T1_Register use record + T1 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype T2_T2_Field is HAL.UInt8; + + -- End point of 3rd piece wise linear function + type T2_Register is record + -- End point of 3rd piece wise linear function + T2 : T2_T2_Field := 16#14#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for T2_Register use record + T2 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype T3_T3_Field is HAL.UInt8; + + -- End point of 4th piece wise linear function + type T3_Register is record + -- End point of 4th piece wise linear function + T3 : T3_T3_Field := 16#19#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for T3_Register use record + T3 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype T4_T4_Field is HAL.UInt8; + + -- End point of 5th piece wise linear function + type T4_Register is record + -- End point of 5th piece wise linear function + T4 : T4_T4_Field := 16#50#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for T4_Register use record + T4 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Temperature Sensor + type TEMP_Peripheral is record + -- Start temperature measurement + TASKS_START : aliased HAL.UInt32; + -- Stop temperature measurement + TASKS_STOP : aliased HAL.UInt32; + -- Temperature measurement complete, data ready + EVENTS_DATARDY : aliased HAL.UInt32; + -- Enable interrupt + INTENSET : aliased INTENSET_Register; + -- Disable interrupt + INTENCLR : aliased INTENCLR_Register; + -- Temperature in degC (0.25deg steps) + TEMP : aliased HAL.UInt32; + -- Slope of 1st piece wise linear function + A0 : aliased A0_Register; + -- Slope of 2nd piece wise linear function + A1 : aliased A1_Register; + -- Slope of 3rd piece wise linear function + A2 : aliased A2_Register; + -- Slope of 4th piece wise linear function + A3 : aliased A3_Register; + -- Slope of 5th piece wise linear function + A4 : aliased A4_Register; + -- Slope of 6th piece wise linear function + A5 : aliased A5_Register; + -- y-intercept of 1st piece wise linear function + B0 : aliased B0_Register; + -- y-intercept of 2nd piece wise linear function + B1 : aliased B1_Register; + -- y-intercept of 3rd piece wise linear function + B2 : aliased B2_Register; + -- y-intercept of 4th piece wise linear function + B3 : aliased B3_Register; + -- y-intercept of 5th piece wise linear function + B4 : aliased B4_Register; + -- y-intercept of 6th piece wise linear function + B5 : aliased B5_Register; + -- End point of 1st piece wise linear function + T0 : aliased T0_Register; + -- End point of 2nd piece wise linear function + T1 : aliased T1_Register; + -- End point of 3rd piece wise linear function + T2 : aliased T2_Register; + -- End point of 4th piece wise linear function + T3 : aliased T3_Register; + -- End point of 5th piece wise linear function + T4 : aliased T4_Register; + end record + with Volatile; + + for TEMP_Peripheral use record + TASKS_START at 16#0# range 0 .. 31; + TASKS_STOP at 16#4# range 0 .. 31; + EVENTS_DATARDY at 16#100# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + TEMP at 16#508# range 0 .. 31; + A0 at 16#520# range 0 .. 31; + A1 at 16#524# range 0 .. 31; + A2 at 16#528# range 0 .. 31; + A3 at 16#52C# range 0 .. 31; + A4 at 16#530# range 0 .. 31; + A5 at 16#534# range 0 .. 31; + B0 at 16#540# range 0 .. 31; + B1 at 16#544# range 0 .. 31; + B2 at 16#548# range 0 .. 31; + B3 at 16#54C# range 0 .. 31; + B4 at 16#550# range 0 .. 31; + B5 at 16#554# range 0 .. 31; + T0 at 16#560# range 0 .. 31; + T1 at 16#564# range 0 .. 31; + T2 at 16#568# range 0 .. 31; + T3 at 16#56C# range 0 .. 31; + T4 at 16#570# range 0 .. 31; + end record; + + -- Temperature Sensor + TEMP_Periph : aliased TEMP_Peripheral + with Import, Address => TEMP_Base; + +end NRF_SVD.TEMP; diff --git a/arch/ARM/Nordic/svd/nrf52/nrf_svd-timer.ads b/arch/ARM/Nordic/svd/nrf52/nrf_svd-timer.ads new file mode 100644 index 000000000..5ed72575f --- /dev/null +++ b/arch/ARM/Nordic/svd/nrf52/nrf_svd-timer.ads @@ -0,0 +1,537 @@ +-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- 2. Redistributions in binary form, except as embedded into a Nordic +-- Semiconductor ASA integrated circuit in a product or a software update for +-- such product, must reproduce the above copyright notice, this list of +-- conditions and the following disclaimer in the documentation and/or other +-- materials provided with the distribution. +-- +-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from this +-- software without specific prior written permission. +-- +-- 4. This software, with or without modification, must only be used with a +-- Nordic Semiconductor ASA integrated circuit. +-- +-- 5. Any software provided in binary form under this license must not be reverse +-- engineered, decompiled, modified and/or disassembled. +-- +-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +-- OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + +-- This spec has been automatically generated from nrf52.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package NRF_SVD.TIMER is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Description collection[0]: Capture Timer value to CC[0] register + + -- Description collection[0]: Capture Timer value to CC[0] register + type TASKS_CAPTURE_Registers is array (0 .. 5) of HAL.UInt32; + + -- Description collection[0]: Compare event on CC[0] match + + -- Description collection[0]: Compare event on CC[0] match + type EVENTS_COMPARE_Registers is array (0 .. 5) of HAL.UInt32; + + -- Shortcut between COMPARE[0] event and CLEAR task + type SHORTS_COMPARE0_CLEAR_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_COMPARE0_CLEAR_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut between COMPARE[1] event and CLEAR task + type SHORTS_COMPARE1_CLEAR_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_COMPARE1_CLEAR_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut between COMPARE[2] event and CLEAR task + type SHORTS_COMPARE2_CLEAR_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_COMPARE2_CLEAR_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut between COMPARE[3] event and CLEAR task + type SHORTS_COMPARE3_CLEAR_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_COMPARE3_CLEAR_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut between COMPARE[4] event and CLEAR task + type SHORTS_COMPARE4_CLEAR_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_COMPARE4_CLEAR_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut between COMPARE[5] event and CLEAR task + type SHORTS_COMPARE5_CLEAR_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_COMPARE5_CLEAR_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut between COMPARE[0] event and STOP task + type SHORTS_COMPARE0_STOP_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_COMPARE0_STOP_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut between COMPARE[1] event and STOP task + type SHORTS_COMPARE1_STOP_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_COMPARE1_STOP_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut between COMPARE[2] event and STOP task + type SHORTS_COMPARE2_STOP_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_COMPARE2_STOP_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut between COMPARE[3] event and STOP task + type SHORTS_COMPARE3_STOP_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_COMPARE3_STOP_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut between COMPARE[4] event and STOP task + type SHORTS_COMPARE4_STOP_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_COMPARE4_STOP_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut between COMPARE[5] event and STOP task + type SHORTS_COMPARE5_STOP_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_COMPARE5_STOP_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut register + type SHORTS_Register is record + -- Shortcut between COMPARE[0] event and CLEAR task + COMPARE0_CLEAR : SHORTS_COMPARE0_CLEAR_Field := NRF_SVD.TIMER.Disabled; + -- Shortcut between COMPARE[1] event and CLEAR task + COMPARE1_CLEAR : SHORTS_COMPARE1_CLEAR_Field := NRF_SVD.TIMER.Disabled; + -- Shortcut between COMPARE[2] event and CLEAR task + COMPARE2_CLEAR : SHORTS_COMPARE2_CLEAR_Field := NRF_SVD.TIMER.Disabled; + -- Shortcut between COMPARE[3] event and CLEAR task + COMPARE3_CLEAR : SHORTS_COMPARE3_CLEAR_Field := NRF_SVD.TIMER.Disabled; + -- Shortcut between COMPARE[4] event and CLEAR task + COMPARE4_CLEAR : SHORTS_COMPARE4_CLEAR_Field := NRF_SVD.TIMER.Disabled; + -- Shortcut between COMPARE[5] event and CLEAR task + COMPARE5_CLEAR : SHORTS_COMPARE5_CLEAR_Field := NRF_SVD.TIMER.Disabled; + -- unspecified + Reserved_6_7 : HAL.UInt2 := 16#0#; + -- Shortcut between COMPARE[0] event and STOP task + COMPARE0_STOP : SHORTS_COMPARE0_STOP_Field := NRF_SVD.TIMER.Disabled; + -- Shortcut between COMPARE[1] event and STOP task + COMPARE1_STOP : SHORTS_COMPARE1_STOP_Field := NRF_SVD.TIMER.Disabled; + -- Shortcut between COMPARE[2] event and STOP task + COMPARE2_STOP : SHORTS_COMPARE2_STOP_Field := NRF_SVD.TIMER.Disabled; + -- Shortcut between COMPARE[3] event and STOP task + COMPARE3_STOP : SHORTS_COMPARE3_STOP_Field := NRF_SVD.TIMER.Disabled; + -- Shortcut between COMPARE[4] event and STOP task + COMPARE4_STOP : SHORTS_COMPARE4_STOP_Field := NRF_SVD.TIMER.Disabled; + -- Shortcut between COMPARE[5] event and STOP task + COMPARE5_STOP : SHORTS_COMPARE5_STOP_Field := NRF_SVD.TIMER.Disabled; + -- unspecified + Reserved_14_31 : HAL.UInt18 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SHORTS_Register use record + COMPARE0_CLEAR at 0 range 0 .. 0; + COMPARE1_CLEAR at 0 range 1 .. 1; + COMPARE2_CLEAR at 0 range 2 .. 2; + COMPARE3_CLEAR at 0 range 3 .. 3; + COMPARE4_CLEAR at 0 range 4 .. 4; + COMPARE5_CLEAR at 0 range 5 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + COMPARE0_STOP at 0 range 8 .. 8; + COMPARE1_STOP at 0 range 9 .. 9; + COMPARE2_STOP at 0 range 10 .. 10; + COMPARE3_STOP at 0 range 11 .. 11; + COMPARE4_STOP at 0 range 12 .. 12; + COMPARE5_STOP at 0 range 13 .. 13; + Reserved_14_31 at 0 range 14 .. 31; + end record; + + -- Write '1' to Enable interrupt for COMPARE[0] event + type INTENSET_COMPARE0_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_COMPARE0_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for COMPARE[0] event + type INTENSET_COMPARE0_Field_1 is + (-- Reset value for the field + Intenset_Compare0_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_COMPARE0_Field_1 use + (Intenset_Compare0_Field_Reset => 0, + Set => 1); + + -- INTENSET_COMPARE array + type INTENSET_COMPARE_Field_Array is array (0 .. 5) + of INTENSET_COMPARE0_Field_1 + with Component_Size => 1, Size => 6; + + -- Type definition for INTENSET_COMPARE + type INTENSET_COMPARE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- COMPARE as a value + Val : HAL.UInt6; + when True => + -- COMPARE as an array + Arr : INTENSET_COMPARE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 6; + + for INTENSET_COMPARE_Field use record + Val at 0 range 0 .. 5; + Arr at 0 range 0 .. 5; + end record; + + -- Enable interrupt + type INTENSET_Register is record + -- unspecified + Reserved_0_15 : HAL.UInt16 := 16#0#; + -- Write '1' to Enable interrupt for COMPARE[0] event + COMPARE : INTENSET_COMPARE_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_22_31 : HAL.UInt10 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENSET_Register use record + Reserved_0_15 at 0 range 0 .. 15; + COMPARE at 0 range 16 .. 21; + Reserved_22_31 at 0 range 22 .. 31; + end record; + + -- Write '1' to Disable interrupt for COMPARE[0] event + type INTENCLR_COMPARE0_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_COMPARE0_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for COMPARE[0] event + type INTENCLR_COMPARE0_Field_1 is + (-- Reset value for the field + Intenclr_Compare0_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_COMPARE0_Field_1 use + (Intenclr_Compare0_Field_Reset => 0, + Clear => 1); + + -- INTENCLR_COMPARE array + type INTENCLR_COMPARE_Field_Array is array (0 .. 5) + of INTENCLR_COMPARE0_Field_1 + with Component_Size => 1, Size => 6; + + -- Type definition for INTENCLR_COMPARE + type INTENCLR_COMPARE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- COMPARE as a value + Val : HAL.UInt6; + when True => + -- COMPARE as an array + Arr : INTENCLR_COMPARE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 6; + + for INTENCLR_COMPARE_Field use record + Val at 0 range 0 .. 5; + Arr at 0 range 0 .. 5; + end record; + + -- Disable interrupt + type INTENCLR_Register is record + -- unspecified + Reserved_0_15 : HAL.UInt16 := 16#0#; + -- Write '1' to Disable interrupt for COMPARE[0] event + COMPARE : INTENCLR_COMPARE_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_22_31 : HAL.UInt10 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENCLR_Register use record + Reserved_0_15 at 0 range 0 .. 15; + COMPARE at 0 range 16 .. 21; + Reserved_22_31 at 0 range 22 .. 31; + end record; + + -- Timer mode + type MODE_MODE_Field is + (-- Select Timer mode + Timer, + -- Deprecated enumerator - Select Counter mode + Counter, + -- Select Low Power Counter mode + Lowpowercounter) + with Size => 2; + for MODE_MODE_Field use + (Timer => 0, + Counter => 1, + Lowpowercounter => 2); + + -- Timer mode selection + type MODE_Register is record + -- Timer mode + MODE : MODE_MODE_Field := NRF_SVD.TIMER.Timer; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MODE_Register use record + MODE at 0 range 0 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + -- Timer bit width + type BITMODE_BITMODE_Field is + (-- 16 bit timer bit width + Val_16Bit, + -- 8 bit timer bit width + Val_08Bit, + -- 24 bit timer bit width + Val_24Bit, + -- 32 bit timer bit width + Val_32Bit) + with Size => 2; + for BITMODE_BITMODE_Field use + (Val_16Bit => 0, + Val_08Bit => 1, + Val_24Bit => 2, + Val_32Bit => 3); + + -- Configure the number of bits used by the TIMER + type BITMODE_Register is record + -- Timer bit width + BITMODE : BITMODE_BITMODE_Field := NRF_SVD.TIMER.Val_16Bit; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BITMODE_Register use record + BITMODE at 0 range 0 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + subtype PRESCALER_PRESCALER_Field is HAL.UInt4; + + -- Timer prescaler register + type PRESCALER_Register is record + -- Prescaler value + PRESCALER : PRESCALER_PRESCALER_Field := 16#4#; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PRESCALER_Register use record + PRESCALER at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- Description collection[0]: Capture/Compare register 0 + + -- Description collection[0]: Capture/Compare register 0 + type CC_Registers is array (0 .. 5) of HAL.UInt32; + + ----------------- + -- Peripherals -- + ----------------- + + -- Timer/Counter 0 + type TIMER_Peripheral is record + -- Start Timer + TASKS_START : aliased HAL.UInt32; + -- Stop Timer + TASKS_STOP : aliased HAL.UInt32; + -- Increment Timer (Counter mode only) + TASKS_COUNT : aliased HAL.UInt32; + -- Clear time + TASKS_CLEAR : aliased HAL.UInt32; + -- Deprecated register - Shut down timer + TASKS_SHUTDOWN : aliased HAL.UInt32; + -- Description collection[0]: Capture Timer value to CC[0] register + TASKS_CAPTURE : aliased TASKS_CAPTURE_Registers; + -- Description collection[0]: Compare event on CC[0] match + EVENTS_COMPARE : aliased EVENTS_COMPARE_Registers; + -- Shortcut register + SHORTS : aliased SHORTS_Register; + -- Enable interrupt + INTENSET : aliased INTENSET_Register; + -- Disable interrupt + INTENCLR : aliased INTENCLR_Register; + -- Timer mode selection + MODE : aliased MODE_Register; + -- Configure the number of bits used by the TIMER + BITMODE : aliased BITMODE_Register; + -- Timer prescaler register + PRESCALER : aliased PRESCALER_Register; + -- Description collection[0]: Capture/Compare register 0 + CC : aliased CC_Registers; + end record + with Volatile; + + for TIMER_Peripheral use record + TASKS_START at 16#0# range 0 .. 31; + TASKS_STOP at 16#4# range 0 .. 31; + TASKS_COUNT at 16#8# range 0 .. 31; + TASKS_CLEAR at 16#C# range 0 .. 31; + TASKS_SHUTDOWN at 16#10# range 0 .. 31; + TASKS_CAPTURE at 16#40# range 0 .. 191; + EVENTS_COMPARE at 16#140# range 0 .. 191; + SHORTS at 16#200# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + MODE at 16#504# range 0 .. 31; + BITMODE at 16#508# range 0 .. 31; + PRESCALER at 16#510# range 0 .. 31; + CC at 16#540# range 0 .. 191; + end record; + + -- Timer/Counter 0 + TIMER0_Periph : aliased TIMER_Peripheral + with Import, Address => TIMER0_Base; + + -- Timer/Counter 1 + TIMER1_Periph : aliased TIMER_Peripheral + with Import, Address => TIMER1_Base; + + -- Timer/Counter 2 + TIMER2_Periph : aliased TIMER_Peripheral + with Import, Address => TIMER2_Base; + + -- Timer/Counter 3 + TIMER3_Periph : aliased TIMER_Peripheral + with Import, Address => TIMER3_Base; + + -- Timer/Counter 4 + TIMER4_Periph : aliased TIMER_Peripheral + with Import, Address => TIMER4_Base; + +end NRF_SVD.TIMER; diff --git a/arch/ARM/Nordic/svd/nrf52/nrf_svd-twi.ads b/arch/ARM/Nordic/svd/nrf52/nrf_svd-twi.ads new file mode 100644 index 000000000..84494a015 --- /dev/null +++ b/arch/ARM/Nordic/svd/nrf52/nrf_svd-twi.ads @@ -0,0 +1,710 @@ +-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- 2. Redistributions in binary form, except as embedded into a Nordic +-- Semiconductor ASA integrated circuit in a product or a software update for +-- such product, must reproduce the above copyright notice, this list of +-- conditions and the following disclaimer in the documentation and/or other +-- materials provided with the distribution. +-- +-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from this +-- software without specific prior written permission. +-- +-- 4. This software, with or without modification, must only be used with a +-- Nordic Semiconductor ASA integrated circuit. +-- +-- 5. Any software provided in binary form under this license must not be reverse +-- engineered, decompiled, modified and/or disassembled. +-- +-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +-- OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + +-- This spec has been automatically generated from nrf52.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package NRF_SVD.TWI is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Shortcut between BB event and SUSPEND task + type SHORTS_BB_SUSPEND_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_BB_SUSPEND_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut between BB event and STOP task + type SHORTS_BB_STOP_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_BB_STOP_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut register + type SHORTS_Register is record + -- Shortcut between BB event and SUSPEND task + BB_SUSPEND : SHORTS_BB_SUSPEND_Field := NRF_SVD.TWI.Disabled; + -- Shortcut between BB event and STOP task + BB_STOP : SHORTS_BB_STOP_Field := NRF_SVD.TWI.Disabled; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SHORTS_Register use record + BB_SUSPEND at 0 range 0 .. 0; + BB_STOP at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + -- Write '1' to Enable interrupt for STOPPED event + type INTENSET_STOPPED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_STOPPED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for STOPPED event + type INTENSET_STOPPED_Field_1 is + (-- Reset value for the field + Intenset_Stopped_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_STOPPED_Field_1 use + (Intenset_Stopped_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for RXDREADY event + type INTENSET_RXDREADY_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_RXDREADY_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for RXDREADY event + type INTENSET_RXDREADY_Field_1 is + (-- Reset value for the field + Intenset_Rxdready_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_RXDREADY_Field_1 use + (Intenset_Rxdready_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for TXDSENT event + type INTENSET_TXDSENT_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_TXDSENT_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for TXDSENT event + type INTENSET_TXDSENT_Field_1 is + (-- Reset value for the field + Intenset_Txdsent_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_TXDSENT_Field_1 use + (Intenset_Txdsent_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for ERROR event + type INTENSET_ERROR_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_ERROR_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for ERROR event + type INTENSET_ERROR_Field_1 is + (-- Reset value for the field + Intenset_Error_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_ERROR_Field_1 use + (Intenset_Error_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for BB event + type INTENSET_BB_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_BB_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for BB event + type INTENSET_BB_Field_1 is + (-- Reset value for the field + Intenset_Bb_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_BB_Field_1 use + (Intenset_Bb_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for SUSPENDED event + type INTENSET_SUSPENDED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_SUSPENDED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for SUSPENDED event + type INTENSET_SUSPENDED_Field_1 is + (-- Reset value for the field + Intenset_Suspended_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_SUSPENDED_Field_1 use + (Intenset_Suspended_Field_Reset => 0, + Set => 1); + + -- Enable interrupt + type INTENSET_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#0#; + -- Write '1' to Enable interrupt for STOPPED event + STOPPED : INTENSET_STOPPED_Field_1 := + Intenset_Stopped_Field_Reset; + -- Write '1' to Enable interrupt for RXDREADY event + RXDREADY : INTENSET_RXDREADY_Field_1 := + Intenset_Rxdready_Field_Reset; + -- unspecified + Reserved_3_6 : HAL.UInt4 := 16#0#; + -- Write '1' to Enable interrupt for TXDSENT event + TXDSENT : INTENSET_TXDSENT_Field_1 := + Intenset_Txdsent_Field_Reset; + -- unspecified + Reserved_8_8 : HAL.Bit := 16#0#; + -- Write '1' to Enable interrupt for ERROR event + ERROR : INTENSET_ERROR_Field_1 := Intenset_Error_Field_Reset; + -- unspecified + Reserved_10_13 : HAL.UInt4 := 16#0#; + -- Write '1' to Enable interrupt for BB event + BB : INTENSET_BB_Field_1 := Intenset_Bb_Field_Reset; + -- unspecified + Reserved_15_17 : HAL.UInt3 := 16#0#; + -- Write '1' to Enable interrupt for SUSPENDED event + SUSPENDED : INTENSET_SUSPENDED_Field_1 := + Intenset_Suspended_Field_Reset; + -- unspecified + Reserved_19_31 : HAL.UInt13 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENSET_Register use record + Reserved_0_0 at 0 range 0 .. 0; + STOPPED at 0 range 1 .. 1; + RXDREADY at 0 range 2 .. 2; + Reserved_3_6 at 0 range 3 .. 6; + TXDSENT at 0 range 7 .. 7; + Reserved_8_8 at 0 range 8 .. 8; + ERROR at 0 range 9 .. 9; + Reserved_10_13 at 0 range 10 .. 13; + BB at 0 range 14 .. 14; + Reserved_15_17 at 0 range 15 .. 17; + SUSPENDED at 0 range 18 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + -- Write '1' to Disable interrupt for STOPPED event + type INTENCLR_STOPPED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_STOPPED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for STOPPED event + type INTENCLR_STOPPED_Field_1 is + (-- Reset value for the field + Intenclr_Stopped_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_STOPPED_Field_1 use + (Intenclr_Stopped_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for RXDREADY event + type INTENCLR_RXDREADY_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_RXDREADY_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for RXDREADY event + type INTENCLR_RXDREADY_Field_1 is + (-- Reset value for the field + Intenclr_Rxdready_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_RXDREADY_Field_1 use + (Intenclr_Rxdready_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for TXDSENT event + type INTENCLR_TXDSENT_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_TXDSENT_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for TXDSENT event + type INTENCLR_TXDSENT_Field_1 is + (-- Reset value for the field + Intenclr_Txdsent_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_TXDSENT_Field_1 use + (Intenclr_Txdsent_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for ERROR event + type INTENCLR_ERROR_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_ERROR_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for ERROR event + type INTENCLR_ERROR_Field_1 is + (-- Reset value for the field + Intenclr_Error_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_ERROR_Field_1 use + (Intenclr_Error_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for BB event + type INTENCLR_BB_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_BB_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for BB event + type INTENCLR_BB_Field_1 is + (-- Reset value for the field + Intenclr_Bb_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_BB_Field_1 use + (Intenclr_Bb_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for SUSPENDED event + type INTENCLR_SUSPENDED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_SUSPENDED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for SUSPENDED event + type INTENCLR_SUSPENDED_Field_1 is + (-- Reset value for the field + Intenclr_Suspended_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_SUSPENDED_Field_1 use + (Intenclr_Suspended_Field_Reset => 0, + Clear => 1); + + -- Disable interrupt + type INTENCLR_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#0#; + -- Write '1' to Disable interrupt for STOPPED event + STOPPED : INTENCLR_STOPPED_Field_1 := + Intenclr_Stopped_Field_Reset; + -- Write '1' to Disable interrupt for RXDREADY event + RXDREADY : INTENCLR_RXDREADY_Field_1 := + Intenclr_Rxdready_Field_Reset; + -- unspecified + Reserved_3_6 : HAL.UInt4 := 16#0#; + -- Write '1' to Disable interrupt for TXDSENT event + TXDSENT : INTENCLR_TXDSENT_Field_1 := + Intenclr_Txdsent_Field_Reset; + -- unspecified + Reserved_8_8 : HAL.Bit := 16#0#; + -- Write '1' to Disable interrupt for ERROR event + ERROR : INTENCLR_ERROR_Field_1 := Intenclr_Error_Field_Reset; + -- unspecified + Reserved_10_13 : HAL.UInt4 := 16#0#; + -- Write '1' to Disable interrupt for BB event + BB : INTENCLR_BB_Field_1 := Intenclr_Bb_Field_Reset; + -- unspecified + Reserved_15_17 : HAL.UInt3 := 16#0#; + -- Write '1' to Disable interrupt for SUSPENDED event + SUSPENDED : INTENCLR_SUSPENDED_Field_1 := + Intenclr_Suspended_Field_Reset; + -- unspecified + Reserved_19_31 : HAL.UInt13 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENCLR_Register use record + Reserved_0_0 at 0 range 0 .. 0; + STOPPED at 0 range 1 .. 1; + RXDREADY at 0 range 2 .. 2; + Reserved_3_6 at 0 range 3 .. 6; + TXDSENT at 0 range 7 .. 7; + Reserved_8_8 at 0 range 8 .. 8; + ERROR at 0 range 9 .. 9; + Reserved_10_13 at 0 range 10 .. 13; + BB at 0 range 14 .. 14; + Reserved_15_17 at 0 range 15 .. 17; + SUSPENDED at 0 range 18 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + -- Overrun error + type ERRORSRC_OVERRUN_Field is + (-- Read: no overrun occured + Notpresent, + -- Read: overrun occured + Present) + with Size => 1; + for ERRORSRC_OVERRUN_Field use + (Notpresent => 0, + Present => 1); + + -- Overrun error + type ERRORSRC_OVERRUN_Field_1 is + (-- Reset value for the field + Errorsrc_Overrun_Field_Reset, + -- Write: clear error on writing '1' + Clear) + with Size => 1; + for ERRORSRC_OVERRUN_Field_1 use + (Errorsrc_Overrun_Field_Reset => 0, + Clear => 1); + + -- NACK received after sending the address (write '1' to clear) + type ERRORSRC_ANACK_Field is + (-- Read: error not present + Notpresent, + -- Read: error present + Present) + with Size => 1; + for ERRORSRC_ANACK_Field use + (Notpresent => 0, + Present => 1); + + -- NACK received after sending the address (write '1' to clear) + type ERRORSRC_ANACK_Field_1 is + (-- Reset value for the field + Errorsrc_Anack_Field_Reset, + -- Write: clear error on writing '1' + Clear) + with Size => 1; + for ERRORSRC_ANACK_Field_1 use + (Errorsrc_Anack_Field_Reset => 0, + Clear => 1); + + -- NACK received after sending a data byte (write '1' to clear) + type ERRORSRC_DNACK_Field is + (-- Read: error not present + Notpresent, + -- Read: error present + Present) + with Size => 1; + for ERRORSRC_DNACK_Field use + (Notpresent => 0, + Present => 1); + + -- NACK received after sending a data byte (write '1' to clear) + type ERRORSRC_DNACK_Field_1 is + (-- Reset value for the field + Errorsrc_Dnack_Field_Reset, + -- Write: clear error on writing '1' + Clear) + with Size => 1; + for ERRORSRC_DNACK_Field_1 use + (Errorsrc_Dnack_Field_Reset => 0, + Clear => 1); + + -- Error source + type ERRORSRC_Register is record + -- Overrun error + OVERRUN : ERRORSRC_OVERRUN_Field_1 := + Errorsrc_Overrun_Field_Reset; + -- NACK received after sending the address (write '1' to clear) + ANACK : ERRORSRC_ANACK_Field_1 := Errorsrc_Anack_Field_Reset; + -- NACK received after sending a data byte (write '1' to clear) + DNACK : ERRORSRC_DNACK_Field_1 := Errorsrc_Dnack_Field_Reset; + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ERRORSRC_Register use record + OVERRUN at 0 range 0 .. 0; + ANACK at 0 range 1 .. 1; + DNACK at 0 range 2 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + -- Enable or disable TWI + type ENABLE_ENABLE_Field is + (-- Disable TWI + Disabled, + -- Enable TWI + Enabled) + with Size => 4; + for ENABLE_ENABLE_Field use + (Disabled => 0, + Enabled => 5); + + -- Enable TWI + type ENABLE_Register is record + -- Enable or disable TWI + ENABLE : ENABLE_ENABLE_Field := NRF_SVD.TWI.Disabled; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ENABLE_Register use record + ENABLE at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + subtype RXD_RXD_Field is HAL.UInt8; + + -- RXD register + type RXD_Register is record + -- Read-only. *** Reading this field has side effects on other resources + -- ***. RXD register + RXD : RXD_RXD_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RXD_Register use record + RXD at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype TXD_TXD_Field is HAL.UInt8; + + -- TXD register + type TXD_Register is record + -- TXD register + TXD : TXD_TXD_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TXD_Register use record + TXD at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype ADDRESS_ADDRESS_Field is HAL.UInt7; + + -- Address used in the TWI transfer + type ADDRESS_Register is record + -- Address used in the TWI transfer + ADDRESS : ADDRESS_ADDRESS_Field := 16#0#; + -- unspecified + Reserved_7_31 : HAL.UInt25 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ADDRESS_Register use record + ADDRESS at 0 range 0 .. 6; + Reserved_7_31 at 0 range 7 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- I2C compatible Two-Wire Interface 0 + type TWI_Peripheral is record + -- Start TWI receive sequence + TASKS_STARTRX : aliased HAL.UInt32; + -- Start TWI transmit sequence + TASKS_STARTTX : aliased HAL.UInt32; + -- Stop TWI transaction + TASKS_STOP : aliased HAL.UInt32; + -- Suspend TWI transaction + TASKS_SUSPEND : aliased HAL.UInt32; + -- Resume TWI transaction + TASKS_RESUME : aliased HAL.UInt32; + -- TWI stopped + EVENTS_STOPPED : aliased HAL.UInt32; + -- TWI RXD byte received + EVENTS_RXDREADY : aliased HAL.UInt32; + -- TWI TXD byte sent + EVENTS_TXDSENT : aliased HAL.UInt32; + -- TWI error + EVENTS_ERROR : aliased HAL.UInt32; + -- TWI byte boundary, generated before each byte that is sent or + -- received + EVENTS_BB : aliased HAL.UInt32; + -- TWI entered the suspended state + EVENTS_SUSPENDED : aliased HAL.UInt32; + -- Shortcut register + SHORTS : aliased SHORTS_Register; + -- Enable interrupt + INTENSET : aliased INTENSET_Register; + -- Disable interrupt + INTENCLR : aliased INTENCLR_Register; + -- Error source + ERRORSRC : aliased ERRORSRC_Register; + -- Enable TWI + ENABLE : aliased ENABLE_Register; + -- Pin select for SCL + PSELSCL : aliased HAL.UInt32; + -- Pin select for SDA + PSELSDA : aliased HAL.UInt32; + -- RXD register + RXD : aliased RXD_Register; + -- TXD register + TXD : aliased TXD_Register; + -- TWI frequency + FREQUENCY : aliased HAL.UInt32; + -- Address used in the TWI transfer + ADDRESS : aliased ADDRESS_Register; + end record + with Volatile; + + for TWI_Peripheral use record + TASKS_STARTRX at 16#0# range 0 .. 31; + TASKS_STARTTX at 16#8# range 0 .. 31; + TASKS_STOP at 16#14# range 0 .. 31; + TASKS_SUSPEND at 16#1C# range 0 .. 31; + TASKS_RESUME at 16#20# range 0 .. 31; + EVENTS_STOPPED at 16#104# range 0 .. 31; + EVENTS_RXDREADY at 16#108# range 0 .. 31; + EVENTS_TXDSENT at 16#11C# range 0 .. 31; + EVENTS_ERROR at 16#124# range 0 .. 31; + EVENTS_BB at 16#138# range 0 .. 31; + EVENTS_SUSPENDED at 16#148# range 0 .. 31; + SHORTS at 16#200# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + ERRORSRC at 16#4C4# range 0 .. 31; + ENABLE at 16#500# range 0 .. 31; + PSELSCL at 16#508# range 0 .. 31; + PSELSDA at 16#50C# range 0 .. 31; + RXD at 16#518# range 0 .. 31; + TXD at 16#51C# range 0 .. 31; + FREQUENCY at 16#524# range 0 .. 31; + ADDRESS at 16#588# range 0 .. 31; + end record; + + -- I2C compatible Two-Wire Interface 0 + TWI0_Periph : aliased TWI_Peripheral + with Import, Address => TWI0_Base; + + -- I2C compatible Two-Wire Interface 1 + TWI1_Periph : aliased TWI_Peripheral + with Import, Address => TWI1_Base; + +end NRF_SVD.TWI; diff --git a/arch/ARM/Nordic/svd/nrf52/nrf_svd-twim.ads b/arch/ARM/Nordic/svd/nrf52/nrf_svd-twim.ads new file mode 100644 index 000000000..2d7b989d7 --- /dev/null +++ b/arch/ARM/Nordic/svd/nrf52/nrf_svd-twim.ads @@ -0,0 +1,1110 @@ +-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- 2. Redistributions in binary form, except as embedded into a Nordic +-- Semiconductor ASA integrated circuit in a product or a software update for +-- such product, must reproduce the above copyright notice, this list of +-- conditions and the following disclaimer in the documentation and/or other +-- materials provided with the distribution. +-- +-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from this +-- software without specific prior written permission. +-- +-- 4. This software, with or without modification, must only be used with a +-- Nordic Semiconductor ASA integrated circuit. +-- +-- 5. Any software provided in binary form under this license must not be reverse +-- engineered, decompiled, modified and/or disassembled. +-- +-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +-- OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + +-- This spec has been automatically generated from nrf52.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package NRF_SVD.TWIM is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Shortcut between LASTTX event and STARTRX task + type SHORTS_LASTTX_STARTRX_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_LASTTX_STARTRX_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut between LASTTX event and SUSPEND task + type SHORTS_LASTTX_SUSPEND_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_LASTTX_SUSPEND_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut between LASTTX event and STOP task + type SHORTS_LASTTX_STOP_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_LASTTX_STOP_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut between LASTRX event and STARTTX task + type SHORTS_LASTRX_STARTTX_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_LASTRX_STARTTX_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut between LASTRX event and STOP task + type SHORTS_LASTRX_STOP_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_LASTRX_STOP_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut register + type SHORTS_Register is record + -- unspecified + Reserved_0_6 : HAL.UInt7 := 16#0#; + -- Shortcut between LASTTX event and STARTRX task + LASTTX_STARTRX : SHORTS_LASTTX_STARTRX_Field := NRF_SVD.TWIM.Disabled; + -- Shortcut between LASTTX event and SUSPEND task + LASTTX_SUSPEND : SHORTS_LASTTX_SUSPEND_Field := NRF_SVD.TWIM.Disabled; + -- Shortcut between LASTTX event and STOP task + LASTTX_STOP : SHORTS_LASTTX_STOP_Field := NRF_SVD.TWIM.Disabled; + -- Shortcut between LASTRX event and STARTTX task + LASTRX_STARTTX : SHORTS_LASTRX_STARTTX_Field := NRF_SVD.TWIM.Disabled; + -- unspecified + Reserved_11_11 : HAL.Bit := 16#0#; + -- Shortcut between LASTRX event and STOP task + LASTRX_STOP : SHORTS_LASTRX_STOP_Field := NRF_SVD.TWIM.Disabled; + -- unspecified + Reserved_13_31 : HAL.UInt19 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SHORTS_Register use record + Reserved_0_6 at 0 range 0 .. 6; + LASTTX_STARTRX at 0 range 7 .. 7; + LASTTX_SUSPEND at 0 range 8 .. 8; + LASTTX_STOP at 0 range 9 .. 9; + LASTRX_STARTTX at 0 range 10 .. 10; + Reserved_11_11 at 0 range 11 .. 11; + LASTRX_STOP at 0 range 12 .. 12; + Reserved_13_31 at 0 range 13 .. 31; + end record; + + -- Enable or disable interrupt for STOPPED event + type INTEN_STOPPED_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_STOPPED_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for ERROR event + type INTEN_ERROR_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_ERROR_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for SUSPENDED event + type INTEN_SUSPENDED_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_SUSPENDED_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for RXSTARTED event + type INTEN_RXSTARTED_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_RXSTARTED_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for TXSTARTED event + type INTEN_TXSTARTED_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_TXSTARTED_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for LASTRX event + type INTEN_LASTRX_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_LASTRX_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for LASTTX event + type INTEN_LASTTX_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_LASTTX_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt + type INTEN_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#0#; + -- Enable or disable interrupt for STOPPED event + STOPPED : INTEN_STOPPED_Field := NRF_SVD.TWIM.Disabled; + -- unspecified + Reserved_2_8 : HAL.UInt7 := 16#0#; + -- Enable or disable interrupt for ERROR event + ERROR : INTEN_ERROR_Field := NRF_SVD.TWIM.Disabled; + -- unspecified + Reserved_10_17 : HAL.UInt8 := 16#0#; + -- Enable or disable interrupt for SUSPENDED event + SUSPENDED : INTEN_SUSPENDED_Field := NRF_SVD.TWIM.Disabled; + -- Enable or disable interrupt for RXSTARTED event + RXSTARTED : INTEN_RXSTARTED_Field := NRF_SVD.TWIM.Disabled; + -- Enable or disable interrupt for TXSTARTED event + TXSTARTED : INTEN_TXSTARTED_Field := NRF_SVD.TWIM.Disabled; + -- unspecified + Reserved_21_22 : HAL.UInt2 := 16#0#; + -- Enable or disable interrupt for LASTRX event + LASTRX : INTEN_LASTRX_Field := NRF_SVD.TWIM.Disabled; + -- Enable or disable interrupt for LASTTX event + LASTTX : INTEN_LASTTX_Field := NRF_SVD.TWIM.Disabled; + -- unspecified + Reserved_25_31 : HAL.UInt7 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTEN_Register use record + Reserved_0_0 at 0 range 0 .. 0; + STOPPED at 0 range 1 .. 1; + Reserved_2_8 at 0 range 2 .. 8; + ERROR at 0 range 9 .. 9; + Reserved_10_17 at 0 range 10 .. 17; + SUSPENDED at 0 range 18 .. 18; + RXSTARTED at 0 range 19 .. 19; + TXSTARTED at 0 range 20 .. 20; + Reserved_21_22 at 0 range 21 .. 22; + LASTRX at 0 range 23 .. 23; + LASTTX at 0 range 24 .. 24; + Reserved_25_31 at 0 range 25 .. 31; + end record; + + -- Write '1' to Enable interrupt for STOPPED event + type INTENSET_STOPPED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_STOPPED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for STOPPED event + type INTENSET_STOPPED_Field_1 is + (-- Reset value for the field + Intenset_Stopped_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_STOPPED_Field_1 use + (Intenset_Stopped_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for ERROR event + type INTENSET_ERROR_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_ERROR_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for ERROR event + type INTENSET_ERROR_Field_1 is + (-- Reset value for the field + Intenset_Error_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_ERROR_Field_1 use + (Intenset_Error_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for SUSPENDED event + type INTENSET_SUSPENDED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_SUSPENDED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for SUSPENDED event + type INTENSET_SUSPENDED_Field_1 is + (-- Reset value for the field + Intenset_Suspended_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_SUSPENDED_Field_1 use + (Intenset_Suspended_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for RXSTARTED event + type INTENSET_RXSTARTED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_RXSTARTED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for RXSTARTED event + type INTENSET_RXSTARTED_Field_1 is + (-- Reset value for the field + Intenset_Rxstarted_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_RXSTARTED_Field_1 use + (Intenset_Rxstarted_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for TXSTARTED event + type INTENSET_TXSTARTED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_TXSTARTED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for TXSTARTED event + type INTENSET_TXSTARTED_Field_1 is + (-- Reset value for the field + Intenset_Txstarted_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_TXSTARTED_Field_1 use + (Intenset_Txstarted_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for LASTRX event + type INTENSET_LASTRX_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_LASTRX_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for LASTRX event + type INTENSET_LASTRX_Field_1 is + (-- Reset value for the field + Intenset_Lastrx_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_LASTRX_Field_1 use + (Intenset_Lastrx_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for LASTTX event + type INTENSET_LASTTX_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_LASTTX_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for LASTTX event + type INTENSET_LASTTX_Field_1 is + (-- Reset value for the field + Intenset_Lasttx_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_LASTTX_Field_1 use + (Intenset_Lasttx_Field_Reset => 0, + Set => 1); + + -- Enable interrupt + type INTENSET_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#0#; + -- Write '1' to Enable interrupt for STOPPED event + STOPPED : INTENSET_STOPPED_Field_1 := + Intenset_Stopped_Field_Reset; + -- unspecified + Reserved_2_8 : HAL.UInt7 := 16#0#; + -- Write '1' to Enable interrupt for ERROR event + ERROR : INTENSET_ERROR_Field_1 := Intenset_Error_Field_Reset; + -- unspecified + Reserved_10_17 : HAL.UInt8 := 16#0#; + -- Write '1' to Enable interrupt for SUSPENDED event + SUSPENDED : INTENSET_SUSPENDED_Field_1 := + Intenset_Suspended_Field_Reset; + -- Write '1' to Enable interrupt for RXSTARTED event + RXSTARTED : INTENSET_RXSTARTED_Field_1 := + Intenset_Rxstarted_Field_Reset; + -- Write '1' to Enable interrupt for TXSTARTED event + TXSTARTED : INTENSET_TXSTARTED_Field_1 := + Intenset_Txstarted_Field_Reset; + -- unspecified + Reserved_21_22 : HAL.UInt2 := 16#0#; + -- Write '1' to Enable interrupt for LASTRX event + LASTRX : INTENSET_LASTRX_Field_1 := Intenset_Lastrx_Field_Reset; + -- Write '1' to Enable interrupt for LASTTX event + LASTTX : INTENSET_LASTTX_Field_1 := Intenset_Lasttx_Field_Reset; + -- unspecified + Reserved_25_31 : HAL.UInt7 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENSET_Register use record + Reserved_0_0 at 0 range 0 .. 0; + STOPPED at 0 range 1 .. 1; + Reserved_2_8 at 0 range 2 .. 8; + ERROR at 0 range 9 .. 9; + Reserved_10_17 at 0 range 10 .. 17; + SUSPENDED at 0 range 18 .. 18; + RXSTARTED at 0 range 19 .. 19; + TXSTARTED at 0 range 20 .. 20; + Reserved_21_22 at 0 range 21 .. 22; + LASTRX at 0 range 23 .. 23; + LASTTX at 0 range 24 .. 24; + Reserved_25_31 at 0 range 25 .. 31; + end record; + + -- Write '1' to Disable interrupt for STOPPED event + type INTENCLR_STOPPED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_STOPPED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for STOPPED event + type INTENCLR_STOPPED_Field_1 is + (-- Reset value for the field + Intenclr_Stopped_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_STOPPED_Field_1 use + (Intenclr_Stopped_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for ERROR event + type INTENCLR_ERROR_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_ERROR_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for ERROR event + type INTENCLR_ERROR_Field_1 is + (-- Reset value for the field + Intenclr_Error_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_ERROR_Field_1 use + (Intenclr_Error_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for SUSPENDED event + type INTENCLR_SUSPENDED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_SUSPENDED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for SUSPENDED event + type INTENCLR_SUSPENDED_Field_1 is + (-- Reset value for the field + Intenclr_Suspended_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_SUSPENDED_Field_1 use + (Intenclr_Suspended_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for RXSTARTED event + type INTENCLR_RXSTARTED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_RXSTARTED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for RXSTARTED event + type INTENCLR_RXSTARTED_Field_1 is + (-- Reset value for the field + Intenclr_Rxstarted_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_RXSTARTED_Field_1 use + (Intenclr_Rxstarted_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for TXSTARTED event + type INTENCLR_TXSTARTED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_TXSTARTED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for TXSTARTED event + type INTENCLR_TXSTARTED_Field_1 is + (-- Reset value for the field + Intenclr_Txstarted_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_TXSTARTED_Field_1 use + (Intenclr_Txstarted_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for LASTRX event + type INTENCLR_LASTRX_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_LASTRX_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for LASTRX event + type INTENCLR_LASTRX_Field_1 is + (-- Reset value for the field + Intenclr_Lastrx_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_LASTRX_Field_1 use + (Intenclr_Lastrx_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for LASTTX event + type INTENCLR_LASTTX_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_LASTTX_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for LASTTX event + type INTENCLR_LASTTX_Field_1 is + (-- Reset value for the field + Intenclr_Lasttx_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_LASTTX_Field_1 use + (Intenclr_Lasttx_Field_Reset => 0, + Clear => 1); + + -- Disable interrupt + type INTENCLR_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#0#; + -- Write '1' to Disable interrupt for STOPPED event + STOPPED : INTENCLR_STOPPED_Field_1 := + Intenclr_Stopped_Field_Reset; + -- unspecified + Reserved_2_8 : HAL.UInt7 := 16#0#; + -- Write '1' to Disable interrupt for ERROR event + ERROR : INTENCLR_ERROR_Field_1 := Intenclr_Error_Field_Reset; + -- unspecified + Reserved_10_17 : HAL.UInt8 := 16#0#; + -- Write '1' to Disable interrupt for SUSPENDED event + SUSPENDED : INTENCLR_SUSPENDED_Field_1 := + Intenclr_Suspended_Field_Reset; + -- Write '1' to Disable interrupt for RXSTARTED event + RXSTARTED : INTENCLR_RXSTARTED_Field_1 := + Intenclr_Rxstarted_Field_Reset; + -- Write '1' to Disable interrupt for TXSTARTED event + TXSTARTED : INTENCLR_TXSTARTED_Field_1 := + Intenclr_Txstarted_Field_Reset; + -- unspecified + Reserved_21_22 : HAL.UInt2 := 16#0#; + -- Write '1' to Disable interrupt for LASTRX event + LASTRX : INTENCLR_LASTRX_Field_1 := Intenclr_Lastrx_Field_Reset; + -- Write '1' to Disable interrupt for LASTTX event + LASTTX : INTENCLR_LASTTX_Field_1 := Intenclr_Lasttx_Field_Reset; + -- unspecified + Reserved_25_31 : HAL.UInt7 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENCLR_Register use record + Reserved_0_0 at 0 range 0 .. 0; + STOPPED at 0 range 1 .. 1; + Reserved_2_8 at 0 range 2 .. 8; + ERROR at 0 range 9 .. 9; + Reserved_10_17 at 0 range 10 .. 17; + SUSPENDED at 0 range 18 .. 18; + RXSTARTED at 0 range 19 .. 19; + TXSTARTED at 0 range 20 .. 20; + Reserved_21_22 at 0 range 21 .. 22; + LASTRX at 0 range 23 .. 23; + LASTTX at 0 range 24 .. 24; + Reserved_25_31 at 0 range 25 .. 31; + end record; + + -- Overrun error + type ERRORSRC_OVERRUN_Field is + (-- Error did not occur + Notreceived, + -- Error occurred + Received) + with Size => 1; + for ERRORSRC_OVERRUN_Field use + (Notreceived => 0, + Received => 1); + + -- NACK received after sending the address (write '1' to clear) + type ERRORSRC_ANACK_Field is + (-- Error did not occur + Notreceived, + -- Error occurred + Received) + with Size => 1; + for ERRORSRC_ANACK_Field use + (Notreceived => 0, + Received => 1); + + -- NACK received after sending a data byte (write '1' to clear) + type ERRORSRC_DNACK_Field is + (-- Error did not occur + Notreceived, + -- Error occurred + Received) + with Size => 1; + for ERRORSRC_DNACK_Field use + (Notreceived => 0, + Received => 1); + + -- Error source + type ERRORSRC_Register is record + -- Overrun error + OVERRUN : ERRORSRC_OVERRUN_Field := NRF_SVD.TWIM.Notreceived; + -- NACK received after sending the address (write '1' to clear) + ANACK : ERRORSRC_ANACK_Field := NRF_SVD.TWIM.Notreceived; + -- NACK received after sending a data byte (write '1' to clear) + DNACK : ERRORSRC_DNACK_Field := NRF_SVD.TWIM.Notreceived; + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ERRORSRC_Register use record + OVERRUN at 0 range 0 .. 0; + ANACK at 0 range 1 .. 1; + DNACK at 0 range 2 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + -- Enable or disable TWIM + type ENABLE_ENABLE_Field is + (-- Disable TWIM + Disabled, + -- Enable TWIM + Enabled) + with Size => 4; + for ENABLE_ENABLE_Field use + (Disabled => 0, + Enabled => 6); + + -- Enable TWIM + type ENABLE_Register is record + -- Enable or disable TWIM + ENABLE : ENABLE_ENABLE_Field := NRF_SVD.TWIM.Disabled; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ENABLE_Register use record + ENABLE at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + ----------------------------------- + -- TWIM_PSEL cluster's Registers -- + ----------------------------------- + + subtype SCL_PSEL_PIN_Field is HAL.UInt5; + + -- Connection + type SCL_CONNECT_Field is + (-- Connect + Connected, + -- Disconnect + Disconnected) + with Size => 1; + for SCL_CONNECT_Field use + (Connected => 0, + Disconnected => 1); + + -- Pin select for SCL signal + type SCL_PSEL_Register is record + -- Pin number + PIN : SCL_PSEL_PIN_Field := 16#1F#; + -- unspecified + Reserved_5_30 : HAL.UInt26 := 16#3FFFFFF#; + -- Connection + CONNECT : SCL_CONNECT_Field := NRF_SVD.TWIM.Disconnected; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SCL_PSEL_Register use record + PIN at 0 range 0 .. 4; + Reserved_5_30 at 0 range 5 .. 30; + CONNECT at 0 range 31 .. 31; + end record; + + subtype SDA_PSEL_PIN_Field is HAL.UInt5; + + -- Connection + type SDA_CONNECT_Field is + (-- Connect + Connected, + -- Disconnect + Disconnected) + with Size => 1; + for SDA_CONNECT_Field use + (Connected => 0, + Disconnected => 1); + + -- Pin select for SDA signal + type SDA_PSEL_Register is record + -- Pin number + PIN : SDA_PSEL_PIN_Field := 16#1F#; + -- unspecified + Reserved_5_30 : HAL.UInt26 := 16#3FFFFFF#; + -- Connection + CONNECT : SDA_CONNECT_Field := NRF_SVD.TWIM.Disconnected; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SDA_PSEL_Register use record + PIN at 0 range 0 .. 4; + Reserved_5_30 at 0 range 5 .. 30; + CONNECT at 0 range 31 .. 31; + end record; + + -- Unspecified + type TWIM_PSEL_Cluster is record + -- Pin select for SCL signal + SCL : aliased SCL_PSEL_Register; + -- Pin select for SDA signal + SDA : aliased SDA_PSEL_Register; + end record + with Size => 64; + + for TWIM_PSEL_Cluster use record + SCL at 16#0# range 0 .. 31; + SDA at 16#4# range 0 .. 31; + end record; + + ---------------------------------- + -- TWIM_RXD cluster's Registers -- + ---------------------------------- + + subtype MAXCNT_RXD_MAXCNT_Field is HAL.UInt8; + + -- Maximum number of bytes in receive buffer + type MAXCNT_RXD_Register is record + -- Maximum number of bytes in receive buffer + MAXCNT : MAXCNT_RXD_MAXCNT_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MAXCNT_RXD_Register use record + MAXCNT at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype AMOUNT_RXD_AMOUNT_Field is HAL.UInt8; + + -- Number of bytes transferred in the last transaction + type AMOUNT_RXD_Register is record + -- Read-only. Number of bytes transferred in the last transaction. In + -- case of NACK error, includes the NACK'ed byte. + AMOUNT : AMOUNT_RXD_AMOUNT_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for AMOUNT_RXD_Register use record + AMOUNT at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- List type + type LIST_LIST_Field is + (-- Disable EasyDMA list + Disabled, + -- Use array list + Arraylist) + with Size => 3; + for LIST_LIST_Field use + (Disabled => 0, + Arraylist => 1); + + -- EasyDMA list type + type LIST_RXD_Register is record + -- List type + LIST : LIST_LIST_Field := NRF_SVD.TWIM.Disabled; + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for LIST_RXD_Register use record + LIST at 0 range 0 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + -- RXD EasyDMA channel + type TWIM_RXD_Cluster is record + -- Data pointer + PTR : aliased HAL.UInt32; + -- Maximum number of bytes in receive buffer + MAXCNT : aliased MAXCNT_RXD_Register; + -- Number of bytes transferred in the last transaction + AMOUNT : aliased AMOUNT_RXD_Register; + -- EasyDMA list type + LIST : aliased LIST_RXD_Register; + end record + with Size => 128; + + for TWIM_RXD_Cluster use record + PTR at 16#0# range 0 .. 31; + MAXCNT at 16#4# range 0 .. 31; + AMOUNT at 16#8# range 0 .. 31; + LIST at 16#C# range 0 .. 31; + end record; + + ---------------------------------- + -- TWIM_TXD cluster's Registers -- + ---------------------------------- + + subtype MAXCNT_TXD_MAXCNT_Field is HAL.UInt8; + + -- Maximum number of bytes in transmit buffer + type MAXCNT_TXD_Register is record + -- Maximum number of bytes in transmit buffer + MAXCNT : MAXCNT_TXD_MAXCNT_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MAXCNT_TXD_Register use record + MAXCNT at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype AMOUNT_TXD_AMOUNT_Field is HAL.UInt8; + + -- Number of bytes transferred in the last transaction + type AMOUNT_TXD_Register is record + -- Read-only. Number of bytes transferred in the last transaction. In + -- case of NACK error, includes the NACK'ed byte. + AMOUNT : AMOUNT_TXD_AMOUNT_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for AMOUNT_TXD_Register use record + AMOUNT at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- EasyDMA list type + type LIST_TXD_Register is record + -- List type + LIST : LIST_LIST_Field := NRF_SVD.TWIM.Disabled; + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for LIST_TXD_Register use record + LIST at 0 range 0 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + -- TXD EasyDMA channel + type TWIM_TXD_Cluster is record + -- Data pointer + PTR : aliased HAL.UInt32; + -- Maximum number of bytes in transmit buffer + MAXCNT : aliased MAXCNT_TXD_Register; + -- Number of bytes transferred in the last transaction + AMOUNT : aliased AMOUNT_TXD_Register; + -- EasyDMA list type + LIST : aliased LIST_TXD_Register; + end record + with Size => 128; + + for TWIM_TXD_Cluster use record + PTR at 16#0# range 0 .. 31; + MAXCNT at 16#4# range 0 .. 31; + AMOUNT at 16#8# range 0 .. 31; + LIST at 16#C# range 0 .. 31; + end record; + + subtype ADDRESS_ADDRESS_Field is HAL.UInt7; + + -- Address used in the TWI transfer + type ADDRESS_Register is record + -- Address used in the TWI transfer + ADDRESS : ADDRESS_ADDRESS_Field := 16#0#; + -- unspecified + Reserved_7_31 : HAL.UInt25 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ADDRESS_Register use record + ADDRESS at 0 range 0 .. 6; + Reserved_7_31 at 0 range 7 .. 31; + end record; + + ----------------------------------- + -- TWIM_PSEL cluster's Registers -- + ----------------------------------- + + ---------------------------------- + -- TWIM_RXD cluster's Registers -- + ---------------------------------- + + ---------------------------------- + -- TWIM_TXD cluster's Registers -- + ---------------------------------- + + ----------------- + -- Peripherals -- + ----------------- + + -- I2C compatible Two-Wire Master Interface with EasyDMA 0 + type TWIM_Peripheral is record + -- Start TWI receive sequence + TASKS_STARTRX : aliased HAL.UInt32; + -- Start TWI transmit sequence + TASKS_STARTTX : aliased HAL.UInt32; + -- Stop TWI transaction. Must be issued while the TWI master is not + -- suspended. + TASKS_STOP : aliased HAL.UInt32; + -- Suspend TWI transaction + TASKS_SUSPEND : aliased HAL.UInt32; + -- Resume TWI transaction + TASKS_RESUME : aliased HAL.UInt32; + -- TWI stopped + EVENTS_STOPPED : aliased HAL.UInt32; + -- TWI error + EVENTS_ERROR : aliased HAL.UInt32; + -- Last byte has been sent out after the SUSPEND task has been issued, + -- TWI traffic is now suspended. + EVENTS_SUSPENDED : aliased HAL.UInt32; + -- Receive sequence started + EVENTS_RXSTARTED : aliased HAL.UInt32; + -- Transmit sequence started + EVENTS_TXSTARTED : aliased HAL.UInt32; + -- Byte boundary, starting to receive the last byte + EVENTS_LASTRX : aliased HAL.UInt32; + -- Byte boundary, starting to transmit the last byte + EVENTS_LASTTX : aliased HAL.UInt32; + -- Shortcut register + SHORTS : aliased SHORTS_Register; + -- Enable or disable interrupt + INTEN : aliased INTEN_Register; + -- Enable interrupt + INTENSET : aliased INTENSET_Register; + -- Disable interrupt + INTENCLR : aliased INTENCLR_Register; + -- Error source + ERRORSRC : aliased ERRORSRC_Register; + -- Enable TWIM + ENABLE : aliased ENABLE_Register; + -- Unspecified + PSEL : aliased TWIM_PSEL_Cluster; + -- TWI frequency + FREQUENCY : aliased HAL.UInt32; + -- RXD EasyDMA channel + RXD : aliased TWIM_RXD_Cluster; + -- TXD EasyDMA channel + TXD : aliased TWIM_TXD_Cluster; + -- Address used in the TWI transfer + ADDRESS : aliased ADDRESS_Register; + end record + with Volatile; + + for TWIM_Peripheral use record + TASKS_STARTRX at 16#0# range 0 .. 31; + TASKS_STARTTX at 16#8# range 0 .. 31; + TASKS_STOP at 16#14# range 0 .. 31; + TASKS_SUSPEND at 16#1C# range 0 .. 31; + TASKS_RESUME at 16#20# range 0 .. 31; + EVENTS_STOPPED at 16#104# range 0 .. 31; + EVENTS_ERROR at 16#124# range 0 .. 31; + EVENTS_SUSPENDED at 16#148# range 0 .. 31; + EVENTS_RXSTARTED at 16#14C# range 0 .. 31; + EVENTS_TXSTARTED at 16#150# range 0 .. 31; + EVENTS_LASTRX at 16#15C# range 0 .. 31; + EVENTS_LASTTX at 16#160# range 0 .. 31; + SHORTS at 16#200# range 0 .. 31; + INTEN at 16#300# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + ERRORSRC at 16#4C4# range 0 .. 31; + ENABLE at 16#500# range 0 .. 31; + PSEL at 16#508# range 0 .. 63; + FREQUENCY at 16#524# range 0 .. 31; + RXD at 16#534# range 0 .. 127; + TXD at 16#544# range 0 .. 127; + ADDRESS at 16#588# range 0 .. 31; + end record; + + -- I2C compatible Two-Wire Master Interface with EasyDMA 0 + TWIM0_Periph : aliased TWIM_Peripheral + with Import, Address => TWIM0_Base; + + -- I2C compatible Two-Wire Master Interface with EasyDMA 1 + TWIM1_Periph : aliased TWIM_Peripheral + with Import, Address => TWIM1_Base; + +end NRF_SVD.TWIM; diff --git a/arch/ARM/Nordic/svd/nrf52/nrf_svd-twis.ads b/arch/ARM/Nordic/svd/nrf52/nrf_svd-twis.ads new file mode 100644 index 000000000..0eff3a276 --- /dev/null +++ b/arch/ARM/Nordic/svd/nrf52/nrf_svd-twis.ads @@ -0,0 +1,1044 @@ +-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- 2. Redistributions in binary form, except as embedded into a Nordic +-- Semiconductor ASA integrated circuit in a product or a software update for +-- such product, must reproduce the above copyright notice, this list of +-- conditions and the following disclaimer in the documentation and/or other +-- materials provided with the distribution. +-- +-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from this +-- software without specific prior written permission. +-- +-- 4. This software, with or without modification, must only be used with a +-- Nordic Semiconductor ASA integrated circuit. +-- +-- 5. Any software provided in binary form under this license must not be reverse +-- engineered, decompiled, modified and/or disassembled. +-- +-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +-- OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + +-- This spec has been automatically generated from nrf52.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package NRF_SVD.TWIS is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Shortcut between WRITE event and SUSPEND task + type SHORTS_WRITE_SUSPEND_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_WRITE_SUSPEND_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut between READ event and SUSPEND task + type SHORTS_READ_SUSPEND_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_READ_SUSPEND_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut register + type SHORTS_Register is record + -- unspecified + Reserved_0_12 : HAL.UInt13 := 16#0#; + -- Shortcut between WRITE event and SUSPEND task + WRITE_SUSPEND : SHORTS_WRITE_SUSPEND_Field := NRF_SVD.TWIS.Disabled; + -- Shortcut between READ event and SUSPEND task + READ_SUSPEND : SHORTS_READ_SUSPEND_Field := NRF_SVD.TWIS.Disabled; + -- unspecified + Reserved_15_31 : HAL.UInt17 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SHORTS_Register use record + Reserved_0_12 at 0 range 0 .. 12; + WRITE_SUSPEND at 0 range 13 .. 13; + READ_SUSPEND at 0 range 14 .. 14; + Reserved_15_31 at 0 range 15 .. 31; + end record; + + -- Enable or disable interrupt for STOPPED event + type INTEN_STOPPED_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_STOPPED_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for ERROR event + type INTEN_ERROR_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_ERROR_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for RXSTARTED event + type INTEN_RXSTARTED_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_RXSTARTED_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for TXSTARTED event + type INTEN_TXSTARTED_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_TXSTARTED_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for WRITE event + type INTEN_WRITE_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_WRITE_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for READ event + type INTEN_READ_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_READ_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt + type INTEN_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#0#; + -- Enable or disable interrupt for STOPPED event + STOPPED : INTEN_STOPPED_Field := NRF_SVD.TWIS.Disabled; + -- unspecified + Reserved_2_8 : HAL.UInt7 := 16#0#; + -- Enable or disable interrupt for ERROR event + ERROR : INTEN_ERROR_Field := NRF_SVD.TWIS.Disabled; + -- unspecified + Reserved_10_18 : HAL.UInt9 := 16#0#; + -- Enable or disable interrupt for RXSTARTED event + RXSTARTED : INTEN_RXSTARTED_Field := NRF_SVD.TWIS.Disabled; + -- Enable or disable interrupt for TXSTARTED event + TXSTARTED : INTEN_TXSTARTED_Field := NRF_SVD.TWIS.Disabled; + -- unspecified + Reserved_21_24 : HAL.UInt4 := 16#0#; + -- Enable or disable interrupt for WRITE event + WRITE : INTEN_WRITE_Field := NRF_SVD.TWIS.Disabled; + -- Enable or disable interrupt for READ event + READ : INTEN_READ_Field := NRF_SVD.TWIS.Disabled; + -- unspecified + Reserved_27_31 : HAL.UInt5 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTEN_Register use record + Reserved_0_0 at 0 range 0 .. 0; + STOPPED at 0 range 1 .. 1; + Reserved_2_8 at 0 range 2 .. 8; + ERROR at 0 range 9 .. 9; + Reserved_10_18 at 0 range 10 .. 18; + RXSTARTED at 0 range 19 .. 19; + TXSTARTED at 0 range 20 .. 20; + Reserved_21_24 at 0 range 21 .. 24; + WRITE at 0 range 25 .. 25; + READ at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- Write '1' to Enable interrupt for STOPPED event + type INTENSET_STOPPED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_STOPPED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for STOPPED event + type INTENSET_STOPPED_Field_1 is + (-- Reset value for the field + Intenset_Stopped_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_STOPPED_Field_1 use + (Intenset_Stopped_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for ERROR event + type INTENSET_ERROR_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_ERROR_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for ERROR event + type INTENSET_ERROR_Field_1 is + (-- Reset value for the field + Intenset_Error_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_ERROR_Field_1 use + (Intenset_Error_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for RXSTARTED event + type INTENSET_RXSTARTED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_RXSTARTED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for RXSTARTED event + type INTENSET_RXSTARTED_Field_1 is + (-- Reset value for the field + Intenset_Rxstarted_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_RXSTARTED_Field_1 use + (Intenset_Rxstarted_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for TXSTARTED event + type INTENSET_TXSTARTED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_TXSTARTED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for TXSTARTED event + type INTENSET_TXSTARTED_Field_1 is + (-- Reset value for the field + Intenset_Txstarted_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_TXSTARTED_Field_1 use + (Intenset_Txstarted_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for WRITE event + type INTENSET_WRITE_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_WRITE_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for WRITE event + type INTENSET_WRITE_Field_1 is + (-- Reset value for the field + Intenset_Write_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_WRITE_Field_1 use + (Intenset_Write_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for READ event + type INTENSET_READ_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_READ_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for READ event + type INTENSET_READ_Field_1 is + (-- Reset value for the field + Intenset_Read_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_READ_Field_1 use + (Intenset_Read_Field_Reset => 0, + Set => 1); + + -- Enable interrupt + type INTENSET_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#0#; + -- Write '1' to Enable interrupt for STOPPED event + STOPPED : INTENSET_STOPPED_Field_1 := + Intenset_Stopped_Field_Reset; + -- unspecified + Reserved_2_8 : HAL.UInt7 := 16#0#; + -- Write '1' to Enable interrupt for ERROR event + ERROR : INTENSET_ERROR_Field_1 := Intenset_Error_Field_Reset; + -- unspecified + Reserved_10_18 : HAL.UInt9 := 16#0#; + -- Write '1' to Enable interrupt for RXSTARTED event + RXSTARTED : INTENSET_RXSTARTED_Field_1 := + Intenset_Rxstarted_Field_Reset; + -- Write '1' to Enable interrupt for TXSTARTED event + TXSTARTED : INTENSET_TXSTARTED_Field_1 := + Intenset_Txstarted_Field_Reset; + -- unspecified + Reserved_21_24 : HAL.UInt4 := 16#0#; + -- Write '1' to Enable interrupt for WRITE event + WRITE : INTENSET_WRITE_Field_1 := Intenset_Write_Field_Reset; + -- Write '1' to Enable interrupt for READ event + READ : INTENSET_READ_Field_1 := Intenset_Read_Field_Reset; + -- unspecified + Reserved_27_31 : HAL.UInt5 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENSET_Register use record + Reserved_0_0 at 0 range 0 .. 0; + STOPPED at 0 range 1 .. 1; + Reserved_2_8 at 0 range 2 .. 8; + ERROR at 0 range 9 .. 9; + Reserved_10_18 at 0 range 10 .. 18; + RXSTARTED at 0 range 19 .. 19; + TXSTARTED at 0 range 20 .. 20; + Reserved_21_24 at 0 range 21 .. 24; + WRITE at 0 range 25 .. 25; + READ at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- Write '1' to Disable interrupt for STOPPED event + type INTENCLR_STOPPED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_STOPPED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for STOPPED event + type INTENCLR_STOPPED_Field_1 is + (-- Reset value for the field + Intenclr_Stopped_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_STOPPED_Field_1 use + (Intenclr_Stopped_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for ERROR event + type INTENCLR_ERROR_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_ERROR_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for ERROR event + type INTENCLR_ERROR_Field_1 is + (-- Reset value for the field + Intenclr_Error_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_ERROR_Field_1 use + (Intenclr_Error_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for RXSTARTED event + type INTENCLR_RXSTARTED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_RXSTARTED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for RXSTARTED event + type INTENCLR_RXSTARTED_Field_1 is + (-- Reset value for the field + Intenclr_Rxstarted_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_RXSTARTED_Field_1 use + (Intenclr_Rxstarted_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for TXSTARTED event + type INTENCLR_TXSTARTED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_TXSTARTED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for TXSTARTED event + type INTENCLR_TXSTARTED_Field_1 is + (-- Reset value for the field + Intenclr_Txstarted_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_TXSTARTED_Field_1 use + (Intenclr_Txstarted_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for WRITE event + type INTENCLR_WRITE_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_WRITE_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for WRITE event + type INTENCLR_WRITE_Field_1 is + (-- Reset value for the field + Intenclr_Write_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_WRITE_Field_1 use + (Intenclr_Write_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for READ event + type INTENCLR_READ_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_READ_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for READ event + type INTENCLR_READ_Field_1 is + (-- Reset value for the field + Intenclr_Read_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_READ_Field_1 use + (Intenclr_Read_Field_Reset => 0, + Clear => 1); + + -- Disable interrupt + type INTENCLR_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#0#; + -- Write '1' to Disable interrupt for STOPPED event + STOPPED : INTENCLR_STOPPED_Field_1 := + Intenclr_Stopped_Field_Reset; + -- unspecified + Reserved_2_8 : HAL.UInt7 := 16#0#; + -- Write '1' to Disable interrupt for ERROR event + ERROR : INTENCLR_ERROR_Field_1 := Intenclr_Error_Field_Reset; + -- unspecified + Reserved_10_18 : HAL.UInt9 := 16#0#; + -- Write '1' to Disable interrupt for RXSTARTED event + RXSTARTED : INTENCLR_RXSTARTED_Field_1 := + Intenclr_Rxstarted_Field_Reset; + -- Write '1' to Disable interrupt for TXSTARTED event + TXSTARTED : INTENCLR_TXSTARTED_Field_1 := + Intenclr_Txstarted_Field_Reset; + -- unspecified + Reserved_21_24 : HAL.UInt4 := 16#0#; + -- Write '1' to Disable interrupt for WRITE event + WRITE : INTENCLR_WRITE_Field_1 := Intenclr_Write_Field_Reset; + -- Write '1' to Disable interrupt for READ event + READ : INTENCLR_READ_Field_1 := Intenclr_Read_Field_Reset; + -- unspecified + Reserved_27_31 : HAL.UInt5 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENCLR_Register use record + Reserved_0_0 at 0 range 0 .. 0; + STOPPED at 0 range 1 .. 1; + Reserved_2_8 at 0 range 2 .. 8; + ERROR at 0 range 9 .. 9; + Reserved_10_18 at 0 range 10 .. 18; + RXSTARTED at 0 range 19 .. 19; + TXSTARTED at 0 range 20 .. 20; + Reserved_21_24 at 0 range 21 .. 24; + WRITE at 0 range 25 .. 25; + READ at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- RX buffer overflow detected, and prevented + type ERRORSRC_OVERFLOW_Field is + (-- Error did not occur + Notdetected, + -- Error occurred + Detected) + with Size => 1; + for ERRORSRC_OVERFLOW_Field use + (Notdetected => 0, + Detected => 1); + + -- NACK sent after receiving a data byte + type ERRORSRC_DNACK_Field is + (-- Error did not occur + Notreceived, + -- Error occurred + Received) + with Size => 1; + for ERRORSRC_DNACK_Field use + (Notreceived => 0, + Received => 1); + + -- TX buffer over-read detected, and prevented + type ERRORSRC_OVERREAD_Field is + (-- Error did not occur + Notdetected, + -- Error occurred + Detected) + with Size => 1; + for ERRORSRC_OVERREAD_Field use + (Notdetected => 0, + Detected => 1); + + -- Error source + type ERRORSRC_Register is record + -- RX buffer overflow detected, and prevented + OVERFLOW : ERRORSRC_OVERFLOW_Field := NRF_SVD.TWIS.Notdetected; + -- unspecified + Reserved_1_1 : HAL.Bit := 16#0#; + -- NACK sent after receiving a data byte + DNACK : ERRORSRC_DNACK_Field := NRF_SVD.TWIS.Notreceived; + -- TX buffer over-read detected, and prevented + OVERREAD : ERRORSRC_OVERREAD_Field := NRF_SVD.TWIS.Notdetected; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ERRORSRC_Register use record + OVERFLOW at 0 range 0 .. 0; + Reserved_1_1 at 0 range 1 .. 1; + DNACK at 0 range 2 .. 2; + OVERREAD at 0 range 3 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- Status register indicating which address had a match + type MATCH_Register is record + -- Read-only. Which of the addresses in {ADDRESS} matched the incoming + -- address + MATCH : Boolean; + -- unspecified + Reserved_1_31 : HAL.UInt31; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MATCH_Register use record + MATCH at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Enable or disable TWIS + type ENABLE_ENABLE_Field is + (-- Disable TWIS + Disabled, + -- Enable TWIS + Enabled) + with Size => 4; + for ENABLE_ENABLE_Field use + (Disabled => 0, + Enabled => 9); + + -- Enable TWIS + type ENABLE_Register is record + -- Enable or disable TWIS + ENABLE : ENABLE_ENABLE_Field := NRF_SVD.TWIS.Disabled; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ENABLE_Register use record + ENABLE at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + ----------------------------------- + -- TWIS_PSEL cluster's Registers -- + ----------------------------------- + + subtype SCL_PSEL_PIN_Field is HAL.UInt5; + + -- Connection + type SCL_CONNECT_Field is + (-- Connect + Connected, + -- Disconnect + Disconnected) + with Size => 1; + for SCL_CONNECT_Field use + (Connected => 0, + Disconnected => 1); + + -- Pin select for SCL signal + type SCL_PSEL_Register is record + -- Pin number + PIN : SCL_PSEL_PIN_Field := 16#1F#; + -- unspecified + Reserved_5_30 : HAL.UInt26 := 16#3FFFFFF#; + -- Connection + CONNECT : SCL_CONNECT_Field := NRF_SVD.TWIS.Disconnected; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SCL_PSEL_Register use record + PIN at 0 range 0 .. 4; + Reserved_5_30 at 0 range 5 .. 30; + CONNECT at 0 range 31 .. 31; + end record; + + subtype SDA_PSEL_PIN_Field is HAL.UInt5; + + -- Connection + type SDA_CONNECT_Field is + (-- Connect + Connected, + -- Disconnect + Disconnected) + with Size => 1; + for SDA_CONNECT_Field use + (Connected => 0, + Disconnected => 1); + + -- Pin select for SDA signal + type SDA_PSEL_Register is record + -- Pin number + PIN : SDA_PSEL_PIN_Field := 16#1F#; + -- unspecified + Reserved_5_30 : HAL.UInt26 := 16#3FFFFFF#; + -- Connection + CONNECT : SDA_CONNECT_Field := NRF_SVD.TWIS.Disconnected; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SDA_PSEL_Register use record + PIN at 0 range 0 .. 4; + Reserved_5_30 at 0 range 5 .. 30; + CONNECT at 0 range 31 .. 31; + end record; + + -- Unspecified + type TWIS_PSEL_Cluster is record + -- Pin select for SCL signal + SCL : aliased SCL_PSEL_Register; + -- Pin select for SDA signal + SDA : aliased SDA_PSEL_Register; + end record + with Size => 64; + + for TWIS_PSEL_Cluster use record + SCL at 16#0# range 0 .. 31; + SDA at 16#4# range 0 .. 31; + end record; + + ---------------------------------- + -- TWIS_RXD cluster's Registers -- + ---------------------------------- + + subtype MAXCNT_RXD_MAXCNT_Field is HAL.UInt8; + + -- Maximum number of bytes in RXD buffer + type MAXCNT_RXD_Register is record + -- Maximum number of bytes in RXD buffer + MAXCNT : MAXCNT_RXD_MAXCNT_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MAXCNT_RXD_Register use record + MAXCNT at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype AMOUNT_RXD_AMOUNT_Field is HAL.UInt8; + + -- Number of bytes transferred in the last RXD transaction + type AMOUNT_RXD_Register is record + -- Read-only. Number of bytes transferred in the last RXD transaction + AMOUNT : AMOUNT_RXD_AMOUNT_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for AMOUNT_RXD_Register use record + AMOUNT at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- RXD EasyDMA channel + type TWIS_RXD_Cluster is record + -- RXD Data pointer + PTR : aliased HAL.UInt32; + -- Maximum number of bytes in RXD buffer + MAXCNT : aliased MAXCNT_RXD_Register; + -- Number of bytes transferred in the last RXD transaction + AMOUNT : aliased AMOUNT_RXD_Register; + end record + with Size => 96; + + for TWIS_RXD_Cluster use record + PTR at 16#0# range 0 .. 31; + MAXCNT at 16#4# range 0 .. 31; + AMOUNT at 16#8# range 0 .. 31; + end record; + + ---------------------------------- + -- TWIS_TXD cluster's Registers -- + ---------------------------------- + + subtype MAXCNT_TXD_MAXCNT_Field is HAL.UInt8; + + -- Maximum number of bytes in TXD buffer + type MAXCNT_TXD_Register is record + -- Maximum number of bytes in TXD buffer + MAXCNT : MAXCNT_TXD_MAXCNT_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MAXCNT_TXD_Register use record + MAXCNT at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype AMOUNT_TXD_AMOUNT_Field is HAL.UInt8; + + -- Number of bytes transferred in the last TXD transaction + type AMOUNT_TXD_Register is record + -- Read-only. Number of bytes transferred in the last TXD transaction + AMOUNT : AMOUNT_TXD_AMOUNT_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for AMOUNT_TXD_Register use record + AMOUNT at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- TXD EasyDMA channel + type TWIS_TXD_Cluster is record + -- TXD Data pointer + PTR : aliased HAL.UInt32; + -- Maximum number of bytes in TXD buffer + MAXCNT : aliased MAXCNT_TXD_Register; + -- Number of bytes transferred in the last TXD transaction + AMOUNT : aliased AMOUNT_TXD_Register; + end record + with Size => 96; + + for TWIS_TXD_Cluster use record + PTR at 16#0# range 0 .. 31; + MAXCNT at 16#4# range 0 .. 31; + AMOUNT at 16#8# range 0 .. 31; + end record; + + subtype ADDRESS_ADDRESS_Field is HAL.UInt7; + + -- Description collection[0]: TWI slave address 0 + type ADDRESS_Register is record + -- TWI slave address + ADDRESS : ADDRESS_ADDRESS_Field := 16#0#; + -- unspecified + Reserved_7_31 : HAL.UInt25 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ADDRESS_Register use record + ADDRESS at 0 range 0 .. 6; + Reserved_7_31 at 0 range 7 .. 31; + end record; + + -- Description collection[0]: TWI slave address 0 + type ADDRESS_Registers is array (0 .. 1) of ADDRESS_Register; + + -- Enable or disable address matching on ADDRESS[0] + type CONFIG_ADDRESS0_Field is + (-- Disabled + Disabled, + -- Enabled + Enabled) + with Size => 1; + for CONFIG_ADDRESS0_Field use + (Disabled => 0, + Enabled => 1); + + -- CONFIG_ADDRESS array + type CONFIG_ADDRESS_Field_Array is array (0 .. 1) of CONFIG_ADDRESS0_Field + with Component_Size => 1, Size => 2; + + -- Type definition for CONFIG_ADDRESS + type CONFIG_ADDRESS_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- ADDRESS as a value + Val : HAL.UInt2; + when True => + -- ADDRESS as an array + Arr : CONFIG_ADDRESS_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for CONFIG_ADDRESS_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Configuration register for the address match mechanism + type CONFIG_Register is record + -- Enable or disable address matching on ADDRESS[0] + ADDRESS : CONFIG_ADDRESS_Field := + (As_Array => False, Val => 16#1#); + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CONFIG_Register use record + ADDRESS at 0 range 0 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + subtype ORC_ORC_Field is HAL.UInt8; + + -- Over-read character. Character sent out in case of an over-read of the + -- transmit buffer. + type ORC_Register is record + -- Over-read character. Character sent out in case of an over-read of + -- the transmit buffer. + ORC : ORC_ORC_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ORC_Register use record + ORC at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + ----------------------------------- + -- TWIS_PSEL cluster's Registers -- + ----------------------------------- + + ---------------------------------- + -- TWIS_RXD cluster's Registers -- + ---------------------------------- + + ---------------------------------- + -- TWIS_TXD cluster's Registers -- + ---------------------------------- + + ----------------- + -- Peripherals -- + ----------------- + + -- I2C compatible Two-Wire Slave Interface with EasyDMA 0 + type TWIS_Peripheral is record + -- Stop TWI transaction + TASKS_STOP : aliased HAL.UInt32; + -- Suspend TWI transaction + TASKS_SUSPEND : aliased HAL.UInt32; + -- Resume TWI transaction + TASKS_RESUME : aliased HAL.UInt32; + -- Prepare the TWI slave to respond to a write command + TASKS_PREPARERX : aliased HAL.UInt32; + -- Prepare the TWI slave to respond to a read command + TASKS_PREPARETX : aliased HAL.UInt32; + -- TWI stopped + EVENTS_STOPPED : aliased HAL.UInt32; + -- TWI error + EVENTS_ERROR : aliased HAL.UInt32; + -- Receive sequence started + EVENTS_RXSTARTED : aliased HAL.UInt32; + -- Transmit sequence started + EVENTS_TXSTARTED : aliased HAL.UInt32; + -- Write command received + EVENTS_WRITE : aliased HAL.UInt32; + -- Read command received + EVENTS_READ : aliased HAL.UInt32; + -- Shortcut register + SHORTS : aliased SHORTS_Register; + -- Enable or disable interrupt + INTEN : aliased INTEN_Register; + -- Enable interrupt + INTENSET : aliased INTENSET_Register; + -- Disable interrupt + INTENCLR : aliased INTENCLR_Register; + -- Error source + ERRORSRC : aliased ERRORSRC_Register; + -- Status register indicating which address had a match + MATCH : aliased MATCH_Register; + -- Enable TWIS + ENABLE : aliased ENABLE_Register; + -- Unspecified + PSEL : aliased TWIS_PSEL_Cluster; + -- RXD EasyDMA channel + RXD : aliased TWIS_RXD_Cluster; + -- TXD EasyDMA channel + TXD : aliased TWIS_TXD_Cluster; + -- Description collection[0]: TWI slave address 0 + ADDRESS : aliased ADDRESS_Registers; + -- Configuration register for the address match mechanism + CONFIG : aliased CONFIG_Register; + -- Over-read character. Character sent out in case of an over-read of + -- the transmit buffer. + ORC : aliased ORC_Register; + end record + with Volatile; + + for TWIS_Peripheral use record + TASKS_STOP at 16#14# range 0 .. 31; + TASKS_SUSPEND at 16#1C# range 0 .. 31; + TASKS_RESUME at 16#20# range 0 .. 31; + TASKS_PREPARERX at 16#30# range 0 .. 31; + TASKS_PREPARETX at 16#34# range 0 .. 31; + EVENTS_STOPPED at 16#104# range 0 .. 31; + EVENTS_ERROR at 16#124# range 0 .. 31; + EVENTS_RXSTARTED at 16#14C# range 0 .. 31; + EVENTS_TXSTARTED at 16#150# range 0 .. 31; + EVENTS_WRITE at 16#164# range 0 .. 31; + EVENTS_READ at 16#168# range 0 .. 31; + SHORTS at 16#200# range 0 .. 31; + INTEN at 16#300# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + ERRORSRC at 16#4D0# range 0 .. 31; + MATCH at 16#4D4# range 0 .. 31; + ENABLE at 16#500# range 0 .. 31; + PSEL at 16#508# range 0 .. 63; + RXD at 16#534# range 0 .. 95; + TXD at 16#544# range 0 .. 95; + ADDRESS at 16#588# range 0 .. 63; + CONFIG at 16#594# range 0 .. 31; + ORC at 16#5C0# range 0 .. 31; + end record; + + -- I2C compatible Two-Wire Slave Interface with EasyDMA 0 + TWIS0_Periph : aliased TWIS_Peripheral + with Import, Address => TWIS0_Base; + + -- I2C compatible Two-Wire Slave Interface with EasyDMA 1 + TWIS1_Periph : aliased TWIS_Peripheral + with Import, Address => TWIS1_Base; + +end NRF_SVD.TWIS; diff --git a/arch/ARM/Nordic/svd/nrf52/nrf_svd-uart.ads b/arch/ARM/Nordic/svd/nrf52/nrf_svd-uart.ads new file mode 100644 index 000000000..ed75ef68b --- /dev/null +++ b/arch/ARM/Nordic/svd/nrf52/nrf_svd-uart.ads @@ -0,0 +1,697 @@ +-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- 2. Redistributions in binary form, except as embedded into a Nordic +-- Semiconductor ASA integrated circuit in a product or a software update for +-- such product, must reproduce the above copyright notice, this list of +-- conditions and the following disclaimer in the documentation and/or other +-- materials provided with the distribution. +-- +-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from this +-- software without specific prior written permission. +-- +-- 4. This software, with or without modification, must only be used with a +-- Nordic Semiconductor ASA integrated circuit. +-- +-- 5. Any software provided in binary form under this license must not be reverse +-- engineered, decompiled, modified and/or disassembled. +-- +-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +-- OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + +-- This spec has been automatically generated from nrf52.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package NRF_SVD.UART is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Shortcut between CTS event and STARTRX task + type SHORTS_CTS_STARTRX_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_CTS_STARTRX_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut between NCTS event and STOPRX task + type SHORTS_NCTS_STOPRX_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_NCTS_STOPRX_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut register + type SHORTS_Register is record + -- unspecified + Reserved_0_2 : HAL.UInt3 := 16#0#; + -- Shortcut between CTS event and STARTRX task + CTS_STARTRX : SHORTS_CTS_STARTRX_Field := NRF_SVD.UART.Disabled; + -- Shortcut between NCTS event and STOPRX task + NCTS_STOPRX : SHORTS_NCTS_STOPRX_Field := NRF_SVD.UART.Disabled; + -- unspecified + Reserved_5_31 : HAL.UInt27 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SHORTS_Register use record + Reserved_0_2 at 0 range 0 .. 2; + CTS_STARTRX at 0 range 3 .. 3; + NCTS_STOPRX at 0 range 4 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + -- Write '1' to Enable interrupt for CTS event + type INTENSET_CTS_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_CTS_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for CTS event + type INTENSET_CTS_Field_1 is + (-- Reset value for the field + Intenset_Cts_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_CTS_Field_1 use + (Intenset_Cts_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for NCTS event + type INTENSET_NCTS_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_NCTS_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for NCTS event + type INTENSET_NCTS_Field_1 is + (-- Reset value for the field + Intenset_Ncts_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_NCTS_Field_1 use + (Intenset_Ncts_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for RXDRDY event + type INTENSET_RXDRDY_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_RXDRDY_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for RXDRDY event + type INTENSET_RXDRDY_Field_1 is + (-- Reset value for the field + Intenset_Rxdrdy_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_RXDRDY_Field_1 use + (Intenset_Rxdrdy_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for TXDRDY event + type INTENSET_TXDRDY_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_TXDRDY_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for TXDRDY event + type INTENSET_TXDRDY_Field_1 is + (-- Reset value for the field + Intenset_Txdrdy_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_TXDRDY_Field_1 use + (Intenset_Txdrdy_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for ERROR event + type INTENSET_ERROR_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_ERROR_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for ERROR event + type INTENSET_ERROR_Field_1 is + (-- Reset value for the field + Intenset_Error_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_ERROR_Field_1 use + (Intenset_Error_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for RXTO event + type INTENSET_RXTO_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_RXTO_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for RXTO event + type INTENSET_RXTO_Field_1 is + (-- Reset value for the field + Intenset_Rxto_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_RXTO_Field_1 use + (Intenset_Rxto_Field_Reset => 0, + Set => 1); + + -- Enable interrupt + type INTENSET_Register is record + -- Write '1' to Enable interrupt for CTS event + CTS : INTENSET_CTS_Field_1 := Intenset_Cts_Field_Reset; + -- Write '1' to Enable interrupt for NCTS event + NCTS : INTENSET_NCTS_Field_1 := Intenset_Ncts_Field_Reset; + -- Write '1' to Enable interrupt for RXDRDY event + RXDRDY : INTENSET_RXDRDY_Field_1 := Intenset_Rxdrdy_Field_Reset; + -- unspecified + Reserved_3_6 : HAL.UInt4 := 16#0#; + -- Write '1' to Enable interrupt for TXDRDY event + TXDRDY : INTENSET_TXDRDY_Field_1 := Intenset_Txdrdy_Field_Reset; + -- unspecified + Reserved_8_8 : HAL.Bit := 16#0#; + -- Write '1' to Enable interrupt for ERROR event + ERROR : INTENSET_ERROR_Field_1 := Intenset_Error_Field_Reset; + -- unspecified + Reserved_10_16 : HAL.UInt7 := 16#0#; + -- Write '1' to Enable interrupt for RXTO event + RXTO : INTENSET_RXTO_Field_1 := Intenset_Rxto_Field_Reset; + -- unspecified + Reserved_18_31 : HAL.UInt14 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENSET_Register use record + CTS at 0 range 0 .. 0; + NCTS at 0 range 1 .. 1; + RXDRDY at 0 range 2 .. 2; + Reserved_3_6 at 0 range 3 .. 6; + TXDRDY at 0 range 7 .. 7; + Reserved_8_8 at 0 range 8 .. 8; + ERROR at 0 range 9 .. 9; + Reserved_10_16 at 0 range 10 .. 16; + RXTO at 0 range 17 .. 17; + Reserved_18_31 at 0 range 18 .. 31; + end record; + + -- Write '1' to Disable interrupt for CTS event + type INTENCLR_CTS_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_CTS_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for CTS event + type INTENCLR_CTS_Field_1 is + (-- Reset value for the field + Intenclr_Cts_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_CTS_Field_1 use + (Intenclr_Cts_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for NCTS event + type INTENCLR_NCTS_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_NCTS_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for NCTS event + type INTENCLR_NCTS_Field_1 is + (-- Reset value for the field + Intenclr_Ncts_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_NCTS_Field_1 use + (Intenclr_Ncts_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for RXDRDY event + type INTENCLR_RXDRDY_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_RXDRDY_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for RXDRDY event + type INTENCLR_RXDRDY_Field_1 is + (-- Reset value for the field + Intenclr_Rxdrdy_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_RXDRDY_Field_1 use + (Intenclr_Rxdrdy_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for TXDRDY event + type INTENCLR_TXDRDY_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_TXDRDY_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for TXDRDY event + type INTENCLR_TXDRDY_Field_1 is + (-- Reset value for the field + Intenclr_Txdrdy_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_TXDRDY_Field_1 use + (Intenclr_Txdrdy_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for ERROR event + type INTENCLR_ERROR_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_ERROR_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for ERROR event + type INTENCLR_ERROR_Field_1 is + (-- Reset value for the field + Intenclr_Error_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_ERROR_Field_1 use + (Intenclr_Error_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for RXTO event + type INTENCLR_RXTO_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_RXTO_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for RXTO event + type INTENCLR_RXTO_Field_1 is + (-- Reset value for the field + Intenclr_Rxto_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_RXTO_Field_1 use + (Intenclr_Rxto_Field_Reset => 0, + Clear => 1); + + -- Disable interrupt + type INTENCLR_Register is record + -- Write '1' to Disable interrupt for CTS event + CTS : INTENCLR_CTS_Field_1 := Intenclr_Cts_Field_Reset; + -- Write '1' to Disable interrupt for NCTS event + NCTS : INTENCLR_NCTS_Field_1 := Intenclr_Ncts_Field_Reset; + -- Write '1' to Disable interrupt for RXDRDY event + RXDRDY : INTENCLR_RXDRDY_Field_1 := Intenclr_Rxdrdy_Field_Reset; + -- unspecified + Reserved_3_6 : HAL.UInt4 := 16#0#; + -- Write '1' to Disable interrupt for TXDRDY event + TXDRDY : INTENCLR_TXDRDY_Field_1 := Intenclr_Txdrdy_Field_Reset; + -- unspecified + Reserved_8_8 : HAL.Bit := 16#0#; + -- Write '1' to Disable interrupt for ERROR event + ERROR : INTENCLR_ERROR_Field_1 := Intenclr_Error_Field_Reset; + -- unspecified + Reserved_10_16 : HAL.UInt7 := 16#0#; + -- Write '1' to Disable interrupt for RXTO event + RXTO : INTENCLR_RXTO_Field_1 := Intenclr_Rxto_Field_Reset; + -- unspecified + Reserved_18_31 : HAL.UInt14 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENCLR_Register use record + CTS at 0 range 0 .. 0; + NCTS at 0 range 1 .. 1; + RXDRDY at 0 range 2 .. 2; + Reserved_3_6 at 0 range 3 .. 6; + TXDRDY at 0 range 7 .. 7; + Reserved_8_8 at 0 range 8 .. 8; + ERROR at 0 range 9 .. 9; + Reserved_10_16 at 0 range 10 .. 16; + RXTO at 0 range 17 .. 17; + Reserved_18_31 at 0 range 18 .. 31; + end record; + + -- Overrun error + type ERRORSRC_OVERRUN_Field is + (-- Read: error not present + Notpresent, + -- Read: error present + Present) + with Size => 1; + for ERRORSRC_OVERRUN_Field use + (Notpresent => 0, + Present => 1); + + -- Parity error + type ERRORSRC_PARITY_Field is + (-- Read: error not present + Notpresent, + -- Read: error present + Present) + with Size => 1; + for ERRORSRC_PARITY_Field use + (Notpresent => 0, + Present => 1); + + -- Framing error occurred + type ERRORSRC_FRAMING_Field is + (-- Read: error not present + Notpresent, + -- Read: error present + Present) + with Size => 1; + for ERRORSRC_FRAMING_Field use + (Notpresent => 0, + Present => 1); + + -- Break condition + type ERRORSRC_BREAK_Field is + (-- Read: error not present + Notpresent, + -- Read: error present + Present) + with Size => 1; + for ERRORSRC_BREAK_Field use + (Notpresent => 0, + Present => 1); + + -- Error source + type ERRORSRC_Register is record + -- Overrun error + OVERRUN : ERRORSRC_OVERRUN_Field := NRF_SVD.UART.Notpresent; + -- Parity error + PARITY : ERRORSRC_PARITY_Field := NRF_SVD.UART.Notpresent; + -- Framing error occurred + FRAMING : ERRORSRC_FRAMING_Field := NRF_SVD.UART.Notpresent; + -- Break condition + BREAK : ERRORSRC_BREAK_Field := NRF_SVD.UART.Notpresent; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ERRORSRC_Register use record + OVERRUN at 0 range 0 .. 0; + PARITY at 0 range 1 .. 1; + FRAMING at 0 range 2 .. 2; + BREAK at 0 range 3 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- Enable or disable UART + type ENABLE_ENABLE_Field is + (-- Disable UART + Disabled, + -- Enable UART + Enabled) + with Size => 4; + for ENABLE_ENABLE_Field use + (Disabled => 0, + Enabled => 4); + + -- Enable UART + type ENABLE_Register is record + -- Enable or disable UART + ENABLE : ENABLE_ENABLE_Field := NRF_SVD.UART.Disabled; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ENABLE_Register use record + ENABLE at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + subtype RXD_RXD_Field is HAL.UInt8; + + -- RXD register + type RXD_Register is record + -- Read-only. *** Reading this field has side effects on other resources + -- ***. RX data received in previous transfers, double buffered + RXD : RXD_RXD_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RXD_Register use record + RXD at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype TXD_TXD_Field is HAL.UInt8; + + -- TXD register + type TXD_Register is record + -- Write-only. TX data to be transferred + TXD : TXD_TXD_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TXD_Register use record + TXD at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- Hardware flow control + type CONFIG_HWFC_Field is + (-- Disabled + Disabled, + -- Enabled + Enabled) + with Size => 1; + for CONFIG_HWFC_Field use + (Disabled => 0, + Enabled => 1); + + -- Parity + type CONFIG_PARITY_Field is + (-- Exclude parity bit + Excluded, + -- Include parity bit + Included) + with Size => 3; + for CONFIG_PARITY_Field use + (Excluded => 0, + Included => 7); + + -- Configuration of parity and hardware flow control + type CONFIG_Register is record + -- Hardware flow control + HWFC : CONFIG_HWFC_Field := NRF_SVD.UART.Disabled; + -- Parity + PARITY : CONFIG_PARITY_Field := NRF_SVD.UART.Excluded; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CONFIG_Register use record + HWFC at 0 range 0 .. 0; + PARITY at 0 range 1 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Universal Asynchronous Receiver/Transmitter + type UART_Peripheral is record + -- Start UART receiver + TASKS_STARTRX : aliased HAL.UInt32; + -- Stop UART receiver + TASKS_STOPRX : aliased HAL.UInt32; + -- Start UART transmitter + TASKS_STARTTX : aliased HAL.UInt32; + -- Stop UART transmitter + TASKS_STOPTX : aliased HAL.UInt32; + -- Suspend UART + TASKS_SUSPEND : aliased HAL.UInt32; + -- CTS is activated (set low). Clear To Send. + EVENTS_CTS : aliased HAL.UInt32; + -- CTS is deactivated (set high). Not Clear To Send. + EVENTS_NCTS : aliased HAL.UInt32; + -- Data received in RXD + EVENTS_RXDRDY : aliased HAL.UInt32; + -- Data sent from TXD + EVENTS_TXDRDY : aliased HAL.UInt32; + -- Error detected + EVENTS_ERROR : aliased HAL.UInt32; + -- Receiver timeout + EVENTS_RXTO : aliased HAL.UInt32; + -- Shortcut register + SHORTS : aliased SHORTS_Register; + -- Enable interrupt + INTENSET : aliased INTENSET_Register; + -- Disable interrupt + INTENCLR : aliased INTENCLR_Register; + -- Error source + ERRORSRC : aliased ERRORSRC_Register; + -- Enable UART + ENABLE : aliased ENABLE_Register; + -- Pin select for RTS + PSELRTS : aliased HAL.UInt32; + -- Pin select for TXD + PSELTXD : aliased HAL.UInt32; + -- Pin select for CTS + PSELCTS : aliased HAL.UInt32; + -- Pin select for RXD + PSELRXD : aliased HAL.UInt32; + -- RXD register + RXD : aliased RXD_Register; + -- TXD register + TXD : aliased TXD_Register; + -- Baud rate + BAUDRATE : aliased HAL.UInt32; + -- Configuration of parity and hardware flow control + CONFIG : aliased CONFIG_Register; + end record + with Volatile; + + for UART_Peripheral use record + TASKS_STARTRX at 16#0# range 0 .. 31; + TASKS_STOPRX at 16#4# range 0 .. 31; + TASKS_STARTTX at 16#8# range 0 .. 31; + TASKS_STOPTX at 16#C# range 0 .. 31; + TASKS_SUSPEND at 16#1C# range 0 .. 31; + EVENTS_CTS at 16#100# range 0 .. 31; + EVENTS_NCTS at 16#104# range 0 .. 31; + EVENTS_RXDRDY at 16#108# range 0 .. 31; + EVENTS_TXDRDY at 16#11C# range 0 .. 31; + EVENTS_ERROR at 16#124# range 0 .. 31; + EVENTS_RXTO at 16#144# range 0 .. 31; + SHORTS at 16#200# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + ERRORSRC at 16#480# range 0 .. 31; + ENABLE at 16#500# range 0 .. 31; + PSELRTS at 16#508# range 0 .. 31; + PSELTXD at 16#50C# range 0 .. 31; + PSELCTS at 16#510# range 0 .. 31; + PSELRXD at 16#514# range 0 .. 31; + RXD at 16#518# range 0 .. 31; + TXD at 16#51C# range 0 .. 31; + BAUDRATE at 16#524# range 0 .. 31; + CONFIG at 16#56C# range 0 .. 31; + end record; + + -- Universal Asynchronous Receiver/Transmitter + UART0_Periph : aliased UART_Peripheral + with Import, Address => UART0_Base; + +end NRF_SVD.UART; diff --git a/arch/ARM/Nordic/svd/nrf52/nrf_svd-uarte.ads b/arch/ARM/Nordic/svd/nrf52/nrf_svd-uarte.ads new file mode 100644 index 000000000..e38bc1275 --- /dev/null +++ b/arch/ARM/Nordic/svd/nrf52/nrf_svd-uarte.ads @@ -0,0 +1,1379 @@ +-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- 2. Redistributions in binary form, except as embedded into a Nordic +-- Semiconductor ASA integrated circuit in a product or a software update for +-- such product, must reproduce the above copyright notice, this list of +-- conditions and the following disclaimer in the documentation and/or other +-- materials provided with the distribution. +-- +-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from this +-- software without specific prior written permission. +-- +-- 4. This software, with or without modification, must only be used with a +-- Nordic Semiconductor ASA integrated circuit. +-- +-- 5. Any software provided in binary form under this license must not be reverse +-- engineered, decompiled, modified and/or disassembled. +-- +-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +-- OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + +-- This spec has been automatically generated from nrf52.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package NRF_SVD.UARTE is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Shortcut between ENDRX event and STARTRX task + type SHORTS_ENDRX_STARTRX_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_ENDRX_STARTRX_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut between ENDRX event and STOPRX task + type SHORTS_ENDRX_STOPRX_Field is + (-- Disable shortcut + Disabled, + -- Enable shortcut + Enabled) + with Size => 1; + for SHORTS_ENDRX_STOPRX_Field use + (Disabled => 0, + Enabled => 1); + + -- Shortcut register + type SHORTS_Register is record + -- unspecified + Reserved_0_4 : HAL.UInt5 := 16#0#; + -- Shortcut between ENDRX event and STARTRX task + ENDRX_STARTRX : SHORTS_ENDRX_STARTRX_Field := NRF_SVD.UARTE.Disabled; + -- Shortcut between ENDRX event and STOPRX task + ENDRX_STOPRX : SHORTS_ENDRX_STOPRX_Field := NRF_SVD.UARTE.Disabled; + -- unspecified + Reserved_7_31 : HAL.UInt25 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SHORTS_Register use record + Reserved_0_4 at 0 range 0 .. 4; + ENDRX_STARTRX at 0 range 5 .. 5; + ENDRX_STOPRX at 0 range 6 .. 6; + Reserved_7_31 at 0 range 7 .. 31; + end record; + + -- Enable or disable interrupt for CTS event + type INTEN_CTS_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_CTS_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for NCTS event + type INTEN_NCTS_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_NCTS_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for RXDRDY event + type INTEN_RXDRDY_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_RXDRDY_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for ENDRX event + type INTEN_ENDRX_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_ENDRX_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for TXDRDY event + type INTEN_TXDRDY_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_TXDRDY_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for ENDTX event + type INTEN_ENDTX_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_ENDTX_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for ERROR event + type INTEN_ERROR_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_ERROR_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for RXTO event + type INTEN_RXTO_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_RXTO_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for RXSTARTED event + type INTEN_RXSTARTED_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_RXSTARTED_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for TXSTARTED event + type INTEN_TXSTARTED_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_TXSTARTED_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt for TXSTOPPED event + type INTEN_TXSTOPPED_Field is + (-- Disable + Disabled, + -- Enable + Enabled) + with Size => 1; + for INTEN_TXSTOPPED_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable interrupt + type INTEN_Register is record + -- Enable or disable interrupt for CTS event + CTS : INTEN_CTS_Field := NRF_SVD.UARTE.Disabled; + -- Enable or disable interrupt for NCTS event + NCTS : INTEN_NCTS_Field := NRF_SVD.UARTE.Disabled; + -- Enable or disable interrupt for RXDRDY event + RXDRDY : INTEN_RXDRDY_Field := NRF_SVD.UARTE.Disabled; + -- unspecified + Reserved_3_3 : HAL.Bit := 16#0#; + -- Enable or disable interrupt for ENDRX event + ENDRX : INTEN_ENDRX_Field := NRF_SVD.UARTE.Disabled; + -- unspecified + Reserved_5_6 : HAL.UInt2 := 16#0#; + -- Enable or disable interrupt for TXDRDY event + TXDRDY : INTEN_TXDRDY_Field := NRF_SVD.UARTE.Disabled; + -- Enable or disable interrupt for ENDTX event + ENDTX : INTEN_ENDTX_Field := NRF_SVD.UARTE.Disabled; + -- Enable or disable interrupt for ERROR event + ERROR : INTEN_ERROR_Field := NRF_SVD.UARTE.Disabled; + -- unspecified + Reserved_10_16 : HAL.UInt7 := 16#0#; + -- Enable or disable interrupt for RXTO event + RXTO : INTEN_RXTO_Field := NRF_SVD.UARTE.Disabled; + -- unspecified + Reserved_18_18 : HAL.Bit := 16#0#; + -- Enable or disable interrupt for RXSTARTED event + RXSTARTED : INTEN_RXSTARTED_Field := NRF_SVD.UARTE.Disabled; + -- Enable or disable interrupt for TXSTARTED event + TXSTARTED : INTEN_TXSTARTED_Field := NRF_SVD.UARTE.Disabled; + -- unspecified + Reserved_21_21 : HAL.Bit := 16#0#; + -- Enable or disable interrupt for TXSTOPPED event + TXSTOPPED : INTEN_TXSTOPPED_Field := NRF_SVD.UARTE.Disabled; + -- unspecified + Reserved_23_31 : HAL.UInt9 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTEN_Register use record + CTS at 0 range 0 .. 0; + NCTS at 0 range 1 .. 1; + RXDRDY at 0 range 2 .. 2; + Reserved_3_3 at 0 range 3 .. 3; + ENDRX at 0 range 4 .. 4; + Reserved_5_6 at 0 range 5 .. 6; + TXDRDY at 0 range 7 .. 7; + ENDTX at 0 range 8 .. 8; + ERROR at 0 range 9 .. 9; + Reserved_10_16 at 0 range 10 .. 16; + RXTO at 0 range 17 .. 17; + Reserved_18_18 at 0 range 18 .. 18; + RXSTARTED at 0 range 19 .. 19; + TXSTARTED at 0 range 20 .. 20; + Reserved_21_21 at 0 range 21 .. 21; + TXSTOPPED at 0 range 22 .. 22; + Reserved_23_31 at 0 range 23 .. 31; + end record; + + -- Write '1' to Enable interrupt for CTS event + type INTENSET_CTS_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_CTS_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for CTS event + type INTENSET_CTS_Field_1 is + (-- Reset value for the field + Intenset_Cts_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_CTS_Field_1 use + (Intenset_Cts_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for NCTS event + type INTENSET_NCTS_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_NCTS_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for NCTS event + type INTENSET_NCTS_Field_1 is + (-- Reset value for the field + Intenset_Ncts_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_NCTS_Field_1 use + (Intenset_Ncts_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for RXDRDY event + type INTENSET_RXDRDY_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_RXDRDY_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for RXDRDY event + type INTENSET_RXDRDY_Field_1 is + (-- Reset value for the field + Intenset_Rxdrdy_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_RXDRDY_Field_1 use + (Intenset_Rxdrdy_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for ENDRX event + type INTENSET_ENDRX_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_ENDRX_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for ENDRX event + type INTENSET_ENDRX_Field_1 is + (-- Reset value for the field + Intenset_Endrx_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_ENDRX_Field_1 use + (Intenset_Endrx_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for TXDRDY event + type INTENSET_TXDRDY_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_TXDRDY_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for TXDRDY event + type INTENSET_TXDRDY_Field_1 is + (-- Reset value for the field + Intenset_Txdrdy_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_TXDRDY_Field_1 use + (Intenset_Txdrdy_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for ENDTX event + type INTENSET_ENDTX_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_ENDTX_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for ENDTX event + type INTENSET_ENDTX_Field_1 is + (-- Reset value for the field + Intenset_Endtx_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_ENDTX_Field_1 use + (Intenset_Endtx_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for ERROR event + type INTENSET_ERROR_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_ERROR_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for ERROR event + type INTENSET_ERROR_Field_1 is + (-- Reset value for the field + Intenset_Error_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_ERROR_Field_1 use + (Intenset_Error_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for RXTO event + type INTENSET_RXTO_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_RXTO_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for RXTO event + type INTENSET_RXTO_Field_1 is + (-- Reset value for the field + Intenset_Rxto_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_RXTO_Field_1 use + (Intenset_Rxto_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for RXSTARTED event + type INTENSET_RXSTARTED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_RXSTARTED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for RXSTARTED event + type INTENSET_RXSTARTED_Field_1 is + (-- Reset value for the field + Intenset_Rxstarted_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_RXSTARTED_Field_1 use + (Intenset_Rxstarted_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for TXSTARTED event + type INTENSET_TXSTARTED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_TXSTARTED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for TXSTARTED event + type INTENSET_TXSTARTED_Field_1 is + (-- Reset value for the field + Intenset_Txstarted_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_TXSTARTED_Field_1 use + (Intenset_Txstarted_Field_Reset => 0, + Set => 1); + + -- Write '1' to Enable interrupt for TXSTOPPED event + type INTENSET_TXSTOPPED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_TXSTOPPED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for TXSTOPPED event + type INTENSET_TXSTOPPED_Field_1 is + (-- Reset value for the field + Intenset_Txstopped_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_TXSTOPPED_Field_1 use + (Intenset_Txstopped_Field_Reset => 0, + Set => 1); + + -- Enable interrupt + type INTENSET_Register is record + -- Write '1' to Enable interrupt for CTS event + CTS : INTENSET_CTS_Field_1 := Intenset_Cts_Field_Reset; + -- Write '1' to Enable interrupt for NCTS event + NCTS : INTENSET_NCTS_Field_1 := Intenset_Ncts_Field_Reset; + -- Write '1' to Enable interrupt for RXDRDY event + RXDRDY : INTENSET_RXDRDY_Field_1 := Intenset_Rxdrdy_Field_Reset; + -- unspecified + Reserved_3_3 : HAL.Bit := 16#0#; + -- Write '1' to Enable interrupt for ENDRX event + ENDRX : INTENSET_ENDRX_Field_1 := Intenset_Endrx_Field_Reset; + -- unspecified + Reserved_5_6 : HAL.UInt2 := 16#0#; + -- Write '1' to Enable interrupt for TXDRDY event + TXDRDY : INTENSET_TXDRDY_Field_1 := Intenset_Txdrdy_Field_Reset; + -- Write '1' to Enable interrupt for ENDTX event + ENDTX : INTENSET_ENDTX_Field_1 := Intenset_Endtx_Field_Reset; + -- Write '1' to Enable interrupt for ERROR event + ERROR : INTENSET_ERROR_Field_1 := Intenset_Error_Field_Reset; + -- unspecified + Reserved_10_16 : HAL.UInt7 := 16#0#; + -- Write '1' to Enable interrupt for RXTO event + RXTO : INTENSET_RXTO_Field_1 := Intenset_Rxto_Field_Reset; + -- unspecified + Reserved_18_18 : HAL.Bit := 16#0#; + -- Write '1' to Enable interrupt for RXSTARTED event + RXSTARTED : INTENSET_RXSTARTED_Field_1 := + Intenset_Rxstarted_Field_Reset; + -- Write '1' to Enable interrupt for TXSTARTED event + TXSTARTED : INTENSET_TXSTARTED_Field_1 := + Intenset_Txstarted_Field_Reset; + -- unspecified + Reserved_21_21 : HAL.Bit := 16#0#; + -- Write '1' to Enable interrupt for TXSTOPPED event + TXSTOPPED : INTENSET_TXSTOPPED_Field_1 := + Intenset_Txstopped_Field_Reset; + -- unspecified + Reserved_23_31 : HAL.UInt9 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENSET_Register use record + CTS at 0 range 0 .. 0; + NCTS at 0 range 1 .. 1; + RXDRDY at 0 range 2 .. 2; + Reserved_3_3 at 0 range 3 .. 3; + ENDRX at 0 range 4 .. 4; + Reserved_5_6 at 0 range 5 .. 6; + TXDRDY at 0 range 7 .. 7; + ENDTX at 0 range 8 .. 8; + ERROR at 0 range 9 .. 9; + Reserved_10_16 at 0 range 10 .. 16; + RXTO at 0 range 17 .. 17; + Reserved_18_18 at 0 range 18 .. 18; + RXSTARTED at 0 range 19 .. 19; + TXSTARTED at 0 range 20 .. 20; + Reserved_21_21 at 0 range 21 .. 21; + TXSTOPPED at 0 range 22 .. 22; + Reserved_23_31 at 0 range 23 .. 31; + end record; + + -- Write '1' to Disable interrupt for CTS event + type INTENCLR_CTS_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_CTS_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for CTS event + type INTENCLR_CTS_Field_1 is + (-- Reset value for the field + Intenclr_Cts_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_CTS_Field_1 use + (Intenclr_Cts_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for NCTS event + type INTENCLR_NCTS_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_NCTS_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for NCTS event + type INTENCLR_NCTS_Field_1 is + (-- Reset value for the field + Intenclr_Ncts_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_NCTS_Field_1 use + (Intenclr_Ncts_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for RXDRDY event + type INTENCLR_RXDRDY_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_RXDRDY_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for RXDRDY event + type INTENCLR_RXDRDY_Field_1 is + (-- Reset value for the field + Intenclr_Rxdrdy_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_RXDRDY_Field_1 use + (Intenclr_Rxdrdy_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for ENDRX event + type INTENCLR_ENDRX_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_ENDRX_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for ENDRX event + type INTENCLR_ENDRX_Field_1 is + (-- Reset value for the field + Intenclr_Endrx_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_ENDRX_Field_1 use + (Intenclr_Endrx_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for TXDRDY event + type INTENCLR_TXDRDY_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_TXDRDY_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for TXDRDY event + type INTENCLR_TXDRDY_Field_1 is + (-- Reset value for the field + Intenclr_Txdrdy_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_TXDRDY_Field_1 use + (Intenclr_Txdrdy_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for ENDTX event + type INTENCLR_ENDTX_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_ENDTX_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for ENDTX event + type INTENCLR_ENDTX_Field_1 is + (-- Reset value for the field + Intenclr_Endtx_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_ENDTX_Field_1 use + (Intenclr_Endtx_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for ERROR event + type INTENCLR_ERROR_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_ERROR_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for ERROR event + type INTENCLR_ERROR_Field_1 is + (-- Reset value for the field + Intenclr_Error_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_ERROR_Field_1 use + (Intenclr_Error_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for RXTO event + type INTENCLR_RXTO_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_RXTO_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for RXTO event + type INTENCLR_RXTO_Field_1 is + (-- Reset value for the field + Intenclr_Rxto_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_RXTO_Field_1 use + (Intenclr_Rxto_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for RXSTARTED event + type INTENCLR_RXSTARTED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_RXSTARTED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for RXSTARTED event + type INTENCLR_RXSTARTED_Field_1 is + (-- Reset value for the field + Intenclr_Rxstarted_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_RXSTARTED_Field_1 use + (Intenclr_Rxstarted_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for TXSTARTED event + type INTENCLR_TXSTARTED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_TXSTARTED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for TXSTARTED event + type INTENCLR_TXSTARTED_Field_1 is + (-- Reset value for the field + Intenclr_Txstarted_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_TXSTARTED_Field_1 use + (Intenclr_Txstarted_Field_Reset => 0, + Clear => 1); + + -- Write '1' to Disable interrupt for TXSTOPPED event + type INTENCLR_TXSTOPPED_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_TXSTOPPED_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for TXSTOPPED event + type INTENCLR_TXSTOPPED_Field_1 is + (-- Reset value for the field + Intenclr_Txstopped_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_TXSTOPPED_Field_1 use + (Intenclr_Txstopped_Field_Reset => 0, + Clear => 1); + + -- Disable interrupt + type INTENCLR_Register is record + -- Write '1' to Disable interrupt for CTS event + CTS : INTENCLR_CTS_Field_1 := Intenclr_Cts_Field_Reset; + -- Write '1' to Disable interrupt for NCTS event + NCTS : INTENCLR_NCTS_Field_1 := Intenclr_Ncts_Field_Reset; + -- Write '1' to Disable interrupt for RXDRDY event + RXDRDY : INTENCLR_RXDRDY_Field_1 := Intenclr_Rxdrdy_Field_Reset; + -- unspecified + Reserved_3_3 : HAL.Bit := 16#0#; + -- Write '1' to Disable interrupt for ENDRX event + ENDRX : INTENCLR_ENDRX_Field_1 := Intenclr_Endrx_Field_Reset; + -- unspecified + Reserved_5_6 : HAL.UInt2 := 16#0#; + -- Write '1' to Disable interrupt for TXDRDY event + TXDRDY : INTENCLR_TXDRDY_Field_1 := Intenclr_Txdrdy_Field_Reset; + -- Write '1' to Disable interrupt for ENDTX event + ENDTX : INTENCLR_ENDTX_Field_1 := Intenclr_Endtx_Field_Reset; + -- Write '1' to Disable interrupt for ERROR event + ERROR : INTENCLR_ERROR_Field_1 := Intenclr_Error_Field_Reset; + -- unspecified + Reserved_10_16 : HAL.UInt7 := 16#0#; + -- Write '1' to Disable interrupt for RXTO event + RXTO : INTENCLR_RXTO_Field_1 := Intenclr_Rxto_Field_Reset; + -- unspecified + Reserved_18_18 : HAL.Bit := 16#0#; + -- Write '1' to Disable interrupt for RXSTARTED event + RXSTARTED : INTENCLR_RXSTARTED_Field_1 := + Intenclr_Rxstarted_Field_Reset; + -- Write '1' to Disable interrupt for TXSTARTED event + TXSTARTED : INTENCLR_TXSTARTED_Field_1 := + Intenclr_Txstarted_Field_Reset; + -- unspecified + Reserved_21_21 : HAL.Bit := 16#0#; + -- Write '1' to Disable interrupt for TXSTOPPED event + TXSTOPPED : INTENCLR_TXSTOPPED_Field_1 := + Intenclr_Txstopped_Field_Reset; + -- unspecified + Reserved_23_31 : HAL.UInt9 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENCLR_Register use record + CTS at 0 range 0 .. 0; + NCTS at 0 range 1 .. 1; + RXDRDY at 0 range 2 .. 2; + Reserved_3_3 at 0 range 3 .. 3; + ENDRX at 0 range 4 .. 4; + Reserved_5_6 at 0 range 5 .. 6; + TXDRDY at 0 range 7 .. 7; + ENDTX at 0 range 8 .. 8; + ERROR at 0 range 9 .. 9; + Reserved_10_16 at 0 range 10 .. 16; + RXTO at 0 range 17 .. 17; + Reserved_18_18 at 0 range 18 .. 18; + RXSTARTED at 0 range 19 .. 19; + TXSTARTED at 0 range 20 .. 20; + Reserved_21_21 at 0 range 21 .. 21; + TXSTOPPED at 0 range 22 .. 22; + Reserved_23_31 at 0 range 23 .. 31; + end record; + + -- Overrun error + type ERRORSRC_OVERRUN_Field is + (-- Read: error not present + Notpresent, + -- Read: error present + Present) + with Size => 1; + for ERRORSRC_OVERRUN_Field use + (Notpresent => 0, + Present => 1); + + -- Parity error + type ERRORSRC_PARITY_Field is + (-- Read: error not present + Notpresent, + -- Read: error present + Present) + with Size => 1; + for ERRORSRC_PARITY_Field use + (Notpresent => 0, + Present => 1); + + -- Framing error occurred + type ERRORSRC_FRAMING_Field is + (-- Read: error not present + Notpresent, + -- Read: error present + Present) + with Size => 1; + for ERRORSRC_FRAMING_Field use + (Notpresent => 0, + Present => 1); + + -- Break condition + type ERRORSRC_BREAK_Field is + (-- Read: error not present + Notpresent, + -- Read: error present + Present) + with Size => 1; + for ERRORSRC_BREAK_Field use + (Notpresent => 0, + Present => 1); + + -- Error source + type ERRORSRC_Register is record + -- Overrun error + OVERRUN : ERRORSRC_OVERRUN_Field := NRF_SVD.UARTE.Notpresent; + -- Parity error + PARITY : ERRORSRC_PARITY_Field := NRF_SVD.UARTE.Notpresent; + -- Framing error occurred + FRAMING : ERRORSRC_FRAMING_Field := NRF_SVD.UARTE.Notpresent; + -- Break condition + BREAK : ERRORSRC_BREAK_Field := NRF_SVD.UARTE.Notpresent; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ERRORSRC_Register use record + OVERRUN at 0 range 0 .. 0; + PARITY at 0 range 1 .. 1; + FRAMING at 0 range 2 .. 2; + BREAK at 0 range 3 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- Enable or disable UARTE + type ENABLE_ENABLE_Field is + (-- Disable UARTE + Disabled, + -- Enable UARTE + Enabled) + with Size => 4; + for ENABLE_ENABLE_Field use + (Disabled => 0, + Enabled => 8); + + -- Enable UART + type ENABLE_Register is record + -- Enable or disable UARTE + ENABLE : ENABLE_ENABLE_Field := NRF_SVD.UARTE.Disabled; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ENABLE_Register use record + ENABLE at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + ------------------------------------ + -- UARTE_PSEL cluster's Registers -- + ------------------------------------ + + subtype RTS_PSEL_PIN_Field is HAL.UInt5; + + -- Connection + type RTS_CONNECT_Field is + (-- Connect + Connected, + -- Disconnect + Disconnected) + with Size => 1; + for RTS_CONNECT_Field use + (Connected => 0, + Disconnected => 1); + + -- Pin select for RTS signal + type RTS_PSEL_Register is record + -- Pin number + PIN : RTS_PSEL_PIN_Field := 16#1F#; + -- unspecified + Reserved_5_30 : HAL.UInt26 := 16#3FFFFFF#; + -- Connection + CONNECT : RTS_CONNECT_Field := NRF_SVD.UARTE.Disconnected; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RTS_PSEL_Register use record + PIN at 0 range 0 .. 4; + Reserved_5_30 at 0 range 5 .. 30; + CONNECT at 0 range 31 .. 31; + end record; + + subtype TXD_PSEL_PIN_Field is HAL.UInt5; + + -- Connection + type TXD_CONNECT_Field is + (-- Connect + Connected, + -- Disconnect + Disconnected) + with Size => 1; + for TXD_CONNECT_Field use + (Connected => 0, + Disconnected => 1); + + -- Pin select for TXD signal + type TXD_PSEL_Register is record + -- Pin number + PIN : TXD_PSEL_PIN_Field := 16#1F#; + -- unspecified + Reserved_5_30 : HAL.UInt26 := 16#3FFFFFF#; + -- Connection + CONNECT : TXD_CONNECT_Field := NRF_SVD.UARTE.Disconnected; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TXD_PSEL_Register use record + PIN at 0 range 0 .. 4; + Reserved_5_30 at 0 range 5 .. 30; + CONNECT at 0 range 31 .. 31; + end record; + + subtype CTS_PSEL_PIN_Field is HAL.UInt5; + + -- Connection + type CTS_CONNECT_Field is + (-- Connect + Connected, + -- Disconnect + Disconnected) + with Size => 1; + for CTS_CONNECT_Field use + (Connected => 0, + Disconnected => 1); + + -- Pin select for CTS signal + type CTS_PSEL_Register is record + -- Pin number + PIN : CTS_PSEL_PIN_Field := 16#1F#; + -- unspecified + Reserved_5_30 : HAL.UInt26 := 16#3FFFFFF#; + -- Connection + CONNECT : CTS_CONNECT_Field := NRF_SVD.UARTE.Disconnected; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CTS_PSEL_Register use record + PIN at 0 range 0 .. 4; + Reserved_5_30 at 0 range 5 .. 30; + CONNECT at 0 range 31 .. 31; + end record; + + subtype RXD_PSEL_PIN_Field is HAL.UInt5; + + -- Connection + type RXD_CONNECT_Field is + (-- Connect + Connected, + -- Disconnect + Disconnected) + with Size => 1; + for RXD_CONNECT_Field use + (Connected => 0, + Disconnected => 1); + + -- Pin select for RXD signal + type RXD_PSEL_Register is record + -- Pin number + PIN : RXD_PSEL_PIN_Field := 16#1F#; + -- unspecified + Reserved_5_30 : HAL.UInt26 := 16#3FFFFFF#; + -- Connection + CONNECT : RXD_CONNECT_Field := NRF_SVD.UARTE.Disconnected; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RXD_PSEL_Register use record + PIN at 0 range 0 .. 4; + Reserved_5_30 at 0 range 5 .. 30; + CONNECT at 0 range 31 .. 31; + end record; + + -- Unspecified + type UARTE_PSEL_Cluster is record + -- Pin select for RTS signal + RTS : aliased RTS_PSEL_Register; + -- Pin select for TXD signal + TXD : aliased TXD_PSEL_Register; + -- Pin select for CTS signal + CTS : aliased CTS_PSEL_Register; + -- Pin select for RXD signal + RXD : aliased RXD_PSEL_Register; + end record + with Size => 128; + + for UARTE_PSEL_Cluster use record + RTS at 16#0# range 0 .. 31; + TXD at 16#4# range 0 .. 31; + CTS at 16#8# range 0 .. 31; + RXD at 16#C# range 0 .. 31; + end record; + + ----------------------------------- + -- UARTE_RXD cluster's Registers -- + ----------------------------------- + + subtype MAXCNT_RXD_MAXCNT_Field is HAL.UInt8; + + -- Maximum number of bytes in receive buffer + type MAXCNT_RXD_Register is record + -- Maximum number of bytes in receive buffer + MAXCNT : MAXCNT_RXD_MAXCNT_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MAXCNT_RXD_Register use record + MAXCNT at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype AMOUNT_RXD_AMOUNT_Field is HAL.UInt8; + + -- Number of bytes transferred in the last transaction + type AMOUNT_RXD_Register is record + -- Read-only. Number of bytes transferred in the last transaction + AMOUNT : AMOUNT_RXD_AMOUNT_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for AMOUNT_RXD_Register use record + AMOUNT at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- RXD EasyDMA channel + type UARTE_RXD_Cluster is record + -- Data pointer + PTR : aliased HAL.UInt32; + -- Maximum number of bytes in receive buffer + MAXCNT : aliased MAXCNT_RXD_Register; + -- Number of bytes transferred in the last transaction + AMOUNT : aliased AMOUNT_RXD_Register; + end record + with Size => 96; + + for UARTE_RXD_Cluster use record + PTR at 16#0# range 0 .. 31; + MAXCNT at 16#4# range 0 .. 31; + AMOUNT at 16#8# range 0 .. 31; + end record; + + ----------------------------------- + -- UARTE_TXD cluster's Registers -- + ----------------------------------- + + subtype MAXCNT_TXD_MAXCNT_Field is HAL.UInt8; + + -- Maximum number of bytes in transmit buffer + type MAXCNT_TXD_Register is record + -- Maximum number of bytes in transmit buffer + MAXCNT : MAXCNT_TXD_MAXCNT_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MAXCNT_TXD_Register use record + MAXCNT at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype AMOUNT_TXD_AMOUNT_Field is HAL.UInt8; + + -- Number of bytes transferred in the last transaction + type AMOUNT_TXD_Register is record + -- Read-only. Number of bytes transferred in the last transaction + AMOUNT : AMOUNT_TXD_AMOUNT_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for AMOUNT_TXD_Register use record + AMOUNT at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- TXD EasyDMA channel + type UARTE_TXD_Cluster is record + -- Data pointer + PTR : aliased HAL.UInt32; + -- Maximum number of bytes in transmit buffer + MAXCNT : aliased MAXCNT_TXD_Register; + -- Number of bytes transferred in the last transaction + AMOUNT : aliased AMOUNT_TXD_Register; + end record + with Size => 96; + + for UARTE_TXD_Cluster use record + PTR at 16#0# range 0 .. 31; + MAXCNT at 16#4# range 0 .. 31; + AMOUNT at 16#8# range 0 .. 31; + end record; + + -- Hardware flow control + type CONFIG_HWFC_Field is + (-- Disabled + Disabled, + -- Enabled + Enabled) + with Size => 1; + for CONFIG_HWFC_Field use + (Disabled => 0, + Enabled => 1); + + -- Parity + type CONFIG_PARITY_Field is + (-- Exclude parity bit + Excluded, + -- Include parity bit + Included) + with Size => 3; + for CONFIG_PARITY_Field use + (Excluded => 0, + Included => 7); + + -- Configuration of parity and hardware flow control + type CONFIG_Register is record + -- Hardware flow control + HWFC : CONFIG_HWFC_Field := NRF_SVD.UARTE.Disabled; + -- Parity + PARITY : CONFIG_PARITY_Field := NRF_SVD.UARTE.Excluded; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CONFIG_Register use record + HWFC at 0 range 0 .. 0; + PARITY at 0 range 1 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- UART with EasyDMA + type UARTE_Peripheral is record + -- Start UART receiver + TASKS_STARTRX : aliased HAL.UInt32; + -- Stop UART receiver + TASKS_STOPRX : aliased HAL.UInt32; + -- Start UART transmitter + TASKS_STARTTX : aliased HAL.UInt32; + -- Stop UART transmitter + TASKS_STOPTX : aliased HAL.UInt32; + -- Flush RX FIFO into RX buffer + TASKS_FLUSHRX : aliased HAL.UInt32; + -- CTS is activated (set low). Clear To Send. + EVENTS_CTS : aliased HAL.UInt32; + -- CTS is deactivated (set high). Not Clear To Send. + EVENTS_NCTS : aliased HAL.UInt32; + -- Data received in RXD (but potentially not yet transferred to Data + -- RAM) + EVENTS_RXDRDY : aliased HAL.UInt32; + -- Receive buffer is filled up + EVENTS_ENDRX : aliased HAL.UInt32; + -- Data sent from TXD + EVENTS_TXDRDY : aliased HAL.UInt32; + -- Last TX byte transmitted + EVENTS_ENDTX : aliased HAL.UInt32; + -- Error detected + EVENTS_ERROR : aliased HAL.UInt32; + -- Receiver timeout + EVENTS_RXTO : aliased HAL.UInt32; + -- UART receiver has started + EVENTS_RXSTARTED : aliased HAL.UInt32; + -- UART transmitter has started + EVENTS_TXSTARTED : aliased HAL.UInt32; + -- Transmitter stopped + EVENTS_TXSTOPPED : aliased HAL.UInt32; + -- Shortcut register + SHORTS : aliased SHORTS_Register; + -- Enable or disable interrupt + INTEN : aliased INTEN_Register; + -- Enable interrupt + INTENSET : aliased INTENSET_Register; + -- Disable interrupt + INTENCLR : aliased INTENCLR_Register; + -- Error source + ERRORSRC : aliased ERRORSRC_Register; + -- Enable UART + ENABLE : aliased ENABLE_Register; + -- Unspecified + PSEL : aliased UARTE_PSEL_Cluster; + -- Baud rate. Accuracy depends on the HFCLK source selected. + BAUDRATE : aliased HAL.UInt32; + -- RXD EasyDMA channel + RXD : aliased UARTE_RXD_Cluster; + -- TXD EasyDMA channel + TXD : aliased UARTE_TXD_Cluster; + -- Configuration of parity and hardware flow control + CONFIG : aliased CONFIG_Register; + end record + with Volatile; + + for UARTE_Peripheral use record + TASKS_STARTRX at 16#0# range 0 .. 31; + TASKS_STOPRX at 16#4# range 0 .. 31; + TASKS_STARTTX at 16#8# range 0 .. 31; + TASKS_STOPTX at 16#C# range 0 .. 31; + TASKS_FLUSHRX at 16#2C# range 0 .. 31; + EVENTS_CTS at 16#100# range 0 .. 31; + EVENTS_NCTS at 16#104# range 0 .. 31; + EVENTS_RXDRDY at 16#108# range 0 .. 31; + EVENTS_ENDRX at 16#110# range 0 .. 31; + EVENTS_TXDRDY at 16#11C# range 0 .. 31; + EVENTS_ENDTX at 16#120# range 0 .. 31; + EVENTS_ERROR at 16#124# range 0 .. 31; + EVENTS_RXTO at 16#144# range 0 .. 31; + EVENTS_RXSTARTED at 16#14C# range 0 .. 31; + EVENTS_TXSTARTED at 16#150# range 0 .. 31; + EVENTS_TXSTOPPED at 16#158# range 0 .. 31; + SHORTS at 16#200# range 0 .. 31; + INTEN at 16#300# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + ERRORSRC at 16#480# range 0 .. 31; + ENABLE at 16#500# range 0 .. 31; + PSEL at 16#508# range 0 .. 127; + BAUDRATE at 16#524# range 0 .. 31; + RXD at 16#534# range 0 .. 95; + TXD at 16#544# range 0 .. 95; + CONFIG at 16#56C# range 0 .. 31; + end record; + + -- UART with EasyDMA + UARTE0_Periph : aliased UARTE_Peripheral + with Import, Address => UARTE0_Base; + +end NRF_SVD.UARTE; diff --git a/arch/ARM/Nordic/svd/nrf52/nrf_svd-uicr.ads b/arch/ARM/Nordic/svd/nrf52/nrf_svd-uicr.ads new file mode 100644 index 000000000..0a26c88d7 --- /dev/null +++ b/arch/ARM/Nordic/svd/nrf52/nrf_svd-uicr.ads @@ -0,0 +1,207 @@ +-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- 2. Redistributions in binary form, except as embedded into a Nordic +-- Semiconductor ASA integrated circuit in a product or a software update for +-- such product, must reproduce the above copyright notice, this list of +-- conditions and the following disclaimer in the documentation and/or other +-- materials provided with the distribution. +-- +-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from this +-- software without specific prior written permission. +-- +-- 4. This software, with or without modification, must only be used with a +-- Nordic Semiconductor ASA integrated circuit. +-- +-- 5. Any software provided in binary form under this license must not be reverse +-- engineered, decompiled, modified and/or disassembled. +-- +-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +-- OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + +-- This spec has been automatically generated from nrf52.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package NRF_SVD.UICR is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Description collection[0]: Reserved for Nordic firmware design + + -- Description collection[0]: Reserved for Nordic firmware design + type NRFFW_Registers is array (0 .. 14) of HAL.UInt32; + + -- Description collection[0]: Reserved for Nordic hardware design + + -- Description collection[0]: Reserved for Nordic hardware design + type NRFHW_Registers is array (0 .. 11) of HAL.UInt32; + + -- Description collection[0]: Reserved for customer + + -- Description collection[0]: Reserved for customer + type CUSTOMER_Registers is array (0 .. 31) of HAL.UInt32; + + subtype PSELRESET_PIN_Field is HAL.UInt6; + + -- Connection + type PSELRESET_CONNECT_Field is + (-- Connect + Connected, + -- Disconnect + Disconnected) + with Size => 1; + for PSELRESET_CONNECT_Field use + (Connected => 0, + Disconnected => 1); + + -- Description collection[0]: Mapping of the nRESET function (see POWER + -- chapter for details) + type PSELRESET_Register is record + -- GPIO number P0.n onto which Reset is exposed + PIN : PSELRESET_PIN_Field := 16#3F#; + -- unspecified + Reserved_6_30 : HAL.UInt25 := 16#1FFFFFF#; + -- Connection + CONNECT : PSELRESET_CONNECT_Field := NRF_SVD.UICR.Disconnected; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PSELRESET_Register use record + PIN at 0 range 0 .. 5; + Reserved_6_30 at 0 range 6 .. 30; + CONNECT at 0 range 31 .. 31; + end record; + + -- Description collection[0]: Mapping of the nRESET function (see POWER + -- chapter for details) + type PSELRESET_Registers is array (0 .. 1) of PSELRESET_Register; + + -- Enable or disable Access Port protection. Any other value than 0xFF + -- being written to this field will enable protection. + type APPROTECT_PALL_Field is + (-- Enable + Enabled, + -- Disable + Disabled) + with Size => 8; + for APPROTECT_PALL_Field use + (Enabled => 0, + Disabled => 255); + + -- Access Port protection + type APPROTECT_Register is record + -- Enable or disable Access Port protection. Any other value than 0xFF + -- being written to this field will enable protection. + PALL : APPROTECT_PALL_Field := NRF_SVD.UICR.Disabled; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#FFFFFF#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for APPROTECT_Register use record + PALL at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- Setting of pins dedicated to NFC functionality + type NFCPINS_PROTECT_Field is + (-- Operation as GPIO pins. Same protection as normal GPIO pins + Disabled, + -- Operation as NFC antenna pins. Configures the protection for NFC operation + Nfc) + with Size => 1; + for NFCPINS_PROTECT_Field use + (Disabled => 0, + Nfc => 1); + + -- Setting of pins dedicated to NFC functionality: NFC antenna or GPIO + type NFCPINS_Register is record + -- Setting of pins dedicated to NFC functionality + PROTECT : NFCPINS_PROTECT_Field := NRF_SVD.UICR.Nfc; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#7FFFFFFF#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for NFCPINS_Register use record + PROTECT at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- User Information Configuration Registers + type UICR_Peripheral is record + -- Unspecified + UNUSED0 : aliased HAL.UInt32; + -- Unspecified + UNUSED1 : aliased HAL.UInt32; + -- Unspecified + UNUSED2 : aliased HAL.UInt32; + -- Unspecified + UNUSED3 : aliased HAL.UInt32; + -- Description collection[0]: Reserved for Nordic firmware design + NRFFW : aliased NRFFW_Registers; + -- Description collection[0]: Reserved for Nordic hardware design + NRFHW : aliased NRFHW_Registers; + -- Description collection[0]: Reserved for customer + CUSTOMER : aliased CUSTOMER_Registers; + -- Description collection[0]: Mapping of the nRESET function (see POWER + -- chapter for details) + PSELRESET : aliased PSELRESET_Registers; + -- Access Port protection + APPROTECT : aliased APPROTECT_Register; + -- Setting of pins dedicated to NFC functionality: NFC antenna or GPIO + NFCPINS : aliased NFCPINS_Register; + end record + with Volatile; + + for UICR_Peripheral use record + UNUSED0 at 16#0# range 0 .. 31; + UNUSED1 at 16#4# range 0 .. 31; + UNUSED2 at 16#8# range 0 .. 31; + UNUSED3 at 16#10# range 0 .. 31; + NRFFW at 16#14# range 0 .. 479; + NRFHW at 16#50# range 0 .. 383; + CUSTOMER at 16#80# range 0 .. 1023; + PSELRESET at 16#200# range 0 .. 63; + APPROTECT at 16#208# range 0 .. 31; + NFCPINS at 16#20C# range 0 .. 31; + end record; + + -- User Information Configuration Registers + UICR_Periph : aliased UICR_Peripheral + with Import, Address => UICR_Base; + +end NRF_SVD.UICR; diff --git a/arch/ARM/Nordic/svd/nrf52/nrf_svd-wdt.ads b/arch/ARM/Nordic/svd/nrf52/nrf_svd-wdt.ads new file mode 100644 index 000000000..fc1139cfc --- /dev/null +++ b/arch/ARM/Nordic/svd/nrf52/nrf_svd-wdt.ads @@ -0,0 +1,503 @@ +-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- 2. Redistributions in binary form, except as embedded into a Nordic +-- Semiconductor ASA integrated circuit in a product or a software update for +-- such product, must reproduce the above copyright notice, this list of +-- conditions and the following disclaimer in the documentation and/or other +-- materials provided with the distribution. +-- +-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from this +-- software without specific prior written permission. +-- +-- 4. This software, with or without modification, must only be used with a +-- Nordic Semiconductor ASA integrated circuit. +-- +-- 5. Any software provided in binary form under this license must not be reverse +-- engineered, decompiled, modified and/or disassembled. +-- +-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +-- OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + +-- This spec has been automatically generated from nrf52.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package NRF_SVD.WDT is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Write '1' to Enable interrupt for TIMEOUT event + type INTENSET_TIMEOUT_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENSET_TIMEOUT_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Enable interrupt for TIMEOUT event + type INTENSET_TIMEOUT_Field_1 is + (-- Reset value for the field + Intenset_Timeout_Field_Reset, + -- Enable + Set) + with Size => 1; + for INTENSET_TIMEOUT_Field_1 use + (Intenset_Timeout_Field_Reset => 0, + Set => 1); + + -- Enable interrupt + type INTENSET_Register is record + -- Write '1' to Enable interrupt for TIMEOUT event + TIMEOUT : INTENSET_TIMEOUT_Field_1 := + Intenset_Timeout_Field_Reset; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENSET_Register use record + TIMEOUT at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Write '1' to Disable interrupt for TIMEOUT event + type INTENCLR_TIMEOUT_Field is + (-- Read: Disabled + Disabled, + -- Read: Enabled + Enabled) + with Size => 1; + for INTENCLR_TIMEOUT_Field use + (Disabled => 0, + Enabled => 1); + + -- Write '1' to Disable interrupt for TIMEOUT event + type INTENCLR_TIMEOUT_Field_1 is + (-- Reset value for the field + Intenclr_Timeout_Field_Reset, + -- Disable + Clear) + with Size => 1; + for INTENCLR_TIMEOUT_Field_1 use + (Intenclr_Timeout_Field_Reset => 0, + Clear => 1); + + -- Disable interrupt + type INTENCLR_Register is record + -- Write '1' to Disable interrupt for TIMEOUT event + TIMEOUT : INTENCLR_TIMEOUT_Field_1 := + Intenclr_Timeout_Field_Reset; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTENCLR_Register use record + TIMEOUT at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Indicates whether or not the watchdog is running + type RUNSTATUS_RUNSTATUS_Field is + (-- Watchdog not running + Notrunning, + -- Watchdog is running + Running) + with Size => 1; + for RUNSTATUS_RUNSTATUS_Field use + (Notrunning => 0, + Running => 1); + + -- Run status + type RUNSTATUS_Register is record + -- Read-only. Indicates whether or not the watchdog is running + RUNSTATUS : RUNSTATUS_RUNSTATUS_Field; + -- unspecified + Reserved_1_31 : HAL.UInt31; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RUNSTATUS_Register use record + RUNSTATUS at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Request status for RR[0] register + type REQSTATUS_RR0_Field is + (-- RR[0] register is not enabled, or are already requesting reload + Disabledorrequested, + -- RR[0] register is enabled, and are not yet requesting reload + Enabledandunrequested) + with Size => 1; + for REQSTATUS_RR0_Field use + (Disabledorrequested => 0, + Enabledandunrequested => 1); + + -- Request status for RR[1] register + type REQSTATUS_RR1_Field is + (-- RR[1] register is not enabled, or are already requesting reload + Disabledorrequested, + -- RR[1] register is enabled, and are not yet requesting reload + Enabledandunrequested) + with Size => 1; + for REQSTATUS_RR1_Field use + (Disabledorrequested => 0, + Enabledandunrequested => 1); + + -- Request status for RR[2] register + type REQSTATUS_RR2_Field is + (-- RR[2] register is not enabled, or are already requesting reload + Disabledorrequested, + -- RR[2] register is enabled, and are not yet requesting reload + Enabledandunrequested) + with Size => 1; + for REQSTATUS_RR2_Field use + (Disabledorrequested => 0, + Enabledandunrequested => 1); + + -- Request status for RR[3] register + type REQSTATUS_RR3_Field is + (-- RR[3] register is not enabled, or are already requesting reload + Disabledorrequested, + -- RR[3] register is enabled, and are not yet requesting reload + Enabledandunrequested) + with Size => 1; + for REQSTATUS_RR3_Field use + (Disabledorrequested => 0, + Enabledandunrequested => 1); + + -- Request status for RR[4] register + type REQSTATUS_RR4_Field is + (-- RR[4] register is not enabled, or are already requesting reload + Disabledorrequested, + -- RR[4] register is enabled, and are not yet requesting reload + Enabledandunrequested) + with Size => 1; + for REQSTATUS_RR4_Field use + (Disabledorrequested => 0, + Enabledandunrequested => 1); + + -- Request status for RR[5] register + type REQSTATUS_RR5_Field is + (-- RR[5] register is not enabled, or are already requesting reload + Disabledorrequested, + -- RR[5] register is enabled, and are not yet requesting reload + Enabledandunrequested) + with Size => 1; + for REQSTATUS_RR5_Field use + (Disabledorrequested => 0, + Enabledandunrequested => 1); + + -- Request status for RR[6] register + type REQSTATUS_RR6_Field is + (-- RR[6] register is not enabled, or are already requesting reload + Disabledorrequested, + -- RR[6] register is enabled, and are not yet requesting reload + Enabledandunrequested) + with Size => 1; + for REQSTATUS_RR6_Field use + (Disabledorrequested => 0, + Enabledandunrequested => 1); + + -- Request status for RR[7] register + type REQSTATUS_RR7_Field is + (-- RR[7] register is not enabled, or are already requesting reload + Disabledorrequested, + -- RR[7] register is enabled, and are not yet requesting reload + Enabledandunrequested) + with Size => 1; + for REQSTATUS_RR7_Field use + (Disabledorrequested => 0, + Enabledandunrequested => 1); + + -- Request status + type REQSTATUS_Register is record + -- Read-only. Request status for RR[0] register + RR0 : REQSTATUS_RR0_Field; + -- Read-only. Request status for RR[1] register + RR1 : REQSTATUS_RR1_Field; + -- Read-only. Request status for RR[2] register + RR2 : REQSTATUS_RR2_Field; + -- Read-only. Request status for RR[3] register + RR3 : REQSTATUS_RR3_Field; + -- Read-only. Request status for RR[4] register + RR4 : REQSTATUS_RR4_Field; + -- Read-only. Request status for RR[5] register + RR5 : REQSTATUS_RR5_Field; + -- Read-only. Request status for RR[6] register + RR6 : REQSTATUS_RR6_Field; + -- Read-only. Request status for RR[7] register + RR7 : REQSTATUS_RR7_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for REQSTATUS_Register use record + RR0 at 0 range 0 .. 0; + RR1 at 0 range 1 .. 1; + RR2 at 0 range 2 .. 2; + RR3 at 0 range 3 .. 3; + RR4 at 0 range 4 .. 4; + RR5 at 0 range 5 .. 5; + RR6 at 0 range 6 .. 6; + RR7 at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- Enable or disable RR[0] register + type RREN_RR0_Field is + (-- Disable RR[0] register + Disabled, + -- Enable RR[0] register + Enabled) + with Size => 1; + for RREN_RR0_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable RR[1] register + type RREN_RR1_Field is + (-- Disable RR[1] register + Disabled, + -- Enable RR[1] register + Enabled) + with Size => 1; + for RREN_RR1_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable RR[2] register + type RREN_RR2_Field is + (-- Disable RR[2] register + Disabled, + -- Enable RR[2] register + Enabled) + with Size => 1; + for RREN_RR2_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable RR[3] register + type RREN_RR3_Field is + (-- Disable RR[3] register + Disabled, + -- Enable RR[3] register + Enabled) + with Size => 1; + for RREN_RR3_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable RR[4] register + type RREN_RR4_Field is + (-- Disable RR[4] register + Disabled, + -- Enable RR[4] register + Enabled) + with Size => 1; + for RREN_RR4_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable RR[5] register + type RREN_RR5_Field is + (-- Disable RR[5] register + Disabled, + -- Enable RR[5] register + Enabled) + with Size => 1; + for RREN_RR5_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable RR[6] register + type RREN_RR6_Field is + (-- Disable RR[6] register + Disabled, + -- Enable RR[6] register + Enabled) + with Size => 1; + for RREN_RR6_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable or disable RR[7] register + type RREN_RR7_Field is + (-- Disable RR[7] register + Disabled, + -- Enable RR[7] register + Enabled) + with Size => 1; + for RREN_RR7_Field use + (Disabled => 0, + Enabled => 1); + + -- Enable register for reload request registers + type RREN_Register is record + -- Enable or disable RR[0] register + RR0 : RREN_RR0_Field := NRF_SVD.WDT.Enabled; + -- Enable or disable RR[1] register + RR1 : RREN_RR1_Field := NRF_SVD.WDT.Disabled; + -- Enable or disable RR[2] register + RR2 : RREN_RR2_Field := NRF_SVD.WDT.Disabled; + -- Enable or disable RR[3] register + RR3 : RREN_RR3_Field := NRF_SVD.WDT.Disabled; + -- Enable or disable RR[4] register + RR4 : RREN_RR4_Field := NRF_SVD.WDT.Disabled; + -- Enable or disable RR[5] register + RR5 : RREN_RR5_Field := NRF_SVD.WDT.Disabled; + -- Enable or disable RR[6] register + RR6 : RREN_RR6_Field := NRF_SVD.WDT.Disabled; + -- Enable or disable RR[7] register + RR7 : RREN_RR7_Field := NRF_SVD.WDT.Disabled; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RREN_Register use record + RR0 at 0 range 0 .. 0; + RR1 at 0 range 1 .. 1; + RR2 at 0 range 2 .. 2; + RR3 at 0 range 3 .. 3; + RR4 at 0 range 4 .. 4; + RR5 at 0 range 5 .. 5; + RR6 at 0 range 6 .. 6; + RR7 at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- Configure the watchdog to either be paused, or kept running, while the + -- CPU is sleeping + type CONFIG_SLEEP_Field is + (-- Pause watchdog while the CPU is sleeping + Pause, + -- Keep the watchdog running while the CPU is sleeping + Run) + with Size => 1; + for CONFIG_SLEEP_Field use + (Pause => 0, + Run => 1); + + -- Configure the watchdog to either be paused, or kept running, while the + -- CPU is halted by the debugger + type CONFIG_HALT_Field is + (-- Pause watchdog while the CPU is halted by the debugger + Pause, + -- Keep the watchdog running while the CPU is halted by the debugger + Run) + with Size => 1; + for CONFIG_HALT_Field use + (Pause => 0, + Run => 1); + + -- Configuration register + type CONFIG_Register is record + -- Configure the watchdog to either be paused, or kept running, while + -- the CPU is sleeping + SLEEP : CONFIG_SLEEP_Field := NRF_SVD.WDT.Run; + -- unspecified + Reserved_1_2 : HAL.UInt2 := 16#0#; + -- Configure the watchdog to either be paused, or kept running, while + -- the CPU is halted by the debugger + HALT : CONFIG_HALT_Field := NRF_SVD.WDT.Pause; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CONFIG_Register use record + SLEEP at 0 range 0 .. 0; + Reserved_1_2 at 0 range 1 .. 2; + HALT at 0 range 3 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- Description collection[0]: Reload request 0 + + -- Description collection[0]: Reload request 0 + type RR_Registers is array (0 .. 7) of HAL.UInt32; + + ----------------- + -- Peripherals -- + ----------------- + + -- Watchdog Timer + type WDT_Peripheral is record + -- Start the watchdog + TASKS_START : aliased HAL.UInt32; + -- Watchdog timeout + EVENTS_TIMEOUT : aliased HAL.UInt32; + -- Enable interrupt + INTENSET : aliased INTENSET_Register; + -- Disable interrupt + INTENCLR : aliased INTENCLR_Register; + -- Run status + RUNSTATUS : aliased RUNSTATUS_Register; + -- Request status + REQSTATUS : aliased REQSTATUS_Register; + -- Counter reload value + CRV : aliased HAL.UInt32; + -- Enable register for reload request registers + RREN : aliased RREN_Register; + -- Configuration register + CONFIG : aliased CONFIG_Register; + -- Description collection[0]: Reload request 0 + RR : aliased RR_Registers; + end record + with Volatile; + + for WDT_Peripheral use record + TASKS_START at 16#0# range 0 .. 31; + EVENTS_TIMEOUT at 16#100# range 0 .. 31; + INTENSET at 16#304# range 0 .. 31; + INTENCLR at 16#308# range 0 .. 31; + RUNSTATUS at 16#400# range 0 .. 31; + REQSTATUS at 16#404# range 0 .. 31; + CRV at 16#504# range 0 .. 31; + RREN at 16#508# range 0 .. 31; + CONFIG at 16#50C# range 0 .. 31; + RR at 16#600# range 0 .. 255; + end record; + + -- Watchdog Timer + WDT_Periph : aliased WDT_Peripheral + with Import, Address => WDT_Base; + +end NRF_SVD.WDT; diff --git a/arch/ARM/Nordic/svd/nrf52/nrf_svd.ads b/arch/ARM/Nordic/svd/nrf52/nrf_svd.ads new file mode 100644 index 000000000..c9abe0894 --- /dev/null +++ b/arch/ARM/Nordic/svd/nrf52/nrf_svd.ads @@ -0,0 +1,122 @@ +-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- +-- 2. Redistributions in binary form, except as embedded into a Nordic +-- Semiconductor ASA integrated circuit in a product or a software update for +-- such product, must reproduce the above copyright notice, this list of +-- conditions and the following disclaimer in the documentation and/or other +-- materials provided with the distribution. +-- +-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its +-- contributors may be used to endorse or promote products derived from this +-- software without specific prior written permission. +-- +-- 4. This software, with or without modification, must only be used with a +-- Nordic Semiconductor ASA integrated circuit. +-- +-- 5. Any software provided in binary form under this license must not be reverse +-- engineered, decompiled, modified and/or disassembled. +-- +-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +-- OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +-- DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- + +-- This spec has been automatically generated from nrf52.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with System; + +-- nRF52832 reference description for radio MCU with ARM 32-bit Cortex-M4 +-- Microcontroller +package NRF_SVD is + pragma Preelaborate; + + -------------------- + -- Base addresses -- + -------------------- + + FICR_Base : constant System.Address := System'To_Address (16#10000000#); + UICR_Base : constant System.Address := System'To_Address (16#10001000#); + BPROT_Base : constant System.Address := System'To_Address (16#40000000#); + POWER_Base : constant System.Address := System'To_Address (16#40000000#); + CLOCK_Base : constant System.Address := System'To_Address (16#40000000#); + RADIO_Base : constant System.Address := System'To_Address (16#40001000#); + UARTE0_Base : constant System.Address := System'To_Address (16#40002000#); + UART0_Base : constant System.Address := System'To_Address (16#40002000#); + SPIM0_Base : constant System.Address := System'To_Address (16#40003000#); + SPIS0_Base : constant System.Address := System'To_Address (16#40003000#); + TWIM0_Base : constant System.Address := System'To_Address (16#40003000#); + TWIS0_Base : constant System.Address := System'To_Address (16#40003000#); + SPI0_Base : constant System.Address := System'To_Address (16#40003000#); + TWI0_Base : constant System.Address := System'To_Address (16#40003000#); + SPIM1_Base : constant System.Address := System'To_Address (16#40004000#); + SPIS1_Base : constant System.Address := System'To_Address (16#40004000#); + TWIM1_Base : constant System.Address := System'To_Address (16#40004000#); + TWIS1_Base : constant System.Address := System'To_Address (16#40004000#); + SPI1_Base : constant System.Address := System'To_Address (16#40004000#); + TWI1_Base : constant System.Address := System'To_Address (16#40004000#); + NFCT_Base : constant System.Address := System'To_Address (16#40005000#); + GPIOTE_Base : constant System.Address := System'To_Address (16#40006000#); + SAADC_Base : constant System.Address := System'To_Address (16#40007000#); + TIMER0_Base : constant System.Address := System'To_Address (16#40008000#); + TIMER1_Base : constant System.Address := System'To_Address (16#40009000#); + TIMER2_Base : constant System.Address := System'To_Address (16#4000A000#); + RTC0_Base : constant System.Address := System'To_Address (16#4000B000#); + TEMP_Base : constant System.Address := System'To_Address (16#4000C000#); + RNG_Base : constant System.Address := System'To_Address (16#4000D000#); + ECB_Base : constant System.Address := System'To_Address (16#4000E000#); + CCM_Base : constant System.Address := System'To_Address (16#4000F000#); + AAR_Base : constant System.Address := System'To_Address (16#4000F000#); + WDT_Base : constant System.Address := System'To_Address (16#40010000#); + RTC1_Base : constant System.Address := System'To_Address (16#40011000#); + QDEC_Base : constant System.Address := System'To_Address (16#40012000#); + COMP_Base : constant System.Address := System'To_Address (16#40013000#); + LPCOMP_Base : constant System.Address := System'To_Address (16#40013000#); + SWI0_Base : constant System.Address := System'To_Address (16#40014000#); + EGU0_Base : constant System.Address := System'To_Address (16#40014000#); + SWI1_Base : constant System.Address := System'To_Address (16#40015000#); + EGU1_Base : constant System.Address := System'To_Address (16#40015000#); + SWI2_Base : constant System.Address := System'To_Address (16#40016000#); + EGU2_Base : constant System.Address := System'To_Address (16#40016000#); + SWI3_Base : constant System.Address := System'To_Address (16#40017000#); + EGU3_Base : constant System.Address := System'To_Address (16#40017000#); + SWI4_Base : constant System.Address := System'To_Address (16#40018000#); + EGU4_Base : constant System.Address := System'To_Address (16#40018000#); + SWI5_Base : constant System.Address := System'To_Address (16#40019000#); + EGU5_Base : constant System.Address := System'To_Address (16#40019000#); + TIMER3_Base : constant System.Address := System'To_Address (16#4001A000#); + TIMER4_Base : constant System.Address := System'To_Address (16#4001B000#); + PWM0_Base : constant System.Address := System'To_Address (16#4001C000#); + PDM_Base : constant System.Address := System'To_Address (16#4001D000#); + NVMC_Base : constant System.Address := System'To_Address (16#4001E000#); + PPI_Base : constant System.Address := System'To_Address (16#4001F000#); + MWU_Base : constant System.Address := System'To_Address (16#40020000#); + PWM1_Base : constant System.Address := System'To_Address (16#40021000#); + PWM2_Base : constant System.Address := System'To_Address (16#40022000#); + SPIM2_Base : constant System.Address := System'To_Address (16#40023000#); + SPIS2_Base : constant System.Address := System'To_Address (16#40023000#); + SPI2_Base : constant System.Address := System'To_Address (16#40023000#); + RTC2_Base : constant System.Address := System'To_Address (16#40024000#); + I2S_Base : constant System.Address := System'To_Address (16#40025000#); + FPU_Base : constant System.Address := System'To_Address (16#40026000#); + P0_Base : constant System.Address := System'To_Address (16#50000000#); + +end NRF_SVD; diff --git a/arch/ARM/cortex_m/src/nvic_cm0/cortex_m-nvic.adb b/arch/ARM/cortex_m/src/nvic_cm0/cortex_m-nvic.adb index 2c7f8863d..75bcc9d1e 100644 --- a/arch/ARM/cortex_m/src/nvic_cm0/cortex_m-nvic.adb +++ b/arch/ARM/cortex_m/src/nvic_cm0/cortex_m-nvic.adb @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2015, AdaCore -- +-- Copyright (C) 2015-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -61,14 +61,14 @@ package body Cortex_M.NVIC is end case; end record with Unchecked_Union, Pack, Size => 32; - IPR_Index : constant Natural := IRQn / 4; - IP_Index : constant Natural := IRQn mod 4; + IPR_Index : constant Natural := Natural (IRQn) / 4; + IP_Index : constant Natural := Natural (IRQn) mod 4; IPR : As_Array; begin IPR.IPR := NVIC_Periph.NVIC_IPR (IPR_Index); - IPR.Arr (IP_Index) := Priority; + IPR.Arr (IP_Index) := UInt8 (Priority); NVIC_Periph.NVIC_IPR (IPR_Index) := IPR.IPR; end Set_Priority; @@ -79,7 +79,7 @@ package body Cortex_M.NVIC is procedure Enable_Interrupt (IRQn : Interrupt_ID) is begin - NVIC_Periph.NVIC_ISER := Shift_Left (1, IRQn); + NVIC_Periph.NVIC_ISER := Shift_Left (1, Natural (IRQn)); end Enable_Interrupt; ------------- @@ -88,7 +88,7 @@ package body Cortex_M.NVIC is procedure Disable_Interrupt (IRQn : Interrupt_ID) is begin - NVIC_Periph.NVIC_ICER := Shift_Left (1, IRQn); + NVIC_Periph.NVIC_ICER := Shift_Left (1, Natural (IRQn)); end Disable_Interrupt; ------------- @@ -97,7 +97,7 @@ package body Cortex_M.NVIC is function Enabled (IRQn : Interrupt_ID) return Boolean is begin - return ((NVIC_Periph.NVIC_ISER and Shift_Left (1, IRQn)) /= 0); + return ((NVIC_Periph.NVIC_ISER and Shift_Left (1, Natural (IRQn))) /= 0); end Enabled; ------------- @@ -106,7 +106,7 @@ package body Cortex_M.NVIC is function Pending (IRQn : Interrupt_ID) return Boolean is begin - return ((NVIC_Periph.NVIC_ISPR and Shift_Left (1, IRQn)) /= 0); + return ((NVIC_Periph.NVIC_ISPR and Shift_Left (1, Natural (IRQn))) /= 0); end Pending; ----------------- @@ -115,7 +115,7 @@ package body Cortex_M.NVIC is procedure Set_Pending (IRQn : Interrupt_ID) is begin - NVIC_Periph.NVIC_ISPR := Shift_Left (1, IRQn); + NVIC_Periph.NVIC_ISPR := Shift_Left (1, Natural (IRQn)); end Set_Pending; ------------------- @@ -124,7 +124,7 @@ package body Cortex_M.NVIC is procedure Clear_Pending (IRQn : Interrupt_ID) is begin - NVIC_Periph.NVIC_ICPR := Shift_Left (1, IRQn); + NVIC_Periph.NVIC_ICPR := Shift_Left (1, Natural (IRQn)); end Clear_Pending; end Cortex_M.NVIC; diff --git a/arch/ARM/cortex_m/src/nvic_cm0/cortex_m-nvic.ads b/arch/ARM/cortex_m/src/nvic_cm0/cortex_m-nvic.ads index 79a649b80..0743eebbc 100644 --- a/arch/ARM/cortex_m/src/nvic_cm0/cortex_m-nvic.ads +++ b/arch/ARM/cortex_m/src/nvic_cm0/cortex_m-nvic.ads @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2015, AdaCore -- +-- Copyright (C) 2015-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -46,8 +46,8 @@ with HAL; use HAL; package Cortex_M.NVIC is -- the Nested Vectored Interrupt Controller - subtype Interrupt_ID is Natural range 0 .. 31; - subtype Interrupt_Priority is UInt8; + type Interrupt_ID is new Natural range 0 .. 31; + type Interrupt_Priority is new UInt8; procedure Set_Priority (IRQn : Interrupt_ID; diff --git a/arch/ARM/cortex_m/src/nvic_cm4_cm7/cortex_m-nvic.adb b/arch/ARM/cortex_m/src/nvic_cm4_cm7/cortex_m-nvic.adb index 5ac8a5366..855729b98 100644 --- a/arch/ARM/cortex_m/src/nvic_cm4_cm7/cortex_m-nvic.adb +++ b/arch/ARM/cortex_m/src/nvic_cm4_cm7/cortex_m-nvic.adb @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2015, AdaCore -- +-- Copyright (C) 2015-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -47,19 +47,20 @@ package body Cortex_M.NVIC is -- Priority_Grouping -- ----------------------- - function Priority_Grouping return UInt32 is + function Priority_Grouping return Interrupt_Priority is begin - return Shift_Right (SCB.AIRCR and SCB_AIRCR_PRIGROUP_Mask, - SCB_AIRCR_PRIGROUP_Pos); + return Interrupt_Priority + (Shift_Right (SCB.AIRCR and SCB_AIRCR_PRIGROUP_Mask, + SCB_AIRCR_PRIGROUP_Pos)); end Priority_Grouping; --------------------------- -- Set_Priority_Grouping -- --------------------------- - procedure Set_Priority_Grouping (Priority_Group : UInt32) is + procedure Set_Priority_Grouping (Priority_Group : Interrupt_Priority) is Reg_Value : UInt32; - PriorityGroupTmp : constant UInt32 := Priority_Group and 16#07#; + PriorityGroupTmp : constant UInt32 := UInt32 (Priority_Group) and 16#07#; Key : constant := 16#5FA#; begin Reg_Value := SCB.AIRCR; @@ -77,11 +78,11 @@ package body Cortex_M.NVIC is procedure Set_Priority (IRQn : Interrupt_ID; - Priority : UInt32) + Priority : Interrupt_Priority) is Index : constant Natural := Integer (IRQn); Value : constant UInt32 := - Shift_Left (Priority, 8 - NVIC_PRIO_BITS) and 16#FF#; + Shift_Left (UInt32 (Priority), 8 - NVIC_PRIO_BITS) and 16#FF#; begin -- IRQ numbers are never less than 0 in the current definition, hence -- the code is different from that in the CMSIS. @@ -93,17 +94,19 @@ package body Cortex_M.NVIC is ---------------------- function Encoded_Priority - (Priority_Group : UInt32; Preempt_Priority : UInt32; Subpriority : UInt32) - return UInt32 + (Priority_Group : Interrupt_Priority; + Preempt_Priority : Interrupt_Priority; + Subpriority : Interrupt_Priority) + return Interrupt_Priority is - PriorityGroupTmp : constant UInt32 := Priority_Group and 16#07#; - PreemptPriorityBits : UInt32; - SubPriorityBits : UInt32; - Temp1 : UInt32; - Temp2 : UInt32; - Temp3 : UInt32; - Temp4 : UInt32; - Temp5 : UInt32; + PriorityGroupTmp : constant Interrupt_Priority := Priority_Group and 16#07#; + PreemptPriorityBits : Interrupt_Priority; + SubPriorityBits : Interrupt_Priority; + Temp1 : Interrupt_Priority; + Temp2 : Interrupt_Priority; + Temp3 : Interrupt_Priority; + Temp4 : Interrupt_Priority; + Temp5 : Interrupt_Priority; begin if (7 - PriorityGroupTmp) > NVIC_PRIO_BITS then PreemptPriorityBits := NVIC_PRIO_BITS; @@ -133,10 +136,10 @@ package body Cortex_M.NVIC is procedure Set_Priority (IRQn : Interrupt_ID; - Preempt_Priority : UInt32; - Subpriority : UInt32) + Preempt_Priority : Interrupt_Priority; + Subpriority : Interrupt_Priority) is - Priority_Group : constant UInt32 := Priority_Grouping; + Priority_Group : constant Interrupt_Priority := Priority_Grouping; begin Set_Priority (IRQn, diff --git a/arch/ARM/cortex_m/src/nvic_cm4_cm7/cortex_m-nvic.ads b/arch/ARM/cortex_m/src/nvic_cm4_cm7/cortex_m-nvic.ads index 6c53ebee3..1b37b2eff 100644 --- a/arch/ARM/cortex_m/src/nvic_cm4_cm7/cortex_m-nvic.ads +++ b/arch/ARM/cortex_m/src/nvic_cm4_cm7/cortex_m-nvic.ads @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2015, AdaCore -- +-- Copyright (C) 2015-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -44,10 +44,12 @@ with System; with HAL; use HAL; -with Ada.Interrupts; use Ada.Interrupts; package Cortex_M.NVIC is -- the Nested Vectored Interrupt Controller + type Interrupt_ID is new Natural range 0 .. 240; + type Interrupt_Priority is new UInt32; + -- 0 bits for pre-emption priority; 4 bits for subpriority Priority_Group_0 : constant UInt32 := 16#00000007#; @@ -64,22 +66,27 @@ package Cortex_M.NVIC is -- the Nested Vectored Interrupt Controller Priority_Group_4 : constant UInt32 := 16#00000003#; - procedure Set_Priority_Grouping (Priority_Group : UInt32) with Inline; + procedure Set_Priority_Grouping (Priority_Group : Interrupt_Priority) + with Inline; - function Priority_Grouping return UInt32 with Inline; + function Priority_Grouping return Interrupt_Priority + with Inline; procedure Set_Priority (IRQn : Interrupt_ID; - Priority : UInt32) with Inline; + Priority : Interrupt_Priority) with Inline; function Encoded_Priority - (Priority_Group : UInt32; Preempt_Priority : UInt32; Subpriority : UInt32) - return UInt32 with Inline; + (Priority_Group : Interrupt_Priority; + Preempt_Priority : Interrupt_Priority; + Subpriority : Interrupt_Priority) + return Interrupt_Priority + with Inline; procedure Set_Priority (IRQn : Interrupt_ID; - Preempt_Priority : UInt32; - Subpriority : UInt32) with Inline; + Preempt_Priority : Interrupt_Priority; + Subpriority : Interrupt_Priority) with Inline; -- A convenience routine that first encodes (Priority_Grouping(), -- Preempt_Priority, and Subpriority), and then calls the other -- Set_Priority with the resulting encoding for the Priority argument. @@ -248,5 +255,3 @@ private -- STM32F4XX uses 4 bits for the priority levels end Cortex_M.NVIC; - - diff --git a/arch/svd.mk b/arch/svd.mk index 80d2100ca..22dc18d31 100644 --- a/arch/svd.mk +++ b/arch/svd.mk @@ -21,7 +21,8 @@ svd: $(SVD2ADA_DIR)/svd2ada $(SVD2ADA_DIR)/CMSIS-SVD/Cortex_M/cm4f.svd --boolean -o $(CORTEX_DIR)/cm4f -p Cortex_M_SVD --base-types-package HAL --gen-uint-always rm -rf $(NORDIC_DIR)/nrf* - $(SVD2ADA_DIR)/svd2ada $(SVD2ADA_DIR)/CMSIS-SVD/Nordic/nrf51.svd --boolean -o $(NORDIC_DIR)/nrf51 -p NRF51_SVD --base-types-package HAL --gen-uint-always + $(SVD2ADA_DIR)/svd2ada $(SVD2ADA_DIR)/CMSIS-SVD/Nordic/nrf51.svd --boolean -o $(NORDIC_DIR)/nrf51 -p NRF_SVD --base-types-package HAL --gen-uint-always + $(SVD2ADA_DIR)/svd2ada $(SVD2ADA_DIR)/CMSIS-SVD/Nordic/nrf52.svd --boolean -o $(NORDIC_DIR)/nrf52 -p NRF_SVD --base-types-package HAL --gen-uint-always rm -rf $(SIFIVE_DIR)/FE* $(SVD2ADA_DIR)/svd2ada $(SVD2ADA_DIR)/CMSIS-SVD/SiFive/FE310.svd --boolean -o $(SIFIVE_DIR)/FE310 -p FE310_SVD --base-types-package HAL --gen-uint-always diff --git a/boards/MicroBit/microbit_zfp.gpr b/boards/MicroBit/microbit_zfp.gpr index fac0069ba..dc35c74b5 100644 --- a/boards/MicroBit/microbit_zfp.gpr +++ b/boards/MicroBit/microbit_zfp.gpr @@ -142,8 +142,9 @@ library project MicroBit_ZFP is Src_Dirs_Root & "/arch/ARM/cortex_m/src/cm0", -- From arch definition Src_Dirs_Root & "/arch/ARM/cortex_m/src/nocache", -- From arch definition Src_Dirs_Root & "/arch/ARM/cortex_m/src/nvic_cm0", -- From arch definition - Src_Dirs_Root & "/arch/ARM/Nordic/devices/", -- From MCU definition - Src_Dirs_Root & "/arch/ARM/Nordic/drivers/", -- From MCU definition + Src_Dirs_Root & "/arch/ARM/Nordic/devices/nrf51", -- From MCU definition + Src_Dirs_Root & "/arch/ARM/Nordic/drivers/nrf_common", -- From MCU definition + Src_Dirs_Root & "/arch/ARM/Nordic/drivers/nrf51", -- From MCU definition Src_Dirs_Root & "/arch/ARM/Nordic/svd/nrf51/", -- From MCU definition Src_Dirs_Root & "/middleware/src/filesystem", -- From middleware config Src_Dirs_Root & "/middleware/src/BLE", -- From middleware config diff --git a/boards/MicroBit/src/microbit-buttons.adb b/boards/MicroBit/src/microbit-buttons.adb index aff26dea3..6860ca634 100755 --- a/boards/MicroBit/src/microbit-buttons.adb +++ b/boards/MicroBit/src/microbit-buttons.adb @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2017, AdaCore -- +-- Copyright (C) 2017-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -29,7 +29,7 @@ -- -- ------------------------------------------------------------------------------ -with nRF51.GPIO; use nRF51.GPIO; +with nRF.GPIO; use nRF.GPIO; with MicroBit.Time; use MicroBit.Time; package body MicroBit.Buttons is diff --git a/boards/MicroBit/src/microbit-console.adb b/boards/MicroBit/src/microbit-console.adb index 999dd4d99..35b78565d 100644 --- a/boards/MicroBit/src/microbit-console.adb +++ b/boards/MicroBit/src/microbit-console.adb @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2019, AdaCore -- +-- Copyright (C) 2019-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -31,12 +31,12 @@ with HAL; use HAL; with HAL.UART; use HAL.UART; -with nRF51.Device; -with nRF51.UART; use nRF51.UART; +with nRF.Device; +with nRF.UART; use nRF.UART; package body MicroBit.Console is - UART : nRF51.UART.UART_Device renames nRF51.Device.UART_0; + UART : nRF.UART.UART_Device renames nRF.Device.UART_0; --------- -- Get -- @@ -105,7 +105,7 @@ package body MicroBit.Console is end New_Line; begin - UART.Configure (nRF51.UART.Baud115200, Parity => False); + UART.Configure (nRF.UART.Baud115200, Parity => False); UART.Enable (MB_UART_TX.Pin, MB_UART_RX.Pin); end MicroBit.Console; diff --git a/boards/MicroBit/src/microbit-display.adb b/boards/MicroBit/src/microbit-display.adb index 4a183a3b6..362b02f06 100644 --- a/boards/MicroBit/src/microbit-display.adb +++ b/boards/MicroBit/src/microbit-display.adb @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2016-2017, AdaCore -- +-- Copyright (C) 2016-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -30,8 +30,8 @@ ------------------------------------------------------------------------------ with HAL; use HAL; -with nRF51.GPIO; use nRF51.GPIO; -with nRF51.Device; use nRF51.Device; +with nRF.GPIO; use nRF.GPIO; +with nRF.Device; use nRF.Device; with MicroBit.Time; use MicroBit.Time; with System.Machine_Code; use System.Machine_Code; diff --git a/boards/MicroBit/src/microbit-i2c.adb b/boards/MicroBit/src/microbit-i2c.adb index 254c3351a..78f3cb846 100644 --- a/boards/MicroBit/src/microbit-i2c.adb +++ b/boards/MicroBit/src/microbit-i2c.adb @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2018, AdaCore -- +-- Copyright (C) 2018-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -29,16 +29,16 @@ -- -- ------------------------------------------------------------------------------ -with nRF51.Device; -with nRF51.TWI; +with nRF.Device; +with nRF.TWI; package body MicroBit.I2C is Init_Done : Boolean := False; - Device : nRF51.TWI.TWI_Master renames nRF51.Device.TWI_0; + Device : nRF.TWI.TWI_Master renames nRF.Device.TWI_0; -- This device should not conflict with the device used in MicroBit.SPI. - -- See nRF51 Series Reference Manual, chapter Memory.Instantiation. + -- See nRF Series Reference Manual, chapter Memory.Instantiation. ----------------- -- Initialized -- @@ -57,9 +57,9 @@ package body MicroBit.I2C is (SCL => MB_SCL.Pin, SDA => MB_SDA.Pin, Speed => (case S is - when S100kbps => nRF51.TWI.TWI_100kbps, - when S250kbps => nRF51.TWI.TWI_250kbps, - when S400kbps => nRF51.TWI.TWI_400kbps) + when S100kbps => nRF.TWI.TWI_100kbps, + when S250kbps => nRF.TWI.TWI_250kbps, + when S400kbps => nRF.TWI.TWI_400kbps) ); Device.Enable; diff --git a/boards/MicroBit/src/microbit-ios-neopixel.adb b/boards/MicroBit/src/microbit-ios-neopixel.adb index 9c70e4f70..e840ec4d0 100644 --- a/boards/MicroBit/src/microbit-ios-neopixel.adb +++ b/boards/MicroBit/src/microbit-ios-neopixel.adb @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2019, AdaCore -- +-- Copyright (C) 2019-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -34,7 +34,7 @@ with System.Machine_Code; use System, System.Machine_Code; -with NRF51_SVD.GPIO; use NRF51_SVD.GPIO; +with NRF_SVD.GPIO; use NRF_SVD.GPIO; with MicroBit.Time; package body MicroBit.IOs.NeoPixel is diff --git a/boards/MicroBit/src/microbit-ios.adb b/boards/MicroBit/src/microbit-ios.adb index 4bdf3305e..a43915fbf 100644 --- a/boards/MicroBit/src/microbit-ios.adb +++ b/boards/MicroBit/src/microbit-ios.adb @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2017, AdaCore -- +-- Copyright (C) 2017-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -31,13 +31,13 @@ with HAL; use HAL; -with nRF51.ADC; use nRF51.ADC; -with nRF51.Device; use nRF51.Device; -with nRF51.PPI; use nRF51.PPI; -with nRF51.Timers; use nRF51.Timers; -with nRF51.GPIO.Tasks_And_Events; use nRF51.GPIO.Tasks_And_Events; -with nRF51.Events; use nRF51.Events; -with nRF51.Interrupts; use nRF51.Interrupts; +with nRF.ADC; use nRF.ADC; +with nRF.Device; use nRF.Device; +with nRF.PPI; use nRF.PPI; +with nRF.Timers; use nRF.Timers; +with nRF.GPIO.Tasks_And_Events; use nRF.GPIO.Tasks_And_Events; +with nRF.Events; use nRF.Events; +with nRF.Interrupts; use nRF.Interrupts; package body MicroBit.IOs is @@ -186,7 +186,7 @@ package body MicroBit.IOs is procedure Deallocate_PWM (Pin : Pin_Id) is begin if PWM_Alloc (Pin) /= No_PWM then - nRF51.GPIO.Tasks_And_Events.Disable (GPIOTE_Channel (PWM_Alloc (Pin))); + nRF.GPIO.Tasks_And_Events.Disable (GPIOTE_Channel (PWM_Alloc (Pin))); PWMs (PWM_Alloc (Pin)).Taken := False; PWM_Alloc (Pin) := No_PWM; end if; @@ -203,19 +203,19 @@ package body MicroBit.IOs is -- Use one PPI channel to triggerd GPTIOTE OUT task on the compare event -- associated with this PWM_Id; - nRF51.PPI.Configure + nRF.PPI.Configure (Chan => Chan1, Evt_EP => PWM_Timer.Compare_Event (Timer_Channel (Id)), Task_EP => Out_Task (GPIOTE_Channel (Id))); -- Use another PPI channel to triggerd GPTIOTE OUT task on compare 3 event - nRF51.PPI.Configure + nRF.PPI.Configure (Chan => Chan2, Evt_EP => PWM_Timer.Compare_Event (PWM_Global_Compare), Task_EP => Out_Task (GPIOTE_Channel (Id))); - nRF51.PPI.Enable_Channel (Chan1); - nRF51.PPI.Enable_Channel (Chan2); + nRF.PPI.Enable_Channel (Chan1); + nRF.PPI.Enable_Channel (Chan2); end Configure_PPI; ---------------------- @@ -225,7 +225,7 @@ package body MicroBit.IOs is procedure Configure_GPIOTE (Id : PWM_Id) is begin -- Configure the GPIOTE OUT task to toggle the pin - nRF51.GPIO.Tasks_And_Events.Enable_Task + nRF.GPIO.Tasks_And_Events.Enable_Task (Chan => GPIOTE_Channel (Id), GPIO_Pin => Points (PWMs (Id).Pin).Pin, Action => Toggle_Pin, @@ -277,10 +277,10 @@ package body MicroBit.IOs is Enable_Interrupt (PWM_Timer.Compare_Event (PWM_Global_Compare)); - nRF51.Interrupts.Register (PWM_Interrupt, + nRF.Interrupts.Register (PWM_Interrupt, PWM_Timer_Handler'Access); - nRF51.Interrupts.Enable (PWM_Interrupt); + nRF.Interrupts.Enable (PWM_Interrupt); end Init_PWM_Timer; --------- diff --git a/boards/MicroBit/src/microbit-ios.ads b/boards/MicroBit/src/microbit-ios.ads index 730446a2c..4dc4c814c 100644 --- a/boards/MicroBit/src/microbit-ios.ads +++ b/boards/MicroBit/src/microbit-ios.ads @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2017, AdaCore -- +-- Copyright (C) 2017-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -29,7 +29,7 @@ -- -- ------------------------------------------------------------------------------ -with nRF51.GPIO; use nRF51.GPIO; +with nRF.GPIO; use nRF.GPIO; package MicroBit.IOs is diff --git a/boards/MicroBit/src/microbit-spi.adb b/boards/MicroBit/src/microbit-spi.adb index ed7191fc6..3c2281897 100644 --- a/boards/MicroBit/src/microbit-spi.adb +++ b/boards/MicroBit/src/microbit-spi.adb @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2018, AdaCore -- +-- Copyright (C) 2018-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -29,16 +29,16 @@ -- -- ------------------------------------------------------------------------------ -with nRF51.Device; -with nRF51.SPI_Master; use nRF51.SPI_Master; +with nRF.Device; +with nRF.SPI_Master; use nRF.SPI_Master; package body MicroBit.SPI is Init_Done : Boolean := False; - Device : SPI_Master renames nRF51.Device.SPI_Master_1; + Device : SPI_Master renames nRF.Device.SPI_Master_1; -- This device should not conflict with the device used in MicroBit.I2C - -- See nRF51 Series Reference Manual, chapter Memory.Instantiation. + -- See nRF Series Reference Manual, chapter Memory.Instantiation. ----------------- -- Initialized -- diff --git a/boards/MicroBit/src/microbit-time.adb b/boards/MicroBit/src/microbit-time.adb index 11c4bc4da..20c74ba73 100644 --- a/boards/MicroBit/src/microbit-time.adb +++ b/boards/MicroBit/src/microbit-time.adb @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2016, AdaCore -- +-- Copyright (C) 2016-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -29,16 +29,16 @@ -- -- ------------------------------------------------------------------------------ -with nRF51.Clock; -with nRF51.Device; use nRF51.Device; -with nRF51.RTC; use nRF51.RTC; -with nRF51.Events; -with nRF51.Interrupts; +with nRF.Clock; +with nRF.Device; use nRF.Device; +with nRF.RTC; use nRF.RTC; +with nRF.Events; +with nRF.Interrupts; with System.Machine_Code; use System.Machine_Code; package body MicroBit.Time is - package Clocks renames nRF51.Clock; + package Clocks renames nRF.Clock; Clock_Ms : Time_Ms := 0 with Volatile; Period_Ms : constant Time_Ms := 1; @@ -72,12 +72,12 @@ package body MicroBit.Time is Enable_Event (RTC_1, Compare_0_Event); - nRF51.Events.Enable_Interrupt (nRF51.Events.RTC_1_COMPARE_0); + nRF.Events.Enable_Interrupt (nRF.Events.RTC_1_COMPARE_0); - nRF51.Interrupts.Register (nRF51.Interrupts.RTC1_Interrupt, + nRF.Interrupts.Register (nRF.Interrupts.RTC1_Interrupt, RTC1_IRQHandler'Access); - nRF51.Interrupts.Enable (nRF51.Interrupts.RTC1_Interrupt); + nRF.Interrupts.Enable (nRF.Interrupts.RTC1_Interrupt); Start (RTC_1); end Initialize; @@ -101,7 +101,7 @@ package body MicroBit.Time is Clear (RTC_1); Start (RTC_1); - nRF51.Events.Clear (nRF51.Events.RTC_1_COMPARE_0); + nRF.Events.Clear (nRF.Events.RTC_1_COMPARE_0); Update_Clock; diff --git a/boards/MicroBit/src/microbit.ads b/boards/MicroBit/src/microbit.ads index 7e53b8ece..c22903b80 100644 --- a/boards/MicroBit/src/microbit.ads +++ b/boards/MicroBit/src/microbit.ads @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2016, AdaCore -- +-- Copyright (C) 2016-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -29,42 +29,42 @@ -- -- ------------------------------------------------------------------------------ -with nRF51.Device; -with nRF51.GPIO; +with nRF.Device; +with nRF.GPIO; package MicroBit is -- http://tech.microbit.org/hardware/edgeconnector_ds/ - MB_P0 : nRF51.GPIO.GPIO_Point renames nRF51.Device.P03; -- 0 pad on edge connector - MB_P1 : nRF51.GPIO.GPIO_Point renames nRF51.Device.P02; -- 1 pad on edge connector - MB_P2 : nRF51.GPIO.GPIO_Point renames nRF51.Device.P01; -- 2 pad on edge connector - MB_P3 : nRF51.GPIO.GPIO_Point renames nRF51.Device.P04; -- Display column 1 - MB_P4 : nRF51.GPIO.GPIO_Point renames nRF51.Device.P05; -- Display column 2 - MB_P5 : nRF51.GPIO.GPIO_Point renames nRF51.Device.P17; -- Button A - MB_P6 : nRF51.GPIO.GPIO_Point renames nRF51.Device.P12; -- Display column 9 - MB_P7 : nRF51.GPIO.GPIO_Point renames nRF51.Device.P11; -- Display column 8 - MB_P8 : nRF51.GPIO.GPIO_Point renames nRF51.Device.P18; - MB_P9 : nRF51.GPIO.GPIO_Point renames nRF51.Device.P10; -- Display column 7 - MB_P10 : nRF51.GPIO.GPIO_Point renames nRF51.Device.P06; -- Display column 3 - MB_P11 : nRF51.GPIO.GPIO_Point renames nRF51.Device.P26; -- Button B - MB_P12 : nRF51.GPIO.GPIO_Point renames nRF51.Device.P20; - MB_P13 : nRF51.GPIO.GPIO_Point renames nRF51.Device.P23; -- SCK - MB_P14 : nRF51.GPIO.GPIO_Point renames nRF51.Device.P22; -- MISO - MB_P15 : nRF51.GPIO.GPIO_Point renames nRF51.Device.P21; -- MOSI - MB_P16 : nRF51.GPIO.GPIO_Point renames nRF51.Device.P16; - MB_P19 : nRF51.GPIO.GPIO_Point renames nRF51.Device.P00; -- SCL - MB_P20 : nRF51.GPIO.GPIO_Point renames nRF51.Device.P30; -- SDA + MB_P0 : nRF.GPIO.GPIO_Point renames nRF.Device.P03; -- 0 pad on edge connector + MB_P1 : nRF.GPIO.GPIO_Point renames nRF.Device.P02; -- 1 pad on edge connector + MB_P2 : nRF.GPIO.GPIO_Point renames nRF.Device.P01; -- 2 pad on edge connector + MB_P3 : nRF.GPIO.GPIO_Point renames nRF.Device.P04; -- Display column 1 + MB_P4 : nRF.GPIO.GPIO_Point renames nRF.Device.P05; -- Display column 2 + MB_P5 : nRF.GPIO.GPIO_Point renames nRF.Device.P17; -- Button A + MB_P6 : nRF.GPIO.GPIO_Point renames nRF.Device.P12; -- Display column 9 + MB_P7 : nRF.GPIO.GPIO_Point renames nRF.Device.P11; -- Display column 8 + MB_P8 : nRF.GPIO.GPIO_Point renames nRF.Device.P18; + MB_P9 : nRF.GPIO.GPIO_Point renames nRF.Device.P10; -- Display column 7 + MB_P10 : nRF.GPIO.GPIO_Point renames nRF.Device.P06; -- Display column 3 + MB_P11 : nRF.GPIO.GPIO_Point renames nRF.Device.P26; -- Button B + MB_P12 : nRF.GPIO.GPIO_Point renames nRF.Device.P20; + MB_P13 : nRF.GPIO.GPIO_Point renames nRF.Device.P23; -- SCK + MB_P14 : nRF.GPIO.GPIO_Point renames nRF.Device.P22; -- MISO + MB_P15 : nRF.GPIO.GPIO_Point renames nRF.Device.P21; -- MOSI + MB_P16 : nRF.GPIO.GPIO_Point renames nRF.Device.P16; + MB_P19 : nRF.GPIO.GPIO_Point renames nRF.Device.P00; -- SCL + MB_P20 : nRF.GPIO.GPIO_Point renames nRF.Device.P30; -- SDA - MB_SCK : nRF51.GPIO.GPIO_Point renames MB_P13; - MB_MISO : nRF51.GPIO.GPIO_Point renames MB_P14; - MB_MOSI : nRF51.GPIO.GPIO_Point renames MB_P15; + MB_SCK : nRF.GPIO.GPIO_Point renames MB_P13; + MB_MISO : nRF.GPIO.GPIO_Point renames MB_P14; + MB_MOSI : nRF.GPIO.GPIO_Point renames MB_P15; - MB_SCL : nRF51.GPIO.GPIO_Point renames MB_P19; - MB_SDA : nRF51.GPIO.GPIO_Point renames MB_P20; + MB_SCL : nRF.GPIO.GPIO_Point renames MB_P19; + MB_SDA : nRF.GPIO.GPIO_Point renames MB_P20; - MB_UART_TX : nRF51.GPIO.GPIO_Point renames nRF51.Device.P24; - MB_UART_RX : nRF51.GPIO.GPIO_Point renames nRF51.Device.P25; + MB_UART_TX : nRF.GPIO.GPIO_Point renames nRF.Device.P24; + MB_UART_RX : nRF.GPIO.GPIO_Point renames nRF.Device.P25; end MicroBit; diff --git a/boards/NRF52_DK/README.md b/boards/NRF52_DK/README.md new file mode 100644 index 000000000..673ae5d17 --- /dev/null +++ b/boards/NRF52_DK/README.md @@ -0,0 +1,2 @@ +See the [example project](../../examples/NRF52_DK/README.md) for instructions on +how to use the Ada_Drivers_Library on the NRF52_DK. diff --git a/boards/NRF52_DK/nrf52_dk_zfp.gpr b/boards/NRF52_DK/nrf52_dk_zfp.gpr new file mode 100644 index 000000000..e44b12144 --- /dev/null +++ b/boards/NRF52_DK/nrf52_dk_zfp.gpr @@ -0,0 +1,257 @@ +-- This project file was generated by the Ada_Drivers_Library project wizard script +library project NRF52_DK_ZFP is + + type Build_Type is ("Debug", "Production"); + Build : Build_Type := external ("ADL_BUILD", "Debug"); + + type Build_Checks_Type is ("Disabled", "Enabled"); + Build_Checks : Build_Checks_Type := external ("ADL_BUILD_CHECKS", "Disabled"); + + -- Target architecture + Target := Project'Target; + + -- Callgraph info is not available on all architectures + Callgraph_Switch := (); + case Target is + when "riscv32-unknown-elf" => null; + when others => Callgraph_Switch := ("-fcallgraph-info=su"); + end case; + + Build_Checks_Switches := (); + case Build_Checks is + when "Disabled" => null; + when others => + Build_Checks_Switches := + ("-gnaty", "-gnatyM120", "-gnatyO", -- Style checks + "-gnatwe"); -- Warnings as errors + end case; + + package Compiler is + case Build is + when "Production" => + for Default_Switches ("Ada") use + ("-O3", -- Optimization + "-gnatp", -- Supress checks + "-gnatn"); -- Enable inlining + when "Debug" => + for Default_Switches ("Ada") use + ("-O0", -- No optimization + "-gnata") -- Enable assertions + & Callgraph_Switch; + end case; + + for Default_Switches ("ada") use Compiler'Default_Switches ("Ada") & + Callgraph_Switch & + Build_Checks_Switches & + ("-g", -- Debug info + "-gnatwa", -- All warnings + "-gnatw_A", -- Turn off warnings for anonymous allocators + "-gnatQ", -- Don't quit. Generate ALI and tree files even if illegalities + "-gnatw.X", -- Disable warnings for No_Exception_Propagation + "-ffunction-sections", -- Create a linker section for each function + "-fdata-sections"); -- Create a linker section for each data + end Compiler; + + + for Languages use ("Ada", "Asm_CPP"); + for Create_Missing_Dirs use "True"; + for Object_Dir use "obj/zfp_" & Build; + for Library_Dir use "obj/zfp_lib_" & Build; + for Library_Kind use "static"; + for Library_Name use "ada_drivers_library"; + + Linker_Switches := ("-T", Project'Project_dir & "/src/zfp/link.ld"); + for Target use "arm-eabi"; + for Runtime ("Ada") use "zfp-cortex-m4f"; + + package Device_Configuration is + for CPU_Name use "ARM Cortex-M4F"; + for Number_Of_Interrupts use "128"; + for Interrupt ("0") use "adl_irq"; + for Interrupt ("1") use "adl_irq"; + for Interrupt ("2") use "adl_irq"; + for Interrupt ("3") use "adl_irq"; + for Interrupt ("4") use "adl_irq"; + for Interrupt ("5") use "adl_irq"; + for Interrupt ("6") use "adl_irq"; + for Interrupt ("7") use "adl_irq"; + for Interrupt ("8") use "adl_irq"; + for Interrupt ("9") use "adl_irq"; + for Interrupt ("10") use "adl_irq"; + for Interrupt ("11") use "adl_irq"; + for Interrupt ("12") use "adl_irq"; + for Interrupt ("13") use "adl_irq"; + for Interrupt ("14") use "adl_irq"; + for Interrupt ("15") use "adl_irq"; + for Interrupt ("16") use "adl_irq"; + for Interrupt ("17") use "adl_irq"; + for Interrupt ("18") use "adl_irq"; + for Interrupt ("19") use "adl_irq"; + for Interrupt ("20") use "adl_irq"; + for Interrupt ("21") use "adl_irq"; + for Interrupt ("22") use "adl_irq"; + for Interrupt ("23") use "adl_irq"; + for Interrupt ("24") use "adl_irq"; + for Interrupt ("25") use "adl_irq"; + for Interrupt ("26") use "adl_irq"; + for Interrupt ("27") use "adl_irq"; + for Interrupt ("28") use "adl_irq"; + for Interrupt ("29") use "adl_irq"; + for Interrupt ("30") use "adl_irq"; + for Interrupt ("31") use "adl_irq"; + for Interrupt ("32") use "adl_irq"; + for Interrupt ("33") use "adl_irq"; + for Interrupt ("34") use "adl_irq"; + for Interrupt ("35") use "adl_irq"; + for Interrupt ("36") use "adl_irq"; + for Interrupt ("37") use "adl_irq"; + for Interrupt ("38") use "adl_irq"; + for Interrupt ("39") use "adl_irq"; + for Interrupt ("40") use "adl_irq"; + for Interrupt ("41") use "adl_irq"; + for Interrupt ("42") use "adl_irq"; + for Interrupt ("43") use "adl_irq"; + for Interrupt ("44") use "adl_irq"; + for Interrupt ("45") use "adl_irq"; + for Interrupt ("46") use "adl_irq"; + for Interrupt ("47") use "adl_irq"; + for Interrupt ("48") use "adl_irq"; + for Interrupt ("49") use "adl_irq"; + for Interrupt ("50") use "adl_irq"; + for Interrupt ("51") use "adl_irq"; + for Interrupt ("52") use "adl_irq"; + for Interrupt ("53") use "adl_irq"; + for Interrupt ("54") use "adl_irq"; + for Interrupt ("55") use "adl_irq"; + for Interrupt ("56") use "adl_irq"; + for Interrupt ("57") use "adl_irq"; + for Interrupt ("58") use "adl_irq"; + for Interrupt ("59") use "adl_irq"; + for Interrupt ("60") use "adl_irq"; + for Interrupt ("61") use "adl_irq"; + for Interrupt ("62") use "adl_irq"; + for Interrupt ("63") use "adl_irq"; + for Interrupt ("64") use "adl_irq"; + for Interrupt ("65") use "adl_irq"; + for Interrupt ("66") use "adl_irq"; + for Interrupt ("67") use "adl_irq"; + for Interrupt ("68") use "adl_irq"; + for Interrupt ("69") use "adl_irq"; + for Interrupt ("70") use "adl_irq"; + for Interrupt ("71") use "adl_irq"; + for Interrupt ("72") use "adl_irq"; + for Interrupt ("73") use "adl_irq"; + for Interrupt ("74") use "adl_irq"; + for Interrupt ("75") use "adl_irq"; + for Interrupt ("76") use "adl_irq"; + for Interrupt ("77") use "adl_irq"; + for Interrupt ("78") use "adl_irq"; + for Interrupt ("79") use "adl_irq"; + for Interrupt ("80") use "adl_irq"; + for Interrupt ("81") use "adl_irq"; + for Interrupt ("82") use "adl_irq"; + for Interrupt ("83") use "adl_irq"; + for Interrupt ("84") use "adl_irq"; + for Interrupt ("85") use "adl_irq"; + for Interrupt ("86") use "adl_irq"; + for Interrupt ("87") use "adl_irq"; + for Interrupt ("88") use "adl_irq"; + for Interrupt ("89") use "adl_irq"; + for Interrupt ("90") use "adl_irq"; + for Interrupt ("91") use "adl_irq"; + for Interrupt ("92") use "adl_irq"; + for Interrupt ("93") use "adl_irq"; + for Interrupt ("94") use "adl_irq"; + for Interrupt ("95") use "adl_irq"; + for Interrupt ("96") use "adl_irq"; + for Interrupt ("97") use "adl_irq"; + for Interrupt ("98") use "adl_irq"; + for Interrupt ("99") use "adl_irq"; + for Interrupt ("100") use "adl_irq"; + for Interrupt ("101") use "adl_irq"; + for Interrupt ("102") use "adl_irq"; + for Interrupt ("103") use "adl_irq"; + for Interrupt ("104") use "adl_irq"; + for Interrupt ("105") use "adl_irq"; + for Interrupt ("106") use "adl_irq"; + for Interrupt ("107") use "adl_irq"; + for Interrupt ("108") use "adl_irq"; + for Interrupt ("109") use "adl_irq"; + for Interrupt ("110") use "adl_irq"; + for Interrupt ("111") use "adl_irq"; + for Interrupt ("112") use "adl_irq"; + for Interrupt ("113") use "adl_irq"; + for Interrupt ("114") use "adl_irq"; + for Interrupt ("115") use "adl_irq"; + for Interrupt ("116") use "adl_irq"; + for Interrupt ("117") use "adl_irq"; + for Interrupt ("118") use "adl_irq"; + for Interrupt ("119") use "adl_irq"; + for Interrupt ("120") use "adl_irq"; + for Interrupt ("121") use "adl_irq"; + for Interrupt ("122") use "adl_irq"; + for Interrupt ("123") use "adl_irq"; + for Interrupt ("124") use "adl_irq"; + for Interrupt ("125") use "adl_irq"; + for Interrupt ("126") use "adl_irq"; + for Interrupt ("127") use "adl_irq"; + + for Memories use ("flash", "ram"); + + for Mem_Kind ("flash") use "rom"; + for Address ("flash") use "0x00000000"; + for Size ("flash") use "512K"; + + for Mem_Kind ("ram") use "ram"; + for Address ("ram") use "0x20000000"; + for Size ("ram") use "64K"; + + for Boot_Memory use "flash"; + end Device_Configuration; + + Vendor := "Nordic"; -- From board definition + Max_Mount_Points := "2"; -- From default value + Boot_Memory := "flash"; -- From default value + Max_Mount_Name_Length := "128"; -- From default value + Runtime_Profile := "zfp"; -- From command line + Device_Name := "nRF52832xxAA"; -- From board definition + Device_Family := "nRF52"; -- From board definition + Has_Ravenscar_SFP_Runtime := "False"; -- From board definition + Runtime_Name := "zfp-cortex-m4f"; -- From default value + Has_Ravenscar_Full_Runtime := "False"; -- From board definition + CPU_Core := "ARM Cortex-M4F"; -- From mcu definition + Board := "NRF52_DK"; -- From command line + Has_ZFP_Runtime := "True"; -- From board definition + Number_Of_Interrupts := "128"; -- From MCU definition + Has_Custom_Memory_Area_1 := "False"; -- From default value + Use_Startup_Gen := "True"; -- From command line + Max_Path_Length := "1024"; -- From default value + Runtime_Name_Suffix := "cortex-m4f"; -- From board definition + Architecture := "ARM"; -- From board definition + + -- Project source directories + Src_Dirs_Root := "../.."; + for Source_Dirs use ( + Src_Dirs_Root & "/hal/src/", -- From HAL config + Src_Dirs_Root & "/boards/NRF52_DK/src/", -- From board definition + Src_Dirs_Root & "/arch/ARM/cortex_m/src", -- From arch definition + Src_Dirs_Root & "/arch/ARM/cortex_m/src/cm4f", -- From arch definition + Src_Dirs_Root & "/arch/ARM/cortex_m/src/fpu", -- From arch definition + Src_Dirs_Root & "/arch/ARM/cortex_m/src/nocache", -- From arch definition + Src_Dirs_Root & "/arch/ARM/cortex_m/src/nvic_cm4_cm7", -- From arch definition + Src_Dirs_Root & "/arch/ARM/Nordic/devices/nrf52", -- From MCU definition + Src_Dirs_Root & "/arch/ARM/Nordic/drivers/nrf_common", -- From MCU definition + Src_Dirs_Root & "/arch/ARM/Nordic/drivers/nrf52", -- From MCU definition + Src_Dirs_Root & "/arch/ARM/Nordic/svd/nrf52/", -- From MCU definition + Src_Dirs_Root & "/middleware/src/filesystem", -- From middleware config + Src_Dirs_Root & "/middleware/src/BLE", -- From middleware config + Src_Dirs_Root & "/middleware/src/utils", -- From middleware config + Src_Dirs_Root & "/middleware/src/audio", -- From middleware config + Src_Dirs_Root & "/middleware/src/monitor", -- From middleware config + Src_Dirs_Root & "/middleware/src/bitmap", -- From middleware config + Src_Dirs_Root & "/middleware/src/command_line", -- From middleware config + Src_Dirs_Root & "/middleware/src/sdmmc", -- From middleware config + Src_Dirs_Root & "/middleware/src/neopixel", -- From middleware config + Src_Dirs_Root & "/components/src/**", -- From components config + "src/zfp/"); +end NRF52_DK_ZFP; diff --git a/boards/NRF52_DK/src/nrf52_dk-buttons.adb b/boards/NRF52_DK/src/nrf52_dk-buttons.adb new file mode 100755 index 000000000..35015abf5 --- /dev/null +++ b/boards/NRF52_DK/src/nrf52_dk-buttons.adb @@ -0,0 +1,141 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright (C) 2017-2020, AdaCore -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of the copyright holder nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +------------------------------------------------------------------------------ + +with nRF.Device; use nRF.Device; +with nRF.GPIO; use nRF.GPIO; +with NRF52_DK.Time; use NRF52_DK.Time; + +package body NRF52_DK.Buttons is + + type Button_State_Array is array (Button_Id) of Button_State; + Points : constant array (Button_Id) of GPIO_Point := (P13, P14, P15, P16); + States : Button_State_Array := (others => Released); + Subscribers : array (1 .. 10) of Button_Callback := (others => null); + + procedure Initialize; + procedure Tick_Handler; + + ---------------- + -- Initialize -- + ---------------- + + procedure Initialize is + Conf : GPIO_Configuration; + begin + Conf.Mode := Mode_In; + Conf.Resistors := Pull_Up; + Conf.Input_Buffer := Input_Buffer_Connect; + Conf.Sense := Sense_Disabled; + + for Pt of Points loop + Pt.Configure_IO (Conf); + end loop; + + if not Tick_Subscribe (Tick_Handler'Access) then + raise Program_Error; + end if; + + end Initialize; + + ------------------ + -- Tick_Handler -- + ------------------ + + procedure Tick_Handler is + Prev_States : constant Button_State_Array := States; + begin + -- Update all components of States array + + for Id in Button_Id loop + if not Set (Points (Id)) then + States (Id) := Pressed; + else + States (Id) := Released; + end if; + end loop; + + -- Notify changes to subscribers + + for Id in Button_Id loop + if States (Id) /= Prev_States (Id) then + for Sub of Subscribers loop + + if Sub /= null then + Sub.all (Id, States (Id)); + end if; + end loop; + end if; + end loop; + end Tick_Handler; + + ----------- + -- State -- + ----------- + + function State (Button : Button_Id) return Button_State is + begin + return States (Button); + end State; + + --------------- + -- Subscribe -- + --------------- + + function Subscribe (Callback : not null Button_Callback) return Boolean is + begin + for Subs of Subscribers loop + if Subs = null then + Subs := Callback; + return True; + end if; + end loop; + + return False; + end Subscribe; + + ----------------- + -- Unsubscribe -- + ----------------- + + function Unsubscribe (Callback : not null Button_Callback) return Boolean is + begin + for Subs of Subscribers loop + if Subs = Callback then + Subs := null; + return True; + end if; + end loop; + return False; + end Unsubscribe; + +begin + Initialize; +end NRF52_DK.Buttons; diff --git a/boards/NRF52_DK/src/nrf52_dk-buttons.ads b/boards/NRF52_DK/src/nrf52_dk-buttons.ads new file mode 100755 index 000000000..b4467b86d --- /dev/null +++ b/boards/NRF52_DK/src/nrf52_dk-buttons.ads @@ -0,0 +1,53 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright (C) 2017-2020, AdaCore -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of the copyright holder nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +------------------------------------------------------------------------------ + +package NRF52_DK.Buttons is + + type Button_State is (Pressed, Released); + type Button_Id is (Button_1, Button_2, Button_3, Button_4); + + function State (Button : Button_Id) return Button_State; + -- Indicate the current state of the requested button + + type Button_Callback is access procedure (Button : Button_Id; + State : Button_State); + + function Subscribe (Callback : not null Button_Callback) return Boolean; + -- Add Callback to the list of subscribers. Return False if Callback cannot + -- be added. + -- + -- Callback will be executed each time a button state changes. + + function Unsubscribe (Callback : not null Button_Callback) return Boolean; + -- Remove Callback from the list of subscribers. Return False if Callback + -- is not in the list of sucbscribers. + +end NRF52_DK.Buttons; diff --git a/boards/NRF52_DK/src/nrf52_dk-ios.adb b/boards/NRF52_DK/src/nrf52_dk-ios.adb new file mode 100644 index 000000000..f43bd901b --- /dev/null +++ b/boards/NRF52_DK/src/nrf52_dk-ios.adb @@ -0,0 +1,437 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright (C) 2017-2020, AdaCore -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of the copyright holder nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +------------------------------------------------------------------------------ + +with HAL; use HAL; + +with nRF.ADC; use nRF.ADC; +with nRF.PPI; use nRF.PPI; +with nRF.Timers; use nRF.Timers; +with nRF.GPIO.Tasks_And_Events; use nRF.GPIO.Tasks_And_Events; +with nRF.Events; use nRF.Events; +with nRF.Interrupts; use nRF.Interrupts; + +package body NRF52_DK.IOs is + + -- The analog out feature is implemented as PWM signal. To generate the PWM + -- signals we use a timer with the configuration described bellow. + -- + -- Because of the limited number of timer comparators and GPIOTE channels, + -- we can only have 3 PWMs on the system at the same time. However there + -- are 5 pins allowed to use PWM, so we need to dynamicaly allocate the + -- PWM based on user requests. + -- + -- Timer configuration: + -- + -- Comparator 0, 1, 2 are used to control the pulse width of the 3 PWMs. + -- Each of those comparator is associated with a PWM and a pin. When the + -- timer counter reaches the value of a comparator, the associated pin + -- toggles. + -- + -- Comparator 3 is use to control the period. When the timer counter reaches + -- its value, all pins toggle. + -- + -- Comparator 3 also trigger an interrupt. In the handler for this + -- interrupt, we update all the comparator values and start the timer again. + -- + -- + -- Int handler and timer start Cmp 0 Cmp 1 Cmp 2 Cmp3, Timer stop and interrupt + -- v v v v v + -- _______________________________ ____ + -- |_______________________| + -- ______________________________________ ____ + -- |________________| + -- _____________________________________________ ____ + -- |_________| + -- + -- ^------------------ Timer loop sequence -------------------^ + -- + -- Since all the timer events trigger a toggle of the pin, we have to make + -- sure that the pin is at a good state (high) when starting the timer, + -- otherwise the waveform could be inverted. This is why the GPIO channels + -- are always configured when the timer is reconfigured. + -- + -- PPI and GPIOTE: + -- + -- To trigger a pin toggle from the timer compare events we use the + -- following configuation. + -- + -- Two PPI channels are used for each PWM pin. For a PWM X, one PPI channel + -- is used to trigger a GPIOTE task on comparator X event, a second PPI + -- channel is used to trigger a GPIOTE event on comparator 3 event. So + -- the comparator 3 event is used by all PWMs. + -- + -- For a PWM X, GPIOTE channel X is configure to do a pin toggle when its + -- task is activated by one of the two PPI channels described above. + + -- We keep track of the current mode of the pin to be able to detect when a + -- change of configuration is needed. + type Pin_Mode is (None, Digital_In, Digital_Out, Analog_In, Analog_Out); + Current_Mode : array (Pin_Id) of Pin_Mode := (others => None); + + -- PWM -- + + Number_Of_PWMs : constant := 3; + + type PWM_Allocated is range 0 .. Number_Of_PWMs; + subtype PWM_Id is PWM_Allocated range 0 .. Number_Of_PWMs - 1; + + No_PWM : constant PWM_Allocated := Number_Of_PWMs; + + PWM_Alloc : array (Pin_Id) of PWM_Allocated := (others => No_PWM); + + PWM_Timer : Timer renames Timer_0; + PWM_Interrupt : constant Interrupt_Name := TIMER0_Interrupt; + PWM_Global_Compare : constant Timer_Channel := 3; + PWM_Precision : constant := 4; + PWM_Period : UInt32 := 2_000 / PWM_Precision; + + type PWM_Status is record + Taken : Boolean := False; + Pulse_Width : Analog_Value; + Cmp : UInt32 := 10; + Pin : Pin_Id; + end record; + + PWMs : array (PWM_Id) of PWM_Status; + + function Has_PWM (Pin : Pin_Id) return Boolean + is (PWM_Alloc (Pin) /= No_PWM); + procedure Allocate_PWM (Pin : Pin_Id; + Success : out Boolean) + with Pre => not Has_PWM (Pin); + procedure Deallocate_PWM (Pin : Pin_Id) + with Pre => Has_PWM (Pin), + Post => not Has_PWM (Pin); + procedure Configure_PPI (Id : PWM_Id); + procedure Configure_GPIOTE (Id : PWM_Id); + procedure Init_PWM_Timer; + function To_Compare_Value (V : Analog_Value) return UInt32; + procedure PWM_Timer_Handler; + + ---------------------- + -- To_Compare_Value -- + ---------------------- + + function To_Compare_Value (V : Analog_Value) return UInt32 + is + Cmp : constant UInt32 := + UInt32 (Float (PWM_Period) * (Float (V) / Float (Analog_Value'Last))); + begin + + if Cmp = 0 then + return 1; + elsif Cmp >= PWM_Period then + return PWM_Period - 1; + else + return Cmp; + end if; + end To_Compare_Value; + + ------------------ + -- Allocate_PWM -- + ------------------ + + procedure Allocate_PWM (Pin : Pin_Id; + Success : out Boolean) + is + begin + for Id in PWM_Id loop + if not PWMs (Id).Taken then + PWMs (Id).Taken := True; + PWMs (Id).Pin := Pin; + PWM_Alloc (Pin) := Id; + + Configure_PPI (Id); + + Success := True; + return; + end if; + end loop; + Success := False; + end Allocate_PWM; + + -------------------- + -- Deallocate_PWM -- + -------------------- + + procedure Deallocate_PWM (Pin : Pin_Id) is + begin + if PWM_Alloc (Pin) /= No_PWM then + nRF.GPIO.Tasks_And_Events.Disable (GPIOTE_Channel (PWM_Alloc (Pin))); + PWMs (PWM_Alloc (Pin)).Taken := False; + PWM_Alloc (Pin) := No_PWM; + end if; + end Deallocate_PWM; + + ------------------- + -- Configure_PPI -- + ------------------- + + procedure Configure_PPI (Id : PWM_Id) is + Chan1 : constant Channel_ID := Channel_ID (Id) * 2; + Chan2 : constant Channel_ID := Chan1 + 1; + begin + + -- Use one PPI channel to triggerd GPTIOTE OUT task on the compare event + -- associated with this PWM_Id; + nRF.PPI.Configure + (Chan => Chan1, + Evt_EP => PWM_Timer.Compare_Event (Timer_Channel (Id)), + Task_EP => Out_Task (GPIOTE_Channel (Id))); + + -- Use another PPI channel to triggerd GPTIOTE OUT task on compare 3 event + nRF.PPI.Configure + (Chan => Chan2, + Evt_EP => PWM_Timer.Compare_Event (PWM_Global_Compare), + Task_EP => Out_Task (GPIOTE_Channel (Id))); + + nRF.PPI.Enable_Channel (Chan1); + nRF.PPI.Enable_Channel (Chan2); + end Configure_PPI; + + ---------------------- + -- Configure_GPIOTE -- + ---------------------- + + procedure Configure_GPIOTE (Id : PWM_Id) is + begin + -- Configure the GPIOTE OUT task to toggle the pin + nRF.GPIO.Tasks_And_Events.Enable_Task + (Chan => GPIOTE_Channel (Id), + GPIO_Pin => Points (PWMs (Id).Pin).Pin, + Action => Toggle_Pin, + Initial_Value => Init_Set); + end Configure_GPIOTE; + + ----------------------- + -- PWM_Timer_Handler -- + ----------------------- + + procedure PWM_Timer_Handler is + begin + Clear (PWM_Timer.Compare_Event (PWM_Global_Compare)); + + PWM_Timer.Set_Compare (PWM_Global_Compare, PWM_Period); + + PWM_Timer.Set_Compare (0, PWMs (0).Cmp); + PWM_Timer.Set_Compare (1, PWMs (1).Cmp); + PWM_Timer.Set_Compare (2, PWMs (2).Cmp); + + PWM_Timer.Start; + end PWM_Timer_Handler; + + -------------------- + -- Init_PWM_Timer -- + -------------------- + + procedure Init_PWM_Timer is + begin + PWM_Timer.Set_Mode (Mode_Timer); + PWM_Timer.Set_Prescaler (6); + PWM_Timer.Set_Bitmode (Bitmode_32bit); + + -- Clear counter internal register and stop when timer reaches compare + -- value 3. + PWM_Timer.Compare_Shortcut (Chan => PWM_Global_Compare, + Stop => True, + Clear => True); + + PWM_Timer.Set_Compare (PWM_Global_Compare, PWM_Period); + + for Id in PWM_Id loop PWM_Timer.Set_Compare (Timer_Channel (Id), + To_Compare_Value (PWMs (Id).Pulse_Width)); + if PWMs (Id).Taken then + Configure_GPIOTE (Id); + end if; + + end loop; + + Enable_Interrupt (PWM_Timer.Compare_Event (PWM_Global_Compare)); + + nRF.Interrupts.Register (PWM_Interrupt, + PWM_Timer_Handler'Access); + + nRF.Interrupts.Enable (PWM_Interrupt); + end Init_PWM_Timer; + + --------- + -- Set -- + --------- + + procedure Set + (Pin : Pin_Id; + Value : Boolean) + is + Pt : GPIO_Point renames Points (Pin); + Conf : GPIO_Configuration; + begin + if Current_Mode (Pin) /= Digital_Out then + if Has_PWM (Pin) then + Deallocate_PWM (Pin); + end if; + + Conf.Mode := Mode_Out; + Conf.Resistors := No_Pull; + Conf.Input_Buffer := Input_Buffer_Connect; + Conf.Sense := Sense_Disabled; + + Pt.Configure_IO (Conf); + Current_Mode (Pin) := Digital_Out; + end if; + + if Value then + Pt.Set; + else + Pt.Clear; + end if; + end Set; + + --------- + -- Set -- + --------- + + function Set + (Pin : Pin_Id) + return Boolean + is + Pt : GPIO_Point renames Points (Pin); + Conf : GPIO_Configuration; + begin + if Current_Mode (Pin) /= Digital_In then + if Has_PWM (Pin) then + Deallocate_PWM (Pin); + end if; + + Conf.Mode := Mode_In; + Conf.Resistors := No_Pull; + Conf.Input_Buffer := Input_Buffer_Connect; + Conf.Sense := Sense_Disabled; + + Pt.Configure_IO (Conf); + + Current_Mode (Pin) := Digital_In; + end if; + + return Pt.Set; + end Set; + + -------------------------- + -- Set_Analog_Period_Us -- + -------------------------- + + procedure Set_Analog_Period_Us (Period : Natural) is + begin + PWM_Period := UInt32 (Period) / PWM_Precision; + + -- Update the comparator values for ech PWM + for PWM of PWMs loop + PWM.Cmp := To_Compare_Value (PWM.Pulse_Width); + end loop; + end Set_Analog_Period_Us; + + ----------- + -- Write -- + ----------- + + procedure Write + (Pin : Pin_Id; + Value : Analog_Value) + is + Success : Boolean; + + Pt : GPIO_Point renames Points (Pin); + Conf : GPIO_Configuration; + begin + + if not Has_PWM (Pin) then + + -- Stop the timer while we configure a new pin + + PWM_Timer.Stop; + PWM_Timer.Clear; + + Allocate_PWM (Pin, Success); + if not Success then + raise Program_Error with "No PWM available"; + end if; + + -- Set the pin as output + Conf.Mode := Mode_Out; + Conf.Resistors := No_Pull; + Conf.Input_Buffer := Input_Buffer_Connect; + Conf.Sense := Sense_Disabled; + + Pt.Configure_IO (Conf); + Pt.Clear; + + Current_Mode (Pin) := Analog_Out; + + Init_PWM_Timer; + + PWM_Timer.Start; + end if; + + PWMs (PWM_Alloc (Pin)).Pulse_Width := Value; + PWMs (PWM_Alloc (Pin)).Cmp := To_Compare_Value (Value); + end Write; + + ------------ + -- Analog -- + ------------ + + function Analog + (Pin : Pin_Id) + return Analog_Value + is + Result : UInt16; + begin + if Current_Mode (Pin) /= Analog_In then + if Has_PWM (Pin) then + Deallocate_PWM (Pin); + end if; + Current_Mode (Pin) := Analog_In; + end if; + + Result := Do_Pin_Conversion (Pin => (case Pin is + when 0 => 4, + when 1 => 3, + when 2 => 2, + when 3 => 5, + when 4 => 6, + when 10 => 7, + when others => 0), + Input => Pin_One_Forth, + Ref => VDD_One_Forth, + Res => Res_10bit); + return Analog_Value (Result); + end Analog; + +end NRF52_DK.IOs; diff --git a/boards/NRF52_DK/src/nrf52_dk-ios.ads b/boards/NRF52_DK/src/nrf52_dk-ios.ads new file mode 100644 index 000000000..0e060a68f --- /dev/null +++ b/boards/NRF52_DK/src/nrf52_dk-ios.ads @@ -0,0 +1,108 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright (C) 2017-2020, AdaCore -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of the copyright holder nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +------------------------------------------------------------------------------ + +with nRF.Device; use nRF.Device; +with nRF.GPIO; use nRF.GPIO; + +package NRF52_DK.IOs is + + type Pin_Id is range 0 .. 31; + + type IO_Features is (Digital, Analog); + + function Supports (Pin : Pin_Id; Feature : IO_Features) return Boolean is + (case Feature is + when Digital => (case Pin is + when 0 .. 2 | 5 .. 27 => True, + when others => False), + when Analog => (case Pin is + when 3 .. 4 | 28 .. 31 => True, + when others => False)); + + procedure Set (Pin : Pin_Id; Value : Boolean) + with Pre => Supports (Pin, Digital); + + function Set (Pin : Pin_Id) return Boolean + with Pre => Supports (Pin, Digital); + + type Analog_Value is range 0 .. 4095; + + procedure Set_Analog_Period_Us (Period : Natural); + -- Set the period (in microseconds) of the PWM signal for all analog output + -- pins. + + procedure Write (Pin : Pin_Id; Value : Analog_Value) + with Pre => Supports (Pin, Analog); + + function Analog (Pin : Pin_Id) return Analog_Value + with Pre => Supports (Pin, Analog); + -- Read the voltagle applied to the pin. 0 means 0V 1023 means 3.3V + +private + + -- Mapping between pin id and GPIO_Points + + Points : array (Pin_Id) of GPIO_Point := + (0 => P00, + 1 => P01, + 2 => P02, + 3 => P03, + 4 => P04, + 5 => P05, + 6 => P06, + 7 => P07, + 8 => P08, + 9 => P09, + 10 => P10, + 11 => P11, + 12 => P12, + 13 => P13, + 14 => P14, + 15 => P15, + 16 => P16, + 17 => P17, + 18 => P18, + 19 => P19, + 20 => P20, + 21 => P21, + 22 => P22, + 23 => P23, + 24 => P24, + 25 => P25, + 26 => P26, + 27 => P27, + 28 => P28, + 29 => P29, + 30 => P30, + 31 => P31 + ); + +end NRF52_DK.IOs; diff --git a/boards/NRF52_DK/src/nrf52_dk-leds.adb b/boards/NRF52_DK/src/nrf52_dk-leds.adb new file mode 100644 index 000000000..33fbd0f8f --- /dev/null +++ b/boards/NRF52_DK/src/nrf52_dk-leds.adb @@ -0,0 +1,57 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright (C) 2020, AdaCore -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of the copyright holder nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +------------------------------------------------------------------------------ + +package body NRF52_DK.LEDs is + + LEDs : array (1 .. 4) of GPIO_Point := (LED1, LED2, LED3, LED4); + + procedure Initialize_LEDs is + Conf : GPIO_Configuration; + begin + Conf.Mode := Mode_Out; + Conf.Resistors := No_Pull; + for LED of LEDs loop + LED.Configure_IO (Conf); + LED.Set; + end loop; + end Initialize_LEDs; + + procedure Turn_On (This : in out User_LED) is + begin + This.Clear; + end Turn_On; + + procedure Turn_Off (This : in out User_LED) is + begin + This.Set; + end Turn_Off; + +end NRF52_DK.LEDs; diff --git a/boards/NRF52_DK/src/nrf52_dk-leds.ads b/boards/NRF52_DK/src/nrf52_dk-leds.ads new file mode 100644 index 000000000..8c55feb6c --- /dev/null +++ b/boards/NRF52_DK/src/nrf52_dk-leds.ads @@ -0,0 +1,48 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright (C) 2020, AdaCore -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of the copyright holder nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +------------------------------------------------------------------------------ + +with nRF.Device; use nRF.Device; +with nRF.GPIO; use nRF.GPIO; + +package NRF52_DK.LEDs is + + subtype User_LED is GPIO_Point; + LED1 : User_LED renames P17; + LED2 : User_LED renames P18; + LED3 : User_LED renames P19; + LED4 : User_LED renames P20; + + procedure Initialize_LEDs; + + procedure Turn_On (This : in out User_LED); + procedure Turn_Off (This : in out User_LED); + +end NRF52_DK.LEDs; diff --git a/boards/NRF52_DK/src/nrf52_dk-time.adb b/boards/NRF52_DK/src/nrf52_dk-time.adb new file mode 100644 index 000000000..5ac9eeaf8 --- /dev/null +++ b/boards/NRF52_DK/src/nrf52_dk-time.adb @@ -0,0 +1,246 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright (C) 2016-2020, AdaCore -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of the copyright holder nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +------------------------------------------------------------------------------ + +with nRF.Clock; +with nRF.Device; use nRF.Device; +with nRF.RTC; use nRF.RTC; +with nRF.Events; +with nRF.Interrupts; +with System.Machine_Code; use System.Machine_Code; + +package body NRF52_DK.Time is + + package Clocks renames nRF.Clock; + + Clock_Ms : Time_Ms := 0 with Volatile; + Period_Ms : constant Time_Ms := 1; + + Subscribers : array (1 .. 10) of Tick_Callback := (others => null); + + procedure Initialize; + procedure Update_Clock; + procedure RTC1_IRQHandler; + + ---------------- + -- Initialize -- + ---------------- + + procedure Initialize is + begin + if not Clocks.Low_Freq_Running then + Clocks.Set_Low_Freq_Source (Clocks.LFCLK_SYNTH); + Clocks.Start_Low_Freq; + + loop + exit when Clocks.Low_Freq_Running; + end loop; + end if; + + Stop (RTC_1); + + -- 1kHz + Set_Prescaler (RTC_1, 0); + Set_Compare (RTC_1, 0, 32); + + Enable_Event (RTC_1, Compare_0_Event); + + nRF.Events.Enable_Interrupt (nRF.Events.RTC_1_COMPARE_0); + + nRF.Interrupts.Register (nRF.Interrupts.RTC1_Interrupt, + RTC1_IRQHandler'Access); + + nRF.Interrupts.Enable (nRF.Interrupts.RTC1_Interrupt); + + Start (RTC_1); + end Initialize; + + ------------------ + -- Update_Clock -- + ------------------ + + procedure Update_Clock is + begin + Clock_Ms := Clock_Ms + Period_Ms; + end Update_Clock; + + --------------------- + -- RTC1_IRQHandler -- + --------------------- + + procedure RTC1_IRQHandler is + begin + Stop (RTC_1); + Clear (RTC_1); + Start (RTC_1); + + nRF.Events.Clear (nRF.Events.RTC_1_COMPARE_0); + + Update_Clock; + + for Subs of Subscribers loop + + if Subs /= null then + -- Call the subscriber + Subs.all; + end if; + + end loop; + end RTC1_IRQHandler; + + ----------- + -- Clock -- + ----------- + + function Clock return Time_Ms is + begin + return Clock_Ms; + end Clock; + + -------------- + -- Delay_Ms -- + -------------- + + procedure Delay_Ms (Milliseconds : UInt64) is + Wakeup_Time : constant UInt64 := Clock + Milliseconds; + begin + while Wakeup_Time > Clock loop + Asm (Template => "wfi", -- Wait for interrupt + Volatile => True); + end loop; + end Delay_Ms; + + ----------------- + -- Tick_Period -- + ----------------- + + function Tick_Period return Time_Ms is + begin + return Period_Ms; + end Tick_Period; + + -------------------- + -- Tick_Subscribe -- + -------------------- + + function Tick_Subscriber (Callback : not null Tick_Callback) return Boolean is + begin + for Subs of Subscribers loop + if Subs = Callback then + return True; + end if; + end loop; + return False; + end Tick_Subscriber; + + -------------------- + -- Tick_Subscribe -- + -------------------- + + function Tick_Subscribe (Callback : not null Tick_Callback) return Boolean is + begin + for Subs of Subscribers loop + if Subs = null then + Subs := Callback; + return True; + end if; + end loop; + + return False; + end Tick_Subscribe; + + ---------------------- + -- Tick_Unsubscribe -- + ---------------------- + + function Tick_Unsubscribe (Callback : not null Tick_Callback) return Boolean is + begin + for Subs of Subscribers loop + if Subs = Callback then + Subs := null; + return True; + end if; + end loop; + return False; + end Tick_Unsubscribe; + + --------------- + -- HAL_Delay -- + --------------- + + Delay_Instance : aliased MB_Delays; + + function HAL_Delay return not null HAL.Time.Any_Delays is + begin + return Delay_Instance'Access; + end HAL_Delay; + + ------------------------ + -- Delay_Microseconds -- + ------------------------ + + overriding + procedure Delay_Microseconds (This : in out MB_Delays; + Us : Integer) + is + pragma Unreferenced (This); + begin + Delay_Ms (UInt64 (Us / 1000)); + end Delay_Microseconds; + + ------------------------ + -- Delay_Milliseconds -- + ------------------------ + + overriding + procedure Delay_Milliseconds (This : in out MB_Delays; + Ms : Integer) + is + pragma Unreferenced (This); + begin + Delay_Ms (UInt64 (Ms)); + end Delay_Milliseconds; + + ------------------- + -- Delay_Seconds -- + ------------------- + + overriding + procedure Delay_Seconds (This : in out MB_Delays; + S : Integer) + is + pragma Unreferenced (This); + begin + Delay_Ms (UInt64 (S * 1000)); + end Delay_Seconds; + +begin + Initialize; +end NRF52_DK.Time; diff --git a/boards/NRF52_DK/src/nrf52_dk-time.ads b/boards/NRF52_DK/src/nrf52_dk-time.ads new file mode 100644 index 000000000..e15523d10 --- /dev/null +++ b/boards/NRF52_DK/src/nrf52_dk-time.ads @@ -0,0 +1,81 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright (C) 2016-2020, AdaCore -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of the copyright holder nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +------------------------------------------------------------------------------ + +with HAL; use HAL; +with HAL.Time; + +package NRF52_DK.Time is + + subtype Time_Ms is UInt64; + + function Clock return Time_Ms; + + procedure Delay_Ms (Milliseconds : UInt64); + + procedure Sleep (Milliseconds : UInt64) renames Delay_Ms; + + function Tick_Period return Time_Ms; + + type Tick_Callback is access procedure; + + function Tick_Subscriber (Callback : not null Tick_Callback) return Boolean; + -- Return True if callback is already a tick event subscriber + + function Tick_Subscribe (Callback : not null Tick_Callback) return Boolean + with Pre => not Tick_Subscriber (Callback), + Post => (if Tick_Subscribe'Result then Tick_Subscriber (Callback)); + -- Subscribe a callback to the tick event. The function return True on + -- success, False if there's no more room for subscribers. + + function Tick_Unsubscribe (Callback : not null Tick_Callback) return Boolean + with Pre => Tick_Subscriber (Callback), + Post => (if Tick_Unsubscribe'Result then not Tick_Subscriber (Callback)); + -- Unsubscribe a callback to the tick event. The function return True on + -- success, False if the callback was not a subscriber. + + function HAL_Delay return not null HAL.Time.Any_Delays; +private + + type MB_Delays is new HAL.Time.Delays with null record; + + overriding + procedure Delay_Microseconds (This : in out MB_Delays; + Us : Integer); + + overriding + procedure Delay_Milliseconds (This : in out MB_Delays; + Ms : Integer); + + overriding + procedure Delay_Seconds (This : in out MB_Delays; + S : Integer); + +end NRF52_DK.Time; diff --git a/boards/NRF52_DK/src/nrf52_dk.ads b/boards/NRF52_DK/src/nrf52_dk.ads new file mode 100644 index 000000000..ae3be09f7 --- /dev/null +++ b/boards/NRF52_DK/src/nrf52_dk.ads @@ -0,0 +1,50 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright (C) 2016-2020, AdaCore -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of the copyright holder nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +------------------------------------------------------------------------------ + +with nRF.Device; +with nRF.GPIO; + +package NRF52_DK is + + -- DK Headers are "Arduino compatible" these names reflect the + -- Arduino locations of these peripherals + + DK_SCK : nRF.GPIO.GPIO_Point renames nRF.Device.P25; + DK_MISO : nRF.GPIO.GPIO_Point renames nRF.Device.P24; + DK_MOSI : nRF.GPIO.GPIO_Point renames nRF.Device.P23; + + DK_SCL : nRF.GPIO.GPIO_Point renames nRF.Device.P31; + DK_SDA : nRF.GPIO.GPIO_Point renames nRF.Device.P30; + + DK_UART_TX : nRF.GPIO.GPIO_Point renames nRF.Device.P12; + DK_UART_RX : nRF.GPIO.GPIO_Point renames nRF.Device.P11; + +end NRF52_DK; diff --git a/boards/NRF52_DK/src/zfp/adl_config.ads b/boards/NRF52_DK/src/zfp/adl_config.ads new file mode 100644 index 000000000..91facb3da --- /dev/null +++ b/boards/NRF52_DK/src/zfp/adl_config.ads @@ -0,0 +1,22 @@ +-- This package was generated by the Ada_Drivers_Library project wizard script +package ADL_Config is + Vendor : constant String := "Nordic"; -- From board definition + Max_Mount_Points : constant := 2; -- From default value + Boot_Memory : constant String := "flash"; -- From default value + Max_Mount_Name_Length : constant := 128; -- From default value + Runtime_Profile : constant String := "zfp"; -- From command line + Device_Name : constant String := "nRF52832xxAA"; -- From board definition + Device_Family : constant String := "nRF52"; -- From board definition + Has_Ravenscar_SFP_Runtime : constant String := "False"; -- From board definition + Runtime_Name : constant String := "zfp-cortex-m4f"; -- From default value + Has_Ravenscar_Full_Runtime : constant String := "False"; -- From board definition + CPU_Core : constant String := "ARM Cortex-M4F"; -- From mcu definition + Board : constant String := "NRF52_DK"; -- From command line + Has_ZFP_Runtime : constant String := "True"; -- From board definition + Number_Of_Interrupts : constant := 128; -- From MCU definition + Has_Custom_Memory_Area_1 : constant Boolean := False; -- From default value + Use_Startup_Gen : constant Boolean := True; -- From command line + Max_Path_Length : constant := 1024; -- From default value + Runtime_Name_Suffix : constant String := "cortex-m4f"; -- From board definition + Architecture : constant String := "ARM"; -- From board definition +end ADL_Config; diff --git a/boards/NRF52_DK/src/zfp/crt0.S b/boards/NRF52_DK/src/zfp/crt0.S new file mode 100644 index 000000000..58a3ee9d7 --- /dev/null +++ b/boards/NRF52_DK/src/zfp/crt0.S @@ -0,0 +1,497 @@ + .syntax unified + .cpu cortex-m0 + .thumb + + .text + .globl __vectors + .p2align 9 + .section .vectors,"a" +__vectors: + /* Cortex-M core interrupts */ + .word __stack_end /* stack top address */ + .word _start /* 1 Reset */ + .word fault /* 2 NMI. */ + .word fault /* 3 Hard fault. */ + .word fault /* 4 Mem manage. */ + .word fault /* 5 Bus fault. */ + .word fault /* 6 Usage fault. */ + .word fault /* 7 reserved. */ + .word fault /* 8 reserved. */ + .word fault /* 9 reserved. */ + .word fault /* 10 reserved. */ + .word __gnat_sv_call_trap /* 11 SVCall. */ + .word __gnat_bkpt_trap /* 12 Breakpoint. */ + .word fault /* 13 reserved. */ + .word __gnat_pend_sv_trap /* 14 PendSV. */ + .word __gnat_sys_tick_trap /* 15 Systick. */ + /* MCU interrupts */ + .word __adl_irq_handler /* 0 */ + .word __adl_irq_handler /* 1 */ + .word __adl_irq_handler /* 2 */ + .word __adl_irq_handler /* 3 */ + .word __adl_irq_handler /* 4 */ + .word __adl_irq_handler /* 5 */ + .word __adl_irq_handler /* 6 */ + .word __adl_irq_handler /* 7 */ + .word __adl_irq_handler /* 8 */ + .word __adl_irq_handler /* 9 */ + .word __adl_irq_handler /* 10 */ + .word __adl_irq_handler /* 11 */ + .word __adl_irq_handler /* 12 */ + .word __adl_irq_handler /* 13 */ + .word __adl_irq_handler /* 14 */ + .word __adl_irq_handler /* 15 */ + .word __adl_irq_handler /* 16 */ + .word __adl_irq_handler /* 17 */ + .word __adl_irq_handler /* 18 */ + .word __adl_irq_handler /* 19 */ + .word __adl_irq_handler /* 20 */ + .word __adl_irq_handler /* 21 */ + .word __adl_irq_handler /* 22 */ + .word __adl_irq_handler /* 23 */ + .word __adl_irq_handler /* 24 */ + .word __adl_irq_handler /* 25 */ + .word __adl_irq_handler /* 26 */ + .word __adl_irq_handler /* 27 */ + .word __adl_irq_handler /* 28 */ + .word __adl_irq_handler /* 29 */ + .word __adl_irq_handler /* 30 */ + .word __adl_irq_handler /* 31 */ + .word __adl_irq_handler /* 32 */ + .word __adl_irq_handler /* 33 */ + .word __adl_irq_handler /* 34 */ + .word __adl_irq_handler /* 35 */ + .word __adl_irq_handler /* 36 */ + .word __adl_irq_handler /* 37 */ + .word __adl_irq_handler /* 38 */ + .word __adl_irq_handler /* 39 */ + .word __adl_irq_handler /* 40 */ + .word __adl_irq_handler /* 41 */ + .word __adl_irq_handler /* 42 */ + .word __adl_irq_handler /* 43 */ + .word __adl_irq_handler /* 44 */ + .word __adl_irq_handler /* 45 */ + .word __adl_irq_handler /* 46 */ + .word __adl_irq_handler /* 47 */ + .word __adl_irq_handler /* 48 */ + .word __adl_irq_handler /* 49 */ + .word __adl_irq_handler /* 50 */ + .word __adl_irq_handler /* 51 */ + .word __adl_irq_handler /* 52 */ + .word __adl_irq_handler /* 53 */ + .word __adl_irq_handler /* 54 */ + .word __adl_irq_handler /* 55 */ + .word __adl_irq_handler /* 56 */ + .word __adl_irq_handler /* 57 */ + .word __adl_irq_handler /* 58 */ + .word __adl_irq_handler /* 59 */ + .word __adl_irq_handler /* 60 */ + .word __adl_irq_handler /* 61 */ + .word __adl_irq_handler /* 62 */ + .word __adl_irq_handler /* 63 */ + .word __adl_irq_handler /* 64 */ + .word __adl_irq_handler /* 65 */ + .word __adl_irq_handler /* 66 */ + .word __adl_irq_handler /* 67 */ + .word __adl_irq_handler /* 68 */ + .word __adl_irq_handler /* 69 */ + .word __adl_irq_handler /* 70 */ + .word __adl_irq_handler /* 71 */ + .word __adl_irq_handler /* 72 */ + .word __adl_irq_handler /* 73 */ + .word __adl_irq_handler /* 74 */ + .word __adl_irq_handler /* 75 */ + .word __adl_irq_handler /* 76 */ + .word __adl_irq_handler /* 77 */ + .word __adl_irq_handler /* 78 */ + .word __adl_irq_handler /* 79 */ + .word __adl_irq_handler /* 80 */ + .word __adl_irq_handler /* 81 */ + .word __adl_irq_handler /* 82 */ + .word __adl_irq_handler /* 83 */ + .word __adl_irq_handler /* 84 */ + .word __adl_irq_handler /* 85 */ + .word __adl_irq_handler /* 86 */ + .word __adl_irq_handler /* 87 */ + .word __adl_irq_handler /* 88 */ + .word __adl_irq_handler /* 89 */ + .word __adl_irq_handler /* 90 */ + .word __adl_irq_handler /* 91 */ + .word __adl_irq_handler /* 92 */ + .word __adl_irq_handler /* 93 */ + .word __adl_irq_handler /* 94 */ + .word __adl_irq_handler /* 95 */ + .word __adl_irq_handler /* 96 */ + .word __adl_irq_handler /* 97 */ + .word __adl_irq_handler /* 98 */ + .word __adl_irq_handler /* 99 */ + .word __adl_irq_handler /* 100 */ + .word __adl_irq_handler /* 101 */ + .word __adl_irq_handler /* 102 */ + .word __adl_irq_handler /* 103 */ + .word __adl_irq_handler /* 104 */ + .word __adl_irq_handler /* 105 */ + .word __adl_irq_handler /* 106 */ + .word __adl_irq_handler /* 107 */ + .word __adl_irq_handler /* 108 */ + .word __adl_irq_handler /* 109 */ + .word __adl_irq_handler /* 110 */ + .word __adl_irq_handler /* 111 */ + .word __adl_irq_handler /* 112 */ + .word __adl_irq_handler /* 113 */ + .word __adl_irq_handler /* 114 */ + .word __adl_irq_handler /* 115 */ + .word __adl_irq_handler /* 116 */ + .word __adl_irq_handler /* 117 */ + .word __adl_irq_handler /* 118 */ + .word __adl_irq_handler /* 119 */ + .word __adl_irq_handler /* 120 */ + .word __adl_irq_handler /* 121 */ + .word __adl_irq_handler /* 122 */ + .word __adl_irq_handler /* 123 */ + .word __adl_irq_handler /* 124 */ + .word __adl_irq_handler /* 125 */ + .word __adl_irq_handler /* 126 */ + .word __adl_irq_handler /* 127 */ + + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + .weak __adl_irq_handler + .thumb_set __adl_irq_handler,__gnat_irq_trap + + .text + + .weak __unknown_interrupt_handler + .thumb_set __unknown_interrupt_handler,__gnat_irq_trap + + .thumb_func +.weak __gnat_irq_trap +.type __gnat_irq_trap, %function +__gnat_irq_trap: +0: b 0b + .size __gnat_irq_trap, . - __gnat_irq_trap + + .thumb_func +.weak __gnat_sv_call_trap +.type __gnat_sv_call_trap, %function +__gnat_sv_call_trap: +0: b 0b + .size __gnat_sv_call_trap, . - __gnat_sv_call_trap + + .thumb_func +.weak __gnat_pend_sv_trap +.type __gnat_pend_sv_trap, %function +__gnat_pend_sv_trap: +0: b 0b + .size __gnat_pend_sv_trap, . - __gnat_pend_sv_trap + + .thumb_func +.weak __gnat_sys_tick_trap +.type __gnat_sys_tick_trap, %function +__gnat_sys_tick_trap: +0: b 0b + .size __gnat_sys_tick_trap, . - __gnat_sys_tick_trap + + .thumb_func +fault: b fault + + + .text + .thumb_func + .globl _start + +_start: + + /* Set the stack pointer */ + ldr r1,=__stack_end + mov sp, r1 + + /* Copy .data */ + .thumb_func +_startup_copy_data: + ldr r0,=__data_start + ldr r1,=__data_words + ldr r2,=__data_load + cmp r1,#0 + beq 1f +0: ldr r4,[r2] + str r4,[r0] + adds r2,#4 + adds r0,#4 + subs r1,r1,#1 + bne 0b +1: + .size _startup_copy_data, . - _startup_copy_data + + /* Clear .bss */ + .thumb_func +_startup_clear_bss: + ldr r0,=__bss_start + ldr r1,=__bss_words + movs r2,#0 + cmp r1,#0 + beq 1f +0: str r2,[r0] + adds r0,#4 + subs r1,r1,#1 + bne 0b +1: + .size _startup_clear_bss, . - _startup_clear_bss + + bl main + + bl _exit + +hang: b . diff --git a/boards/NRF52_DK/src/zfp/link.ld b/boards/NRF52_DK/src/zfp/link.ld new file mode 100644 index 000000000..e8f9bdef3 --- /dev/null +++ b/boards/NRF52_DK/src/zfp/link.ld @@ -0,0 +1,119 @@ + + +/* This is a ARM specific version of this file */ + +/* This script replaces ld's default linker script, providing the + appropriate memory map and output format. */ + +SEARCH_DIR(.) +__DYNAMIC = 0; + +_DEFAULT_STACK_SIZE = 2048; + +ENTRY(_start); + +MEMORY +{ + flash (rx) : ORIGIN = 0x0, LENGTH = 0x80000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x10000 +} + +/* + * Boot memory (.text, .ro_data, interrupt vector): flash + * Main RAM memory (.data, .bss, stacks, interrupt stacks): flash + */ + +SECTIONS +{ + + .text : + { + KEEP (*(.vectors)) + *(.text .text.* .gnu.linkonce.t*) + *(.gnu.warning) + } > flash + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > flash + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > flash + PROVIDE_HIDDEN (__exidx_end = .); + + .rodata : + { + *(.lit) + *(.rodata .rodata.* .gnu.linkonce.r*) + . = ALIGN(0x4); + __rom_end = .; + } > flash + + __data_load = LOADADDR(.data); + .data : + { + __data_start = .; + *(.data .data.* .gnu.linkonce.d*) + + /* Ensure that the end of the data section is always word aligned. + Initial values are stored in 4-bytes blocks so we must guarantee + that these blocks do not fall out the section (otherwise they are + truncated and the initial data for the last block are lost). */ + + . = ALIGN(0x4); + __data_end = .; + } > ram AT> flash + __data_words = (__data_end - __data_start) >> 2; + + + + .bss (NOLOAD): { + . = ALIGN(0x8); + __bss_start = .; + + *(.bss .bss.*) + *(COMMON) + + . = ALIGN(0x8); /* Align the stack to 64 bits */ + __bss_end = .; + + __interrupt_stack_start = .; + *(.interrupt_stacks) + . = ALIGN(0x8); + __interrupt_stack_end = .; + + __stack_start = .; + . += DEFINED (__stack_size) ? __stack_size : _DEFAULT_STACK_SIZE; + . = ALIGN(0x8); + __stack_end = .; + + _end = .; + __heap_start = .; + __heap_end = ORIGIN(ram) + LENGTH(ram); + } > ram + __bss_words = (__bss_end - __bss_start) >> 2; + + + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* DWARF 3 */ + .debug_pubtypes 0 : { *(.debug_pubtypes) } + .debug_ranges 0 : { *(.debug_ranges) } + .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) } + /DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) } +} \ No newline at end of file diff --git a/boards/board_projects_generator.py b/boards/board_projects_generator.py index 801d24621..377746dbe 100755 --- a/boards/board_projects_generator.py +++ b/boards/board_projects_generator.py @@ -8,6 +8,7 @@ 'HiFive1': { 'rts_profiles': ['zfp']}, 'Unleashed': { 'rts_profiles': ['zfp', 'ravenscar-sfp', 'ravenscar-full']}, 'MicroBit': { 'rts_profiles': ['zfp']}, + 'NRF52_DK': { 'rts_profiles': ['zfp']}, 'Native': { 'rts_profiles': ['none']}, 'OpenMV2': { 'rts_profiles': ['ravenscar-sfp', 'ravenscar-full']}, 'STM32F407_Discovery': { 'rts_profiles': ['ravenscar-sfp', 'ravenscar-full']}, @@ -24,6 +25,7 @@ 'HiFive1': 'HiFive1', 'Unleashed': 'Unleashed', 'MicroBit': 'MicroBit', + 'NRF52_DK': 'NRF52_DK', 'Native': 'native', 'OpenMV2': 'OpenMV2', 'STM32F407_Discovery': 'stm32f407_discovery', @@ -34,7 +36,7 @@ 'NUCLEO_F446ZE': 'nucleo_f446ze', 'Feather_STM32F405': 'feather_stm32f405'} -USE_STARTUP_GEN = ['HiFive1', 'MicroBit'] +USE_STARTUP_GEN = ['HiFive1', 'MicroBit', 'NRF52_DK'] def gen_project(board_name, rts): assert board_name is not None, "board is undefined" diff --git a/examples/MicroBit/BLE_beacon/src/beacon.adb b/examples/MicroBit/BLE_beacon/src/beacon.adb index add1eddf5..fd6b331f4 100644 --- a/examples/MicroBit/BLE_beacon/src/beacon.adb +++ b/examples/MicroBit/BLE_beacon/src/beacon.adb @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------ -- -- --- Copyright (C) 2016, AdaCore -- +-- Copyright (C) 2016-2020, AdaCore -- -- -- -- Redistribution and use in source and binary forms, with or without -- -- modification, are permitted provided that the following conditions are -- @@ -29,10 +29,10 @@ -- -- ------------------------------------------------------------------------------ -with nRF51.Tasks; -with nRF51.Events; -with nRF51.Radio; use nRF51.Radio; -with nRF51.Clock; use nRF51.Clock; +with nRF.Tasks; +with nRF.Events; +with nRF.Radio; use nRF.Radio; +with nRF.Clock; use nRF.Clock; with Bluetooth_Low_Energy.Packets; use Bluetooth_Low_Energy.Packets; with Bluetooth_Low_Energy; use Bluetooth_Low_Energy; @@ -116,16 +116,16 @@ package body Beacon is Set_Packet (Memory_Address (Beacon_Packet)); -- Clear all events - nRF51.Events.Clear (nRF51.Events.Radio_DISABLED); - nRF51.Events.Clear (nRF51.Events.Radio_ADDRESS); - nRF51.Events.Clear (nRF51.Events.Radio_PAYLOAD); - nRF51.Events.Clear (nRF51.Events.Radio_END); + nRF.Events.Clear (nRF.Events.Radio_DISABLED); + nRF.Events.Clear (nRF.Events.Radio_ADDRESS); + nRF.Events.Clear (nRF.Events.Radio_PAYLOAD); + nRF.Events.Clear (nRF.Events.Radio_END); -- Start transmission - nRF51.Tasks.Trigger (nRF51.Tasks.Radio_TXEN); + nRF.Tasks.Trigger (nRF.Tasks.Radio_TXEN); -- Wait for end of transmission - while not nRF51.Events.Triggered (nRF51.Events.Radio_DISABLED) loop + while not nRF.Events.Triggered (nRF.Events.Radio_DISABLED) loop null; end loop; end Send_Beacon_Packet; diff --git a/examples/NRF52_DK/BLE_beacon/BLE_beacon.gpr b/examples/NRF52_DK/BLE_beacon/BLE_beacon.gpr new file mode 100644 index 000000000..1291f6112 --- /dev/null +++ b/examples/NRF52_DK/BLE_beacon/BLE_beacon.gpr @@ -0,0 +1,28 @@ +with "../../../boards/NRF52_DK/nrf52_dk_zfp.gpr"; + +project BLE_Beacon is + + for Runtime ("ada") use NRF52_DK_ZFP'Runtime ("Ada"); + for Target use "arm-eabi"; + for Main use ("main.adb"); + for Languages use ("Ada"); + for Source_Dirs use ("src"); + for Object_Dir use "obj"; + for Create_Missing_Dirs use "True"; + + package Compiler renames NRF52_DK_ZFP.Compiler; + + package Linker is + for Default_Switches ("Ada") use + NRF52_DK_ZFP.Linker_Switches & + ("-Wl,--print-memory-usage", + "-Wl,--gc-sections"); + end Linker; + + package Ide is + for Program_Host use ":1234"; + for Communication_Protocol use "remote"; + for Connection_Tool use "pyocd"; + end Ide; + +end BLE_Beacon; diff --git a/examples/NRF52_DK/BLE_beacon/src/beacon.adb b/examples/NRF52_DK/BLE_beacon/src/beacon.adb new file mode 100644 index 000000000..fd6b331f4 --- /dev/null +++ b/examples/NRF52_DK/BLE_beacon/src/beacon.adb @@ -0,0 +1,133 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright (C) 2016-2020, AdaCore -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of the copyright holder nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +------------------------------------------------------------------------------ + +with nRF.Tasks; +with nRF.Events; +with nRF.Radio; use nRF.Radio; +with nRF.Clock; use nRF.Clock; + +with Bluetooth_Low_Energy.Packets; use Bluetooth_Low_Energy.Packets; +with Bluetooth_Low_Energy; use Bluetooth_Low_Energy; +with Bluetooth_Low_Energy.Beacon; use Bluetooth_Low_Energy.Beacon; + +with HAL; use HAL; + +package body Beacon is + + Current_Adv_Channel : BLE_Advertising_Channel_Number := 37; + Beacon_Packet : BLE_Packet; + + ---------------------- + -- Initialize_Radio -- + ---------------------- + + procedure Initialize_Radio is + Beacon_UUID : constant BLE_UUID := + Make_UUID ((1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)); + begin + + Beacon_Packet := Make_Beacon_Packet + (MAC => (16#A1#, 16#AD#, 16#A1#, 16#AD#, 16#A1#, 16#AD#), + UUID => Beacon_UUID, + Major => 0, + Minor => 0, + Power => 0); + + -- Setup high frequency clock for BLE transmission + Set_High_Freq_Source (HFCLK_RC); + Start_High_Freq; + while not High_Freq_Running loop + null; + end loop; + + -- Setup radio module for BLE + Setup_For_Bluetooth_Low_Energy; + + -- Set BLE advertising address + Set_Logic_Addresses (Base0 => 16#89_BE_D6_00#, + Base1 => 16#00_00_00_00#, + Base_Length_In_Byte => 3, + AP0 => 16#8E#, + AP1 => 16#00#, + AP2 => 16#00#, + AP3 => 16#00#, + AP4 => 16#00#, + AP5 => 16#00#, + AP6 => 16#00#, + AP7 => 16#00#); + + -- Select logic address + Set_TX_Address (0); + + -- Transmission power + Set_Power (Zero_Dbm); + + -- Enable shortcuts for easier radio operation + Enable_Shortcut (Ready_To_Start); + Enable_Shortcut (End_To_Disable); + end Initialize_Radio; + + ------------------------ + -- Send_Beacon_Packet -- + ------------------------ + + procedure Send_Beacon_Packet is + begin + Configure_Whitening (True, UInt6 (Current_Adv_Channel)); + + Set_Frequency + (Radio_Frequency_MHz (Channel_Frequency (Current_Adv_Channel))); + + if Current_Adv_Channel /= BLE_Advertising_Channel_Number'Last then + Current_Adv_Channel := Current_Adv_Channel + 1; + else + Current_Adv_Channel := BLE_Advertising_Channel_Number'First; + end if; + + -- Set TX packet address + Set_Packet (Memory_Address (Beacon_Packet)); + + -- Clear all events + nRF.Events.Clear (nRF.Events.Radio_DISABLED); + nRF.Events.Clear (nRF.Events.Radio_ADDRESS); + nRF.Events.Clear (nRF.Events.Radio_PAYLOAD); + nRF.Events.Clear (nRF.Events.Radio_END); + + -- Start transmission + nRF.Tasks.Trigger (nRF.Tasks.Radio_TXEN); + + -- Wait for end of transmission + while not nRF.Events.Triggered (nRF.Events.Radio_DISABLED) loop + null; + end loop; + end Send_Beacon_Packet; + +end Beacon; diff --git a/examples/NRF52_DK/BLE_beacon/src/beacon.ads b/examples/NRF52_DK/BLE_beacon/src/beacon.ads new file mode 100644 index 000000000..26f6d9940 --- /dev/null +++ b/examples/NRF52_DK/BLE_beacon/src/beacon.ads @@ -0,0 +1,35 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright (C) 2016-2020, AdaCore -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of the copyright holder nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +------------------------------------------------------------------------------ + +package Beacon is + procedure Initialize_Radio; + procedure Send_Beacon_Packet; +end Beacon; diff --git a/examples/NRF52_DK/BLE_beacon/src/main.adb b/examples/NRF52_DK/BLE_beacon/src/main.adb new file mode 100644 index 000000000..a981680c9 --- /dev/null +++ b/examples/NRF52_DK/BLE_beacon/src/main.adb @@ -0,0 +1,48 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright (C) 2016-2020, AdaCore -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of the copyright holder nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +------------------------------------------------------------------------------ + +with NRF52_DK.Time; +with NRF52_DK.LEDs; use NRF52_DK.LEDs; +with Beacon; + +procedure Main is +begin + Initialize_LEDs; + Beacon.Initialize_Radio; + + loop + Turn_On (LED1); + Beacon.Send_Beacon_Packet; + Turn_Off (LED1); + NRF52_DK.Time.Delay_Ms (500); + end loop; +end Main; + diff --git a/examples/NRF52_DK/README.md b/examples/NRF52_DK/README.md new file mode 100644 index 000000000..c63ddb5bd --- /dev/null +++ b/examples/NRF52_DK/README.md @@ -0,0 +1,45 @@ +The nRF52 Development Kit is a board designed by Nordic Semiconductor to evaluate +the nRF52832 chip. This chip has an Arm Cortex-M4F core and an integrated multi- +protocol 2.4GHz radio. You can get it for most large distributors including: + + - [Digikey (US)](https://www.digikey.com/en/products/detail/nordic-semiconductor-asa/nrf52-dk/5773879) + - [Digikey (CA)](https://www.digikey.ca/en/products/detail/nordic-semiconductor-asa/nrf52-dk/5773879) + - [Farnell (UK/EU)](https://uk.farnell.com/nordic-semiconductor/nrf52-dk/dev-kit-bluetooth-low-energy-soc/dp/2842319) + +# How to setup the Ada development environment for the Micro:Bit + +GNAT Community now comes with nRF52 support built-in. So you only +need to download the ARM ELF and the native package from +[here](https://www.adacore.com/download) + +## pyOCD programmer + +The nRF52 DK comes with a Segger J-Link embedded +programming/debugging. You can use the J-Link tools to program the board. + +A better option is a build of the +[DAPLink](https://github.com/ARMmbed/DAPLink) firmware implementing +[CMSIS-DAP](https://docs.mbed.com/docs/mbed-os-handbook/en/latest/advanced/DAP/) +protocol defined by ARM that can be written over the JLink firmware. + +The binary and the instructions for programing the firmware over USB +can be found on the [DAPLink release +site](https://armmbed.github.io/DAPLink/) by searching for `Nordic-nRF52-DK` + +## Open one of example projects and build it + +Start GNAT Programming studio (GPS) and open the micro:bit example project: + + - [Buttons](buttons/) + - [Digital Output](digital_out/) + - [BLE beacon](BLE_beacon/) + +Press F4 and then press Enter to build the project. + +## Program the board + +In the GPS toolbar, click on the "flash to board" button to program the +nRF52 DK. + +After a few seconds, you should be able to interact with the example +application as specified in the project's README.md file. diff --git a/examples/NRF52_DK/buttons/README.md b/examples/NRF52_DK/buttons/README.md new file mode 100644 index 000000000..7885288c9 --- /dev/null +++ b/examples/NRF52_DK/buttons/README.md @@ -0,0 +1,64 @@ +Buttons Example +=============== + +In this example we will see how to use the four buttons of the nRF52 Development Kit. + +Code +==== + +To know if a button is pressed or not, we will use the procedure `State` of the +`NRF52_DK.Buttons` package. + +```ada + type Button_State is (Pressed, Released); + + type Button_Id is (Button_1, Button_2, Button_3, Button_4); + + function State (Button : Button_Id) return Button_State; +``` + +Arguments: + + - Button : The Id of the button that we want to check. There are four Ids: + `Button_1`, `Button_2`, `Button_3`, and `Button_4` which correspond + to the silkscreen on the board. + +Return value: + +The procedure `State` return the `Button_State` that can be either `Pressed` or +`Released`. + +Here is the code: +```ada +with NRF52_DK.Buttons; use NRF52_DK.Buttons; +with NRF52_DK.LEDs; use NRF52_DK.LEDs; +with NRF52_DK.Time; + +procedure Main is +begin + Initialize_LEDs; + loop + Turn_Off (LED1); + Turn_Off (LED2); + Turn_Off (LED3); + Turn_Off (LED4); + if NRF52_DK.Buttons.State (Button_1) = Pressed then + Turn_On (LED1); + end if; + + if NRF52_DK.Buttons.State (Button_2) = Pressed then + Turn_On (LED2); + end if; + + if NRF52_DK.Buttons.State (Button_3) = Pressed then + Turn_On (LED3); + end if; + + if NRF52_DK.Buttons.State (Button_4) = Pressed then + Turn_On (LED4); + end if; + + NRF52_DK.Time.Delay_Ms (200); + end loop; +end Main; +``` diff --git a/examples/NRF52_DK/buttons/buttons.gpr b/examples/NRF52_DK/buttons/buttons.gpr new file mode 100644 index 000000000..dd82cddac --- /dev/null +++ b/examples/NRF52_DK/buttons/buttons.gpr @@ -0,0 +1,28 @@ +with "../../../boards/NRF52_DK/nrf52_dk_zfp.gpr"; + +project Buttons is + + for Runtime ("ada") use NRF52_DK_ZFP'Runtime ("Ada"); + for Target use "arm-eabi"; + for Main use ("main.adb"); + for Languages use ("Ada"); + for Source_Dirs use ("src"); + for Object_Dir use "obj"; + for Create_Missing_Dirs use "True"; + + package Compiler renames NRF52_DK_ZFP.Compiler; + + package Linker is + for Default_Switches ("Ada") use + NRF52_DK_ZFP.Linker_Switches & + ("-Wl,--print-memory-usage", + "-Wl,--gc-sections"); + end Linker; + + package Ide is + for Program_Host use ":1234"; + for Communication_Protocol use "remote"; + for Connection_Tool use "pyocd"; + end Ide; + +end Buttons; diff --git a/examples/NRF52_DK/buttons/src/main.adb b/examples/NRF52_DK/buttons/src/main.adb new file mode 100644 index 000000000..1dcaec966 --- /dev/null +++ b/examples/NRF52_DK/buttons/src/main.adb @@ -0,0 +1,64 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright © AdaCore and other contributors, 2018-2020 -- +-- See https://github.com/AdaCore/Ada_Drivers_Library/graphs/contributors -- +-- for more information -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of the copyright holder nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +------------------------------------------------------------------------------ + +with NRF52_DK.Buttons; use NRF52_DK.Buttons; +with NRF52_DK.LEDs; use NRF52_DK.LEDs; +with NRF52_DK.Time; + +procedure Main is +begin + Initialize_LEDs; + loop + Turn_Off (LED1); + Turn_Off (LED2); + Turn_Off (LED3); + Turn_Off (LED4); + if NRF52_DK.Buttons.State (Button_1) = Pressed then + Turn_On (LED1); + end if; + + if NRF52_DK.Buttons.State (Button_2) = Pressed then + Turn_On (LED2); + end if; + + if NRF52_DK.Buttons.State (Button_3) = Pressed then + Turn_On (LED3); + end if; + + if NRF52_DK.Buttons.State (Button_4) = Pressed then + Turn_On (LED4); + end if; + + NRF52_DK.Time.Delay_Ms (200); + end loop; +end Main; diff --git a/examples/NRF52_DK/digital_out/README.md b/examples/NRF52_DK/digital_out/README.md new file mode 100644 index 000000000..94337bf8d --- /dev/null +++ b/examples/NRF52_DK/digital_out/README.md @@ -0,0 +1,56 @@ +Digital Output Example +====================== + +In this example we will see how to control a pin as digital output by flashing +an on-board LED. This means that the voltage on the pin connected to the LED +will be either 0 volts or 3.3 volts. + +Code +==== + +To control the IO pin we are going to use the procedure `Set` of the package +`NRF52_DK.IOs`. + +```ada + procedure Set (Pin : Pin_Id; Value : Boolean) + with Pre => Supports (Pin, Digital); +``` + +Arguments: + + - Pin : The id of the pin that we want to control as digital output + - Value : A boolean that says if we want the pin to be high (True) or low + (False) + +Precondition: + +The procedure `Set` has a precondition that the pin must support digital IO. + +We also use the procedure `Delay_Ms` of the package `NRF52_DK.Time` to stop the +program for a short amount of time. + +Here is the code: +```ada +with NRF52_DK.IOs; +with NRF52_DK.Time; + +procedure Main is +begin + + -- Loop forever + loop + -- Turn on the LED connected to pin 17 + NRF52_DK.IOs.Set (17, True); + + -- Wait 500 milliseconds + NRF52_DK.Time.Delay_Ms (500); + + -- Turn off the LED connected to pin 17 + NRF52_DK.IOs.Set (17, False); + + -- Wait 500 milliseconds + NRF52_DK.Time.Delay_Ms (500); + end loop; +end Main; + +``` diff --git a/examples/NRF52_DK/digital_out/digital_out.gpr b/examples/NRF52_DK/digital_out/digital_out.gpr new file mode 100644 index 000000000..0c34dc184 --- /dev/null +++ b/examples/NRF52_DK/digital_out/digital_out.gpr @@ -0,0 +1,28 @@ +with "../../../boards/NRF52_DK/nrf52_dk_zfp.gpr"; + +project Digital_Out is + + for Runtime ("ada") use NRF52_DK_ZFP'Runtime ("Ada"); + for Target use "arm-eabi"; + for Main use ("main.adb"); + for Languages use ("Ada"); + for Source_Dirs use ("src"); + for Object_Dir use "obj"; + for Create_Missing_Dirs use "True"; + + package Compiler renames NRF52_DK_ZFP.Compiler; + + package Linker is + for Default_Switches ("Ada") use + NRF52_DK_ZFP.Linker_Switches & + ("-Wl,--print-memory-usage", + "-Wl,--gc-sections"); + end Linker; + + package Ide is + for Program_Host use ":1234"; + for Communication_Protocol use "remote"; + for Connection_Tool use "pyocd"; + end Ide; + +end Digital_Out; diff --git a/examples/NRF52_DK/digital_out/src/main.adb b/examples/NRF52_DK/digital_out/src/main.adb new file mode 100644 index 000000000..b170e844c --- /dev/null +++ b/examples/NRF52_DK/digital_out/src/main.adb @@ -0,0 +1,52 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright (C) 2018-2020, AdaCore -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of the copyright holder nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +------------------------------------------------------------------------------ + +with NRF52_DK.IOs; +with NRF52_DK.Time; + +procedure Main is +begin + + -- Loop forever + loop + -- Turn on the LED connected to pin 17 + NRF52_DK.IOs.Set (17, True); + + -- Wait 500 milliseconds + NRF52_DK.Time.Delay_Ms (500); + + -- Turn off the LED connected to pin 17 + NRF52_DK.IOs.Set (17, False); + + -- Wait 500 milliseconds + NRF52_DK.Time.Delay_Ms (500); + end loop; +end Main; diff --git a/scripts/build_all_examples.py b/scripts/build_all_examples.py index 6a10e52ef..58d7b3fe5 100755 --- a/scripts/build_all_examples.py +++ b/scripts/build_all_examples.py @@ -139,6 +139,12 @@ def gprbuild(project_file, debug=False): "/examples/MicroBit/follower/follower.gpr", "/examples/MicroBit/accelerometer/accelerometer.gpr", + # NRF52_SDK + "/boards/NRF52_DK/nrf52_dk_zfp.gpr", + "/examples/NRF52_DK/buttons/buttons.gpr", + "/examples/NRF52_DK/BLE_beacon/BLE_beacon.gpr", + "/examples/NRF52_DK/digital_out/digital_out.gpr", + # STM32 driver examples STM_DRIVERS + "/demo_adc_dma/demo_adc_dma.gpr", STM_DRIVERS + "/demo_adc_interrupts/demo_adc_interrupts.gpr", diff --git a/scripts/config/boards.py b/scripts/config/boards.py index 8a2d533c5..f38c2ed94 100644 --- a/scripts/config/boards.py +++ b/scripts/config/boards.py @@ -13,6 +13,7 @@ def list_of_boards(): 'Feather_STM32F405', 'OpenMV2', "MicroBit", + "NRF52_DK", "HiFive1", "Unleashed", 'Native'] @@ -157,6 +158,17 @@ def load_board_config(config): config.pre_define('Runtime_Name_Suffix', 'cortex-m0', origin) config.add_source_dir('boards/MicroBit/src/', origin) + elif board == "NRF52_DK": + config.pre_define('Architecture', 'ARM', origin) + config.pre_define('Vendor', 'Nordic', origin) + config.pre_define('Device_Family', 'nRF52', origin) + config.pre_define('Device_Name', 'nRF52832xxAA', origin) + config.pre_define('Has_ZFP_Runtime', 'True', origin) + config.pre_define('Has_Ravenscar_SFP_Runtime', 'False', origin) + config.pre_define('Has_Ravenscar_Full_Runtime', 'False', origin) + config.pre_define('Runtime_Name_Suffix', 'cortex-m4f', origin) + config.add_source_dir('boards/NRF52_DK/src/', origin) + elif board == "HiFive1": config.pre_define('Architecture', 'RISC-V', origin) config.pre_define('Vendor', 'SiFive', origin) diff --git a/scripts/config/devices.py b/scripts/config/devices.py index 7ccb2dd29..01c9f446e 100644 --- a/scripts/config/devices.py +++ b/scripts/config/devices.py @@ -33,6 +33,8 @@ def list_of_devices(config): 'STM32F769NIHx'] elif family == "nRF51": return ['nRF51822xxAA'] + elif family == "nRF52": + return ['nRF52832xxAA'] elif family == "FE3": return ['FE310'] elif family == "U5": @@ -60,7 +62,7 @@ def list_of_families(config): if vendor == "STMicro": return ["STM32F4", "STM32F7"] elif vendor == "Nordic": - return ["nRF51"] + return ["nRF51", "nRF52"] elif vendor == "SiFive": return ['FE3', 'U5'] else: @@ -168,8 +170,9 @@ def load_device_config(config, source_dir): 'arch/ARM/STM32/drivers/sd/sdmmc/'] elif mcu.startswith('nRF51'): - src += ['arch/ARM/Nordic/devices/', - 'arch/ARM/Nordic/drivers/', + src += ['arch/ARM/Nordic/devices/nrf51', + 'arch/ARM/Nordic/drivers/nrf_common', + 'arch/ARM/Nordic/drivers/nrf51', 'arch/ARM/Nordic/svd/nrf51/'] config.pre_define('Number_Of_Interrupts', 32, origin) @@ -185,6 +188,17 @@ def load_device_config(config, source_dir): else: config.add_memory('ram', 'ram', '0x20000000', '16K') + elif mcu.startswith('nRF52'): + src += ['arch/ARM/Nordic/devices/nrf52', + 'arch/ARM/Nordic/drivers/nrf_common', + 'arch/ARM/Nordic/drivers/nrf52', + 'arch/ARM/Nordic/svd/nrf52/'] + + config.pre_define('Number_Of_Interrupts', 128, origin) + + config.add_memory('rom', 'flash', '0x00000000', '512K') + config.add_memory('ram', 'ram', '0x20000000', '64K') + elif mcu == 'FE310': src += ['arch/RISC-V/SiFive/svd/FE310/', 'arch/RISC-V/SiFive/devices/FE310/', diff --git a/scripts/project_wizard.py b/scripts/project_wizard.py index c65e707f9..0ddae7330 100755 --- a/scripts/project_wizard.py +++ b/scripts/project_wizard.py @@ -48,6 +48,8 @@ def mcu_config(config, source_dir): core = "ARM Cortex-M7F" elif device.startswith("nRF51"): core = "ARM Cortex-M0" + elif device.startswith("nRF52"): + core = "ARM Cortex-M4F" elif device.startswith("FE3"): core = "RISC-V32" elif device.startswith("U5"):