2121#define DMA_MAX_TRANSFER_COUNT 1024
2222#define DMA_CH_PRIORITY_HIGH 1
2323#define DMA_CH_PRIORITY_LOW 0
24- #define VALID_BURST_LENGTH 0
2524#define UDMA_ADDR_INC_NONE 0x03
2625
2726LOG_MODULE_REGISTER (si91x_dma , CONFIG_DMA_LOG_LEVEL );
2827
28+ enum {
29+ TRANSFER_MEM_TO_MEM ,
30+ TRANSFER_TO_OR_FROM_PER ,
31+ };
32+
2933struct dma_siwx91x_config {
3034 UDMA0_Type * reg ; /* UDMA register base address */
3135 uint8_t channels ; /* UDMA channel count */
@@ -45,17 +49,17 @@ struct dma_siwx91x_data {
4549 */
4650};
4751
48- static int siwx91x_is_peripheral_request (uint32_t dir )
52+ static int siwx91x_transfer_direction (uint32_t dir )
4953{
5054 if (dir == MEMORY_TO_MEMORY ) {
51- return 0 ;
55+ return TRANSFER_MEM_TO_MEM ;
5256 }
5357
5458 if (dir == MEMORY_TO_PERIPHERAL || dir == PERIPHERAL_TO_MEMORY ) {
55- return 1 ;
59+ return TRANSFER_TO_OR_FROM_PER ;
5660 }
5761
58- return -1 ;
62+ return - EINVAL ;
5963}
6064
6165static int siwx91x_data_width (uint32_t data_width )
@@ -72,13 +76,13 @@ static int siwx91x_data_width(uint32_t data_width)
7276 }
7377}
7478
75- static int siwx91x_burst_length (uint32_t blen )
79+ static bool siwx91x_is_burst_length_valid (uint32_t blen )
7680{
7781 switch (blen / 8 ) {
7882 case 1 :
79- return VALID_BURST_LENGTH ; /* 8-bit burst */
83+ return true ; /* 8-bit burst */
8084 default :
81- return - EINVAL ;
85+ return false ;
8286 }
8387}
8488
@@ -112,12 +116,12 @@ static int siwx91x_channel_config(const struct device *dev, RSI_UDMA_HANDLE_T ud
112116 RSI_UDMA_CHA_CFG_T channel_config = {};
113117 int status ;
114118
115- if (siwx91x_is_peripheral_request (config -> channel_direction ) < 0 ) {
119+ if (siwx91x_transfer_direction (config -> channel_direction ) < 0 ) {
116120 return - EINVAL ;
117121 }
118122
119123 channel_config .channelPrioHigh = config -> channel_priority ;
120- channel_config .periphReq = siwx91x_is_peripheral_request (config -> channel_direction );
124+ channel_config .periphReq = siwx91x_transfer_direction (config -> channel_direction );
121125 channel_config .dmaCh = channel ;
122126
123127 if (channel_config .periphReq ) {
@@ -140,8 +144,8 @@ static int siwx91x_channel_config(const struct device *dev, RSI_UDMA_HANDLE_T ud
140144 siwx91x_data_width (config -> dest_data_size ) < 0 ) {
141145 return - EINVAL ;
142146 }
143- if (siwx91x_burst_length (config -> source_burst_length ) < 0 ||
144- siwx91x_burst_length (config -> dest_burst_length ) < 0 ) {
147+ if (siwx91x_is_burst_length_valid (config -> source_burst_length ) == false ||
148+ siwx91x_is_burst_length_valid (config -> dest_burst_length ) == false ) {
145149 return - EINVAL ;
146150 }
147151
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