[ext] Update modm-devices and STM32 CMSIS headers

Author: salkinium

README.md

@@ -71,7 +71,7 @@ git clone --recurse-submodules https://github.com/modm-io/modm.git
 ## Targets
 
 modm can generate code for <!--avrcount-->506<!--/avrcount-->
-AVR, <!--samcount-->163<!--/samcount--> SAM and <!--stmcount-->2010<!--/stmcount-->
+AVR, <!--samcount-->163<!--/samcount--> SAM and <!--stmcount-->2185<!--/stmcount-->
 STM32 devices, however, there are different levels of support and testing.
 
 <center>

ext/modm-devices

@@ -29,6 +29,31 @@
 #include <{{ header }}>
 %% endfor
 
+%% if target.family in ["g0"]
+// these defines are missing from the STM32G0 header files
+#define RCC_CFGR_SW_HSI (0UL)          /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE (0x00000001UL) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL (0x00000002UL) /*!< PLL selected as system clock */
+#define RCC_CFGR_SW_LSI (0x00000003UL) /*!< LSI selected as system clock */
+#define RCC_CFGR_SW_LSE (0x00000004UL) /*!< LSE selected as system clock */
+
+#define RCC_CFGR_HPRE_DIV1   (0x0UL)        /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2   (0x00000800UL) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4   (0x00000900UL) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8   (0x00000A00UL) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16  (0x00000B00UL) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64  (0x00000C00UL) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 (0x00000D00UL) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 (0x00000E00UL) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 (0x00000F00UL) /*!< SYSCLK divided by 512 */
+
+#define RCC_CFGR_PPRE_DIV1  (0x0UL)        /*!< HCLK not divided */
+#define RCC_CFGR_PPRE_DIV2  (0x00004000UL) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE_DIV4  (0x00005000UL) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE_DIV8  (0x00006000UL) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE_DIV16 (0x00007000UL) /*!< HCLK divided by 16 */
+%% endif
+
 /// @cond
 // This is a hack to make the *_Typedef's known to GDB, so that you can debug
 // the peripherals directly in GDB in any context.

ext/st/device.hpp.in

@@ -152,6 +152,7 @@ def build(env):
     env.substitutions.update({
         "headers": [bprops["device_header"], bprops["system_header"]],
         "defines": [bprops["define"]],
+        "target": env[":target"].identifier,
     })
     env.outbasepath = "modm/src/modm/platform"
     env.template("device.hpp.in")

ext/st/module.lb

@@ -103,3 +103,81 @@ samd21e15c-uf
 samd21e15c-uu
 samd21e16c-uf
 samd21e16c-uu
+# FIXME: Shared IRQs on UART, SPI, I2C
+stm32g0b0cet6
+stm32g0b0ket6
+stm32g0b0ret6
+stm32g0b0vet6
+stm32g0b1cbt6
+stm32g0b1cbt6n
+stm32g0b1cbu6
+stm32g0b1cbu6n
+stm32g0b1cct6
+stm32g0b1cct6n
+stm32g0b1ccu6
+stm32g0b1ccu6n
+stm32g0b1cet6
+stm32g0b1cet6n
+stm32g0b1ceu6
+stm32g0b1ceu6n
+stm32g0b1kbt6
+stm32g0b1kbt6n
+stm32g0b1kbu6
+stm32g0b1kbu6n
+stm32g0b1kct6
+stm32g0b1kct6n
+stm32g0b1kcu6
+stm32g0b1kcu6n
+stm32g0b1ket6
+stm32g0b1ket6n
+stm32g0b1keu6
+stm32g0b1keu6n
+stm32g0b1mbt6
+stm32g0b1mct6
+stm32g0b1met6
+stm32g0b1ney6
+stm32g0b1rbi6n
+stm32g0b1rbt6
+stm32g0b1rbt6n
+stm32g0b1rci6n
+stm32g0b1rct6
+stm32g0b1rct6n
+stm32g0b1rei6n
+stm32g0b1ret6
+stm32g0b1ret6n
+stm32g0b1vbi6
+stm32g0b1vbt6
+stm32g0b1vci6
+stm32g0b1vct6
+stm32g0b1vei6
+stm32g0b1vet6
+stm32g0c1cct6
+stm32g0c1cct6n
+stm32g0c1ccu6
+stm32g0c1ccu6n
+stm32g0c1cet6
+stm32g0c1cet6n
+stm32g0c1ceu6
+stm32g0c1ceu6n
+stm32g0c1kct6
+stm32g0c1kct6n
+stm32g0c1kcu6
+stm32g0c1kcu6n
+stm32g0c1ket6
+stm32g0c1ket6n
+stm32g0c1keu6
+stm32g0c1keu6n
+stm32g0c1mct6
+stm32g0c1met6
+stm32g0c1ney6
+stm32g0c1rci6n
+stm32g0c1rct6
+stm32g0c1rct6n
+stm32g0c1rei6n
+stm32g0c1ret6
+stm32g0c1ret6n
+stm32g0c1vci6
+stm32g0c1vct6
+stm32g0c1vei6
+stm32g0c1vet6
+