Commit 75a1381
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OmpSs-2-at-FPGA release 2.0.0
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- README.md+15-14
- ait/backend/xilinx/HLS/src/Adapter_instr.cpp+1-1
- ait/backend/xilinx/IPs/axis_tid_demux.v-21
- ait/backend/xilinx/IPs/bsc_ompss_addrInterleaver.v+14-37
- ait/backend/xilinx/IPs/bsc_ompss_axis_subset_converter.v+49
- ait/backend/xilinx/IPs/bsc_ompss_axis_tid_demux.v+45
- ait/backend/xilinx/IPs/bsc_ompss_hsToStreamAdapter.v+2-4
- ait/backend/xilinx/IPs/bsc_ompss_hwcounter.v+2-3
- ait/backend/xilinx/IPs/bsc_ompss_picosompssmanager_6.0.zip-3
- ait/backend/xilinx/IPs/bsc_ompss_picosompssmanager_7.1.zip+3
- ait/backend/xilinx/IPs/bsc_ompss_streamToHsAdapter.v+2-4
- ait/backend/xilinx/board/alveo_u200/baseDesign.tcl+432-150
- ait/backend/xilinx/board/alveo_u200/constraints/basic_constraints.xdc+1-1
- ait/backend/xilinx/board/alveo_u200/constraints/static_floorplan.xdc+5-5
- ait/backend/xilinx/board/alveo_u200/staticRegSlices.tcl+6-6
- ait/backend/xilinx/board/alveo_u250/baseDesign.tcl+435-150
- ait/backend/xilinx/board/alveo_u250/constraints/basic_constraints.xdc+1-1
- ait/backend/xilinx/board/alveo_u280/baseDesign.tcl+936
- ait/backend/xilinx/board/alveo_u280/basic_info.json+26
- ait/backend/xilinx/board/alveo_u280/constraints/basic_constraints.xdc+11
- ait/backend/xilinx/board/alveo_u280/constraints/bitstream.xdc+12
- ait/backend/xilinx/board/alveo_u280/constraints/ports.xdc+18
- ait/backend/xilinx/board/alveo_u280_hbm/baseDesign.tcl+892
- ait/backend/xilinx/board/alveo_u280_hbm/basic_info.json+26
- ait/backend/xilinx/board/alveo_u280_hbm/constraints/basic_constraints.xdc+11
- ait/backend/xilinx/board/alveo_u280_hbm/constraints/bitstream.xdc+12
- ait/backend/xilinx/board/alveo_u280_hbm/constraints/ports.xdc+18
- ait/backend/xilinx/board/alveo_u55c/baseDesign.tcl+885
- ait/backend/xilinx/board/alveo_u55c/basic_info.json+26
- ait/backend/xilinx/board/alveo_u55c/constraints/basic_constraints.xdc+11
- ait/backend/xilinx/board/alveo_u55c/constraints/create_pblocks.xdc+14
- ait/backend/xilinx/board/alveo_u55c/constraints/ports.xdc+24
- ait/backend/xilinx/board/axiom/baseDesign.tcl+38-68
- ait/backend/xilinx/board/axiom/constraints/basic_constraints.xdc+1-1
- ait/backend/xilinx/board/axiom/procs.tcl+33
- ait/backend/xilinx/board/com_express/baseDesign.tcl+30-54
- ait/backend/xilinx/board/com_express/constraints/basic_constraints.xdc+1-1
- ait/backend/xilinx/board/euroexa_maxilink/baseDesign.tcl+83-103
- ait/backend/xilinx/board/euroexa_maxilink/constraints/basic_constraints.xdc+1-1
- ait/backend/xilinx/board/euroexa_maxilink/constraints/static_floorplan.xdc+3-3
- ait/backend/xilinx/board/euroexa_maxilink/procs.tcl+25-13
- ait/backend/xilinx/board/euroexa_maxilink/staticRegSlices.tcl+7-7
- ait/backend/xilinx/board/euroexa_maxilink_quad/baseDesign.tcl+83-103
- ait/backend/xilinx/board/euroexa_maxilink_quad/constraints/basic_constraints.xdc+1-1
- ait/backend/xilinx/board/euroexa_maxilink_quad/constraints/static_floorplan.xdc+3-3
- ait/backend/xilinx/board/euroexa_maxilink_quad/procs.tcl+24-13
- ait/backend/xilinx/board/euroexa_maxilink_quad/staticRegSlices.tcl+7-7
- ait/backend/xilinx/board/simulation/baseDesign.tcl+12-12
- ait/backend/xilinx/board/simulation/basic_info.json+1-2
- ait/backend/xilinx/board/simulation/procs.tcl+24-17
- ait/backend/xilinx/board/zcu102/baseDesign.tcl+31-62
- ait/backend/xilinx/board/zcu102/constraints/basic_constraints.xdc+1-1
- ait/backend/xilinx/board/zedboard/baseDesign.tcl+27-51
- ait/backend/xilinx/board/zedboard/constraints/basic_constraints.xdc+1-1
- ait/backend/xilinx/board/zybo/baseDesign.tcl+30-51
- ait/backend/xilinx/board/zybo/constraints/basic_constraints.xdc+1-1
- ait/backend/xilinx/board/zynq702/baseDesign.tcl+27-51
- ait/backend/xilinx/board/zynq702/constraints/basic_constraints.xdc+1-1
- ait/backend/xilinx/board/zynq706/baseDesign.tcl+30-54
- ait/backend/xilinx/board/zynq706/constraints/basic_constraints.xdc+1-1
- ait/backend/xilinx/driver.py+23-18
- ait/backend/xilinx/info.py+22
- ait/backend/xilinx/steps/HLS.py+1-1
- ait/backend/xilinx/steps/bitstream.py+1-1
- ait/backend/xilinx/steps/boot.py+1-1
- ait/backend/xilinx/steps/design.py+83-74
- ait/backend/xilinx/steps/implementation.py+1-1
- ait/backend/xilinx/steps/synthesis.py+1-1
- ait/backend/xilinx/tcl/scripts/axi_datapath.tcl+65-27
- ait/backend/xilinx/tcl/scripts/axis_datapath.tcl+79-44
- ait/backend/xilinx/tcl/scripts/board.tcl+191-181
- ait/backend/xilinx/tcl/scripts/generate_bitstream.tcl+3-3
- ait/backend/xilinx/tcl/scripts/generate_design.tcl+182-119
- ait/backend/xilinx/tcl/scripts/hwr_central_interconnect.tcl+8-8
- ait/backend/xilinx/tcl/scripts/hwr_dist_interconnect.tcl+16-16
- ait/backend/xilinx/tcl/scripts/implement_design.tcl+3-3
- ait/backend/xilinx/tcl/scripts/synthesize_design.tcl+1-1
- ait/backend/xilinx/tcl/scripts/utils.tcl+31
- ait/backend/xilinx/tcl/templates/Picos_OmpSs_Manager.tcl+49-45
- ait/backend/xilinx/utils/checkers.py+1-1
- ait/backend/xilinx/utils/parser.py+2-5
- ait/frontend/config.py+5-5
- ait/frontend/core.py+1-1
- ait/frontend/parser.py+4-4
- ait/frontend/utils.py+1-2
- test/test_parser.py+1-1
This file was deleted.
Submodule nanos6-fpga updated 300 files
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